Vol. 34, No.

Journal of Semiconductors

September 2013

VLSI scaling methods and low power CMOS buffer circuit

Vijay Kumar Sharma and Manisha Pattanaik
Department of Information Technology, ABV-Indian Institute of Information Technology & Management, Gwalior-474015, India

Abstract: Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuits performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. Key words: LPTG buffer; power dissipation; propagation delay; scaling; nanoscale CMOS; figure of merit DOI: 10.1088/1674-4926/34/9/095001 EEACC: 2570

1. Introduction
The MOS transistor is the basic building block of integrated circuits. Scaling of the MOS transistor improves its size, cost and performance. Todays fabricated integrated circuits are many times faster and occupy much less area, like todays microprocessors that contain nearly one billion transistors on a single chip. The role of supply voltage is vital for controlling the power consumption and hence reducing the power dissipation. It is reducing for each new technology generation. Threshold voltage of the device must be reduced proportionally as supply voltage reduces to sustain the transistors output performance. The reduction in threshold voltage increases the leakage current drastically with each new technology generation1 . As the leakage current increases with a new technology generation, it will affect the overall logic circuits power dissipation. Leakage current is the major problem in the deep submicron region, so we need a powerful leakage reduction technique to minimize the effect of threshold voltage scaling. Scaling methods pay a significant role in reducing the power dissipation from one technology node to another node. There are various scaling methods used for VLSI circuits. Most common are voltage scaling2 , load scaling3 , technology scaling4 and transistor sizing (width scaling)5 . The purpose of studying various scaling methods is to decide a suitable method for scaling while keeping power dissipation and propagation delay in mind. In this paper the work investigations are carried out on the above said four scaling methods for a CMOS buffer circuit. The paper is organized as follows. Section 2 describes the

various scaling methods in low power design. The methodology of the proposed approach is provided in Section 3 with conventional design. The leakage reduction and robustness capability of the proposed approach is verified in Section 4. Finally, conclusions of this work are outlined in Section 5.

2. Scaling methods
2.1. Voltage scaling A common and very effective method of reducing the power dissipation of a circuit is to reduce its supply voltage. The dynamic power dissipation component is directly propor2 tional to VDD that makes this technique so effective6 . Power reduction is possible through the voltage scaling at a constant clock frequency. It is observed that a CMOS inverter will continue to operate correctly with a supply voltage which is as low as the limit value shown in Eq. (1)6 VDD; min D jVtn j C Vtp : (1) One MOS device is always in on condition in CMOS inverter for any input voltage. The term voltage scaling used here is different from that of constant voltage scaling because here all other parameters are kept constant instead of scaling them by the same factor. This is the reason for propagation delay increasing because only the supply voltage is reduced. This is analytically observed from Eq. (2)6 for propagation delay of the CMOS inverter as D CL VDD D l CL VDD C .w= l/.VGS n OX Vth /2 ; (2)

Corresponding author. Email: vijay.buland@gmail.com Received 15 February 2013, revised manuscript received 20 March 2013

2013 Chinese Institute of Electronics

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Fig. 2. Total load capacitance CL at the output node. Fig. 1. Load capacitance and its components.

where is the propagation delay due to low to high and high to low output voltage transition. Vth is the threshold voltages of the MOS device. CL is the load capacitance and VDD is the power supply voltage. The circuits operate more slowly as the supply voltage decreases when assuming no other changes are made. This is the drawback of this approach. Another drawback is that some circuit styles cannot function at low supply voltages. The propagation delay increases with reducing the power supply voltage and can be compensating if the threshold voltage of the transistor is reduced accordingly. However, a reduction in the threshold voltage will cause an exponential increase in the device sub-threshold leakage current. In turn, this increases the static power of the device to unacceptable levels7 . This study clearly justifies the need for leakage reduction techniques. 2.2. Load scaling Load scaling is the other way to reduce the power dissipation. Larger load capacitance draws more charge from the power supply during each switching and hence increases the dynamic power dissipation8 . The larger capacitance reduces the speed of operation. Figure 1 shows the load capacitance and its components at output node Vout . Here Cgd1 and Cgd2 are the overlap capacitances, Cg1 and Cg2 are the gate capacitances, Cdb1 and Cdb2 are the drain/source diffusion capacitances, and Cint is the interconnect capacitance which is due to parallel plate capacitance, fringing capacitance and wire-wire capacitance. Therefore the capacitances are given as below: Cgate D Cg1 C Cg2 ; Cdiff D Cdb1 C Cdb2 : Total capacitance CL is then CL D Cgate C Cdiff C Cint : Total capacitance is depicted in Fig. 2. (5) (3) (4)

Fig. 3. Circuit model for analyzing the effect of transistor sizing.

If RL is the summed resistance of the overall circuit at the load terminal then propagation delay of the circuit is the multiply of load capacitance and load resistance. 2.3. Transistor width scaling Transistor sizing is also known as channel width scaling. Transistor width scaling effectively reduces power dissipation9 . If the channel width of the transistor is increased, then it reduces the signal transition at the output and hence propagation delay of the logic circuit. The small value of channel width is utilized for optimization of power dissipation and chip area while the large value is used to optimize the propagation delay of the logic circuit. For high performance calculation it may be seen that finding a single critical path can degrade the performance of the entire circuit. However, in low power design the focusable target is on lower power dissipation while taking propagation delay constraints and assuming the certain active area for the logic circuit. Figure 3 shows the 2-gate circuit with the first gate driving the gate capacitance Cg and the parasitic capacitance CP to the next gate. The input gate capacitance of both gates is given by NCref , where Cref is the gate capacitance of an MOS device with the possible smallest aspect ratio. The propagation delay through the first gate at a supply voltage Vref is given by Eq. (6)10 DK 1C N Vref ; Vth /2 (6)

.Vref

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Fig. 4. Scaling of an MOSFET by a factor of S . Fig. 5. Conventional CMOS buffer.

where is the ratio of CP to Cref , and K stands for the conditions independent of the devices width and voltage. 2.4. Transistors technology scaling CMOS technology has continued to scale down at a dramatic rate to opt high performance. In 1975, Moore predicted that the number of transistors per square inch in an IC would double every 18 months. In each new technology generation, the overall lateral and vertical dimensions of the transistors are scaled down by a factor. Figure 4 reflects the reduction of the key dimensions of a typical MOSFET while increasing of the doping densities. The new technology generation has an impact on reducing the power dissipation, as well as increasing the circuits speed due to reduction of all capacitance effects. As todays technology scales below 45 nm, the transistor density will continue to grow11 . A number of limitation factors like short channel effects, sub-threshold conduction, body effect etc. arise in the very deep submicron region for further scaling of the transistors. In practice, there are two types of scaling strategies for MOSFET devices: full scaling and constant voltage scaling. Constant field scaling reduces both the drain voltage and the drain current by a factor of S . Therefore, the power dissipation of the transistor decreases by a factor of S 2 , while it increases by the factor S in constant voltage scaling. This significant reduction of the power dissipation is one of the most attractive features of constant field scaling. However, the constant field scaling causes the sub-threshold leakage currents to grow exponentially and becomes an increasingly larger component of the total power dissipation12 . From the above said scaling methods, various important outcomes appear to explain them in the very deep submicron region. As we are moving towards the very deep submicron region the supply voltage as well as threshold voltage must be scaled in proper ratio to maintain the correct operation of the logic circuit13 . Power dissipation is the important term in the deep submicron region because of reduction in threshold voltage and effects of various other parameters to increase the leakage current components. As the technology node scales down below 65 nm node, many reliability problems are coming into being as a result14 . The above discussions tell that power dissipation and parameter variations are the main issues as technology scales down below 65 nm. To reduce the power dissipation a number of leakage reduction techniques are used. These techniques have their own advantages and disadvantages. In this section we have proposed a reliable leakage reduction technique for a CMOS buffer circuit. Our proposed low power transmission gate (LPTG) approach is a circuit level approach for reducing the leakage current and hence, leakage power directly affected the total power dissipation of the logic circuit. This approach is very effectively reducing both the active as well as the standby mode leakage current. Through a literature survey we know that many leakage reduction techniques are there in low power design but one simple and effective technique called LECTOR15 , is the single threshold voltage circuit level technique. The drawback of this technique is its low output swing voltage. Our proposed approach gives full output swing voltage as well as lower power dissipation as compared to LECTOR technique. The proposed approach used the extra insertion of transmission gates between the pull-up to output and output to pull-down network for minimizing the leakage current. These extra inserted transmission gates are called low power transmission gates (LPTG). LPTG provides a high conducting path when this block is on and a high resistive path when this block is off. The LPTG circuit block contains one NMOS and one PMOS transistor. The schematic of the CMOS LPTG buffer circuit is shown in Fig. 12. Here con and conbar are the control signals which are complementary to each other. These signals are used for activation or deactivation of the LPTG blocks. These signals depend on the output functionality of the buffer circuit. These signals must be precisely defined to give the re-

3. Conventional and LPTG CMOS buffer

A conventional CMOS buffer consists of two inverters cascaded as shown in Fig. 5. The input and the output have a definite delay time due to the device transitions in the CMOS circuits. The buffer circuit is generally used to drive large capacitive loads developed both by the next stage and the interconnect capacitances too. So, while building buffers, both strong NMOS and PMOS are used. This would help the device in charging and discharging the buffers quicker than normal. But these strong MOS devices in turn provide large capacitance and affect the time delays of the previous stages of the circuits.

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Fig. 6. Power dissipation for conventional buffer with voltage scaling.

Fig. 7. Propagation delay for convention buffer with voltage scaling.

liable and accurate performance of the circuit. If input voltage is uniformly on/off periodic pulse with time period tp then con and conbar are given as: Vin .VDD / D Vcon .Vin / D ( 0; 0 < t < tp =2; VDD ; tp =2 < t < tp ; VDD ; 0 < t < tp =2; 0; tp =2 < t < tp ; (7)

(8)

( 0; 0 < t < tp =2; Vconbar .Vin / D VDD ; tp =2 < t < tp :

(9)

These control signals also depend on the logic states of input voltage. Control signals con and conbar are assigned with appropriate potential based on the logic states of the input voltage.

4. Results and discussion

4.1. Voltage scaling for CMOS conventional buffer HSPICE EDA tool is used for calculating power dissipation and propagation delay for the conventional CMOS buffer at 65 nm, 45 nm and 32 nm technology nodes. For making a fine comparison, other parameters except supply voltage of these particular technology nodes are taken the same throughout the scaling of supply voltage. The supply voltage range for different technology nodes is precisely defined before analyzing the logic circuit because it is related to reliability of the circuit. The supply voltages for different technologies are chosen so as to maintain the high noise margin with proper output function while keeping the effective work of process parameters. According to ITRS the nominal supply voltage for 65 nm is 1.0 V, for 45 nm it is 0.9 V, and for 32 nm node it is 0.8 V. The supply voltage range is 20% of the nominal value and it is 0.80 to 1.20 V for 65 nm technology node, 0.72 to 1.08 V for 45 nm technology node and 0.64 to 0.96 V for 32 nm technology node for precise and reliable operation of the circuit. Figure 6 depicts the supply voltage scaling at different technology nodes.

It is observed from Fig. 6 that power dissipation is reduced with the reduction of supply voltage but propagation delay increases. For 65 nm technology, where supply voltage range is 0.80 to 1.20 V, % reduction in power dissipation is 86.73% while propagation delay increases by 112.14%. For 45 nm technology, where supply voltage range is 0.72 to 1.08 V, % reduction in power dissipation is 85.28% while propagation delay increases by 114.66%. For 32 nm technology, the supply voltage range is 0.64 to 0.96 V, % reduction in power dissipation is 91.64% while propagation delay increases by 155.31%. It is concluded from the above results that the voltage scaling is more efficient when technology scaled in terms of power dissipation saving, while it is challenging to reduce the propagation delay. Figure 7 shows the decrease in propagation delay with corresponding increasing in supply voltage and technology node of the conventional buffer. As the power dissipation increases in direct proportion with the supply voltage, so a compromise is to be made between the propagation delay and power dissipation of the conventional buffer depending upon the application requirements. A figure of merit is utilized to decide the acceptable level of propagation delay in low power VLSI circuit design. Figure of merit is the product of leakage power and propagation delay of the logic circuits. The supply voltage scaling improves the figure of merit by 78.70% when scaling from 0.96 to 0.64 V for 32 nm technology node. 4.2. Load scaling for CMOS conventional buffer With the reduction in the load capacitance, both power dissipation and propagation delay are reduced as shown in Figs. 8 and 9 at 65 nm, 45 nm and 32 nm technology nodes. For making a fine comparison, other parameters, except load capacitance, of these particular technology nodes are taken as the same for scaling of load capacitance. The load capacitance range for different technology nodes are precisely defined before analyzing the logic circuit because it is related to stability of the circuit. The ranges of load capacitances are chosen so as to optimize the power dissipation and propagation delay, while controlling the good input output characteristics of the logic circuit. Total power dissipation is the summation of dynamic and static power dissipation, where dynamic power is directly pro-

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Fig. 8. Power dissipation for conventional buffer with load scaling at 65 nm, 45 nm and 32 nm technology.

Fig. 10. Power dissipation and propagation delay for conventional buffer at different technologies.

of the logic circuit is evaluated by the figure of merit. The lower value of figure of merit is desirable for energy efficient operation of the logic circuit. Figure 10 shows the power dissipation and propagation delay curves at different technology nodes. It is clear that as technology scaled down from 65 to 32 nm, 356.48% power dissipation and 18.64% propagation delay is increased. Figure of merit increases with reduction of technology node. It increases very rapidly below 45 nm technology node. The technology scaling degrades the figure of merit by 516% when scaling from 65 nm to 32 nm technology node. A good VLSI designer wants to minimize the figure of merit to optimize the logic circuit design. It is the challenging task of the designers in the very deep submicron region and it requires the effective architecture, technique or algorithm to optimize both power dissipation and propagation delay of the circuit.
Fig. 9. Propagation delay for conventional buffer with load scaling at different technologies.

4.4. Transistor width scaling for CMOS conventional buffer The results for width scaling at 32 nm technology node are given in Fig. 11. The nominal supply voltage is 0.8 V at 32 nm node. The nominal width of NMOS device is twice of the corresponding channel length and it is six times in PMOS device. The width ratio of PMOS to NMOS device is increasing from 1 to 5. The power dissipation of conventional buffer is increased by 438.47% while propagation delay reduces by 66.28% from width ratio scaling of 1 to 5. It is inferred that with decreasing width ratio of the transistors, the power dissipation decreases with increment in the propagation delay penalty. By taking the appropriate transistors sizing, the designer made his design very valuable. The transistors width scaling improves the figure of merit by 44.90% when scaling from 5 to 1 for 32 nm technology node. 4.5. LPTG CMOS buffer The above discussions for a conventional CMOS buffer are presented for different scaling methods. Technology scaling is the prime requirement of the future nanoscale devices due to scaling of the various device parameters. The limitation of technology scaling is its poor figure of merit. We have proposed a low power transmission gate CMOS buffer circuit for improving the figure of merit of the technology scaling method.

portional to the load capacitance CL . It is concluded that power dissipation is reducing as load capacitance is decreased, as power dissipation directly depends on the load capacitance. Figure 9 shows that reduction in the load capacitance is reducing the propagation delay. As load capacitance is decreased, the output signal is changed rapidly and hence reduces the transition times at the output of conventional buffer. At 65 nm technology node the propagation delay is increasing with increase in the load capacitance values. The load capacitance scaling improves the figure of merit by 71.54% when scaling from 2.0 to 0.1 fF for 32 nm technology node. 4.3. Technology scaling for CMOS conventional buffer The results for technology scaling are presented in Fig. 10 at different technology nodes. It is concluded that power dissipation and propagation delay are increased with technology scaling. The incremental change in power dissipation with technology is due to leakage current components which are more dominant at lower technology node. Sub-threshold and gate leakage are the dominant components of leakage current in the very deep sub-micron region13 . The energy efficiency

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Fig. 11. Power dissipation and propagation delay for conventional buffer with width ratio scaling.

Fig. 13. Power dissipation (PD) and propagation delay for CMOS buffer at different technologies.

Fig. 14. Power dissipation and propagation delay versus width ratio for CMOS buffer. Fig. 12. Schematic of LPTG CMOS buffer.

The generalized schematic of the LPTG CMOS buffer is shown in Fig. 12. In the proposed design, eight extra transistors are employed for providing the path resistance from power supply to ground. The area requirement is reduced by choosing a fitting width scaling. Comparison of the conventional buffer and the LPTG CMOS buffer on power dissipation and propagation delay performance at different technologies is shown in Fig. 13. The LPTG approach reduces the power dissipation effectively when moving towards low technology nodes. In the LPTG approach we used the MOS devices which have accurate and efficient turning on/off characteristic. The number of off MOS devices between power supply to ground provides the greater body bias of these MOS devices, thus reducing the power dissipation. At 32 nm technology node LPTG approach reduces 95.16% power dissipation while increasing the propagation delay by 226.19%. The increments in propagation delays are of less concern because the LPTG approach has the better figure of merit. The figure of merit at 32 nm technology reduces by 84.23%. Our proposed approach is more valuable in the very deep nanoscale region as it reduces the figure of merit by 44.10% to 84.23% when moving from 65 nm to 32 nm technology node. The graph clarifies that the power dissipation of the LPTG

buffer circuit is very low and less influenced at low technology node in the very deep submicron region as compared to the conventional buffer. On the basis of propagation delay, the LPTG buffer circuit having the greater delay because of the number of transistors used in the LPTG buffer, increases the propagation delay of the circuit. Now we consider the effect of width ratio variation of the LPTG buffer circuit at 32 nm technology node while taking power supply voltage 0.8 V. A width comparison of the conventional CMOS buffer and LPTG CMOS buffer is shown in Fig. 14. The LPTG CMOS buffer circuit reduces the power dissipation by nearly 90.98% at width ratio 1. The sub-threshold leakage current component directly affected the power dissipation of the CMOS buffer circuit while larger width ratio causes larger chip area and proportionally reduces the speed of the circuit. An important result is reduction of the propagation delay with increment in width as compared to the conventional CMOS buffer. At normal width calculation, the % change in propagation delay is 196.83% while it is 259.83% at width ratio 5. The LPTG approach diminishes normally 70.70% figure of merit as width ratio varies from 1 to 5 as compared to the conventional CMOS buffer. The power dissipation and delay vs. temperature effects are analyzed as explained in Fig. 15. The temperature range is taken from 25 to 125 C. Power dissipation and propagation

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Fig. 17. Histogram of leakage current variations for CMOS buffer. Fig. 15. Power dissipation and propagation delay versus temperature for CMOS buffer.

cess, voltage and temperature parameters with MonteCarlo 1000 runs at 32 nm node. The LPTG approach is less susceptible to the process variations as compared to conventional circuit. The value of mean and standard deviation of leakage current components are 86.83 nA and 79.05 nA respectively for conventional CMOS buffer while in LPTG CMOS buffer, these are 72.86 nA and 31.50 nA respectively. The leakage current uncertainty is 0.91 in conventional while it is 0.43 in LPTG CMOS buffer. Thus our proposed approach mitigates 2.12X reliability issues in CMOS buffer circuit.

5. Conclusion
Low power design is drawing a huge deal of awareness in VLSI digital design, principally for portable high performance systems. The quick switching of billions of transistors dissipates tremendous power and overheats the chip, reducing the reliability of the chip and necessitating expensive and large cooling systems. In this article, scaling methods like voltage scaling, load scaling, technology scaling and width scaling for a nanoscale CMOS buffer circuit have been analyzed. Based on the analysis of these scaling methods we proposed a reliable low power transmission gate approach which effectively reduces the power dissipation and enhances the reliability. Different scaling variations are used to analyze the power dissipation and propagation delay behavior in the CMOS buffer circuit. The necessity of future nanoscale circuits is mitigation of the energy consumption per cycle. The least value of figure of merit provides the energy efficient design at future nanoscale nodes. Our proposed approach saves power dissipation by 95.16% with 84.20% progress in figure of merit in the CMOS buffer at 32 nm technology node. The LPTG approach decreases the leakage current uncertainty from 0.91 to 0.43 in the CMOS buffer for reliable operation of the logic circuit in the very deep submicron region.

Fig. 16. Power dissipation and propagation delay versus supply voltage for CMOS buffer.

delay for both circuits are increased with increasing the temperature. The increment in power dissipation is due to thermal voltage dependency of the leakage current. If we calculate the % change of these two parameters then % saving of power dissipation is decreasing while propagation delay increases as temperature increasing. Leakage uncertainty is less in the LPTG approach as compared to the conventional. The LPTG approach is less affected, normally 64.10% figure of merit with temperature varying from 25 to 125 C as compared to the conventional CMOS buffer. The effect of voltage scaling of 20% variations from nominal value is analyzed for LPTG and conventional CMOS buffer circuit. The output results are illustrated in Fig. 16 at 32 nm technology node. The rising rate of performance parameters are very slow in the LPTG approach with increasing in VDD as compared to conventional circuit. The 20% power supply voltage variations are less influenced, normally 73.20% figure of merit as compared to conventional CMOS buffer. The summation of leakage current components under various process, voltage and temperature variations are distributed as shown in Fig. 17. These leakage current components are responsible for power dissipation and reliability issues in buffer circuit. Figure 17 is plotted by taking 10% variations in pro-

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