INDEX

S.No. 1. 2.

TITLE Design all gates using VHDL. Write VHDL programs for the following circuits, check the wave forms and the hardware generated a. half adder b. full adder Write VHDL programs for the following circuits, check the wave forms and the hardware generated a. half subtractor b. full subtractor Write VHDL programs for the multiple"er, check the wave forms and the hardware generated Write VHDL programs for the demultiple"er, check the wave forms and the hardware generated Write VHDL programs for the encoder, check the wave forms and the hardware generated Write VHDL programs for the decoder, check the wave forms and the hardware generated Write VHDL programs for the comparator, check the wave forms and the hardware generated Write VHDL programs for the D flip(flop, check the wave forms and the hardware generated *o stud+ the ,-LD and .-/0.

DATE

SIGNATURE

!. #. $. %. &.

'.

1).

PRACTICAL-1
Aim:- Write program in VHDL to imp ement A Gate!. Apparat"! Re#"ire$1 ( 2uartus 33 40ltera5 , -, etc. AND Gate:*he 06D gate is a basic digital logic gate that implements logical con7unction ( it behaves according to the truth table to the right. 0 H3/H output 415 results onl+ if both the inputs to the 06D gate are H3/H 415. 3f neither or onl+ one input to the 06D gate is H3/H, a L8W output results. 3n another sense, the function of 06D effectivel+ finds the minimum between two binar+ digits, 7ust as the 89 function finds the maximum. *herefore, the output is alwa+s ) e"cept when all the inputs are 1s.

Logi% S&m'o

Tr"t( Ta' e

)r Gate:*he 89 gate is a digital logic gate that implements logical dis7unction ( it behaves according to the truth table to the right. 0 H3/H output 415 results if one or both the inputs to the gate are H3/H 415. 3f neither input is H3/H, a L8W output 4)5 results. 3n another sense, the function of 89 effectivel+ finds the maximum between two binar+ digits, 7ust as the complementar+ 06D function finds the minimum.

Logi% S&m'o

Tr"t( Ta' e

N)T Gate:0 68* gate, often called an inverter, is a nice digital logic gate to start with because it has onl+ a single input with simple behavior. 0 68* gate performs logical negation on its input. 3n other words, if the input is true, then the output will be false. :imilarl+, a false input results in a true output.

Logi% S&m'o Tr"t( Ta' e NAND Gate:0 606D gate is logicall+ an inverted 06D gate. *he output is high when either of inputs 0 or ; is high, or if neither is high. 3n other words, it is normall+ high, going low onl+ if both 0 and ; are high.

Logi% S&m'o

Tr"t( Ta' e

N)R Gate:0 689 gate is logicall+ an inverted 89 gate. *he output is high onl+ when neither 0 nor ; is high. *hat is, it is normall+ high but an+ kind of non(<ero input will take it low. *he 689 gate and the 606D gate can be said to be universal gates since combinations of them can be used to accomplish an+ of the basic operations and can thus produce an inverter, an 89 gate or an 06D gate.

Logi% S&m'o

Tr"t( Ta' e

*)R Gate:*he =89 gate is a digital logic gate that implements an e"clusive or. that is, a true output 415 results if one, and onl+ one, of the inputs to the gate is true 415. 3f both inputs are false 4)5 or both are true 415, a false output 4)5 results. 3ts behavior is summari<ed in the truth table shown on the right. 0 wa+ to remember =89 is >one or the other but not both

Logi% S&m'o

Tr"t( Ta' e

*N)R Gate:*he =689 gate is a digital logic gate whose function is the inverse of the e"clusive 89 4=895 gate. *he two(input version implements logical e?ualit+, behaving according to the truth table to the right. 0 H3/H output 415 results if both of the inputs to the gate are the same. 3f one but not both inputs are H3/H 415, a L8W output 4)5 results.

Logi% S&m'o VHDL Co$e:librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ LogicAgates is port4a,b1 in stdAlogic@ c1out stdAlogicAvector4# downto )55@ end LogicAgates@ architecture dataAflow of LogicAgates is begin c4#5 BC a and b@ c4!5BC a or b@ c4 5BC a nand b@

Tr"t( Ta' e

c425BC a nor b@ c415BC a "or b@ c4)5BC a "nor b@ end dataAflow@

RTL Vie+:-

Sim" ation )"tp"t:-

Pre%a"tion!:1. *ake due precautions to handle -, and interfacing devices. .ollow laid down guidelines while working in D:D Lab. 8bserve waveforms carefull+. Re!" t:0ll basic gates has been s+nthesi<ed.

PRACTICAL-,

Aim:- Write program in VHDL to imp ement Ha - A$$er an$ ." A$$er.
Apparat"! Re#"ire$1 ( 2uartus 33 40ltera5 , -, etc. *he half adder adds two single binar+ digits A and B. 3t has two outputs, sum 4S5 and carr+ 4C5. *he carr+ signal represents an overflow into the ne"t digit of a multi(digit addition. *he value of the sum is 2C D S. *he simplest half(adder design, pictured on the right, incorporates an =89 gate for S and an 06D gate for C. With the addition of an 89 gate to combine their carr+ outputs, two half adders can be combined to make a full adder.

Logi% Cir%"it Ta' e VHDL Co$e:1) Using Data Flow modeling

Tr"t(

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ halfAadder is port4a,b1in bit@ s,c1out bit5@ end halfAadder@ architecture dataAflow of halfAadder is begin s BC a "or b@ c BC a and b@
end data_flow;

2)

Using Behavioural Modelling

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ halfAadderAb is port4a,b1in bit@ s,c1out bit5@ end halfAadderAb@ architecture behavioural of halfAadderAb is begin process4a,b5 begin s BC a "or b@ c BC a and b@ end process@ end architecture behavioural@
3) Structural Modeling:-

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ halfAadderAstur is port4a,b1in bit@ s,c1out bit5@ end halfAadderAstur@ architecture structral of halfAadderAstur is component "orA2 port4d,e1 in bit@ f1 out bit5@ end component@ component andA2 port4g,h1 in bit@ i1 out bit5@ end component@

begin =11 "orA2 portmap4a,b,s5@ =21 andA2 portmap4a,b,c5@ end structural@

RTL Vie+:-

Sim" ation )"tp"t:-

." A$$er:0 -" a$$er adds binar+ numbers and accounts for values carried in as well as out. 0 one(bit full adder adds three one(bit numbers, often written as A, B, and Cin@ A and B are the operands, and Cin is a bit carried in from the ne"t less significant stage. *he full(adder is usuall+ a component in a cascade of adders, which add &, 1$, 2, etc. binar+ numbers. *he circuit produces a two(bit output, output carr+ and sum t+picall+ represented b+ the signals Cout and S.

Logi% Cir%"it Ta' e VHDL Co$e:1. Using Data Flow modeling

Tr"t(

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ fullAadder is port4a,b,"1in bit@ s,+1out bit5@ end fullAadder@ architecture dataAflow of fullAadder is signal *1,*2,* 1 bit@ begin *1 BC a "or b@ *2 BC *1 and "@ * BC a and b@ s BC *1 "or "@ + BC *2 or * @ end dataAflow@
2. Behavior Modelling

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@

entit+ faA2 is port 4a1 in bit@ b1 in bit@ "1 in bit@ c1 out bit@ s1 out bit5@ end faA2@ architecture behavioural of faA2 is begin s BC 44a "or b5 "or "5@ c BC 4a and b5 or 4b and "5 or 4a and "5@ end behavioural@
3. Structural Modelling

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ fullAadderAst is port4a,b,"1in bit@ s,+1out bit5@ end fullAadderAst@ architecture structural of fullAadderAst is component "orA2 port4d,e1 in bit@ f1 out bit5@ end component@ component andA2 port4 g,h1in bit@ i1 out bit5@ end component@ component orA2 port4 7,k1 in bit@ l1 out bit5@ end component@

signal *1,*2,* 1 bit@ begin =11 "orA2 port map4a,b,*15@ =21 "orA2 port map 4*1,",s5@ = 1 andA2 port map 4a,b,* 5@ =!1 andA2 port map 4*1,",*25@ =#1 orA2 port map 4*2,* ,+5@ end structural@

RTL Vie+:-

Sim" ation )"tp"t:-

Re!" t:
*he output of Half 0dder and .ull 0dder has been s+nthesi<ed.

PRACTICAL-/
Aim:- Write program in VHDL to imp ement Ha - S"'tra%tor an$ ." S"'tra%tor.

Apparat"! Re#"ire$1 ( 2uartus 33 40ltera5 , -, etc.

Ha - S"'tra%tor:0 combinational circuit which performs the subtraction of two bits is called half subtractor. *he input variables designate the minuend and the subtrahend bit, whereas the output variables produce the difference and borrow bits.

Logi% Cir%"it VHDL Co$e:1.Using Data Flow Modelling

Tr"t( Ta' e

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ halfAsubtractor is port4=,E1 in bit@ D,;1 out bit5@ end halfAsubtractor@ architecture H0AdataAflow of halfAsubtractor is signal =;091 bit@ begin =;09BC not =@ DBC = "or E@ ;BC=;09 and E@ end H0AdataAflow@
2.Behavior Modelling

librar+ ieee@

use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ H:A;ehavior is port4=,E1 in bit@ D,;1 out bit5@ end H:A;ehavior@ architecture H:F;Abehavior of H:A;ehavior is begin process4=,E5 variable =;091 bit@ begin =;091C not =@ DBC = "or E@ ;BC=;09 and E@ end process@ end H:F;Abehavior@
3.Strcuture Modelling

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ H:Astructure is port4=,E1 in bit@ D,;1 out bit5@ end H:Astructure@ architecture H:F;Astructure of H:Astructure is component "orA2 port4G,.1 in bit@ g1 out bit5@ end component@ component notA2 port4H1 in bit@

31 out bit5@ end component@ component andA2 port4H,I1 in bit@ L1 out bit5@ end component@ signal =;091 bit@ begin =11 "orA2 portmap4=,E,D5@ 611 notA2 portmap4=,=;095@ 011 andA2 portmap4=;09,E,;5@ end H:F;Astructure@

RTL Vie+:-

Sim" ation )"tp"t:-

." S"'tra%tor:0 combinational circuit which performs the subtraction of three input bits is called full subtractor. *he three input bits include two significant bits and a previous borrow bit. 0 full subtractor circuit can be implemented with two half subtractors and one 89 gate.

Logi% Cir%"it VHDL Co$e:1.Using Data Flow Modelling

Tr"t( Ta' e

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ fullAsubtractor is port4=,E,J1 in bit@ D,;1 out bit5@ end fullAsubtractor@ architecture .:AdataAflow of fullAsubtractor is signal *1,*2,* ,*!,*#1 bit@ begin *1BC not =@ *2BC = "or E@ * BC not *2@ *!BC * and J@ *#BC *1 and E@ DBC = "or E "or J@ ;BC *! or *#@ end .:AdataAflow@
2.Behavior Modelling

librar+ ieee@

use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ .ullAsubAbeh is port4=,E,J1 in bit@ D,;1 out bit5@ end .ullAsubAbeh@ architecture .:Abehavior of .ullAsubAbeh is begin -rocess4=,E,J5 variable *1,*2,* ,*!,*#1 bit@ begin *11C not =@ *21C = "or E@ * 1C not *2@ *!1C * and J@ *#1C *1 and E@ DBC *2 "or J@ ;BC*! or *#@ end process@ end .:Abehavior@
3.Structural Modelling

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ .:Astructure is port4=,E,J1 in bit@ D,;1 out bit5@ end .:Astructure@ architecture .:F;Astructure of .:Astructure is component "orA1 port4G,.1 in bit@ g1 out bit5@

end component@ component notA1 port4H1 in bit@ 31 out bit5@ end component@ component andA1 port4H,I1 in bit@ L1 out bit5@ end component@ component orA1 port4K,61 in bit@ 81 out bit5@ end component@ signal *1,*2,* ,*!,*#1 bit@ begin 611 notA1 port map 4=,*15@ 621 notA1 port map 4*2,* 5@ =11 "orA1 port map 4=,E,*25@ =21 "orA1 port map 4*2,J,D5@ 011 andA1 port map 4*1,E,*#5@ 021 andA1 port map 4* ,J,*!5@ 811 orA1 port map 4*!,*#,;5@ end .:F;Astructure@

RTL Vie+:-

Sim" ation )"tp"t:-

Pre%a"tion!:1. *ake due precautions to handle -, and interfacing devices. 2. .ollow laid down guidelines while working in D:D Lab. . 8bserve waveforms carefull+.

Re!" t:*he output of Half :ubtractor and Full Subtractor has been s+nthesi<ed.

Pra%ti%a -0
Aim:- Write program in VHDL to imp ement 1" tip e2er.

Apparat"! Re#"ire$1 ( 2uartus 33 40ltera5 , -, etc. T(eor&:- n electronics, a multiple"er 4or mu"5 is a device that selects one of several analog or
digital input signals and forwards the selected input into a single line. 0 multiple"er of 2 n inputs has n select lines, which are used to select which input line to send to the output. Kultiple"ers are mainl+ used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth.

Logi% Cir%"it VHDL Co$e:1) Using data Flow:-

Tr"t( Ta' e

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ multiple"er is port43),31,32,3 ,:),:11 in bit@ +1 out bit5@ end multiple"er@ architecture mu"!"1AdataAflow of multiple"er is signal :);09,:1;09,*),*1,*2,* 1 bit@ begin :);09BC not :)@ :1;09BC not :1@ *)BC :);09 and :1;09 and 3)@ *1BC :) and :1;09 and 31@

*2BC :);09 and :1 and 32@ * BC :) and :1 and 3 @ +BC *) or *1 or *2 or * @ end mu"!"1AdataAflow@
2) Behavioral Modelling:-

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ Ku"Abehaviour is port43),31,32,3 ,:),:11 in bit@ +1 out bit5@ end Ku"Abehaviour@ architecture mu"!"1Abehaviour of Ku"Abehaviour is process 43),31,32,3 ,:),:15 begin variable :);09,:1;09,*),*1,*2,* 1 bit@ :);09BC not :)@ :1;09BC not :1@ *)BC :);09 and :1;09 and 3)@ *1BC :) and :1;09 and 31@ *2BC :);09 and :1 and 32@ * BC :) and :1 and 3 @ +BC *) or *1 or *2 or * @ end process@ end mu"!"1Abehaviour@ 5 Structral Modelling:librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ Ku"Astructure is port43),31,32,3 ,:),:11 in bit@

+1 out bit5@ end Ku"Astructure@ architecture mu"!"1Astructure of Ku"Astructure is component andA2 port4a,b,c1 in bit@ d1 out bit5@ end component@ component notA2 port4e1 in bit@ f1 out bit5@ end component@ component orA2 port4g,h,i,71 in bit@ k1 out bit5@ end component@ signal :);09,:1;09,*),*1,*2,* 1 stdAlogic@ begin 611 notA2 port map 4:),:);095@ 621 notA2 port map 4:1,:1;095@ 011 andA2 port map 43),:);09,:1;09,*)5@ 021 andA2 port map 431,:),:1;09,*15@ 0 1 andA2 port map 432,:);09,:1,*25@ 0!1 andA2 port map 43),:),:1,* 5@ 811 orA2 port map 4*),*1,*2,* ,+5@ end mu"!"1Astructure@

RTL Vie+:-

Sim" ation )"tp"t:-

Pre%a"tion!:1. *ake due precautions to handle -, and interfacing devices. 2. .ollow laid down guidelines while working in D:D Lab. .8bserve waveforms carefull+.

Re!" t:*he output of Kultiple"er has been s+nthesi<ed.

Pra%ti%a -3
Aim:- Write program in VHDL to imp ement Dem" tip e2er.

Apparat"! Re#"ire$1 ( 2uartus 33 40ltera5 , -, etc. T(eor&:- 0 demultiple"er, sometimes abbreviated dmu", is a circuit that has one input and
more than one output. 3t is used when a circuit wishes to send a signal to one of man+ devices. *his description sounds similar to the description given for a decoder, but a decoder is used to select among man+ devices while a demultiple"er is used to send a signal among man+ devices.

Logi% S&m'o VHDL Co$e:14 Data . o+:librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ demu"1"! is port43,:),:11 in bit@E),E1,E2,E 1 out bit5@ end demu"1"!@ architecture demu"1"!AdataAflow of demu"1"! is signal :);09,:1;091 bit@ begin :);09BC not :)@ :1;09BC not :1@ E)BC :);09 and :1;09 and 3@ E1BC :) and :1;09 and 3@ E2BC :);09 and :1 and 3@ E BC :) and :1 and 3@ end demu"1"!AdataAflow@

Tr"t( Ta' e:-

,4 5e(a6ior mo$e ing librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ demu"Abehavior is port43,:),:11 in bit@E),E1,E2,E 1 out bit5@ end demu"Abehavior@ architecture demu"1"!AdataAflow of demu"Abehavior is begin process 43, :), :15 variable :);09,:1;091 bit@ begin :);091C not :)@ :1;091C not :1@ E)BC :);09 and :1;09 and 3@ E1BC :) and :1;09 and 3@ E2BC :);09 and :1 and 3@ E BC :) and :1 and 3@ end process@ end demu"1"!AdataAflow@ 5 Str"%t"re 1o$e ing librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ demu"Astructure is port43,:),:11 in bit@ E),E1,E2,E 1 out bit5@ end demu"Astructure@

architecture demu"1"!Astructure of demu"Astrcuture is component notA1 port401 in bit@ ;1 out bit5@ end component@ component andA port4,,D,G1 in bit@ .1 out bit5@ end component@ :ignal :);09, :1;091 bit@ begin 611 notA1 portmap4:), :);095@ 621 notA1 portmap4:1,:1;095@ 011 andA2 portmap43,:);09,:1;09,E)5@ 021 andA2 portmap43,:),:1;09,E15@ 0 1 andA2 portmap43,:);09,:1,E25@ 0!1 andA2 portmap43,:),:1,E 5@ end demu"1"!AdataAflow@

RTL Vie+:-

Sim" ation )"tp"t:-

Pre%a"tion!:1. *ake due precautions to handle -, and interfacing devices. 2. .ollow laid down guidelines while working in D:D Lab. . 8bserve waveforms carefull+.

Re!" t:*he output of De-multiplexer has been s+nthesi<ed.

Pra%ti%a -7

Aim:- Write program in VHDL to imp ement En%o$er. Apparat"! Re#"ire$1 ( 2uartus 33 40ltera5 , -, etc. T(eor&: 0n encoder is a device, circuit, transducer, software program, algorithm or person
that converts information from one format or code to another, for the purposes of standardi<ation, speed, secrec+, securit+, or saving space b+ shrinking si<e. Tr"t( ta' e:

VHDL Co$e: 14 U!ing Data - o+ mo$e ing librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ encoder&" is port43),31,32,3 ,3!,3#,3$,3%,G1 in bit@ a,b,c1 out bit5@ end encoder&" @ architecture encoder&" AdataAflow of encoder&" is begin aBC3! or 3# or 3$ or 3% or G@ bBC32 or 3 or 3$ or 3% or G@ ,BC31 or 3 or 3# or 3% 89 G@ end encoder&" AdataAflow@ 25 U!ing 5e(a6ior 1o$e ing

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ decoder1 is port40,;,,1 in bit@ G1 in bit@ 3),31,32,3 ,3!,3#,3$,3%1 out bit5@ end decoder1@ architecture decoder1Abeh of decoder1 is signal 0;09, ;;09 ,,;091 bit@ begin process40,b,,5 begin 0;09BC not 0@ ;;09BC not ;@ ,;09BC not ,@ 3)BC 0;09 and ;;09 and ,;09 and G@ 31BC 0;09 and ;;09 and , and G@ 32BC 0;09 and ; and ,;09 and G@ 3 BC 0;09 and ; and , and G@ 3!BC 0 and ;;09 and ,;09 and G@ 3#BC 0 and ;;09 and , and G@ 3$BC 0 and ; and ,;09 and G@ 3%BC 0 and ; and , and G@ end process@ end decoder1Abeh@ /4 U!ing Str"%t"re 1o$e ing

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ encoder1 is port43),31,32,3 ,3!,3#,3$,3%,G1 in bit@ a,b,c1 out bit5@ end encoder1@ architecture encoderAstr of encoder1 is component orA1 is port4d,e,f,g,h1in bit@ 71 out bit5@ end component@ begin 811orA1 port map43!,3#,3$,3%,G,05@ 811orA1 port map432,3 ,3$,3%,G,;5@ 811orA1 port map431,3 ,3#,3%,G,,5@ end encoderAstr@ RTL Vie+:

Sim" ation )"tp"t:

Pre%a"tion!:15 *ake due precautions to handle -, and interfacing devices. 25 .ollow laid down guidelines while working in D:D Lab. 5 8bserve waveforms carefull+.

Re!" t:*he output of Encoder has been s+nthesi<ed.

Pra%ti%a -8

Aim:- Write program in VHDL to imp ement De%o$er. Apparat"! Re#"ire$1 ( 2uartus 33 40ltera5 , -, etc. De%o$er1 0 decoder is a device which does the reverse operation of an encoder, undoing the
encoding so that the original information can be retrieved. *he same method used to encode is usuall+ 7ust reversed in order to decode. 3t is a combinational circuit that converts binar+ information from n input lines to a ma"imum of 2n uni?ue output lines. 3n digital electronics, a decoder can take the form of a multiple(input, multiple(output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. e.g. n(to(2n, binar+(coded decimal decoders. Gnable inputs must be on for the decoder to function.

Tr"t( ta' e:

VHDL Co$e: 14 U!ing Data - o+ mo$e ing librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ decoder "& is port40,;,,1 in bit@ G1 in bit@ 3),31,32,3 ,3!,3#,3$,3%1 out bit5@ end decoder "&@ architecture decoder "&AdataAflow of decoder "& is signal 0;09, ;;09 ,,;091 bit@ begin 0;09BC not 0@ ;;09BC not ;@ ,;09BC not ,@ 3)BC 0;09 and ;;09 and ,;09 and G@

31BC 0;09 and ;;09 and , and G@ 32BC 0;09 and ; and ,;09 and G@ 3 BC 0;09 and ; and , and G@ 3!BC 0 and ;;09 and ,;09 and G@ 3#BC 0 and ;;09 and , and G@ 3$BC 0 and ; and ,;09 and G@ 3%BC 0 and ; and , and G@ end decoder "&AdataAflow@

,4 U!ing 5e(a6ior 1o$e ing

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ encoder1 is port43),31,32,3 ,3!,3#,3$,3%,G1 in bit@ a,b,c1 out bit5@ end encoder1@ architecture encoderAbeh of encoder1 is begin process43),31,32,3 ,3!,3#,3$,3%,G5 begin aBC3! or 3# or 3$ or 3% or G@ bBC32 or 3 or 3$ or 3% or G@ ,BC31 or 3 or 3# or 3% 89 G@ end process@ end encoderAbeh@

/4 U!ing Str"%t"ra 1o$e ing

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ decoder1 is port40,;,,,G1 in bit@

3),31,32,3 ,3!,3#,3$,3%1 out bit5@ end decoder1@ architecture decoder1Astr of decoder1 is signal 0;09, ;;09 ,,;091 bit@ component andA1 is port4f,g,h,71in bit@ k1out bit5@ end component@ component notA1 is port4l1 in bit@ m1 out bit5@ end component@ begin J11notA1 port map4a,abar5@ J11notA1 port map4b,bbar5@ J11notA1 port map4c,cbar5@ 011andA1 port map4abar,bbar,cbar5@ 011andA1 port map4abar,bbar,c5@ 011andA1 port map4abar,b,cbar5@ 011andA1 port map4abar,b,c5@ 011andA1 port map4a,bbar,cbar5@ 011andA1 port map4a,bbar,c5@ 011andA1 port map4a,b,cbar5@ 011andA1 port map4a,b,c5@ end decoder1Astr@

RTL Vie+:

Sim" ation )"tp"t:

Pre%a"tion!:15 *ake due precautions to handle -, and interfacing devices. 25 .ollow laid down guidelines while working in D:D Lab. 5 8bserve waveforms carefull+.

Re!" t:*he output of Decoder has been s+nthesi<ed.

Pra%ti%a -7

Aim:- Write program in VHDL to imp ement Comparator. Apparat"! Re#"ire$1 ( 2uartus 33 40ltera5 , -, etc. T(eor&1 0 digital comparator or magnitude comparator is a hardware electronic device that
takes two numbers as input in binar+ form and determines whether one number is greater than, less than or e?ual to the other number. ,omparators are used in central processing units 4,-Fs5 and microcontrollers 4K,Fs5. Tr"t( ta' e:

VHDL Co$e: 14 U!ing Data . o+ 1o$e ing librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ comparator is port4a,b1 in bit@ less,e?ual,greater1out bit5@ end comparator@ architecture dataAflow of comparator is signal abar,bbar,t1,t21bit@ begin abarBC not a@ bbarBCnot b@ t1BCabar and bbar@ t2BCa and b@

greaterBC a and bbar@ e?ualBCt1 or t2@ lessBC abar and b@ end dataAflow@ ,4 U!ing 5e(a6ior 1o$e ing librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ comparatorAbeh is port4a,b1 in bit@ less,e?ual,greater1out bit5@ end comparatorAbeh@ architecture behavioural of comparatorAbeh is begin process4a,b5 variable abar,bbar,t1,t21bit@ begin abar1C not a@ bbar1Cnot b@ t11Cabar and bbar@ t21Ca and b@ greaterBC a and bbar@ e?ualBCt1 or t2@ lessBC abar and b@ end process@ end behavioural@ 5 U!ing Str"%t"ra 1o$e ing

librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ comparatorAstr is port4a,b1 in bit@ less,e?ual,greater1out bit5@ end comparatorAstr@ architecture structure of comparatorAstr is component andA1 is port4c,d1in bit@ e1out bit5@ end component @ component notA1 is port4g1in bit@ h1out bit5@ end component@ component orA1 is port4i,71in bit1 k1out bit5@ end component@ signal abar,bbar,t1,t21bit@ begin 311 notA1 port map4a,abar5@ 321 notA1 port map4b,bar5@ 011 andA1 port map4abar,bbar,t15@ 021 andA1 port map4abar,b,less5@ 0 1 andA1 port map4a,bbar,greater5@

0!1 andA1 port map4a,b,t25@ 011 orA1 port map4t1,t2,e?ual5@ end structural@ RTL Vie+:

Sim" ation )"tp"t:-

Pre%a"tion!:15 *ake due precautions to handle -, and interfacing devices. 25 .ollow laid down guidelines while working in D:D Lab. 5 8bserve waveforms carefull+.

Re!" t:*he output of Comparator has been s+nthesi<ed.

Pra%ti%a -9 Aim:- Write program in VHDL to imp ement D . ip-. op.

Apparat"! Re#"ire$1 ( 2uartus 33 40ltera5 , -, etc. T(eor&1 *he D Lip(Lop is widel+ used. 3t is also known as a data or dela+ flip(flop. *he D flip(
flop captures the value of the D(input at a definite portion of the clock c+cle 4such as the rising edge of the clock5. *hat captured value becomes the 2 output. 0t other times, the output 2 does not change. *he D flip(flop can be viewed as a memor+ cell, a <ero(order hold, or a dela+ line. Tr"t( ta' e:

D ) 1 VHDL Co$e: 14 U!ing Data . o+ 1o$e ing librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ dAff is port 4clk,d 1 in bit@ ?,?bar1 inout bit5@ end dAff@ architecture dAdataAflow of dAff is signal t1,t2,t 1bit@ begin t1BC not d@ t2BC d nand clk@ t BC t1 nand clk@ ?BC t2 nand ?bar@ ?barBC t nand ?@

24oMp5 )4reset5 14set5

end dAdataAflow@ ,4 U!ing 5e(a6iora 1o$e ing librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@ use ieee.stdAlogicAunsigned.all@ entit+ dAff is port 4clk,pr,cr,d 1 in bit@ ? 1 out bit5@ end dAff@ architecture dAbeh of dAff is begin process 4clk,cr,pr5 begin if4pr C N)N and cr C N1N and clk CN1N5 then ? BC N1N@ else if 4prCN1N and crC N)Nand clk CN1N5 then ? BC d@ end if@ end if@ end process@ end dAbeh@ /4 U!ing Str"%t"ra 1o$e ing librar+ ieee@ use ieee.stdAlogicA11$!.all@ use ieee.stdAlogicAarith.all@

use ieee.stdAlogicAunsigned.all@ entit+ dAff is port 4clk,d 1 in bit@ ?,?bar1 inout bit5@ end dAff@ architecture dAstr of dAff is signal t1,t2,t 1bit@ component nandA1 is port4a,b1 in bit@ c1 out bit5@ end component@ component notA1 is port4g1in bit@ 71 out bit5@ end component@ begin 311 notA1 port map4d,t15@ 611 nandA1 port map4d,clk,t25@ 621 nandA1 port map4t1,clk,t 5@ 6 1 nandA1 port map4t2,?bar,?5@ 6!1 nandA1 port map4?,t ,?bar5@ end dAstr@

RTL Vie+:

Sim" ation )"tp"t:

Pre%a"tion!:15 *ake due precautions to handle -, and interfacing devices. 25 .ollow laid down guidelines while working in D:D Lab. 5 8bserve waveforms carefull+.

Re!" t:*he output of D-flipflop has been s+nthesi<ed.

Pra%ti%a -1:

Aim:- To !t"$& t(e .PGA an$ CPLD.

T(eor&: CPLD: 0 comple" programmable logic device 4,-LD5 is a programmable logic device with comple"it+ between that of -0Ls and .-/0s, and architectural features of both. *he building block of a ,-LD is the macrocell, which contains logic implementing dis7unctive normal form e"pressions and more speciali<ed logic operations. 0 ,-LD contains a bunch of -LD blocks whose inputs and outputs are connected together b+ a global interconnection matri". :o a ,-LD has two levels of programmabilit+1 each -LD block can be programmed, and then the interconnections between the -LDs can be programmed. .eat"re!:

6on(volatile configuration memor+. Fnlike man+ .-/0s, an e"ternal configuration 98K isnNt re?uired, and the ,-LD can function immediatel+ on s+stem start(up. .or man+ legac+ ,-LD devices, routing constrains most logic blocks to have input and output signals connected to e"ternal pins, reducing opportunities for internal state storage and deepl+ la+ered logic. *his is usuall+ not a factor for larger ,-LDs and newer ,-LD product families.

.PGA: 0 field(programmable gate arra+ 4.-/051 0 completel+ different architecture was introduced in the mid(1'&)Os that uses 90K(based lookup tables instead of 06D(89 gates to implement combinational logic. *hese devices are called field programmable gate arra+s 4.-/0s5. *he device consists of an arra+ of configurable logic blocks 4,L;s5 surrounded b+ an arra+ of 3M8 blocks. *he :partan( G from =ilin" also contains some blocks of 90K, 1& " 1& multipliers, as well as Digital ,lock Kanager 4D,K5 blocks. *hese D,Ks are used to eliminate clock distribution dela+ and can also increase or decrease the fre?uenc+ of the clock. *he .-/0 configuration is generall+ specified using a hardware description language 4HDL5, similar to that used for an application(specific integrated circuit 40:3,5 4circuit diagrams were previousl+ used to specif+ the configuration, as the+ were for 0:3,s, but this is increasingl+ rare5. ,ontemporar+ .-/0s have large resources of logic gates and 90K blocks to implement comple" digital computations. 0s .-/0 designs emplo+ ver+ fast 38s and bidirectional data buses it becomes a challenge to verif+ correct timing of valid data within setup time and hold

time. .loor planning enables resources allocation within .-/0 to meet these time constraints. .-/0s can be used to implement an+ logical function that an 0:3, could perform. *he abilit+ to update the functionalit+ after shipping, partial re(configuration of a portion of the design and the low non(recurring engineering costs relative to an 0:3, design 4notwithstanding the generall+ higher unit cost5, offer advantages for man+ applications. .eat"re!: ;esides primitive logic elements and programmable routing, some .-/0 families add other features Gmbedded memor+ P Kan+ hardware applications need memor+ for data storage. Kan+ .-/0s include blocks of 90K for this purpose. Dedicated logic for carr+ generation, or other arithmetic functions -hase locked loops for clock s+nchroni<ation, division, multiplication.

Re!" t:*he output of Comparator has been studied successfull+.