Sequential Circuit Design: Part 1

Design of memory elements
Static latches Pseudo-static latches Dynamic latches

Timing parameters Two-phase clocking Clocked inverters

Krish Chakrabarty

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Sequential Logic
FFs

LO G I C

Ou t

tp , co m b

In

2 sto ra ge mechanisms positi ve fe edba ck charg e-b a sed
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Sequencing
Combinational logic
output depends on current inputs

Sequential logic
output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline

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Sequencing Cont.
If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: ber-optic cable
Light pulses (tokens) are sent down cable Next pulse sent before rst reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses

This is called wave pipelining in circuits In most circuits, dispersion is high

Delay fast tokens so they dont catch slow ones.
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Sequencing Overhead
Use ip-ops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay
Called sequencing overhead

Some people call this clocking overhead

But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence
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Sequencing Elements
Latch: Level sensitive
a.k.a. transparent latch, D latch

Flip-op: edge triggered

A.k.a. master-slave ip-op, D ip-op, D register

Timing Diagrams
Transparent Opaque Edge-trigger

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Flip-Flop: Timing Denitions

t

t s e t u p I n
DA T A

t h o l d

S TA B LE

t

O ut

t pF F
DA T A S TA B LE t

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Maximum Clock Frequency

FFs

LO G IC t p, c om b

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Latch Design
Pass Transistor Latch Pros
+ Tiny + Low clock load

Cons
Vt drop nonrestoring backdriving output noise sensitivity dynamic diffusion input
Krish Chakrabarty

Used in 1970s

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Latch Design
Transmission gate
+ No Vt drop - Requires inverted clock

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Latch Design
Inverting buffer
+ Restoring + No backdriving + Fixes either Output noise sensitivity Or diffusion input Inverted output

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Latch Design
Buffered input
+ Fixes diffusion input + Noninverting

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Latch Design
Buffered output
+ No backdriving

Widely used in standard cells

+ Very robust (most important) - Rather large - Rather slow (1.5 2 FO4 delays) - High clock loading
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Latch Design
Tristate feedback
+ Static Backdriving risk

Static latches are now essential

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Latch Design
Datapath latch
+ Smaller, faster - unbuffered input

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Design of Memory Elements

D C C C C Q Q

Positive edge-triggered D ip-op Why use inverters on outputs? Skew Problem : may be delayed with respect to (both may be 1 at the same time) This is what happens- D Eliminating/Reducing skew: in 1 C
Krish Chakrabarty

Q Q Transmission gate acts a buffer, should have same delay as inverter

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Latch design
D C C Q D C Q

Static D latch

Jamb latch

Weak inverter

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Latch Design
Variant of D latch
D C Q C

D

Q

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Flip-Flop Design
Flip-op is built as pair of back-to-back latches

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Enable
Enable: ignore clock when en = 0
Mux: increase latch D-Q delay Clock Gating: increase en setup time, skew

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Reset
Force output low when reset asserted Synchronous vs. asynchronous

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Set / Reset
Set forces output high when enabled Flip-op with asynchronous set and reset

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Dynamic Latches
So far, all latches have been static-store state when clock is stopped but power is maintained Dynamic latches reduce transistor count Eliminate feedback inverter and transmission gate Latch value stored on the capacitance of the input (gate capacitance)

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Dynamic Latch and Flip-Flop

D Dynamic D latch C C Q
Data stored as Charge on gate capacitance

Dynamic negative edge-triggered D ip-op

D

C

C

Q

Difcult to ensure reliable operation Similar to DRAM Refresh cycles are required

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Charge-Based Storage
D Q Q

N o n - ov e r la p p in g c lo c k s

Sc h e ma ti c d ia gr a m Pseudo- st at i c L at ch

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Master-Slave Flip-Flop
D
A B

Q

To reduce skew: generate complement of clock within the cell Extra inverter per cell

Ov erl a p p in g Cl o cks Ca n Ca u se Ra ce Co n d it i o n s Un d efi n ed Sig n a ls
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Two-Phase Clocking
Inverting a single clock can lead to skew problems Employ two non-overlapping clocks for master and slave sections of a ip-op Also, use two phases for alternating pipeline stages

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Two-Phase Clocking
1 2 1(t) . 2(t) = 0 1=1, 2 = 0 D 1=0, 2 = 1 D 1 2 Q Q
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D

C

C

Q

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2-phase non-overlapping clocks

1 Pseudo-static D ip-op D 2 Q

2

1

1 2 t
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Important: Non-overlap time t must be kept small

2-phase dynamic ip-op

1 D 2 Q

I n pu tSa m p le d 1 2 Ou tp u tE n a b le
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Use of p Leakers
1 D Flip-op based on nMOS pass gates Degraded voltage VDD-Vt 2 Q No need to route signals

1 D

2 Q pMOS leaker transistors provide full-restored logic levels

Problem: Increased delay (extra inverter)

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Clocked Inverters
Similar to tristate buffer = 1, acts as inverter = 0, output = Z i2 i3 Q

D D Q i1

D Latch

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Flip-op insensitive to clock overlap

VD D M2 V D D M 6

D

M4 M3 M1 CL 1

X

M 8

Q
M 7 M 5 C L 2

-section

-section C2MOS master-slave negative edge-triggered D ip-op

C2MOS flip-flop
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C2MOS avoids Race Conditions

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