CMOS: the most abundant devices on earth

At present, complementary MOS or CMOS has replaced NMOS at all level of integration, in both analog and digital applications. The basic reason of this replacement is that the power dissipation in CMOS logic circuits is much less than in NMOS circuits, which makes CMOS very attractive. Although the processing is more complicated for CMOS circuits than for NMOS circuits. However, the advantages of CMOS digital circuits over NMOS circuits justify their use.

CMOS properties
Full rail-to-rail swing high noise margins

Logic levels not dependent upon the relative device sizes transistors can be minimum size ratio less

Always a path to Vdd or GND in steady state low output impedance (output resistance in k range) large fan-out. Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors

16.3.1:p-Channel MOSFET Revisited

In p-channel enhancement device. A negative gate-tosource voltage must be applied to create the inversion layer, or channel region, of holes that, connect the source and drain regions. The threshold voltage VTP for p-channel enhancement load device is always negative and positive for depletion-mode PMOS.

Cross-section of p-channel enhancement mode MOSFET

The operation of the p-channel is same as the n-channel device , except that the hole is the charge carrier, rather than the electron, and the conventional current direction and voltage polarities are reversed.

Simplified cross section of a CMOS inverter

In the fabrication process, a separate p-well region is formed within the starting n-substrate. The n-channel MOSFET is fabricated in the p-well region and p-channel MOSFET is fabricated in the n-substrate.
VDD

CMOS Inverter: Steady State Response

VDD

VOL = 0 VOH = VDD

Rp Vout = 1 Rn Vout = 0

Vin = 0

Vin = V DD

Voltage Transfer Curve

CMOS Inverter Load Lines

PMOS Vin = 0V

2.5 2

X 10-4

NMOS Vin = 2.5V

Vin = 0.5V 1.5

Vin = 2.0V

IDn (A)

Vin = 1.0V 1

Vin = 1.5V Vin = 2.0V

Vin = 2V 0.5

Vin = 1.5V

Vin = 1V

Vin = 1.5V

Vin = 0.5V
Vin = 1.0V Vin = 0.5V

0 0.5 1 1.5 Vout (V) 2

Vin = 2.5V 0

2.5 Vin = 0V

0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V

DC analysis of the CMOS inverter

NMOS in sat PMOS in non sat NMOS off PMOS in non sat

NMOS in sat PMOS in sat

NMOS in non sat PMOS in sat

NMOS in nonsat PMOS off

The figure shows series combination of a CMOS inverter. To form the input, gate of the two MOSFET are connected. To form the output, the drains are connected together. Vo VI The transistor KN is also known as pull down 1 0 Device, it is pulling the output voltage down towards ground. 0 1 The transistor KP is known as the pull up device because it
is pulling the output voltage up towards VDD. This property speed up the operation considerably.

It is to be noted that the static power dissipation during both extreme cases (logic 1 or 0) is almost zero because iDp=iDn=0.

CMOS inverter in either high or low state (ideal case)

Ideally, the power dissipation of the CMOS inverter is zero. However, real CMOS inverter exhibits a very small power dissipation in the nanowatt range rather than in the milliwatt rang of NMOS inverter.

Different biasing conditions for a CMOS inverter.

Case I: when NMOS is biased in saturation region and PMOS is biased in nonsaturation region. The above condition can be achieved when NMOS just start to conduct (VI=VTN). Under this condition we can write, iDN=iDP KN[VGSN-VTN]2=KP[2(VGSP+VTP)VSDP-VSDP2)] In terms of input output voltage we can write, KN[VI-VTN]2=KP[2(VDD-VI+VTP)VDD-VO)-(VDD-VO)2]

Transition points for PMOS and NMOS

As we know transition point for the PMOS can be define as, VSDP(sat)=VSGP+VTP
Or

Biasing conditions for the CMOS inverter (cont.)

Case II: When both transistors are biased in the saturation region. iDN=iDP KN[VGSN-VTN]2=KP(VGSP+VTP)2 In terms of input output voltage we can write, KN[VI-VTN]2=KP(VDD-VI+VTP)2 The input voltage can be determine by simplifying above equation as,
VDD + VTP + VI = VIt = 1+ KN VTN KP

VOPt=VIPt-VTP VOPt=VIPt+|VTP|

Or

Similarly, the transition point for NMOS can be written as VDSN(sat)=VGSN-VTN or VoNt=VINT-VTN

Both are in Saturation region

KN KP

The above eq. can also be used to determine input voltage at the transition points.

CMOS inverter design consideration

The CMOS inverter usually design to have, (i)VTN =|VTP| (ii) Kn(W/L)=Kp (W/L) But Kn> Kp (because n>p) How equation (ii) can be satisfied? This can achieved if width of the PMOS is made two or three times than that of the NMOS device. This is very important in order to provide a symmetrical VTC, results in wide noise margin.

Symmetrical properties of the CMOS inverter