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Digital Design

Chapter 2: Combinational Logic Design


Slides to accompany the textbook Digital Design, with RTL Design, VHDL, and Verilog, 2nd Edition, by Frank Vahid, John Wiley and Sons Publishers, 2010. http://www.ddvahid.com

Copyright 2010 Frank Vahid


Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities, subject to keeping this copyright notice in place and unmodified. These slides may be posted as unanimated pdf versions on publicly-accessible course websites.. PowerPoint source (or pdf Digital 2e with animations) may Design not be posted to publicly-accessible websites, but may be posted for students on internal protected sites or distributed directly to students by other electronic means. Copyright 2010 1 Instructors may make printouts of the slides available to students for a reasonable photocopying charge, without incurring royalties. Any other use requires explicit permission. Instructors Frank Vahid may obtain PowerPoint source or obtain special use permissions from Wiley see http://www.ddvahid.com for information.

Converting to Boolean Equations


a

Q1. A fire sprinkler system should spray water if high heat is sensed and the system is set to enabled.
Answer: Let Boolean variable h represent high heat is sensed, e represent enabled, and F represent spraying water. Then an equation is: F = h AND e.

Q2. A car alarm should sound if the alarm is enabled, and either the car is shaken or the door is opened.
Answer: Let a represent alarm is enabled, s represent car is shaken, d represent door is opened, and F represent alarm sounds. Then an equation is: F = a AND (s OR d). (a) Alternatively, assuming that our door sensor d represents door is closed instead of open (meaning d=1 when the door is closed, 0 when open), we obtain the following equation: F = a AND (s OR NOT(d)).
Digital Design 2e Copyright 2010 Frank Vahid

NOT gate

1
x 0 1 F 1 0

1 0

1 x 0 1 F 0 time
Digital Design 2e Copyright 2010 Frank Vahid

0 (a)

0 (b)

When the input is 0

When the input is 1

OR gate
0 y x 0 1 0 y x F
1 x 0 1 y 0 1 F 0 time
Digital Design 2e Copyright 2010 Frank Vahid

x 0 0 1 1

y 0 1 0 1

F 0 1 1 1

0 0 0

1 1 y
a

0 F 0 y
a

1 (a)

1 (b)

When an input is 1

When both inputs are 0


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AND gate
x 0 0 1 1 y 0 1 0 1 F 0 0 0 1

0 1 1 F 1 x 0

0 1 F 0

y 1 x 1

y 1 x
a

1 x 0 1 y 0 1 F 0 time
Digital Design 2e Copyright 2010 Frank Vahid

0
a

1 (a)

1 (b)

When both inputs are 1

When an input is 0
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Building Circuits Using Gates

Recall Chapter 1 motion-in-dark example


Turn on lamp (F=1) when motion sensed (a=1) and no light (b=0) F = a AND NOT(b) Build using logic gates, AND and NOT, as shown We just built our first digital circuit!
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Digital Design 2e Copyright 2010 Frank Vahid

Example: Converting a Boolean Equation to a Circuit of Logic Gates


Start from the output, work back towards the inputs Q: Convert the following equation to logic gates: F = a AND NOT( b OR NOT(c) )

b c

a F

Digital Design 2e Copyright 2010 Frank Vahid

More examples
F = (a AND NOT(b)) OR (b AND NOT(c)) 2 1 3 a b F c

F = a AND (s OR d) 1 2 s

a F

d (a)
a a

(b)

Start from the output, work back towards the inputs


Digital Design 2e Copyright 2010 Frank Vahid

Using gates with more than 2 inputs


F = a AND b AND c a b c (a) F a b c (b) F

Can think of as AND(a,b,c)

Digital Design 2e Copyright 2010 Frank Vahid

Example: Seat Belt Warning Light System


Design circuit for warning light Sensors
s=1: seat belt fastened k=1: key inserted

w = NOT(s) AND k
BeltWarn k w

Capture Boolean equation


seat belt not fastened, and key inserted

Convert equation to circuit Timing diagram illustrates circuit behavior


We set inputs to any values Output set according to circuit
Inputs 1 k 0 1 s 0 Outputs 1 w 0

s Seatbelt

Digital Design 2e Copyright 2010 Frank Vahid

time

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Gates vs. switches


Notice
Boolean algebra enables easy capture as equation and conversion to circuit
How design with switches? Of course, logic gates are built from switches, but we think at level of logic gates, not switches
1 0 s w 0 k 1
Digital Design 2e Copyright 2010 Frank Vahid

w = NOT(s) AND k
BeltWarn k w

BeltWarn

s Seatbelt

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More examples: Seat belt warning light extensions


Only illuminate warning light if person is in the seat (p=1), and seat belt not fastened and key inserted w = p AND NOT(s) AND k
k Belt W a rn

w
a

Given t=1 for 5 seconds after key inserted. Turn on warning light when t=1 (to check that warning lights are working) w = (p AND NOT(s) AND k) OR t
Digital Design 2e Copyright 2010 Frank Vahid

k p

BeltWarn

w s t
a

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Some Gate-Based Circuit Drawing Conventions


no x y F yes

no

yes
a

ok
a

not ok

Digital Design 2e Copyright 2010 Frank Vahid

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Boolean Algebra

2.5

By defining logic gates based on Boolean algebra, we can use algebraic methods to manipulate circuits Notation: Writing a AND b, a OR b, NOT(a) is cumbersome
Use symbols: a * b (or just ab), a + b, and a
Original: w = (p AND NOT(s) AND k) OR t New: w = psk + t
Spoken as w equals p and s prime and k, or t Or just w equals p s prime k, or t s known as complement of s

While symbols come from regular algebra, dont say times or plus
"product" and "sum" are OK and commonly used
Boolean algebra precedence, highest precedence first. Symbol ()
Digital Design 2e Copyright 2010 Frank Vahid

Name

Description

Parentheses Evaluate expressions nested in parentheses first NOT AND OR Evaluate from left to right Evaluate from left to right Evaluate from left to right 14

* +

Boolean Algebra Operator Precedence


Evaluate the following Boolean equations, assuming a=1, b=1, c=0, d=1.
Q1. F = a * b + c.
Answer: * has precedence over +, so we evaluate the equation as F = (1 *1) + 0 = (1) + 0 = 1 + 0 = 1.

Q2. F = ab + c.
Answer: the problem is identical to the previous problem, using the shorthand notation for *.

Q3. F = ab.
Answer: we first evaluate b because NOT has precedence over AND, resulting in F = 1 * (1) = 1 * (0) = 1 * 0 = 0.
a

Q4. F = (ac).
Answer: we first evaluate what is inside the parentheses, then we NOT the result, yielding (1*0) = (0) = 0 = 1.

Q5. F = (a + b) * c + d.
Answer: Inside left parentheses: (1 + (1)) = (1 + (0)) = (1 + 0) = 1. Next, * has precedence over +, yielding (1 * 0) + 1 = (0) + 1. The NOT has precedence over the OR, giving (0) + (1) = (0) + (0) = 0 + 0 = 0. Boolean algebra precedence, highest precedence first. Symbol ()
Digital Design 2e Copyright 2010 Frank Vahid

Name

Description

Parentheses Evaluate expressions nested in parentheses first NOT AND OR Evaluate from left to right Evaluate from left to right Evaluate from left to right 15

* +

Boolean Algebra Terminology


Example equation: Variable F(a,b,c) = abc + abc + ab + c
Represents a value (0 or 1) Three variables: a, b, and c

Literal
Appearance of a variable, in true or complemented form Nine literals: a, b, c, a, b, c, a, b, and c

Product term
Product of literals Four product terms: abc, abc, ab, c

Sum-of-products
Equation written as OR of product terms only Above equation is in sum-of-products form. F = (a+b)c + d is not.
Digital Design 2e Copyright 2010 Frank Vahid

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Boolean Algebra Properties


Commutative
a+b=b+a a*b=b*a

Example uses of the properties


Show abc equivalent to cba.
Use commutative property:
a*b*c = a*c*b = c*a*b = c*b*a

Distributive
a * (b + c) = a * b + a * c
Can write as: a(b+c) = ab + ac

a + (b * c) = (a + b) * (a + c)
(This second one is tricky!) Can write as: a+(bc) = (ab)(ac)

Show abc + abc = ab.


Use first distributive property
abc + abc = ab(c+c).
a

Associative
(a + b) + c = a + (b + c) (a * b) * c = a * (b * c)

Complement property
Replace c+c by 1: ab(c+c) = ab(1).

Identity property
ab(1) = ab*1 = ab.

Identity
0+a=a+0=a 1*a=a*1=a

Show x + xz equivalent to x + z.
Second distributive property
Replace x+xz by (x+x)*(x+z).

Complement
a + a = 1 a * a = 0

Complement property
Replace (x+x) by 1,

To prove, just evaluate all possibilities


Digital Design 2e Copyright 2010 Frank Vahid

Identity property
replace 1*(x+z) by x+z. 17

Example that Applies Boolean Algebra Properties


Want automatic door opener circuit (e.g., for grocery store)
Output: f=1 opens door Inputs:
p=1: person detected h=1: switch forcing hold open c=1: key forcing closed

Can the circuit be simplified?


f = hc' + h'pc f = c'h + c'h'p f = c'(h + h'p) f = c'((h+h')*(h+p)) f = c'((1)*(h + p)) f = c'(h+p)
a

Want open door when


h=1 and c=0, or h=0 and p=1 and c=0

(by the commutative property) (by the first distrib. property) (2nd distrib. prop.; tricky one) (by the complement property) (by the identity property)

Equation: f = hc + hpc
h c p DoorOpener f
h p f DoorOpener c

Simplified circuit

Digital Design 2e Copyright 2010 Frank Vahid

Simplification of circuits is covered in Sec. 2.11 / Sec 6.2.

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Example that Applies Boolean Algebra Properties


Found inexpensive chip that computes:
f = chp + chp + chp
h c p DoorOpener f

Commutative
a+b=b+a a*b=b*a

Can we use it for the door opener?


Is it the same as f = hc + hpc?

Apply Boolean algebra:


f = chp + chp + chp f = ch(p + p) + chp (by the distributive property) f = ch(1) + chp f = ch + chp f = hc + hpc (by the complement property) (by the identity property)
a

Distributive
a * (b + c) = a * b + a * c a + (b * c) = (a + b) * (a + c) (a + b) + c = a + (b + c) (a * b) * c = a * (b * c) 0+a=a+0=a 1*a=a*1=a a + a = 1 a * a = 0
Digital Design 2e Copyright 2010 Frank Vahid

Associative

Identity

(by the commutative property)

Same! Yes, we can use it.

Complement

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Boolean Algebra: Additional Properties


Null elements
a+1=1 a*0=0

Idempotent Law
a+a=a a*a=a

Involution Law
(a) = a

DeMorgans Law
(a + b) = ab (ab) = a + b Very useful!

To prove, just evaluate all possibilities


Digital Design 2e Copyright 2010 Frank Vahid

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Example Applying DeMorgans Law


Aircraft lavatory sign example
Behavior

(a + b) = ab (ab) = a + b

Alternative: Instead of Three lavatories, each with sensor (a, lighting Available, b, c), equals 1 if door locked light Occupied Light Available sign (S) if any lavatory Opposite of available Available function Equation and circuit S = a + b + c S = a + b + c So S = (a + b + c) Transform
(abc) = a+b+c (by DeMorgans Law) S = (abc) S = (a) * (b) * (c) (by DeMorgans Law) S = a * b * c (by Involution Law)

Circuit a b c S

New circuit

Makes intuitive sense


Circuit a b c S

Occupied if all doors are locked

Digital Design 2e Copyright 2010 Frank Vahid

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Example Applying Properties


Commutative
a + b = b + a a * b = b * a

For door opener f = c'(h+p) , prove door stays closed (f=0) when c=1
f = c'(h+p) Let c = 1 (door forced closed) f = 1'(h+p) f = 0(h+p) f = 0h + 0p (by the distributive property) f=0+0 (by the null elements property) f=0

Distributive
a * (b + c) = a * b + a * c a + (b * c) = (a + b) * (a + c)

Associative
(a + b) + c = a + (b + c) (a * b) * c = a * (b * c)

Identity
0 + a = a + 0 = a 1 * a = a * 1 = a

Null elements
a + 1 = 1 a * 0 = 0

Complement
a + a = 1 a * a = 0

Idempotent Law
a + a = a a * a = a

Involution Law
(a) = a

DeMorgans Law
Digital Design 2e Copyright 2010 Frank Vahid

(a + b) = ab (ab) = a + b

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Complement of a Function
Commonly want to find complement (inverse) of function F
0 when F is 1; 1 when F is 0

Use DeMorgans Law repeatedly


Note: DeMorgans Law defined for more than two variables, e.g.:
(a + b + c)' = (abc)' (abc)' = (a' + b' + c')

Complement of f = w'xy + wx'y'z'


f ' = (w'xy + wx'y'z')' f ' = (w'xy)'(wx'y'z')' (by DeMorgans Law) f ' = (w+x'+y')(w'+x+y+z) (by DeMorgans Law)

Can then expand into sum-of-products form

Digital Design 2e Copyright 2010 Frank Vahid

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Representations of Boolean Functions


English 1: F outputs 1 when a is 0 and b is 0, or when a is 0 and b is 1. English 2: F outputs 1 when a is 0, regardless of bs value (a) a a b Equation 1: F(a,b) = ab + ab Equation 2: F(a,b) = a (b) Circuit 1 a Circuit 2 The function F F (c) F 0 0 1 1 b 0 1 0 1 F 1 1 0 0

2.6

Truth table (d)

A function can be represented in different ways


Above shows seven representations of the same functions F(a,b), using four different methods: English, Equation, Circuit, and Truth Table
Digital Design 2e Copyright 2010 Frank Vahid

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Truth Table Representation of Boolean Functions


Define value of F for each possible combination of input values
2-input function: 4 rows 3-input function: 8 rows 4-input function: 16 rows
a 0 0 1 1 b 0 1 0 1 (a) F a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 (b) a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 F
0 0 0 0 0 1 1 1

Q: Use truth table to define function F(a,b,c) that is 1 when abc is 5 or greater in binary

a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

c 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 (c)

d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Digital Design 2e Copyright 2010 Frank Vahid

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Converting among Representations


Can convert from any representation to another Common conversions
Equation to circuit (we did this earlier) Circuit to equation
Start at inputs, write expression of each gate output
1 Equations 4 3 Truth tables 2 Circuits 6 5

c h p

c' F = c'(h+p) h+p

Digital Design 2e Copyright 2010 Frank Vahid

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Converting among Representations


More common conversions
Truth table to equation (which we can then convert to circuit)
Easyjust OR each input term that should output 1

1 Equations 4 3 Truth tables 2 Circuits 6 5

Inputs a 0 0 1 1 b 0 1 0 1

Outputs F 1 1 0 0

Term F = sum of ab ab

Equation to truth table


Easyjust evaluate equation for each input combination (row) Creating intermediate columns helps

F = ab + ab

Q: Convert to equation
a 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 F
0 0 0 0 0 1 1 1

Q: Convert to truth table: F = ab + ab


Inputs
a

Output a' b' 1 0 0 0 a' b 0 1 0 0 F 1 1 0 0

Digital Design 2e Copyright 2010 Frank Vahid

a 0 0 1 1

b 0 1 0 1

abc abc abc

F = abc + abc + abc

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Example: Converting from Truth Table to Equation


Parity bit: Extra bit added to data, intended to enable detection of error (a bit changed unintentionally)
e.g., errors can occur on wires due to electrical interference

Even parity: Set parity bit so total number of 1s (data + parity) is even
e.g., if data is 001, parity bit is 1 0011 has even number of 1s

a 0 0 0 0 1 1 1 1

b 0 0 1 1 0 0 1 1

c 0 1 0 1 0 1 0 1

P 0 1 1 0 1 0 0 1

Want equation, but easiest to start from truth table for this example
Digital Design 2e Copyright 2010 Frank Vahid

Convert to eqn. P = a'b'c + a'bc' + ab'c' + abc

Example: Converting from Circuit to Truth Table


First convert to circuit to equation, then equation to table
a ab (ab)'

b
c

c'

(ab)'c'

Inputs a 0 0 0 0 1 b 0 0 1 1 0 c 0 1 0 1 0 ab 0 0 0 0 0 (ab)' 1 1 1 1 1 c' 1 0 1 0 1

Outputs F 1 0 1 0 1 0 0 0 29

1
Digital Design 2e Copyright 2010 Frank Vahid

0
1 1

1
0 1

0
1 1

1
0 0

0
1 0

1 1

Standard Representation: Truth Table


How can we determine if two functions are the same?
Recall automatic door example
Same as f = hc + hpc? Used algebraic methods But if we failed, does that prove not equal? No. f = chp + chp + ch f = ch(p + p) + chp f = ch(1) + chp f = ch + chp (what if we stopped here?) f = hc + hpc

Solution: Convert to truth tables


Only ONE truth table representation of a given function
Standard representationfor given function, only one version in standard form exists

Q: Determine if F=ab+a is same function as F=ab+ab+ab, by converting each to truth table first
F = ab + a' a 0 0 1 1 b 0 1 0 1 F 1 1 0 1 F = ab + ab + ab a 0 0 1 1 b 0 1 0 1 F 1 1 0 1
a

Digital Design 2e Copyright 2010 Frank Vahid

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Verilog Hardware Description Language


Verilog is a hardware description language (HDL) and not a programming language like C++ or Java. The function of HDL is to provide logic designers with a means of representing the structure and behavior of logic circuits. We will learn several representations of logic structure and behavior
truth table, state table, state diagram, schematic All of these examples are not real logic circuits they do however function well as a description that can be intrpreted and transformed into a logic circuit.

HDL is useless unless there exists an interpreter that can translate the language statements to real logic instances and wire configurations. Verilog can be used to describe how a simulator can be used to verify correct functionality.

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Testbenches
Testbench
Assigns values to a system's inputs, check that system outputs correct values A key use of HDLs is to simulate system to ensure design is correct

Testbench Set input values, check output values

Unit Under Test (UUT) SystemToTest

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Simulation and Testbenches A First Look


How does our new module behave? Simulation
User provides input values, simulator generates output values
Test vectors sequence of input values Waveform graphical depiction of sequence
1

AND/OR/NOT Gates

Timescale directive is for simulation. More later.


`timescale 1 ns/1 ns module And2(X, Y, F); input X, Y; output F; reg F; always @(X, Y) begin F <= X & Y; end

User provides test vectors Simulator generates output values based on HDL description

X Y 0 1 0 1 F 0 time

endmodule

Simulator
Verilog for Digital Design Copyright 2007 Frank Vahid and Roman Lysecky

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Simulation and Testbenches A First Look


Instead of drawing test vectors, user can describe them with HDL
1 X Y 0 1 0 time
... Y_s #10 #10 #10 ... `timescale 1 ns/1 ns <= 0; X_s Y_s <= 0; Y_s <= 1; Y_s <= 1; <= 0; X_s <= 1; X_s <= 0; X_s <= 1; module And2(X, Y, F); input X, Y; output F; reg F; always @(X, Y) begin F <= X & Y; end endmodule

AND/OR/NOT Gates

10 20 30 (ns)
1 F 0

"#10" Tells simulator to keep present values for 10 ns, before executing the next statement
Verilog for Digital Design Copyright 2007 Frank Vahid and Roman Lysecky

Simulator
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Simulation and Testbenches


Idea: Create new "Testbench" module that provides test vectors to component's inputs
`timescale 1 ns/1 ns

AND/OR/NOT Gates

Testbench procedure X_s Y_s X Y CompToTest


(And2)

module Testbench();

F_s

reg X_s, Y_s; wire F_s; And2 CompToTest(X_s, Y_s, F_s); initial begin // Test all possible input combinations Y_s = 0; X_s = 0; #10 Y_s = 0; X_s = 1; #10 Y_s = 1; X_s = 0; #10 Y_s <= 1; X_s = 1; end endmodule

HDL testbench
Module with no ports Declare reg variable for each input port, wire for each output port Instantiate module, map variables to ports (more in next section) Set variable values at desired times
Verilog for Digital Design Copyright 2007 Frank Vahid and Roman Lysecky

More information on next slides

Note: CompToTest short for Component To Test


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Testbench: Lab 1
`timescale

1ns / 1ps module detector_detector_sch_tb(); // Inputs reg A; reg B; // Output wire F; // Bidirs // Instantiate the UUT detector UUT ( .A(A), .B(B), .F(F) ); // Initialize Inputs initial begin #100; A = 0; B = 0; #100 B = 1; #100 A = 1; #100 B = 0; #100 A = 1; B = 1; end; endmodule

Automatically generated by Xilinx

Delay 100 time units

Designer writes this

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Xilinx Simulation Display

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Homework
Chapter 2: 11,18, 21, 26 Due: January 27

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