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A Comparison of CMOS Circuit Techniques: Differential Cascode Voltage Switch Logic Versus Conventional Logic

KAN M. CHU

AND

DAVID

L. PULFREY,

MEMBER, IEEE

Abstract

Differential

caseode voltage switch (DCVS) advantages delay, layout out density, comparison

logic is a CMOS

Vdd

circuit logic

technique flexibility.

NAND/

aud and the logic of

..1... .. .. ....

LOAO .. . . . . . . . . . . . . . . . . . . . . 0 II

conventional performance Specifically, and two dyuamic DCVS pared gation appears are logic is carried

power dissipation,

In this paper a detailed of fnfl adders designed comparisons implementations between of both two NORA

by simulation,

xl--i

11 .. ... .1 . . . . . . . . . . . 1. . .

..l

[

CMOS

and, in the

:; SIGNALS xn~ x+--j

Dcvs WEE

FOR

uNcTION Q x) ~

gate capacitance,

of transistors to input

delay time, and average power dissipation. to be superior to frill CMOS in regards

In the static case, DCVS capacitance The speeds of the can be faster of

JG

Fig. 1, Block diagram of a DCVS circuit. The load circuitry nected to nodes Q and Q. is con-

device count but inferior two technologies increased than more conventiottaf device count

are similar.

case, DCVS

L INTRODUCTION

the worst-case

power DCVS [2]. A

is computed

at the maximum

frequency

D

circuit tion, age

INFERENTIAL is a recently

techniques layout of both of area,

in terms and logic and circuits

logic which

of each circuit.

CMOS

of circuit flexibility

circuit

clelay, [1]. faults fact

is claimed

to have advantages

over traditional

NAND/NOR dissipaalso has coverfurther can be based [3]. to make To logic fullto

II.

CIRCUIT

TECHNIQUES

FOR DCVS

LOGIC

property

which

dynamic is the

The basic DCVS circuit comprises two parts: a binary decision tree and a load (see Fig. 1). The tree is specified such that: 1) when vector the input of the vector switching x = (xl, c . . . x.) function Q(x), node is the true then G and the the

designed

maps

(K-maps)

features

DCVS

promising

CMOS we have

output Q is disconnected from node Q is connected to G; and 2) when X =(X1,..., then the reverse holds.

investigate and adder this here building uses parameters sipation. needed more purpose circuit

possibility, as a test

of Q(x),

adder

block

in digital

assess speed,

There are two trees required to implement a full adder, one to perform the sum and one to perform the carry function (see Fig. 2). These circuits, which were designed using the K-map procedure described in [3], are used as the tree circuits for all the DCVS circuit forms examined in this paper. The various DCVS forms differ in their load circuitry, as is now described. The load for a static DCVS circuit is the simple latch

dis-

is represented

of transistors is quantified

to implement

Manuscript received August 29, 1986,; revised January 26, 1987. This work was supported by the Natural Sciences and Engineering Research Council of Canada. The authors are with the Electrical Engineering Department, University of British Columbia, Vancouver, B.C. V6T 1W5, Canada. IEEE Log Number 8714872.

shown in Fig. 3. Depending on the differential inputs, either node Q or Q is pulled down by the DCVS tree network. Regenerative action sets the PMOS latch to static outputs Q and Q of V~~ and ground 01987 IEEE or vice versa. The

0018-9200/87/0800-0528$01.00

529

Ci ?

co

T1 f

12 f VREF

T3

T4

*

+: .: .: &i

Q Q . . . .. . .. . . . . . .. .. Dcvs TREE ! j

...1

......... ..... ]G

The DCVS trees for a full adder. (a) The circui~ providing the S(A, B, C) = A + B + C. (b) The circuit yielding the carry,

9

1

11

.. . . . . . . . . . ... . . . . . ..

1-l

i

--------l-i---~ +7 Gnd

Fig. 5.

The load

and circuit

arrangement circuit.

for

a DCVS

DOMINO

Fig. 3.

4 logic sets. A variation of this static DCVS circuit is the differential split-level (DSL) logic circuit n-transistors T3 and T4 with reference at nodes Q and pulled level. current voltage Q and Q. If Q down are clamped from from [4] shown in Fig. 4. Two their gates connected to a + ~k, where node Q is

Fig. 6.

current

after

the latch

V~~~ are added to reduce the logic swing V~~~ is set to v~~/2 at V~~/2. its low-current Suppose voltage of the n device, then the nodes

~k is the threshold

+

The load and circuit arrangement for a DCVS NOM section. pipelined

T1 switches

because T4 is initially

The voltage

ON. Node

logical

functions.

In its original

form

the NORA

mode. times

Q is raised up to 2.5 V until T3 is in the cutoff DSL circuits would be expected to be about two than standard DCVS circuits on account of

gates to enhance logic cause long delay times logic in the NORA

faster

and consume

the need for logic swings of only half the rail-to-rail voltage difference. This should result in a reduction by two times of circuit. Turning consider Nodes charge the charges needed to be manipulated operation of DCVS during in the

technique will eliminate p-logic gates because of the inherent availability of complementary signals. The general structure of a DCVS NORA pipelined section consisting of only one dynamic gate is shown in Fig. 6. This type of circuit logic technique design, is suitable the for use in a heavily example, [8]. of pipelined a newly as in case, for multiplier

now first

to dynamic

the DOMINO

of Fig. 5 [1].

Q and

Q are precharged

developed

8 X 8 pipelined

Q (node

(f) discharges to low during the evaluation phase (~ = 1). Transistor T1 (or T2) is a high impedance p transistor which serves as the feedback device to maintain the high logic level at node Q (or Q), where charges may be lost due to charge sharing [6]. For dynamic operation NORA (NO RACE) of pipelined architectures, for imple-

As Fig. 6 indicates, the load circuitry is symmetrical, and thus, for analysis purposes, only one side of it need be considered. During the evaluation phase (-~ = 1), node Q is either floating or discharged depending on the inputs. The output register acts as a clocked high or low. inverter, and tlhe output phase can be either During the precharge

techniques

(0= O), the ground path of the register is blocked. If the output resulting from the previous evaluation is high, then

530

+

c

-+

B+

c+ *

A<D

c 8+ A+ ~B

Fig. 7.

j+

&

A+

i-a

Fig. 8.

CASRY IY.JT

CARRYW

+4$

j+ 113

TIo

I h-t

7i6

w + ,,7

c+ /+

transistor

is ON, then

continues to be low because no charges can be added through T2. Thus for a @ section of a pipeline, the output changes freely when @ is high and is latched at the falling edge of +. HI.

CONVENTIONAL CMOS CIRCUIT TECHNIQUES

l-+$ 1

111 4 115 118 112

To provide

of the DCVS

circuits

described in Section II, conventional CMOS ating under static and dynamic conditions considered. The circuit used here for a static CMOS shown generate in Fig. 7. Two subcircuits the sum signal and one to generate

EXCLUSIVE-OR

designs operneed to be

*

full adder is

Fig. 9. Circuit for a modified NORA full adder (from [9]).

are identified,

one to cuits simulated ent load laid with DCVS circuits generated were those shown in Figs. 79. Four differtwo static and two dynamic, circuits were were the full-adder tree of Fig. 2 to the

stack level

circuits,

by connecting

adder. This circuit is relatively fast compared to other possible static full CMOS implementations because the complemented outputs are obtained through only one gate delay from the complementary inputs. Two versions of conventional approaches to dynamic CMOS NORA Fig. full-adder design were studied. One, a conventional adder with serial n- and p-logic blocks, is shown in circuit, a modified NORA adder [9], is a special three-way XOR gate to

out on a Metheus X700 workstation in accordance design rules for the single-metal 3-pm CMOS process

of Northern Telecom, Ottawa, Canada [10]. The areas occupied by the DCVS circuits were about 2.2x 10-4 and 3.5 x 104 cmz for the static and dynamic versions, respectively. matics loading transistors The results of SPICE simulations from the scheof all the circuits are summarized in Table I. gate capacitance of fixed length gives a measure of the input is, for the case of widths. A general of the circuit. This parameter and their

8. The other

COMPARISON

The input

OF THE FULL

ADDERS

by the number

of transistors

To compare the performance of the various forms of full adders, each of the circuits described in Sections II and III was simulated using SPICE. The conventional CMOS cir-

guideline used in the first iteration of a design was to size the transistors in a tree network such that the equivalent conductance of any single discharging path was the same as the conductance of a minimum-size (W= 3 pm in our

531

TABLE I

COMPARISON OF SIMULATION RESULTS FOR DIFFERENT TYPES OF FULL ADDERS Iw

cMuI1

value. static

between power

the

dissipa-

gate capaci-

Mm

WACIIAKE (if)

~,

#ffnWrm

~~

lECiNY&S

CVACITMCE (fF)

!xLA;~ME

KlwLmn

PwER-m-hv WBXWT

tance of the static DCVS circuit. The number of devices is less because the DCVS implementation uses only p-channel transistors, vices, input typically CMOS channel n-channel conventional as opposed to both p- and n-channel deas pull-ups in the load and buffer circuitry. The gate capacitance loading in the DCVS circuit is a factor circuits devices of 2 or 3 times smaller which require to be driven, circuit CMOS than conventional complementary since the inputs

155 05 65

155 85 85

20 22 14

0.58

1.11 1.35

1.00

2.$1 1.63

tree devices. DCVS static consumes more power than the circuit because the charging tree

The static

case) n transistor. connected that right path For example, requires transistors to be 12 pm ( =4x 3 pm)

175 I 1361 on

four serially in the of contained Consider wide.

times of nodes Q and Q in Fig. 3 depend and turn-off paths within the DCVS An asymmetry at nodes Q and flow through the the power

a path with

and these are, generally, not symmetrical. in the rise and fall times of the potential Q will latch prolong the period of current dtu-ing the transient

each transistor

dissipation, The apparent attractiveness of the static DSL circuit in regards to speed is negated somewhat by three possible problems which may arise when using this technique. For example, with reference to Fig. 4, if node Q is at 2.5 V, on node ~. this and rethen T2 is partially Although problem, reducing ON and it is possible to destroy the low otherwise have appeared drive the size of the p device alleviates capability should Thus a trade-off

transistors (or stack level) contained in path ABC is three implies that each transistor in this path should be 9 pm wide. If the width of transistor C is 9 pm, then the width of B in path BC can be estimated as 4.5 pm. Similar principles can be applied to the sizing of transistors in the charging form , usually or discharging small, paths in other circuits. The final of a design was arrived at by making adjustments, on the basis by SPICE I refer to

of the transistors

of minimizing

sults in longer

be consid-

situations where the input signals are such that the circuit operation is likely to be slowest. For example, in the conventional NORA circuit of Fig. 8, the speed performance this will be poorest when A = B = HI phase H, via and C = LO, In (@= 1), node transistor F case, during through the evaluation which node

ered when the sizes of T1 and T2 are chosen. Another problem is due to the body effect existing in T3 and T4. Although the threshold voltage V,h is equal to 0.8 V in the Northern Telecom 3-pm CMOS process [10], SPIICE simulations show that it is necessary to set V~~~ equal to 4.2 V in order Also to clamp either of the nodes Q or Q to 2.5 V. V~E~. The third problem is the clamped logic swing is sensitive to the stack level static power dissipation. There is a

connected to the output stage to render the sum signal LO. Power dissipation was computed using the procedure described by Kang [11]. The figures quoted in Table I refer dissipation at the maximum frequency of to average power

through transistors T1 and T2 and T4 when Q is low. circuits, all the designs

to the dynamic

operation of each circuit, i.e., as determined by the worstcase delay times. The power-delay product, normalized to the static full CMOS case, is also shown in Table I. The output load capacitances used in the simulations are meant buffered to represent and would typical load conditions. A fan-out of are two was used for the dynamic loads than the static gates. designs as these circuits

have a similar power-delay product. The DCVS circuits appear to have a speed advantage, but this is achieved at the expense of an increased device count. The conventional NORA circuit, Fig. 8, is characterized by a large input gate capacitance block, delay and due to the half wide transistors in the p-logic by p and a slow speed due to the use of two levels of gate because of the logic is performed Considerable improvement in these two areas by the modified NORA adder of Fig. 9. This

be expected

transistors. is achieved

DISCUSSION

circuit has two times smaller input gate capacitance and is nearly twice as fast as the serial NORA adder. The disadvantage of this circuit is that accidental discharge due to faster circuit one-half than do of the races is possible under certain conditions. For example, if A = O, B =1, and C =1, the gate of T14 (or source of T15) and the gate of T15 (or source of T14) are pulled the drain down. If nodes of T7 and TIO do not pull down at similar

the static designs, it appears that, the This is to be expected due to the which are only

532

rates so that a voltage difference is developed drain ing paths tion nodeof careful load paths requires capacitive through T13 discharges

[2]

IU3FERENCES

G. Heller, W. R. Griffin, J. W. Davis,, and N. G. Thcsma, Cascode voltage switch logic: A differential CMOS logic family; in TSSCC Dig. Tech. Papers, 1984, pp. 1617. R. K. Montoye, Testing scheme for differential cascode voltage switch circuits, IBM Tech. Disc. Bull., vol. 27, pp. 6148-6152, 1985. K. M. Chu and D. L. Pulfrey, Design procedures for differential IEEE J. Solid-State Circuits, vol. cascode voltage switch circuits, SC-21, pp. 1082-1087, Dec. 1986. L. C. Pfennings, W. G. J. Mel, J. J. J. Bastiaens, and J. Ivf. F. Van Dijk, Differential split-level CMOS logic for subnanosecond Dig. Tech. Papers, 1985, pp. 212-213; afso speeds, in ISSCC IEEE J. Solid-State Circuits, vol. SC-20, pp. 1050-1055, Ott 1985. R. H. Krambeck. C. M. Lee. and H. Law. Hi~h-s~eed comr)act circuits with CMOS, IEEE J. Solid-State Circui~s, ;o1. SC-17; pp. 614-619, June 1982. L. G. Heller, Stabilizing cascode voltage switch logic, IBM Tech. Disc. Bull., vol. 27, p. 6015, 1985. N. F. Goncalves and H. J. De Man, NO~: A racefree dynamic CMOS techuique for pipelined logic structure, IEEE J. Solid-State Circuits, vol. SC-18, pp. 261-266? June 1983. L.

across the gate nodes of T14 and accidentally. sizing of the transistors the conductance with process control extraction associated Tight each

To avoid and

[4] [3]

so that

is equal.

circuit NORA

and delay time than the conventional the area consumed buffer the symmetrical circuits

[5]

[6] [7] [8] [9]

complementary outputs. The DCVS NORA circuit is as fast as the modified NORA adder, but only at the expense of a higher device count and increased input gate capacitance. However, the DCVS version of NORA is superior to the modified conventional version, in terms of circuit flexibility, due to its provision of complementary outputs, and reliability, occur. due to the fact The DCVS NORA that accidental (Fig. discharge 5) adder kind is cannot similar evaluated adder without DOMINO

K. M. Chu, Cascode voltage switch logic circuits; M. A. SC.thesis, Univ. of British Columbia, Vancouver, Canada, 1986. A. H. C. Park, CMOS LSI design of a high-throughput digitaf filter. M. SC. thesis. Mass. Inst. of Technol., Cambridge, ch. 4, -.

1984: G. Puukila, Canadian Microelectronics Corporation guide for designers using the Northern Telecom CM0S3 Process; Canadian Microelectronics Corp., Kingston, Ont., Rep. IC 85-6, 1985. S. M. Kang, Accurate simulation of power dissipation in VLSI circuits, IEEE J. Solid-State Circuits, vol. SC-21, pp. 889-891,

[10]

[11]

can be included

Oct. 1986

Kan M. Chu was born in Hong Kong on May 16, 1962. He received the B.Eng. (Honors E. E.) degree from McGill University, Montreaf, Canada, in 1984 and the M. A. SC. (E. E.) degree from the University of British Columbia, Vancouver, B. C., Canada, in 1986. He plans to work towards a Ph.D. degree in electrical engineering. His research interests are in CMOS-integrated circuit design and semiconductor device modeling.

for realizing

with conventional

forms of CMOS

is often gained

circuit area and active power consumption. The fastest static logic technique investigated

differential split-level (IXW) version of DCVS logic. The worst-case delay time for this implementation was 14 ns, while that of a conventional CMOS circuit was 20 ns. However, DSL may have some problems in terms of static power dissipation, security of charge storage, and sensitivity of the logic swing to the number of input signals. In dynamic operation, appear DCVS versions of NORA and faster DOMINO circuits to be a few nanoseconds

David L. Pulfrey (IvP73) is a Professor in the Electrical Engineering Department at the University of British cohrmbia, Vancouver, B. C., Canada. His research interests are in the fields of semiconductor device physics and integrated-circuit design. He has worked on the topics of electrical breakdown in thin dielectrics, the preparation and properties of plasma-anodized thinoxide films, and the analysis and fabrication of solar cell structures suited to large-area terrestrial applications. His present work at the University of British Columbia is in the areas of high-gain polysilicon emitter transistors, the characterization and applications of MIS tunnel junctions, and the algorithmic generation of IC marcocells,

(9-10 versus 10-18) titan their conventional counterparts. Further, DCVS logic may overcome the problem of accidental discharge, which appears to be a concern with one of the conventional NORA techniques evaluated in this study.

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