Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

SNS COLLEGE OF TECHNOLOGY COIMBATORE 641 035

Departme t !" Me#$atr! %#& E '% eer% '

ME3315 - Microcontroller & Programmable Logic Controller Laboratory

LABORATORY MAN(AL
)CYCLE 1*

+repare, -. R/S%0a-a1a2r%&$ a A&&%&ta t +r!"e&&!r Dept/ !" Me#$atr! %#&

-1
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

LABORATORY
OB3ECTI4E To expose the students the operation of Microcontroller and PLC and gives them hands on experience/ LIST OF E5+ERIMENT 1. Study of Microcontroller its. !. "#$1 % "#&1 Programming 'xercises. &. Stepper Motor interface. (. ).C. motor controller interface. $. Study of interrupt structure of "#$1. *. Linear actuation of hydraulic cylinder +ith counter and speed control. ,. -ydraulic rotation +ith timer and speed control. ". Se.uential operation of pneumatic cylinders. /. Traffic light controller. 1#. Speed control of )C motor using PLC. 11. Testing of 0elays using PLC.

-!
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

S/N!

Date

Name !" t$e e6per%me t

Mar2&

S%' at7re

8051 ARCHITECT(RE DIAGRAM -&

Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

E5 N!9 1 -(
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

Date 9

ST(DY OF MICROCONTROLLER 8051 :ITS AIM

To study a1out the 1asic concepts of Microcontroller "#$1 and its functionalities.

INTROD(CTION
2n 1/"13 2ntel Corporation introduced an "-1it micro controller called the "#$1. This micro controller had 1!"1ytes of 04M3 (5 1ytes of on-clip 06M3 to+ timers3 one serial port and four ports all on a single chip. 4t that time it +as also referred to as a system on a chip. The "#$1 is an "-1it processor3 meaning that the CP7 can +or5 on only "-1it of data at a time.
8'4T70'S 06M 04M T2M'0 2%6 Pins S'024L P60T 2nterrupt service 974:T2T; (5 1ytes 1!" 1ytes ! &! 1 *

The most +idely used registers at the "#$1 are 43 <3 0#3 013 0!3 0&3 0(3 0$3 0*30,3 0"3 )PT0 =data pointer> and PC =Program Counter>. 4ll of the a1ove system registers and "-digit except )PT0 and the program counter. The accumulator 43 is used for an arithmetic and logic instructions. To3 understand the use of these registers? +e +ill use them in various simple instructions.

+IN DESTR(CTION OF THE 8051

4lthough3 "#$1 family mem1ers come in different pac5ages such as )2P =)ual imines Pac5age>3 98P =9uad flat pac5age> and LLC3 they all have (# pins that are dedicated for various functions such that 2%63 30)@03 address3 data and interrupts. 'xamination figure3 +e note that of the (#pins3 a total of &! pins are set aside for the four ports. P#3 P13 P! and P& are the four ports availa1le in "#$1. 'ach port ta5es " pins. The rest of the pins are designated as CLC3 A:)3 BT4L13 BT4L!3 0ST3 '43 PS':3 of these " pins. Six of them are used 1y all mem1ers of the "#$1 and "#&1 8amily.

F(NCTION OF EACH +IN

Pins 1-"C Port 1 'ach of these pins can 1e configured as an input or an output. Pin /C 0S a logic one on this pin disa1les the microcontroller and clears the contents of most registers. 2n other +ords3 the positive voltage on this pin resets the
-$
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

microcontroller. <y applying logic Dero to this pin3 the program starts execution from the 1eginning. Pins1#-1,C Port & Similar to port 13 each of these pins can serve as general input or output. <esides3 all of them have alternative functionsC Pin 1#C 0B) Serial asynchronous communication input or Serial synchronous communication output. Pin 11C TB) Serial asynchronous communication output or Serial synchronous communication cloc5 output. Pin 1!C 2:T# 2nterrupt # input. Pin 1&C 2:T1 2nterrupt 1 input. Pin 1(C T# Counter # cloc5 input. Pin 1$C T1 Counter 1 cloc5 input. Pin 1*C @0 @rite to external =additional> 04M. Pin 1,C 0) 0ead from external 04M. Pin 1"3 1/C B! E B1 2nternal oscillator input and output. 4 .uartD crystal +hich specifies operating fre.uency is usually connected to these pins. 2nstead of it3 miniature ceramics resonators can also 1e used for fre.uency sta1ility. Later versions of microcontrollers operate at a fre.uency of # -D up to over $# -D. Pin !#C A:) Around. Pin !1-!"C Port ! 2f there is no intention to use external memory then these port pins are configured as general inputs%outputs. 2n case external memory is used3 the higher address 1yte3 i.e. addresses 4"-41$ +ill appear on this port. Pin !/C PS': if external 06M is used for storing program then a logic Dero =#> appears on it every time the microcontroller reads a 1yte from memory. Pin &#C 4L' Prior to reading from external memory3 the microcontroller puts the lo+er address 1yte =4#-4,> on P# and activates the 4L' output. 4fter receiving signal from the 4L' pin3 the external register =usually ,(-CT&,& or ,(-CT&,$ add-on chip> memoriDes the state of P# and uses it as a memory chip address. 2mmediately after that3 the 4L7 pin is returned its previous logic state and P# is no+ used as a )ata <us. Pin &1C '4 <y applying logic Dero to this pin3 P! and P& are used for data and address transmission +ith no regard to +hether there is internal memory or not. 2t means that even there is a program +ritten to the microcontroller3 it +ill not 1e executed. 2nstead3 the program +ritten to external 06M +ill 1e executed. <y applying logic one to the '4 pin3 the microcontroller +ill use 1oth memories3 first internal then external =if exists>. Pin &!-&/C Port # Similar to P!3 if external memory is not used3 these pins can 1e used as general inputs%outputs. 6ther+ise3 P# is configured as address output =4#4,> +hen the 4L' pin is driven high =1> or as data output =)ata <us> +hen the 4L' pin is driven lo+ =#>. Pin (#C FCC G$F po+er supply.

-*
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

MEMORIES
The "#$1 has t+o types of memory and these are Program Memory and )ata Memory. Program Memory =06M> is used to permanently save the program 1eing executed3 +hile )ata Memory =04M> is used for temporarily storing data and intermediate results created and used during the operation of the microcontroller. )epending on the model in use =+e are still tal5ing a1out the "#$1 microcontroller family in general> at most a fe+ 1 of 06M and 1!" or !$* 1ytes of 04M is used

E5TERNAL INTERR(+TS INTO AND INT 1

There are only t+o external hard+are interrupts in the "#$1. 2:T6 and 2:T1. They are located on pins p&.! and p&.& of port &3 respectively. The interrupt vector ta1le locations ###&- and ##1&- are set aside for 2:T6 and 2:T1.

+ROGRAMMING 8051 TIMERS a/ T%mer 0 re'%&ter&9

The 1*-1it register of timer # is accused as lo+ 1yte and high 1yte. The lo+ 1yte register called TL# and the high 1yte register is as T-#.

-/ T%mer 1 re'%&ter&9
Timer 1 is also 1* 1its and its 1*1it register in split into ! 1ytes referred to as TL1 and T-13 these register are accessi1le in the same +ay as the register of timer #.

RES(LT

-,
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

FLO;CHART
8<B%t A,,%t%!

ST40T

CL'40 C400; 8L4A

A'T )4T41 2: 4CC

4)) )4T4! @2T- 4CC

2S C400 ; :6T S'T

YES

NO
2:C0'M':T C400; C67:T'0

A'T 4))0'SS1 2: )PT0

ST60' 4CC7M7L4T60 2: 4))0'SS1

A'T 4))0'SS! 2: )PT0

ST60' C400; 2: 4))0'SS!

ST6P -"
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

E5 N!9 =/a Date 9

8051>8031 +r!'ramm% ' E6er#%&e& 8 BIT ARITHMETIC O+ERATIONS )ADDITION>S(BTRACTION* (SING 8051
AIM
To +rite the assem1ly language programs for performing the follo+ing arithmetic operationsC a> " 1it 1inary addition. 1> " 1it 1inary su1traction.

A++ARAT(S RE?(IRED
"#$1 Microcontroller 5it ey1oard
Po+er Chord

ALGORITHM
8<B%t A,,%t%!

1. !. &. (. $. *. ,. ". 1. !. &. (. $. *. ,. ".

Start 2nitialiDe carry register to Dero. Store data 1 in accumulator. 4dd the data ! to that of the accumulator. 2f a carry is generated3 increment the carry counter. Store the contents of the 4ccumulator3 +hich is the sum in memory. Move the carry register contents to 4ccumulator and store the same in emory. Stop. Start 2nitialiDe <arro+ register to Dero. Store data 1 in accumulator. Su1tract the data ! to that of the accumulator. 2f a 1orro+ is generated3 increment the 1orro+ counter. Store the contents of the 4ccumulator3 +hich is the sum in memory. Move the 1orro+ register contents to 4ccumulator and store the same in memory. Stop.

8 B%t S7-tra#t%!

-/
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

8 B%t S7-tra#t%!

ST40T

CL'40 <6006@ 8L4A

A'T )4T41 2: 4CC

S7< )4T4! @2T- 4CC

2S <6006 @ :6T S'T

YES

NO
2:C0'M':T <6006@ C67:T'0

A'T 4))0'SS1 2: )PT0

ST60' 4CC7M7L4T60 2: 4))0'SS1

A'T 4))0'SS! 2: )PT0

ST60' <6006@ 2: 4))0'SS!

ST6P - 1#
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

+ROGRAM 8<B%t A,,%t%!

+C a,,re&& (1## (1#1 (1#& (1#$ (1#* (1#/ (1#4 (1#) (1#' (1#8 (11# (111
8 B%t S7-tra#t%!

Op#!,e

La-e1

M em! %#& CL0 C M6F 0#3H##M6F 43H)4T41 4)) 43H)4T4 ! I:C L66P1 =(1#/> 2:C 0# M6F )PT03H(!##M6FB J)PT034 2:C )PT0 M6F 43 0# M6FB J)PT034 SIMP -'0' =(111> M em! %#& CL0 C M6F 0#3H##M6F 43H)4T41 S7<< 43H)4T4 ! I:C L66P1 =(1#/> 2:C 0# M6F )PT03H(!##M6FB J)PT034 2:C )PT0 M6F 43 0# M6FB J)PT034 SIMP -'0' =(1!#>

L66P 1

-'0' Op#!,e La-e1

+C a,,re&& (1## (1#1 (1#& (1#$ (1#* (1#/ (1#4 (1#) (1#' (1#8 (11# (111

L66P1

-'0'

RES(LT

- 11
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

FLO;CHART
ST40T

A'T )4T41 2: 4CC

A'T )4T4! 2: < 0'A2ST'0

M7LT2L; )4T41 @2T- )4T4!

A'T 4))0'SS1 2: )PT0

ST60' 4CC7M7L4T60 2: 4))0'SS1

A'T 4))0'SS! 2: )PT0

ST60' < 0'A2ST'0 2: 4))0'SS!

ST6P

- 1!
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

E5 N!9 =/Date 9

8051>8031 +r!'ramm% ' E6er#%&e& 8 BIT ARITHMETIC O+ERATIONS )M(LTI+LICATIO>DI4ISION*

AIM
To +rite the assem1ly language programs for performing the follo+ing arithmetic operationsC a> " 1it 1inary multiplication. 1> " 1it 1inary division.

A++ARAT(S RE?(IRED
"#$1 Microcontroller 5it ey1oard
Po+er Chord

ALGORITHM
8 BIT M(LTI+LICATION

1. !. &. (. $. *. ,.

Start. Store data 1 in register 4ccumulator. Store data ! in register <. Load the data pointer +ith external memory address Multiply 4 and < register Move the 4 and < register contents to the memory Stop.

8 BIT DI4ISION

1. !. &. (. $. *. ,.

Start. Store data 1 in register 4ccumulator. Store data ! in register <. Load the data pointer +ith external memory address )ivide 4 and < register Move the 4 and < register contents to the memory Stop.

- 1&
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

FLO;CHART
ST40T

A'T )4T41 2: 4CC

A'T )4T4! 2: < 0'A2ST'0

M7LT2L; )4T41 @2T- )4T4!

A'T 4))0'SS1 2: )PT0

ST60' 4CC7M7L4T60 2: 4))0'SS1

A'T 4))0'SS! 2: )PT0

ST60' < 0'A2ST'0 2: 4))0'SS!

ST6P

- 1(
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

+ROGRAM 8<B%t M71t%p1%#at%!

+C a,,re&& (1## (1#! (1#( (1#$ (1#" (1#/ (1#4 (1#< (1#C
8 B%t D%0%&%!

Op#!,e

La-e1

-'0'

M em! %#& M6F 43H)4T41 M6F <3H)4T4 ! M7L 4< M6F )PT03H(!##M6FB J)PT034 2:C )PT0 M6F 43< M6FB J)PT034 SIMP -'0' =(1#C>

+C a,,re&& (1## (1#! (1#( (1#$ (1#" (1#/ (1#4 (1#< (1#C

Op#!,e

La-e1

-'0'

M em! %#& M6F 43H)4T41 M6F <3H)4T4 ! )2F 4< M6F )PT03H(!##M6FB J)PT034 2:C )PT0 M6F 43< M6FB J)PT034 SIMP -'0' =(1#C>

RES(LT

- 1$
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

FLO; CHART

- 1*
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

E5 N!9 =/# Date 9

LARGEST AND SMALLEST ELEMENT IN AN ARRAY AIM

To find the 1iggest num1er in an array of "-1it unsigned num1ers of predetermined length.

A++ARAT(S RE?(IRED
"#$1 Microcontroller 5it ey1oard
Po+er Chord

ALGORITHM Lar'e&t E1eme t

1. !. &. (. $. Start. Load the array count in a register. Load internal memory (#- +ith value ##-. Load first array element in the memory address to accumulator. Compare the num1er in accumulator +ith (#- if not e.ual and 4cc value less than (#-. 2f true then go to step ,. *. Move the value in accumulator to (#-. ,. Choose next array element in the memory address. ". Chec5 array counter not e.ual to ##-. 2f true then go to step (. /. Move the value in (#- to accumulator. 1#. Move the accumulator value to memory address. 11. Stop.

Sma11e&t E1eme t
1. !. &. (. $. Start. Load the array count in a register. Load internal memory (#- +ith value ##-. Load first array element in the memory address to accumulator. Compare the num1er in accumulator +ith (#- if not e.ual and 4cc value less than (#-. 2f true then go to step ,. *. Move the value in accumulator to (#-. ,. Choose next array element in the memory address. ". Chec5 array counter not e.ual to ##-. 2f true then go to step (. /. Move the value in (#- to accumulator. 1#. Move the accumulator value to memory address. 11. Stop.
- 1,
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

FLO; CHART

- 1"
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

+ROGRAM
Lar'e&t E1eme t

+C a,,re&&
(1## (1#& (1#* (1#" (1#/ (1#C (1#) (1#8 (111 (11( (11$ (11, (11/ (11<

Op#!,e

La-e1

M em! %#&
M6F )PT03H(!## M6F (#-3H## M6F 0$3H#$M6FB 43J)PT0 CI:' 43(#-3L66P1 2:C )PT0 )I:K 0$3L66P! M6F 43(#M6F )PT03H(!$# M6FB J)PT034 SIMP -LT IC L66P& M6F (#-34 SIMP L66P&

L66P! L66P&

-LT L66P1

Sma11e&t E1eme t

+C a,,re&&
(1## (1#& (1#* (1#" (1#/ (1#C (1#) (1#8 (111 (11( (11$ (11, (11/ (11<

Op#!,e

La-e1

M em! %#&
M6F )PT03H(!## M6F (#-3H88 M6F 0$3H#$M6FB 43J)PT0 CI:' 43(#-3L66P1 2:C )PT0 )I:K 0$3L66P! M6F 43(#M6F )PT03H(!$# M6FB J)PT034 SIMP -LT I:C L66P& M6F (#-34 SIMP L66P&

L66P! L66P&

-LT L66P1

RES(LT

- 1/
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

FLO; CHART

ST40T 2:2T24L2K' C67:T'0 1 2:T24L2K' M'M60; P62:T'0

2:2T24L2K' C67:T'0 !

A'T T-' :7M<'0

2:C0'M':T M'M60; P62:T'0 A'T T-' :7M<'0

2S =P62:T'0> L =P62:T'0G1

YES
2:T'0C-4:A' C6:T':T 68 C6MP40') M'M60; L6C4T26:S

> NO
)'C0'M':T C67:T'0 !

NO

2S C67:T' 0 !M #N

1 YES ! - !#
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

E5 N!9 =/, Date 9

ASCENDING ORDER OF AN ARRAY AIM

To o1tain the decimal e.uivalent of an "-1it hex num1er stored in memory.

A++ARAT(S RE?(IRED
"#$1 Microcontroller 5it ey1oard
Po+er Chord

ALGORITHM
1. Start. !. 2nitialiDe counter varia1le 1. &. 2nitialiDe memory pointer. (. 2nitialiDe counter varia1le !. $. Load the lo+er 1yte of memory address to 0egister 0!. *. Aet the first num1er from memory pointer. ,. Move the accumulator value to < register. ". 2ncrement memory pointer. /. Aet the next num1er from memory pointer. 1#. Compare the accumulator +ith < register3 2f not e.ual chec5 for greater or less3 go to step 1!. 11. 6ther+ise go to step 1(. 1!. 2f accumulator is greater than < register3 the go to step. 1&. 'xchange the content of t+o memory locations 1(. 2f 01 not e.ual to #3 then go to step $. 1$. 2f 0# not e.ual to #3 then go to step !. 1*. Stop.

- !1
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

)'C0'M':T C67:T'01

NO

2S C67:T' 0 1M #N

YES

ST6P

- !!
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

+ROGRAM +C a,,re&&
(1## (1#! (1#$ (1#, (1#/ (1#4 (1#C (1#) (1#' (111 (11& (11$ (11, (11" (11/ (11< (11C (11'

Op#!,e

La-e1
4A42: <4C

M em! %#&
M6F 0#3H#$M6F )PT03H!###M6F 013H#$M6F 0!3)PL M6FB 43J)PT0 M6F <34 2:C )PT0 M6FB 43J)PT0 CI:' 43<3:'BT =(11&> 4IMP S 2P =(11C> I:C S 2P =(11C> M6F )PL30! M6FB J)PT034 2:C )PT0 M6F 43< M6FB J)PT034 )I:K 013<4C =(1#,> )I:K 0#34A42: =(1#!>

:'BT

S 2P

RES(LT

- !&
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

DIAGRAM

- !(
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

E5 N!9 3 Date 9

STE++ER MOTOR INTERFACE AIM

To interface stepper motor +ith Microcontroller "#$1 and execute the program to run the stepper motor in for+ard direction continuously.

A++ARAT(S RE?(IRED
"#$1 Microcontroller 5it ey1oard
Po+er Chord

Stepper motor interface 5it

INTROD(CTION
4 motor in +hich the rotor is a1le to assume only discrete stationary angular position is a stepper motor. The rotary motion occurs in a step+ise manner from one e.uili1rium position to the next.
CONSTR(CTIONAL FEAT(RES

4 Stepper motor could 1e either of the reluctance type or of the permanent magnet type =PM>. 4 PM stepper motor consists of multi phase stator and t+o part permanent magnet rotor. The F0 stepper motor has unmagnetised rotor. PM stepper motor is the most commonly used type. The 1asic t+o phase stepper motor consists of t+o pairs of stator poles. 'ach of the four poles has its o+n +inding. The excitation of any one +inding generates a north pole =:>3 a south pole =S> gets induced at the diametrically opposite side. 4s sho+n in the figure !-1 the four pole structure is continuous +ith the stator frame and the magnetic field passes through the cylindrical stator annular ring. The rotor magnetic system has t+o end faces. The left face is permanently magnetiDed as South Pole and the right face as :orth Pole. The South Pole structure and the :orth Pole structure possess similar pole faces. The :orth Pole structure is t+isted +ith respect to the South Pole structure so that South Pole comes precisely 1et+een t+o north poles. The :orth Pole structure is offset +ith respect to the South Pole structure 1y one pole pitch. The cross sectional vie+ is sho+n in figure !-!. 2n an arrangement +here there are four stator poles and three pairs of rotor poles3 there exists 1! possi1le sta1le positions in +hich a south pole of the rotor can loc5 +ith a north pole of the stator.

- !$
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

=<+HASE S;ITCHING SCHEME

- !*
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

Aenerally step siDe of the stepper motor depends upon :0. These sta1le positions can 1e attained 1y simply energiDing the +inding on any one of the stator poles +ith a )C. There are three different schemes availa1le for OsteppingO a stepper motor. These areC =a> @ave scheme =1> !-phase scheme and =c> -alf stepping or mixed scheme.

+ROGRAM +C a,,re&&
(1## (1#! (1#$ (1#* (1#/ (1#< (1#C (1#8 (111 (11! (11$ (11, (11" (11< ($## ($#! ($#( ($#, ($#4

Op#!,e

La-e1
L66P1

M em! %#&
M6F 43H#/M6F )PT03H88C# M6FB J)PT034 4C4LL ($## M6F 43H#$M6FB J)PT034 4C4LL ($## M6F 43H#*M6FB J)PT034 4C4LL ($## M6F 43H#4M6FB J)PT03 4 4C4LL ($## SIMP L66P1 M6F 013H""M6F 0!3H"")I:K 0!3($#( )I:K 013($#! 0'T

- !,
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

STE+ SI@E
The step siDe for stepper motor is given 1y3

&*## :r B :s
:s is the :o. of stator poles. :r is the :o. of pairs of rotor poles.

=<+HASE S;ITCHING SCHEME

CLOC:;ISE STE+ A1 A= B1 B= STE+ ANTI CLOC:;ISE A1 A= B1 B=

1 ! & (

1 # # 1

# 1 1 #

# # 1 1

1 1 # #

1 ! & (

1 # # 1

# 1 1 #

1 1 # #

# # 1 1

- !"
Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

=<+HASE SCHEME
2n this scheme3 any t+o adPacent stator +indings are energiDed. There are t+o magnetic fields active in .uadrature and none of the rotor pole faces can 1e in direct alignment +ith the stator poles. Typical e.uili1rium conditions of the rotor +hen the +indings on t+o successive stator poles are excited are illustrated in 8ig.!.(. 2n step =a>3 41 and <1 are energiDed. The pole-face S1 tries to align itself +ith the axis of 41 =:> and the pole face S! +ith <1 =:>. The :orth Pole :& of the rotor finds itself in the neutral Done 1et+een 41 =:> and <1 =:>. S1 and S! of the rotor3 position themselves symmetrically +ith respect to the t+o stator north pole. :ext3 +hen <1 and 4! are energiDed3 S! tends to align +ith <1 =:> and S& +ith 4! =:>. 6f course3 again under e.uili1rium conditions3 only partial alignment is possi1le and :1 finds itself in the neutral region3 mid+ay 1et+een <1 =:> and 4! =:> QStep =1>R. 2n step =c>3 4! and <! are on. S& and S1 tend to align +ith 4! =:> and <! =:>3 respectively3 +ith :! in the neutral Done. Step =d> illustrates the case +hen 41 and <! are on. The step angle is &#S as in the +ave scheme. -o+ever3 the rotor is offset 1y 1$S in the t+o-phase scheme +ith respect to the +ave scheme. 4 total of 1! steps are re.uired to move the rotor 1y &*#S =mechanical>. T+o-phase drives produce more tor.ue than the +ave drives.

RES(LT

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Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

IE: INTERRUPT ENABLE REGISTER - BIT ADDRESSABLE

2f the 1it is #3 the corresponding interrupt is disa1led. 2f the 1it is 13 the corresponding interrupt is ena1led.

'4 2'., - )isa1les all interrupts. 2f '4 M #3 no interrupt +ill 1e ac5no+ledged. 2f '4 M 13 each interrupt source is individually ena1led or disa1led 1y setting or clearing its ena1le 1it. 2'.* - :ot implemented3 reserved for future use. 'T! 2'.$ - 'na1le or disa1le the Timer ! overflo+ interrupt. 'S 2'.( - 'na1le or )isa1le the Serial Port interrupt. 'T1 2'.& - 'na1le or )isa1le the Timer 1 overflo+ interrupt. 'B1 2'.! - 'na1le or )isa1le the 'xternal 2nterrupt 1. 'T# 2'.1 - 'na1le or )isa1le the Timer # overflo+ interrupt. 'B# 2'.# - 'na1le or )isa1le the 'xternal 2nterrupt #.
IP: INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE 2f the 1it is #3 the corresponding interrupt has a lo+er priority and if the 1it is 13 the corresponding interrupt has a higher priority

2P., PT! PS PT1 PB1 PT# PB#

2P.* - :ot implemented3 reserved for future use. 2P.$ - )efines the Timer ! interrupt priority. 2P.( - )efines the Serial Port interrupt priority. 2P.& - )efines the Timer 1 interrupt priority. 2P.! - )efines 'xternal 2nterrupt 1 priority. 2P.1 - )efines the Timer # interrupt priority. 2P.# - )efines 'xternal 2nterrupt # priority

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Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

E5 N!9 4 Date 9

ST(DY OF INTERR(+T STR(CT(RE OF 8051 AIM

To study a1out the 1asic concepts of interrupt structure of "#$1and its functionalities.

INTROD(CTION
"#$1 has $ interrupt sourcesC ! external interrupts3 ! timer interrupts and one serial port interrupt The 'xternal interrupts 2:T#T and 2:T1 A can each 1e either level-activated or transition-activated3 depending on 1its 2T# and 2T1 in 0egister TC6:. The flags that actually generate these interrupts are 1its 2'# and 2'1 in TC6:. @hen an external interrupt is generated3 the flag that generated it is cleared 1y the hard+are3 +hen the service routine is vectored to3 only if the interrupt +as transition-activated. 2f the interrupt +as level-activated3 then3 the external re.uesting source is +hat controls the re.uest flag3 rather than the on-chip hard+are.
PRIORITY LEVEL STRUCTURE

'ach interrupt source can also 1e individually programmed to one of the t+o priority levels 1y setting or clearing a 1it in the Special 8unction 0egister 2P. 4 lo+ priority interrupt can itself 1e interrupted 1y a high priority interrupt3 1ut not 1y another lo+-priority interrupt. 4 high priority interrupt canUt 1e interrupted 1y another interrupt source. 2f t+o re.uests of different priority levels are received simultaneously3 the re.uest of higher priority level +ill 1e serviced first.

HOW INTERRUPTS ARE HANDLED

The interrupt flags are sampled at S$P! of every machine cycle =2n "#$13 a machine cycle consists of a se.uence of * states3 num1ered S1 through S*. 'ach state time lasts for t+o oscillator periods. 'ach state is divided into a Phase 1 half and a Phase ! half>. The samples are polled during the follo+ing machine cycle. 2f one of the flags +as in a set condition at S$P! of the preceding cycle3 the polling cycle +ill find it and the interrupt system +ill generate a LC4LL to the appropriate service routine3 provided this hard+are-generated LC4LL is not 1loc5ed 1y any of the
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Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

INTERR(+T HANDLING

4ECTOR ADDRESS OF ALL THE INTERR(+T SO(RCES

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Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

follo+ing conditionsC 1. 4n interrupt of e.ual or higher priority level is already in progress. !. The current =polling> cycle is not the final cycle in the execution of the instruction in progress. &. The instruction in progress is 0'T2 or any access to the 2' or 2P registers. 4ny of these three conditions +ill 1loc5 the generation of the LC4LL to the 2nterrupt Service 0outine. Condition ! ensures that the instruction in progress +ill 1e completed 1efore vectoring to any service routine. Condition & ensures that if the instruction in progress is 0'T2 or any access to 2' or 2P3 then at least one more instruction +ill 1e executed 1efore any interrupt is vectored to. The polling cycle is repeated +ith each machine cycle and the values polled are the values that +ere present at S$P! of the previous machine cycle. :ote that if an interrupt flag is active 1ut not 1eing responded too for one of the a1ove conditions3 if the flag is not still active +hen the 1loc5ing condition is removed3 the denied interrupt +ill not 1e serviced. 2n other +ords3 the fact that the interrupt flag +as once active 1ut not serviced is not remem1ered. 'very polling cycle is ne+. :ote that if an interrupt of higher priority level goes active prior to S$P! of the machine cycle la1eled C& in the 8igure 8*.13 then3 in accordance +ith the a1ove rules3 it +ill 1e vectored to during C$ and C*3 +ithout any instruction of the lo+er priority routine having 1een executed.

RES(LT

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Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

F(NCTIONAL BLOC: DIAGRAM

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Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

E5 N!9 5 Date 9

DC MOTOR CONTROLLER INTERFACE AIM

To interface the )C Motor +ith the microcontroller "#$1 and execute the program to control the seed of the )c Motor.

A++ARAT(S RE?(IRED
"#$1 Microcontroller 5it ey1oard
Po+er Chord

)C motor interface 5it

INTROD(CTION
+r% #%p1e !" !perat%! This 1oard uses a simple method for measurement and control of the )C motor speed. This 1oard uses the principle that the speed of any motor decreases as the input po+er to the motor decreases. -ence3 1y varying the input voltage to the motor3 the speed can 1e varied. The speed measurement is 1ased on the principle that the motor rotation is converted in to pulses using optical pic5up and these pulses are used to decremented a counter for a 5no+n time. This count value can 1e cali1rated to 0PM =rotation per minute>3 +hich is the standard unit for speed measurement.

I>O ADDRESS DETAILS

The 1elo+ given ta1le sho+s the 2:P7T%67TP7T address details involved in this speed measurement and control module. This 1oard can 1e accessed from any of the Microprocessor trainer designed 1y us.

+er%p$era1&
)4C Timer Channel # Timer Channel 1 Timer Channel ! Timer Channel reg. Aate high Aate lo+

Rea, !r ;r%te
@ 0%@ 0%@ 0%@ @ 0%@ 0%@

I>O a,,re&& % $e6

C# C" C4 CC C' )# )"

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Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

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Microcontroller & Programmable Logic Controller Laboratory

Department of Mechatronics Engineering, SNS Tech, Coimbatore-35.

+ROGRAM +C a,,re&&
(1## (1#! (1#$ (1#*

Op#!,e

La-e1

M em! %#&
M6F 43H)4T4 =##-88> M6F )PT03H88C# M6FB J)PT034 SIMP -'0' =(1#*>

-'0'

RES(LT

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Microcontroller & Programmable Logic Controller Laboratory