RT9173/A

Peak 3A Bus Termination Regulator

General Description Features

The RT9173/A regulator is designed to convert voltage
Support Both DDR 1 (1.25VTT) and DDR 2
supplies ranging from 1.6V to 6V into a desired output (0.9VTT) Requirements
voltage which adjusted by two external voltage divider
SOP-8, TO-252-5 and TO-263-5 Packages
resistors. The regulator is capable of sourcing or sinking
Capable of Sourcing and Sinking 3A Peak Current
up to 3A of peak current while regulating an output voltage
Current-limiting Protection
to within 2% (DDR 1) and 3% (DDR 2) or less.
Thermal Protection

Integrated Power MOSFETs
The RT9173/A, used in conjunction with series termination

Generates Termination Voltages for SSTL-2
resistors, provides an excellent voltage source for active

High Accuracy Output Voltage at Full-Load
termination schemes of high speed transmission lines as

Adjustable VOUT by External Resistors
those seen in high speed memory buses and distributed

Minimum External Components
backplane designs. The voltage output of the regulator

Shutdown for Standby or Suspend Mode
can be used as a termination voltage for DDR SDRAM.
Operation with High-impedance Output
Current limits in both sourcing and sinking mode, plus
on-chip thermal shutdown make the circuit tolerant of the Applications
output fault conditions.
DDR Memory Termination

Active Termination Buses
Ordering Information
Supply Splitter

RT9173/A Pin Configurations

Package Type (TOP VIEW)
M5 : TO-263-5
L5 : TO-252-5 5 VOUT
S : SOP-8 4 REFEN
Operating Temperature Range 3 VCNTL (TAB)
C : Commercial Standard 2 GND
P : Pb Free with Commercial Standard
1 VIN
3A Sink & Source
1.5A Sink & Source TO-263-5 (RT9173A)

Function Block Diagram 5 VOUT

VCNTL VIN
4 REFEN
3 VCNTL (TAB)
2 GND
Current 1 VIN
Limiting Sensor

REFEN CNTL VOUT TO-252-5 (RT9173A)

Thermal

VIN 8 VCNTL
GND
GND 2 7 VCNTL
REFEN 3 6 VCNTL
VOUT 4 5 VCNTL

SOP-8 (RT9173)

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Functional Pin Description
Pin Name Pin Function
VIN Power Input
GND Ground
VCNTL Gate Drive Voltage
REFEN Reference Voltage Input and Chip Enable
VOUT Output Voltage

Absolute Maximum Ratings

Input Voltage ----------------------------------------------------------------------------------------------------------- 7V

Power Dissipation ----------------------------------------------------------------------------------------------------- Internally Limited

ESD Rating ------------------------------------------------------------------------------------------------------------- 2kV

Storage Temperature Range --------------------------------------------------------------------------------------- −65°C to 150°C

Lead Temperature (Soldering, 5 sec.) --------------------------------------------------------------------------- 260°C

Package Thermal Resistance
TO-263,θJC ------------------------------------------------------------------------------------------------------------- 7.7° C/W
TO-252,θJC ------------------------------------------------------------------------------------------------------------- 8° C/W
SOP-8, θJC -------------------------------------------------------------------------------------------- 15.7° C/W

Electrical Characteristics
(VIN = 2.5V, VCNTL = 3.3V, VREFEN = 1.25V, COUT = 10µF (Ceramic), TA = 25°C, unless otherwise specified.)
Parameter Symbol Test Conditions Min Typ Max Units
Output Offset Voltage VOS IOUT = 0A, Figure 1 (Note 1) -20 0 20 mV
IL : 0A → 1.5A, Figure 1 -- 0.8/1.2 2/3
Load Regulation (DDR 1/2) ∆VLOAD %
IL : 0A → -1.5A -- 0.8/1.2 2/3
Input Voltage Range (DDR 1/2) VIN Keep VCNTL ≥ VIN on operation power 1.6 2.5/1.8 --
V
(Note 2) VCNTL on and power off sequences -- 3.3 6
Operating Current of VCNTL ICNTL No Load -- 6.5 10 mA
Current In Shutdown Mode ISHDN VREFEN < 0.2V, RL = 180Ω, Figure 2 -- 50 90 µA
Short Circuit Protection
Current limit ILIMIT Figure 3,4 3.0 -- -- A
Over Temperature Protection
Thermal Shutdown Temperature TSD 3.3V ≤ VCNTL ≤ 5V 125 150 -- °C
Thermal Shutdown Hysteresis Guaranteed by design -- 50 -- °C
Shutdown Function
VTRIGGER Output = High, Figure 5 0.8 -- --
Shutdown Threshold Trigger V
VTRIGGER Output = Low, Figure 5 -- -- 0.2
Note 1. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN.
Note 2. For safely operate your system, the 3.3V rail MUST be tied to VCNTL rather than 5V rail, especially for the
new part of RT9173ACL5.

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 RT9173/A
Typical Application Circuit
VCNTL = 3.3V

VIN = 2.5V
RTT

R1 VIN VCNTL CIN CCNTL

RT9173/A
REFEN VOUT
2N7002
CSS COUT
EN R2 GND
RDUMMY

R1 = R2 = 100kΩ, RTT = 50Ω / 33Ω / 25Ω

COUT(min) = 10µF (Ceramic) + 1000µF under the worst case testing condition
RDUMMY = 1kΩ as for VOUT discharge when VIN is not present but VCNTL is present
CSS = 1µF, CIN = 470µF (Low ESR), CCNTL = 47µF

Test Circuit
2.5V 3.3V

VIN VCNTL
RT9173/A VOUT
1.25V REFEN VOUT

GND COUT V
IL

Figure 1. Output Voltage Tolerance, ∆VLOAD

3.3V
2.5V A

VIN VCNTL
RT9173/A 1.25V
V OUT
1.25V REFEN VOUT
0V
GND RL C OUT
0.2V V

R L and C OUT
Time deleay

Figure 2. Current in Shutdown Mode, ISHDN

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RT9173/A

2.5V 3.3V

VIN VCNTL
RT9173/A VOUT
1.25V REFEN VOUT

GND A COUT V
IL

Figure 3. Current Limit for High Side, ILIMIT

Power Supply
3.3V
with Current Limit
2.5V
A
VIN VCNTL
IL
RT9173/A V OUT
1.25V REFEN VOUT

GND COUT V

Figure 4. Current Limit for Low Side, ILIMIT

3.3V
2.5V

VIN VCNTL
RT9173/A V OUT
1.25V REFEN VOUT
V REFEN
0.2V GND RL C OUT
V
1.25V

V OUT
0V
V OUT would be low if VREFEN < 0.2V
V OUT would be high if VREFEN > 0.8V

R L and COUT
Time deleay

Figure 5. REFEN Pin Shutdown Threshold, VTRIGGER

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Typical Operating Characteristics
Sourcing Current (Peak) vs. Temperature Sinking Current (Peak) vs. Temperature
8.0 8.0

7.0 7.0

6.0 6.0

5.0 5.0

4.0 4.0

3.0 3.0

2.0 2.0
VCNTL = 3.3V VCNTL = 3.3V
1.0 VIN = 2.5V 1.0 VIN = 2.5V
VOUT = 1.25V VOUT = 1.25V
0.0 0.0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Temperature (°C) Temperature (°C)

Turn-On Threshold vs. Temperature Turn-On Threshold vs. Temperature

700 700

650 650

600 600

550 550

500 500

450 450
VCNTL = 3.3V VCNTL = 5.0V
VIN = 2.5V VIN = 2.5V
400 400
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Temperature (°C) Temperature (°C)

1.25VTT @ 1.5A Transient Response 1.25VTT @ 3A Transient Response

100 100
Output Transient

Output Transient

VIN = 2.5V VCNTL = 3.3V VIN = 2.5V VCNTL = 3.3V

Voltage (mV)

Voltage (mV)

50 VREFEN = 1.25V Swing Frequency = 1KHz 50 VREFEN = 1.25V Swing Frequency = 1KHz

0 0

-50 -50
≈ ≈ ≈ ≈
2 4
Output Current (A)

Output Current (A)

1 2

0 0

-1 -2

-2 -4
Time (250us/Div) Time (250us/Div)

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0.9VTT @ 1.5A Transient Response 0.9VTT @ 3A Transient Response

100 100
Output Transient

Output Transient
VIN = 1.8V VCNTL = 3.3V VIN = 1.8V VCNTL = 3.3V
Voltage (mV)

Voltage (mV)
50 VREFEN = 0.9V Swing Frequency = 1KHz 50 VREFEN = 0.9V Swing Frequency = 1KHz

0 0

-50 -50
≈ ≈ ≈ ≈
2 4
Output Current (A)

Output Current (A)

1 2

0 0

-1 -2

-2 -4
Time (250us/Div) Time (250us/Div)

Temperature vs. RDS(ON) Temperature vs. RDS(ON)

0.31 0.32
VIN = 0.9V
0.30 VIN = 0.9V 0.31

0.29 VIN = 0.85V 0.30

(Ω)
(Ω)

0.28 0.29 VIN = 0.85V

DS(ON)
DS(ON)

0.27 VIN = 0.8V 0.28

0.27 VIN = 0.8V

0.26

0.25 0.26

0.24 0.25

0.23 VCNTL = 3.3V 0.24 VCNTL = 5.0V

VREFEN = 1.0V VREFEN = 1.0V
0.22 0.23
25 35 45 55 65 75 85 95 105 115 125 25 35 45 55 65 75 85 95 105 115 125
Temperature (°C) Temperature (°C)

Output Short-Circuit Protection Output Short-Circuit Protection

12 12
Sink VIN = 2.5V Source VIN = 2.5V
10 VCNTL = 3.3V 10 VCNTL = 3.3V
VREFEN = 1.25V VREFEN = 1.25V
Output Short Circuit (A)

Output Short Circuit (A)

8 8

6 6

4 4

2 2

0 0

-2 -2
Force the output shorted to VDDQ Force the output shorted to ground
-4 -4
Time (5ms/Div) Time (5ms/Div)

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Copper Area vs. Power Dissipation

350
RT9173ACL5
TJ = 125°C
300
2

250

200

150

100
TA = 65°C TA = 50°C TA = 25°C
50

0
1.5 2 2.5 3 3.5 4 4.5 5 5.5
Power Dissipation (W)

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RT9173/A
Application Information
Internal Parasitic Diode Thermal Consideration
Avoid forward-bias internal parasitic diode, VOUT to VCNTL, The RT9173/A is capable of sinking and souring 3A peak
and VOUT to VIN, the VOUT should not be forced some current. However its continuous current capability is
voltage respect to ground on this pin while the VCNTL or decided by internal thermal limiting and is highly
VIN is disappeared. dependent of system thermal performance. Internal 125°C
thermal limit point (VCNTL = 3.3V) must not be exceeded
Consideration while Designs the Resistance of for normal operation.
Voltage Divider
It is noted that when VCNTL powered by 5V the thermal
Make sure the sinking current capability of pull-down
limit point is approx. 20°C lower than that powered by
NMOS if the lower resistance was chosen so that the
3.3V. It is highly recommended that 3.3V rail is used as
voltage on VREFEN is below 0.2V.
VCNTL to minimize the thermal concern when RT9173CS
In addition, the capacitor and voltage divider form the low- in SOP-8 package is designed.
pass filter. There are two reasons doing this design; one
For high continuous current and high ambient temperature
is for output voltage soft-start while another is for noise
application, RT9173A is recommend for its better thermal
immunity.
performance.
How to reduce power dissipation on Notebook PC or the
dual channel DDR SDRAM application? Layout Consideration
The RT9173CS regulator is packaged in plastic SOP-8
In notebook application, using RichTek's Patent
package. This small footprint package is unable to
"Distributed Bus Terminator Topology" with choosing
convectively dissipate the heat generated when the
RichTek's product is encouraged.
regulator is operating at high current levels. In order to
Distributed Bus Terminating Topology control die operating temperatures, the PC board layout
should allow for maximum possible copper area at the
Terminator Resistor
VCNTL pins of the RT9173CS.
R0
BUS(0) The multiple VCNTL pins on the SOP-8 package are
R1
BUS(1) internally connected, but lowest thermal resistance will
VOUT R2
RT9173/A BUS(2) result if these pins are tightly connected on the PC board.
R3
BUS(3) This will also aid heat dissipation at high power levels.
R4
REFEN
BUS(4) If the large copper around the IC is unavailable, a buried
R5
BUS(5) layer may be used as a heat spreader, use vias to conduct
R6
BUS(6) the heat into the buried or backside of PCB layer. The
R7
RT9173/A
VOUT
BUS(7) vias should be small enough to retain solder when the
R8
BUS(8)
board is wave-soldered. (See Figure 6. shown on next
R9
BUS(9)
page).

RN
BUS(N+1)
RN1
BUS(N)

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Use vias to conduct the heat into the
buried or backside of PCB layer .

RT9173CS (SOP-8)

The PCB heat sink copper area should be

solder-painted without masked. This
approaches a “best case” pad heat sink.

Figure 6. Layout Consideration

To prevent this maximum junction temperature from being

exceeded, the appropriate power plane heat sink MUST
be used. Higher continuous currents or ambient
temperature require additional heatsinking.

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Outline Dimension

C
D U
B

V
E

L1

L2

e b
b2

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
D 9.652 10.668 0.380 0.420
B 1.143 1.676 0.045 0.066
E 8.128 9.652 0.320 0.380
A 4.064 4.826 0.160 0.190
C 1.143 1.397 0.045 0.055
U 6.223 Ref. 0.245 Ref.
V 7.620 Ref. 0.300 Ref.
L1 14.605 15.875 0.575 0.625
L2 2.286 2.794 0.090 0.110
b 0.660 0.914 0.026 0.036
b2 0.305 0.584 0.012 0.023
e 1.524 1.829 0.060 0.072

5-Lead TO-263 Plastic Surface Mount Package

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 RT9173/A

E C2
b3

L3

D
H

b P
L2

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 2.184 2.388 0.086 0.094
b 0.381 0.889 0.015 0.035
b3 4.953 5.461 0.195 0.215
C2 0.457 0.889 0.018 0.035
D 5.334 6.223 0.210 0.245
E 6.350 6.731 0.250 0.265
H 9.000 10.414 0.354 0.410
L 0.508 1.780 0.020 0.070
L2 0.508 Ref. 0.020 Ref.
L3 0.889 2.032 0.035 0.080
P 1.270 Ref. 0.050 Ref.
V 4.572 -- 0.180 --

5-Lead TO-252 Plastic Package

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RT9173/A

H
A

J B

C
I
D

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 4.801 5.004 0.189 0.197
B 3.810 3.988 0.150 0.157
C 1.346 1.753 0.053 0.069
D 0.330 0.508 0.013 0.020
M 0.406 1.270 0.016 0.050
F 1.194 1.346 0.047 0.053
I 0.102 0.254 0.004 0.010
J 5.791 6.198 0.228 0.244
H 0.178 0.254 0.007 0.010

8-Lead SOP Plastic Package

RICHTEK TECHNOLOGY CORP. RICHTEK TECHNOLOGY CORP.

Headquarter Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City 8F-1, No. 137, Lane 235, Paochiao Road, Hsintien City
Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)89191466 Fax: (8862)89191465
Email: marketing@richtek.com

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