52

Chapter 6

Interfacing Concepts

Interfacing is the process of connecting devices together so that they can exchange information. A
special interface must translate between the signal that the computer uses and those that the peripheral
uses. An interface includes the physical connection, the hardware and a set of rules or procedures, i.e.,
the software. The interface must provide the proper timing and control. Formally, an interface is a
device and/or set of rules to match the output of one device to the input of another device for sending
information from one to the other. For example, the connection between a microprocessor and
external memory is an interface. There are physical connections for addressing, data flow and control
signals. The software consists of instructions that read from and/or write to an addressed location.

The major problems with interfacing are:
- wide variety of peripheral devices
- enormous range of peripheral speeds
- variety in signal types and signal levels in peripheral devices
- complexity of the signaling structure (strobes, handshaking, etc.)

Basic Input/Output Interfacing

The process of reading input signals and sending output signals is called input/output (I/O). The
subsystems are known as I/O subsystems which are sometimes called an interface. Input and output
are similar to memory accesses. The processor can transfer data to and from the peripherals in the
same way that it transfers data to and from memory. In fact, memory is simply another peripheral. I/O
direction is relative to the MCU. Input is data read by the MCU. Output is data sent out by the MCU.

A simple I/O section in a microcomputer system may include a temperature sensor that provides data
every 5 minutes, a modem device that transfers 56K bits every second and a floppy disk that transfers
bits in the order of megabits per second.

Simple Input Interface

An input operation is similar to a memory read cycle.
1. P generates address and control signals to select the input device.
2. Input device generates data and loads data lines.
3. P reads data from the data bus and places it in a register.

Most Ps accept data from an input device through the data bus connections and therefore require
some form of switch to connect this data to the bus at the appropriate time. One effective digital
switch available is the three-state buffer.

Example: Eight On/Off switches can be connected to the CPU by the use of a three-state buffer as
follows:










Device
Decoder
+5v
R

+5v
R

to P data bus
INSTROBE
from P
address
bus
74LS244
53
INSTROBE is the timing control signal. Device decoder generates the INSTROBE signal for the
required input device.

Simple Output Interface

An output operation is similar to a memory write cycle.
1. P generates address and control signals to select the output device.
2. P places data on the data bus.
3. P waits for the transfer to be successfully completed.

Whenever data is sent out from the P to an external output device, it appears on the data bus for only
a brief period of time. In almost all instances, the external output device uses some form of latch to
grab onto and hold the data bus information.

Example: Eight LEDs can be connected to the CPU by the use of latch as follows:





.
.










Other examples of output devices are 7-segment displays, liquid crystal displays (LCD), relays,
solenoids, etc.

Input/Output Mapping

Most I/O sections consist of more than one device. Such I/O sections require bus structures that must
be combined with those required by the memory section. Almost all microprocessors use the same bus
for both memory and I/O transfers.

There are two basic input/output schemes:

1. Memory-mapped I/O; in which I/O devices (parallel I/O lines) are treated exactly the same as
memory locations
2. Isolated I/O; in which memory and I/O addresses are decoded separately.

Example: (Memory-mapped I/O) (used by most Motorola processor)

Suppose that it is required to use eight I/O devices and the locations $CF00 through $CFFF are to be
used for this purpose.



Device
Decoder
OUTSTROBE
from P
address
bus

R
D Q

R
D Q
from P
data bus
54















CFxx selects the I/O space (page selection)
For each device only the higher order 3-bits of the remaining 8 address bits are used.

















Decoder Circuit


















Input Strobe Generator Circuit

Device 0
Device 1
Device 2
Device 3
Device 4
Device 5
Device 6
Device 7

A5
A6
A7
0
1
2
3
4
5
6
7
A
B
C
E1
E2
E3

A15
A14
A13
A12
A11
A10
A9
A8
CFxx
PAGE CF
1
0
$0000



$CF00

$CFFF



$FFFF




I/O area

Memory Map
Device 0: $CF00-$CF1F
Device 1: $CF20-$CF3F
Device 2: $CF40-$CF5F
Device 3: $CF60-$CF7F
Device 4: $CF80-$CF9F
Device 5: $CFA0-$CFBF
Device 6: $CFC0-$CFDF
Device 7: $CFE0-$CFFF

In fact there are
256 locations and
eight different
devices use this
space with
overlays
INCF00
INCF20
INCF40
INCF60
INCF80

INCFA0

INCFC0

INCFE0


A5
A6
A7
0
1
2
3
4
5
6
7
A
B
C
E1
E2
E3

MEMR
PAGE CF
1
E
R / W
55
To access the input device 0, one can use LDAA $CF00 and to access the input device 7, one can use
LDAA $CFE0. Input and output devices should use R/W signal for proper activation.

Advantages of memory-mapped I/O are:

- Any instruction that operates on data in memory can operate on data at input and output
devices.
- No separate decoding or control system is necessary for input and output.

Drawbacks of memory-mapped I/O are:

- I/O transfers may be difficult to distinguish from other operations in software.
- I/O devices occupy some of the address space.
- The decoding system may become complex because I/O devices occupy much less than
memory chips. In order to avoid complexity the memory space has to be wasted.

Example: (Isolated I/O) (used by most Intel and Zilog processors)

In this type of I/O, there are separate memory and I/O instructions and separate memory and I/O
maps. Suppose that it is required to use eight I/O devices and the locations between $80 through $9F
in the I/O map are to be used for this purpose.
































Decoder Circuit
$00


$80

$9F




$FF




I/O area

I/O Map
Device 0: $80-$83
Device 1: $84-$87
Device 2: $88-$8B
Device 3: $8C-$8F
Device 4: $90-$93
Device 5: $94-$97
Device 6: $98-$9B
Device 7: $9C-$9F

In fact there are 32
locations and eight
different devices
use this space with
overlays
$0000









$FFFF






Memory Map
Device 0
Device 1
Device 2
Device 3
Device 4
Device 5
Device 6
Device 7

A10
A11
A12
0
1
2
3
4
5
6
7
A
B
C
E1
E2
E3
A13
A14
A15
For example in Intel 8085,
address lines A7-A0 and A15-A8
have the same information when
I/O map is used, i.e., address of
one of 256 ports is issued in both
low and high order address bytes.
56

Example: Draw the strobe generation circuit for four input and four output ports between addresses
$00-$3F in the isolated I/O mode

















Advantages of isolated I/O are:

- I/O device addresses can be short.
- Programs are clearer because I/O transfers are distinguished from other operations.
- Memory and I/O design can be separated

Drawback of isolated I/O is the requirement for extra decoding and extra instructions.

General Input/Output Interfacing and I/O Registers

I/O systems do not control only simple switches and leds. I/O systems usually transfer data to and
from more complex peripheral devices. Data is usually required to be input whenever it is ready at the
device side. Similarly data is usually required to be output whenever the peripheral device is ready to
accept it. Microcontrollers generally have built-in I/O subsystems because they are designed to handle
the different types of interface requirements commonly found in industry. Some applications require
more I/O than can be handled by the MCUs built in I/O subsystems. In this case the MCU board
could include programmable I/O peripheral chips.

Both microcontrollers and programmable I/O chips handle I/O processing using registers. Generally,
an I/O section has some associated registers like the control, status and data registers.

The control register is programmed (suitable data is written) to define the operation characteristics of
the I/O section. An I/O section can therefore be programmed as follows:
- the signal lines can be defined as input or output
- availability of the external data or the readiness of the external device can be detected by a
transition in an associated signal line
- the transition type can be defined to be level (high or low) or edge (rising or falling edge)
sensitive
- whenever a transition occurs, an interrupt signal may or may not be generated.

The status register is read to check the status of the I/O. By reading it, one can understand,
- whether the external data is available (external device made its data ready) or whether the
external device is ready to input its data
- whether there is an error in the transfer or not.

IN00
IN10
IN20
IN30
OUT00
OUT10
OUT20
OUT30

A12
A13
IOR
0
1
2
3
4
5
6
7
A
B
C
E1
E2
E3
A14
A15

IOR
IOW
Overlayed usage
57
The data register holds the input data that has been received or the output data that was most recently
sent out.

The above I/O functionality can be done on a separate chip which then can be connected to the P
appropriately or the I/O functionality can be implemented on the microcontroller itself. The MC6821
Peripheral Interface Adapter (PIA) chip is a programmable I/O interface chip.

The Peripheral Interface Adapter (PIA)

A set of ports (parallel I/O signal lines), sometimes on chip memory, registers, programmable counter
and a timer may constitute the peripheral interface adapter (PIA). In general, PIA is a programmable
LSI device with the following features.
- buffers and latches for input and output data
- status and control signals for handshaking
- other control and timing signals for peripherals
- direct interface with the processor address, data and control buses

PIA usage:









For simple parallel input/output:

1. address the PIA control register
2. transfer control information into PIA
3. address the PIA data register
4. transfer data (in or out) through PIA

A typical simplified port pin connection of a PIA is as follows:




















P

PIA
Device
P buses



D Q
OUT
Port Pin
Data bus
WR port
IN
RD port
IN and OUT are generated by
software, WR Port and RD Port
signals are generated by the
decoding circuitry.
58
The MC6821 Peripheral Interface Adapter (PIA)

Data Registers (DR), when addressed, store the data present on the MPU data bus during an MPU
write operation.
During an MPU read operation, the data present on peripheral lines programmed as inputs is
transferred directly to the system data bus.

The Data Direction Registers (DDR) are used to establish each individual peripheral bus line as
either an input or an output. This is accomplished by having the MPU write "ones" or "zeros"
into the eight bit positions of the DDR. Zeros or ones cause the corresponding peripheral data
lines to function as inputs or outputs, respectively.
Selection of 6821 and Internal Registers:
There are three chip select inputs and one enable input.

Since all data transfers take place during the high portion of the clock cycle, the Enable (E) input is
normally connected to E clock of the 6811.
The PIA occupies four memory locations through two RS pins. Since there are six registers, but four
addresses, DDR and DR share the same address from the point of MPU address bus. These
two are selected via bit-2 of CR. If it is zero DDR is selected, if one DR is selected.
Internal addressing (register selection) of the PIA is as follows:
RS1 RSO CRA-2 CRB-2 Selected Register
0
0
0
1
1
1

0
0
1
0
0
1

0
1
X
X
X
X

X
X
X
0
1
X

DDRA
DRA (Peripheral Register)
CRA
DDRB
DRB (Peripheral Register)
CRB

Before the selection of DDR and DR, bit-2 of the corresponding CR has to be set to the proper level.
The control registers (CR) allow the MPU to establish and control the operating modes of the
peripheral control lines, CA1, CA2, CB1, CB2.

59
Organization of the PIA control registers is as follows:

Bit-7 (IRQA1 Interrupt Flag): Goes high on active transition of CA.); automatically cleared by MPU
read of DRA, may also be cleared by hardware reset. It is read only (CRB-7).
Bit-6 (IRQA2 Interrupt Flag):
If CA2 is input: Goes high on active transition of CA2, cleared in the same way as bit-7.
If CA2 is output: It is equal to zero, not affected by CA2 transitions. (CRB-6)
Bit-0 (Interrupt Request Enable/Disable): If it is equal to zero, disables IRQA interrupt which will
be caused by CA1 active transition. If it is one, enable CA1 interrupt. (CRB-0)
Bit-1 (Active transition determination): if 0, high-to-low transition of CA1 sets IRQA1;
if 1, low-to-high transition sets IRQA1. (CRB-1)

Bit-2 (DDRA access): If 0, DDRA is selected; if 1, DRA selected. (CRB-2)
Bit-5 (CA2 input-output control):

RESET: The RESET input clears all the PIA registers. All the data and control lines are initially
inputs, all interrupts are disabled and DDR is selected.



60
Examples on I/O applications

If PIA is used, the device has to be initialized by programming. General initialization procedure is as
follows:
- clear bit-2 of CRA (CRB) to select DDRA (DDRB)
- load DDR in order to program the ports as input or output lines in the required manner
- set bit-2 of CRA (CRB) to select DRA (DRB)
- write and read

Example: Transfer the contents of location $0040 via port A of the PIA. Assume the following PIA
register address:
DDRA, DRA: $8008
CRA: $8009

mnemonic comment
CLR $8009 CRA-2 is cleared. $8008 is the address of DDRA
LDAB #$FF
STAB $8008 DDRA is loaded with all 1s. Port A is programmed as output
LDAB #$04
STAB $8009 CRA-2 is set. $8008 is the address of DRA
LDAA $40 Load the contents of location $40 to Acc.A
STAA $8008 Transfer the contents of Acc.A to Port A
.
.
.

Example: It is required to control a 4-bit LED display with a 4-bit DIP switch via a 6811+6821
system. You are allowed to use only Port A of the PIA and assume the following PIA register address:
DDRA, DRA: $8008
CRA: $8009











label mnemonic comment
CLR $8009 CRA-2 is cleared. $8008 is the address of DDRA
LDAB #$F0
STAB $8008 DDRA is loaded with four 1s and four 0s. Port A is
programmed as half output and half input
LDAB #$04
STAB $8009 CRA-2 is set. $8008 is the address of DRA
LOOP LDAA $8008 Read the position of the DIP switch
ASLA
ASLA
ASLA
ASLA Transfer LSN to MSN
STAA $8008 Transfer the info to display
BRA LOOP
PA0
PA1
PA2
PA3
PIA PA4
PA5
PA6
PA7

DIP
SWITCH
LED
DISPLAY
61
Example: Consider the following connection of 6821 to 6811 and determine the address of the PIA
registers.



















Example: Determine the contact position of the following eight-position switch. If there is no contact
then wait for the switch to make a contact.













PIA base address: $6000

label mnemonic comment
LDX #$6000 get the base address of PIA
CLR $01,X access DDRA
CLR $00,X make all lines input
LDAA #$04
STAA $01,X $6000 is the address of DRA
LDAA #$FF if the switch is not at any position, i.e.
WAIT CMPA $00,X if the input byte is $FF then wait for
BEQ WAIT a position to be contacted
CLRB the switch is on position and begin with zero
position
LDAA $00,X get switch data
SRCHPOS RORA check is the next bit is grounded
BCC FOUND if so, position is found
INCB if not, increment ACCB and go on
BRA SRCHPOS with checking if the position is the next one
FOUND WAI
A15 A14 A13 . . . A2 A1 A0
0 1 x . . . x 0 0 : DDRA/DRA
0 1 x . . . x 0 1 : CRA
0 1 x . . . x 1 0 : DDRB/DRB
0 1 x . . . x 1 1 : CRB

With overlays:
$4000-$7FFF : 16K locations are used for the PIA
$4000 : DDRA/DRA ($7FFC)
$4001 : CRA ($7FFD)
$4002 : DDRB/DRB ($7FFE)
$4003 : CRB ($7FFF)

CS0
CS1
CS2
R/W PIA
E
RS0
RS1

1
A14
A15
R/W
E
A0
A1

CS0 PA0
CS1 PA1
CS2 PA2
R/W PA3
E PA4
RS0 PA5
RS1 PA6
PA7

A13
A14
A15
R/W
E
A0
A1

+5v
R

PIA
62
Interfacing using polling or interrupts

There are two methods for controlling the flow of data in and out of the computer:

1. Program controlled I/O (polling):

P repeatedly executes a program code and checks periodically whether a peripheral requests
servicing. When it finds that a peripheral has requested service, the P performs the data
transfer operation, either a read or write.

An external peripheral may request service by sending a pulse on an I/O request line. The I/O
request may be for a read or a write operation. Either a low-to-high transition or a high-to-low
transition on the I/O request line causes a bit in the associated status register to set (or reset).

To determine whether or not to serve a peripheral, the MCU reads (polls) a status register
periodically to check the corresponding status bit (request flag). If an I/O request is detected,
then it proceeds to handle the request as required, i.e. the MCU executes an I/O service
routine. For a read operation, it may be something like read the data register and pass the
value to the main program in an accumulator. For a write operation, it may be an output
routine that passes an accumulator value to the data register.

Advantage: Simple program.

Disadvantage: Inefficient use of P time. P may miss data if the input data changes more
rapidly than P loop time.

2. Interrupt controlled I/O:

An I/O device sends an interrupt signal to P to notify the computer that either the peripheral
has data for the P or it expects the computer to output data for the peripheral. The P then
suspends its current task to service the interrupt. P goes to the interrupt service subroutine
which then services the interrupt by reading from or writing to I/O ports. After the service, P
returns back to its original execution.

Like polling, an active transition on the request line may set the request flag. In this case it
also asserts an interrupt.

The P stacks the P registers and sets I bit in the condition code register.

P then executes the service routine addressed by the interrupt vector. If more than one
device could cause the same interrupt, the P checks other status bits to determine which
service has caused the interrupt. The P clears the request flag and then completes the I/O
depending on the requirements. After completion of the interrupt service, return from
interrupt (RTI) instruction is eceuted by the MPU, which returns the control to the interrupted
program.

Adv: More efficient

Disadvantage: Complex program.

Which of the two methods are to be used is programmed through the control register of the PIA chip
(CRA-1 for 6821).


63
How interrupt is sent to P?











If bit0 (interrupt enable bit for CA1) of CRA is set, then PIAs IRQA line will go low whenever CA1
is triggered. This sets status bit 7 (CRA-7) and passes an interrupt request to P. P services the
interrupt by reading the DRA. After the execution, PIA automatically clears the status bit 7, which
clears the interrupt signal on IRQA.

Example: (Rotary switch example) If the task of monitoring switches is placed under interrupt control,
the P is freed from the tasks of monitoring the switches and can perform other tasks.















PIA base address: $6000

label mnemonic comment
LDX #$6000 get the base address of PIA
CLR $01,X access DDRA
CLR $00,X make all lines input
LDAA #$05 control word %00000101 (active CA1 transition is
high -to-low and IRQA is enabled)
STAA $01,X $6000 is the address of DRA
CLI


ISR LDAA #$FF if the switch is not at any position, i.e.
CLRB the switch is at a position, begin with zero pos.
LDAA $00,X get switch data
SRCHPOS RORA check is the next bit is grounded
BCC FOUND if so, position is found
INCB if not, increment ACCB and go on
BRA SRCHPOS with checking if the position is the next one
FOUND RTI


P
IRQ
PIA (6821)



IRQA CA1

IRQB CA2
CS0 PA0
CS1 PA1
CS2 PA2
R/W PA3
E PA4
RS0 PA5
RS1 PA6
PA7

A13
A14
A15
R/W
E
A0
A1

+5v
R
CA1
64
I/O Systems and registers for 68HC11







MC68HC11 block diagram










65
MC68HC11 E series registers

66










67
Port functions

The 68HC11 has five 8-bit ports. Any of these can be used as parallel I/O ports, depending on how
their respective control registers are configured. Of these, ports B and C can only be used for parallel
I/O. Port D is for serial I/O, port A is for programmable timer and port E is for analog/digital
converter.

Any of the port C and D lines can be used as input or output, depending on how their respective data
direction bits are configured. Pin 7 of port A (PA7) is also bidirectional. When port A is used for
parallel I/O, lines 0,1 and 2 are input only and lines 3,4,5 and 6 are output only. Port B is used for
output only. Port E is an input port when used for parallel I/O.

Parallel I/O

Each line carries 1 bit of data word.
All 5 ports on the 68HC11 can be used for parallel I/O.
Mostly used parallel ports are Port B and Port C.
Port B is an output port.
Port C can be configured to be either input or output.
Ports B and C can be used for strobed I/O or full handshake I/O.
Uses: LED, keyboard, printer interface, switches.

Serial I/O

Uses a single line to transmit bits one after the other. This reduces the number of lines but
slows down the rate of data transfer.
May be synchronous or asynchronous.
Port D used for serial I/O
Often used for: Computer connection, modem, mouse, network
One of the most common standards is asynchronous serial which is called the RS-232
interface.

Programmable timer

Port A is used for timer functions such as timed outputs or measuring input times.
Uses: Generate time delays, measure frequency of input signals, measure pulse widths

Analog/digital converter

Converts an analog voltage into a binary number
Port E is used for A/D conversion
Uses: Many physical quantities are represented by anolog values such as temperature,
voltage, pressure, light intensity,...

Summary of port functions

PORT A: Timer operations or parallel I/O
o PA0-PA2 input only
o PA4-PA6 output only
o PA3 and PA7 output or input
PORT B: Upper 8 bits of address bus (expanded multiplexed mode) or parallel I/O
o PB0-PB7 output only
PORT C: Multiplexed address/data bus (expanded multiplexed mode) or parallel I/O
68
o PC0-PC7 input or output
PORT D: Asynchronous serial I/O (PD0-PD1), synchronous serial I/O (PD2-PD5) or parallel
I/O
o PD0-PD5 input or output
PORT E: A/D converter or parallel I/O
o PE0-PE7 input only