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Measurement and Design of a Small-signal Amplifier


Luan Vieira Mendes (SID 43409695)
ELEC376 Engineering Unit
Macquarie University NSW 2019 Australia
E-mail: luan.vieira-mendes@students.mq.edu.br
27 March 2014



Abstract it is described in this report the stages of a small-
signal amplifier construction.
I. INTRODUCTION
The aim of this project was to design, build and test a
small-signal amplifier. According to [4], the function of an
amplifier is to do amplification. Basically, an amplified output
is obtained in the collector circuit when a weak signal is given
as the input in the base of the transistor. It will be described,
in this report, the amplifier building stages which are;
transistor biasing, buffer and cascode stages. The knowledge
acquired in the building and testing of the amplifier was:
Theory
o Transistor characteristics
o Bias configurations
o Bias circuit calculations
o Capacitors coupling and bypass
o Frequency response
o Impedance
o Buffer stage
o Cascode stage
Simulation
o AWR simulation software
o TINA simulation software
Practical
o Components soldering
o Multimeter
o Oscilloscope
o Frequency generator
o Power supply
II. SPECIFICATIONS
After many researches on diodes, transistors, bias
configurations, trans-dependence, buffer, and cascade stage,
the specifications to start designing the amplifier given are:

Gain 25db from source voltage to load
Frequency response: 1kHz to 10MHz
Source resistance 1kohm
Load resistance 50 ohm
Power supply 12v and 1.2mA maximum


III. TASKS DIVISION
The tasks were divided in order to maximize the
knowledge acquired in each stage and the division can be seen
in the table below. Where there is (H/L), read as Hilton and
Luan did together, (L) read as Luan did with Hiltons support,
(H) read as Hilton did with Luans support.

Stage
Common-emitter Buffer Cascode
Designing H/L H/L H/L
Simulation L L L
Building H H H
Testing H/L H/L
IV. TRANSISTOR BIASING
The configuration of the bias used was chosen
according to the project specifications; therefore it was chosen
the common emitter (CE) amplifier as shown in Figure II.1.
The reason of the choice is that this type of configuration
permits a high current power and voltage gain, and a
moderate output to input impedance ratio [3].
An important requirement to do amplification is to
ensure no change in the signal shape with signal magnitude
increase [4]. To certify that, it is required that the input circuit
of the transistor remains forward biased and output circuit
always remains reverse biased during all parts of the signal; it
is known as transistor biasing [4].

Figure II.1 - CE configuration
It is possible to calculate the value of the resistors
using the Kirchhoffs law. The equations are shown on the
Equations II.1.

2

Equations II.1
According to the equations II.1 and the requirements
to build the amplifier, it was calculated the circuit resistors. It
was found the following values:


Figure II.2 - Values found
Due to the unavailability of these values, it was
chosen approximate commercial values which were
120kOhms, 6.8kOhms, 22kOhms, and 1.5kOhms respectively.
As it can be seen in the figure II.3, it was added the
voltage generator, the 10MOhms resistor load, and three
capacitors which have different functions. The first capacitor
(C1) is known as input capacitor and its role is to couple the
signal to the base of the transistor, if it is not used, the bias
will be changed due to the signal source resistance will come
across R3 [3]. The role of the second capacitor (C2) is to
couple the signal to the load, as the second capacitor, if it is
not used, the bias will be changed [3]. The third capacitor
(C3) is known as emitter bypass capacitor and it is used in
parallel with R4 to provide a low reactance path to the
amplified signal in order maximize the gain [3]. The
capacitors were calculated by using the equation II.2.

Equation II.2 Capacitor

Figure II.3 - Amplifier
The figure II.4 shows the simulation graph of the
gain (dB) versus frequency (Hz) of the amplifier with a
10MOhms load resistance due to the oscilloscope used in the
practical and the figure II.4 shows the practical gain graph.
The values obtained in the practical were compared with
those in the simulation.

Figure II.4 Amplifier gain

Figure II.5 - Practical gain graph without load
V. BUFFER STAGE
The next stage of the amplifier project was to design
a buffer and include it in the circuit. According to [6], a buffer
amplifier is an electronic amplifier designed to have an
amplifier gain of 1 and its main objective is that it is used in
impedance matching. As it was given in the specifications, the
1kOhms source resistance should be handled in order to
follow the requirements with 50Ohms in the load.
The figure II.5 shows the circuit with the buffer and
the 1MOhms load resistance. In the practical, it was used the
oscilloscope with the 1MOmhs impedance to check the values
instead of the 50Ohms load resistance which was not added in
order to facilitate the building due to this was the intermediate
stage.

Figure II.5 - Buffer
Vcc = (R1)x(i1)+(R3)x(i3)
Vcc-0.7 = (R1)x(i1)+(R4)x(i4)
Vcc-Vce = (R2)x(i2)+(R4)x(i4)
i4 = (i2)+(ib)
i3 = (i1)+(ib)
ib =
i3
R1 = 122kOhms
R2 = 6kOhms
R3 = 23kOhms
R4 = 1.5kOhms
Xc =
1
2 f C
T
Frequency [Hz]
100.00 1.00k 10.00k 100.00k 1.00M 10.00M 100.00M
G
a
i
n

[
d
B
]
0.0
10.0
20.0
30.0
40.0
50.0
1
10
100
0.1 10 1000
G
a
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n

(
d
B
)

Frequency (kHz)
Practical
Gain

3
It was calculated the resistance (R5) according to the
equation below and the approximate commercial value found
in order to obtain at the most 1.2mA in the power supply was
39kOhms.

Equation II.2
The figure II.6 shows the gain graph of the circuit
with the buffer using the simulator software and the figure
II.7 is the gain graph of the values measured in the practical.

Figure II.6 - Gain with buffer

Figure II.7 - Gain with buffer (practical)
VI. CASCODE STAGE
The last part of our project was to design and add the
cascode in the circuit. According to [1], a cascode eliminates
the Miller effect, which is the increase in the equivalent
capacitance of an inverting voltage amplifier due to the
capacitance effect between the input and output [1], and
contributes to a much higher bandwidth by improving the
input-output isolation.
The figure II.9 shows the final circuit on the
simulation software with the cascode and 50Ohms resistor
load added. As can be seen in the figure, it was added C2 and
R6; and R1 had to be recalculated, by using the Kirchhoffs
law, due to the addition of R6. In addition, the bypass
capacitor was changed to 2uF in order to obtain a better gain
around the 1 KHz frequency.

Figure II.8 - Final circuit
After the recalculation and simulation processes, the
final circuit was welded and so ready to be measured. There
was no time to obtain, in the practical, the measurements of
the final circuit, however, the final graph, which was obtained
by using the simulator software, is shown in the figure II.9.

Figure II.9 - Final graph gain
VII. CONCLUSIONS
The aim of the project was to design, build and test a small-
signal amplifier. Three main steps were fundamentals to the
construction of the amplifier which were: transistor biasing,
buffer stage, and cascode stage. The total source current of the
project was 982uA, and it was obtained approximately 20dB
gain in the 1 kHz frequency, 22dB gain in the 1 MHz
frequency, and the mid-band gain approximately 27dB. It can
be concluded that according to the specifications; the small-
signal amplifier was successful built.
REFERENCES
[1] F. Dennis, Cascode amplifiers.
[2] L. Jim, Buffer and current amplifiers, viewed in 29 march
2014.
[3] Principle of electronics, Transistors Chapter 8, viewed in 29
march 2014.
[4] Principle of electronics, Transistor Biasing Chapter 9,
viewed in 29 march 2014.
[5] Principle of electronics, Single stage transistor amplifiers
Chapter10, viewed in 29 march 2014.
[6] Texas Instruments, Applications of wide-band buffer
amplifiers, viewed in 29 march 2014.
VCC = (R2)x(i2) + (0.7) + (R5)x(i5)
T
Frequency [Hz]
100.0 1.0k 10.0k 100.0k 1.0M 10.0M 100.0M
G
a
i
n

[
d
B
]
0.0
10.0
20.0
30.0
40.0
50.0
1
10
100
0.1 10 1000
G
a
i
n

(
d
B
)

Frequency (kHz)
Practical
Gain
T
Frequency [Hz]
100.00 1.00k 10.00k 100.00k 1.00M 10.00M
G
a
i
n

[
d
B
]
0.0
10.0
20.0
30.0

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