1

Data Converter Architectures

Walt Kester, Analog Devices

INTRODUCTION

Today's signal processing and data acquisition applications span the frequency
spectrum from precision industrial weigh scale measurements to software radios for
cellular telephone basestationsto name only a few. Selecting the proper ADC for the
application can be a daunting task for system design engineers. While IC manufacturers'
selection guides and parametric search engines can be quite useful, a fundamental
understanding of basic ADC architectures is invaluable in optimizing the converter
selection process. Rather than simply treating the ADC as a "black box," the engineer
who understands the basic architectures is not only much better equipped to select the
proper data converter but to also design the required input and output interface circuits.

In addition to high resolutions, high sampling rates, and excellent ac performance,
modern data converters offer low power, small surface mount packages, and low cost. In
order to achieve these objectives, nearly all data converters are fabricated on fine-line
geometry, low voltage CMOS or BiCMOS processes. While not a disadvantage in digital
circuits, operating data converters at low supply voltages can present challenges not only
to the IC designer but to the customer who must apply the devices and design the proper
interfaces. Some of these issues will be addressed later in this paper. Also, in order to
maintain good dc performance at low cost, calibration techniques using link trimming or
volatile and non-volatile on-chip memory have largely replaced expensive thin film
resistor laser wafer trimming.

The most popular ADC architectures today are successive approximation, sigma-
delta (-), and pipelined. Figure 1 shows how these architectures relate to resolution
(number of bits in the ADC), sampling rate, and applications. The dotted line shows the
approximate state-of-the-art in commercial converter offerings. The rest of this paper
discusses each of these architectures, placing the emphasis application issues.

SUCCESSIVE APPROXIMATION (SAR) ADCs

The successive approximation ADC architecture has been the backbone of data
acquisition systems from the modular and hybrid devices of the 1970s to modern low
power ICs of today. The architecture was utilized by Bell Labs in vacuum tube ADCs in
the 1940s, and Bernard Gordon introduced the first commercial vacuum tube SAR ADC
in 1954.
2
















Figure 1: ADC Architectures, Applications, Resolution, Sampling Rates

The basic SAR architecture is shown in Figure 2. In order to process ac signals,
SAR ADCs have an input sample-and-hold (SHA) to keep the signal constant during the
conversion cycle. The conversion starts with the internal DAC set to midscale. The
comparator determines whether the SHA output is above or below the DAC output, and
the result (bit 1, the most significant bit of the conversion) is stored in the successive
approximation register (SAR). The DAC is then set either to scale or scale
(depending on the value of bit 1), and the comparator makes the decision for bit 2 of the
conversion. The result is stored in the register, and the process continues until all of the
bit values have been determined. At the end of the conversion process, a logic signal
(EOC, DRDY, BUSY, etc.) is asserted. The acronym, SAR, actually stands for Successive
Approximation Register (the logic block that controls the conversion process), but is
universally accepted as the acronym for the architecture itself.













Figure 2: Basic Successive Approximation ADC
SHA
CONTROL
LOGIC:
SUCCESSIVE
APPROXIMATION
REGISTER
(SAR)
DAC
TIMING
CONVERT
START
EOC,
DRDY,
OR BUSY
OUTPUT
ANALOG
INPUT
COMPARATOR
10 100 1k 10k 100k 1M 10M 100M 1G
8
10
12
14
16
18
20
22
24
-
-
SAR
PIPELINE
INDUSTRIAL
MEASUREMENT
VOICEBAND,
AUDIO
DATA ACQUISITION
VIDEO, IF SAMPLING,
SOFTWARE RADIO, ETC.
SAMPLING RATE (Hz)
R
E
S
O
L
U
T
I
O
N

(
B
I
T
S
)
CURRENT
STATE-OF-THE-ART
(APPROXIMATE)
3
The timing diagram for a typical SAR ADC is shown in Figure 3. The exact labels
assigned to these functions can vary from converter to converter, but are generally
present in most SAR ADCs. Note that at the end of the conversion time, the data
corresponding to the sampling clock edge is available with no "pipeline" delay. This
makes the SAR ADC easy to use in multiplexed applications.











Figure 3: Typical SAR ADC Timing

Modern IC SAR ADCs are available in resolutions from 8 to 18 bits, and
sampling rates up to several MHz. Output data is generally provided on a standard serial
interface (I
2
C

or SPI

, for example), although some devices have parallel outputs at the

obvious expense of increasing the pin count and package size. The internal DAC is a
critical part of a SAR ADC, since it determines the overall accuracy. Early IC SAR
ADCs, such as the AD574, utilized laser wafer trimmed DACs; however, modern ones
use switched capacitor DACs as shown in Figure 4 which not only reduce the cost but
reduce the settling time. The capacitor matching is controlled by the precise lithography,
and extra capacitors and switches can be added for linearity trimming either at the factory
or as part of autocalibration routines run at the system level after installation.












Figure 4: 3-Bit Switched Capacitor DAC

Because CMOS is the ideal process for analog switches, the addition of input
multiplexers to the basic SAR ADC function is relatively straightforward and allows the
CONVST
CONVERSION
TIME
SAMPLE X SAMPLE X+1 SAMPLE X+2
DATA
X
DATA
X+1
OUTPUT
DATA
EOC,
BUSY
EOC,
BUSY
TRACK/
ACQUIRE
CONVERSION
TIME
TRACK/
ACQUIRE
_
+
_
+
C/ 4 C/ 2 C C/ 4
A
IN
V
REF
S
IN
S
C
S1 S2 S3 S4
BIT1
(MSB)
BIT2 BIT3
(LSB)
SWITCHES SHOWN IN
TRACK (SAMPLE) MODE
AA
C
TOTAL
= 2C
4
integration of a complete data acquisition system on a single chip. Additional digital
functionality is also easy to add to SAR-based ADCs, and features such as multiplexer
sequencing, autocalibration circuitry, etc., are becoming common.

SIGMA-DELTA (-) ADCs

The basic concepts behind the - ADC architecture had their origins in the
1950s in work done at Bell Labs on experimental digital transmission systems utilizing
delta modulation and differential PCM. By the end of the 1960s, the - architecture was
well understood. However, because digital filters were an integral part of the architecture,
practical IC implementations did not occur until the late 1980s when digital CMOS
processes became widely available. The basic concepts of - are oversampling, noise
shaping, digital filtering, and decimation and are illustrated in Figure 5.















Figure 5: Oversampling, Digital filtering, Noise Shaping, and Decimation

Figure 5A shows traditional Nyquist operation, where the ADC input signal falls
between dc and f
s
/2, and the quantization noise is uniformly spread over the same
bandwidth. In Figure 5B, the sampling frequency has been increased by a factor of K (the
oversampling ratio), but the input signal bandwidth remains the same. The quantization
noise falling outside the signal bandwidth is then removed with a digital filter. The output
data rate can now be reduced (decimated) back to the original f
s
frequency. Notice that
this process of oversampling followed by digital filtering and decimation has increased
the SNR within the Nyquist bandwidth, dc to f
s
/2. Each time K is double, the SNR within
the dc to f
s
/2 bandwidth is increased by 3 dB. Figure 5C shows the basic - architecture,
where the traditional ADC is replaced by a - modulator. Notice that the effect of the
modulator is to shape the quantization noise so that most of it occurs outside the
bandwidth of interest, thereby greatly increasing the SNR in the dc to f
s
/2 region.

f
s
2
f
s
2
f
s
Kf
s
2
Kf
s
Kf
s Kf
s
2
f
s
2
DIGITAL FILTER
REMOVED NOISE
REMOVED NOISE
QUANTIZATION
NOISE = q / 12
q = 1 LSB
ADC
ADC
DIGITAL
FILTER

MOD
DIGITAL
FILTER
f
s
Kf
s
Kf
s
DEC
f
s
Nyquist
Operation
Oversampling
+ Digital Filter
+ Decimation
Oversampling
+ Noise Shaping
+ Digital Filter
+ Decimation
A
B
C
DEC
f
s
5
The basic first-order - ADC is shown in Figure 6, where the - modulator is
shown in some detail.














Figure 6: First-Order Sigma-Delta ADC

The output of the modulator is a 1-bit stream of data. Because of negative
feedback, the signal at B must (on the average) equal V
IN
. If V
IN
is zero (midscale), there
are an equal number of "1"s and "0"s in the output data stream. As the input signal goes
more positive, the number of "1"s increases, and the number of "0"s decreases. Likewise,
as the input signal goes more negative, the number of "1"s decreases, and the number of
"0"s increases. The dc value of the input must therefore equal to the ratio of the "1"s in
the output stream to the total number of samples in the same interval, i.e., the ones-
density. The modulator also accomplishes the noise shaping function by acting as a
lowpass filter for the signal and a highpass filter for the quantization noise. Note that the
digital filter is an integral part of the - ADC, and it can be optimized to give excellent
50-Hz/60-Hz power line rejection. However, the digital filter does introduce inherent
pipeline delay which definitely must be considered in multiplexed and servo applications.

Although the simple first-order single-bit - ADC is inherently linear and
monotonic because of the 1-bit ADC and 1-bit DAC, it does not provide sufficient noise
shaping for high resolution applications. Increasing the number of integrators in the
modulator (similar to adding poles to a filter) provides more noise shaping at the expense
of a more complex design as shown in Figure 7. Higher order modulators (greater than 3
rd

order) are difficult to stabilize and present significant design challenges.

A popular alternative to higher order modulators is to use the multbit architecture,
where the simple comparator is replaced with an N-bit flash converter, and the single-bit
DAC is replaced with a highly linear N-bit DAC. Techniques such as data scrambling are
used to achieve the required linearity of the internal ADC and DAC in multibit - ADC.
This avoids the need for expensive laser trimming.

+
_
+V
REF
V
REF
DIGITAL
FILTER
AND
DECIMATOR
+
_
CLOCK
Kf
s
V
IN
N-BITS
f
s
f
s
A
B
1-BIT DATA
STREAM
1-BIT
DAC
LATCHED
COMPARATOR
(1-BIT ADC)
1-BIT,
Kf
s
SIGMA-DELTA MODULATOR
INTEGRATOR
6











Figure 7: Sigma-Delta Modulators Shape Quantization Noise

While older integrating architectures such as dual-slope are still used in digital
voltmeters, CMOS sigma-delta ADCs are the dominant converter for today's industrial
measurement applications. These converters offer excellent 50-Hz/60-Hz power line
common-mode rejection and resolutions up to 24 bits with various digital features, such
as on-chip calibration. Many have programmable gain amplifiers (PGAs) which allow the
direct digitization of small signals from bridge and thermocouple transducers without the
need for additional external signal conditioning circuits. Figure 8 shows a direct
connection between a bridge-based load cell and a high resolution - ADC, the
AD7730. The fullscale bridge output of 10 mV is digitized to approximately 14.5 noise-
free bits by the ADC at a throughput rate of 200 Hz. Ratiometric operation eliminates the
need for a precision voltage reference.















Figure 8: Load Cell Conditioning Using a High Resolution Sigma-Delta ADC

In addition to providing attractive solutions for a variety of industrial
measurement applicationssensor monitoring, energy metering, and motor controlthe
- converter dominates modern voiceband and audio applications. A major benefit of
f
s
2
Kf
s
2
2ND ORDER
1ST ORDER
DIGITAL
FILTER
AD7730 was designed for bridge transducers
Chopper, Buffer, PGA, Digital filter, tare DAC, Calibrations,
Fully Ratiometric, changes on V
EXC
= V
REF
eliminated
Load V
OUT
/ V
EXC
, AD7730 Data V
IN
/ V
REF
, V
REF
= V
EXC
V
EXC
= +5V
V
REF
= +5V
AIN = 10mV
ADC
24-BIT
CALIBRATION
HOST
SYSTEM
DIGITAL
AD7730
+5V
V
DD
= +5V
FORCE
FORCE
SENSE
SENSE
7
the high oversampling rate associated with - converters is the simplification of the
input anti-aliasing filter for the ADC and the output anti-imaging for the DAC. In
addition, the ease of adding digital functionality to a CMOS-based converter makes
features such as digital filter programmability practical with only small increases in
overall die area, power, and cost.

PIPELINED ADCs

Although the flash (all-parallel) architecture dominated the 8-bit video IC ADC
market in the 1980s and early 1990s, the pipelined architecture has relegated the flash
ADC to a relatively small number of high power Gallium Arsenide (GaAs) converters
where sampling rates greater than 1 GHz are required with resolution of 6 or 8 bits. Of
course, the flash architecture still remains a popular building block for higher resolution
pipelined ADCs.

The pipelined ADC had its origins in the subranging architecture which was first
used in the 1950s. A block diagram of the subranging architecture is shown in Figure 9,
where a 6-bit, two-stage ADC is shown.
















Figure 9: 6-Bit, Two-Stage Subranging ADC

The output of the SHA is digitized by the first-stage 3-bit sub-ADC (SADC)
usually a flash converter. The coarse 3-bit MSB conversion is then converted back to an
analog signal using a 3-bit sub-DAC (SDAC). The SDAC output is then subtracted from
the SHA output, amplified, and applied to a second-stage 3-bit SADC. The "residue
signal" is then digitized by the 3-bit second-stage SADC, thereby generating the three
LSBs of the total 6-bit output word. This subranging ADC can best be analyzed by
examining the residue waveform at the input to the second-stage ADC as shown in Figure
10. This waveform assumes a low frequency ramp input signal to the overall ADC. In
SAMPLE
AND HOLD

+

OUTPUT REGISTER
ANALOG
INPUT
DATA OUTPUT, N-BITS = N1 + N2 = 3 + 3 = 6
CONTROL
SAMPLING
CLOCK
See: R. Staffin and R. Lohman, " Signal Amplitude Quantizer,"
U.S. Patent 2,869,079, Filed December 19, 1956, Issued January 13, 1959
RESIDUE
SIGNAL
N1 MSBs (3) N2 LSBs (3)
G
N1-BIT
(3-BIT)
SADC
N1-BIT
(3-BIT)
SDAC
N2-BIT
(3-BIT)
SADC
8
order for there to be no missing codes or, the residue waveform must exactly fill the input
range of the second-stage ADC, as shown in the ideal case of Figure 10A. This implies
that both the N1 SADC and the N1 SDAC must be better than N1 +N2 bits accuratein
the example shown, N1 =3, N2 =3, and N1 +N2 =6. This architecture, as shown, is
useful for resolutions up to about 8 bits (N1 =N2 =4), however maintaining better than
8-bit alignment between the two stages (over temperature variations, in particular) can be
difficult. The situation shown in Figure 10B will result in missing codes when the residue
waveform goes outside the range of the N2 SADC, "R", and falls within the "X" or "Y"
regionscaused by a nonlinear N1 SADC or interstage gain and/or offset mismatch .















Figure 10: Residue Waveform at Input of Second-Stage SADC

At this point it is worth noting that there is no particular reasonother than
certain design issues beyond the scope of this discussionwhy there must be an equal
number of bits per stage in the subranging architecture. In addition, there can be more
than two stages. Regardless, the architecture as shown in Figure 9 is limited to
approximately 8-bit resolution unless some form of error correction is added.

The error corrected subranging ADC appeared in the mid-1960s as an efficient
means to achieve higher resolutions with the subranging architecture. In the two-stage
subranging ADC, for example, an extra bit is added to the second-stage ADC which
allows the digitization of the regions shown as "X" and "Y" in Figure 10. The extra range
in the second-stage ADC allows the residue waveform to deviate from its ideal value
provided it does not exceed the range of the second-stage ADC. However, the internal
SDAC must still be accurate to more than the overall resolution, N1 +N2.

A basic 6-bit subranging ADC with error correction is shown in Figure 11, where
the second-stage resolution is increased to 4 bits, rather than the original 3 bits. Logic is
also required to modify the results of the N1 SADC when the residue waveform falls in
the "X" or "Y" over range regions. This is implemented with a simple adder in
MISSING CODES
MISSING CODES
R = RANGE
OF N2 SADC
X
R
Y
(A)
IDEAL
N1 SADC
(B)
NONLINEAR
N1 SADC
9
conjunction with a dc offset voltage added to the residue waveform. In this arrangement,
the MSB of the second-stage SADC controls whether the MSBs are incremented by 001
or passed through unmodified.



















Figure 11: 6-Bit Subranging Error Corrected ADC, N1 = 3, N2 = 4

It should be noted that more than one correction bit can be used in the second-
stage ADCbut this type of tradeoff is part of the converter design process, and not the
subject of this discussion.

The error-corrected subranging ADC shown in Figure 11 does not have pipeline
delay. The input SHA remains in the hold mode during the time required for the
following events occur: the first-stage SADC makes its decision, its output is
reconstructed by the first-stage SDAC, the SDAC output is subtracted from the SHA
output, amplified, and digitized by the second-stage SADC. After the digital data passes
through the error correction logic and the output registers, it is ready for use, and the
converter is ready for another sampling clock input.

The pipelined architecture shown in Figure 12 is a digitally corrected subranging
architecture in which each stage operates on the data for the entire conversion cycle and
then passes its residue output to the next stage in the pipeline, prior the next conversion
cycle. The interstage track-and-hold (T/H) serves as an analog delay linetiming is set
such that it enters the hold mode when the first stage conversion is complete. This gives
more settling time for the internal SADCs, SDACs, and amplifiers, and allows the
pipelined converter to operate at a much higher overall sampling rate than a non-
pipelined version.
SAMPLE
AND HOLD

+

OVERRANGE LOGIC AND OUTPUT REGISTER

ANALOG
INPUT
DATA OUTPUT
CONTROL
SAMPLING
CLOCK
ADDER ( + 001 )
RESIDUE
SIGNAL
MSB
CARRY
G
SEE: T. C. Verster, " A Method to Increase the Accuracy of Fast Serial-
Parallel Analog-to-Digital Converters," IEEE Transactions on Electronic
Computers,EC-13, 1964, pp. 471-473
OFFSET
OFFSET
N1
3-BIT
SADC
N1
3-BIT
SDAC
N2
4-BIT
SADC
10








Figure 12: Generalized Pipeline Stages in a Subranging ADC with Error Correction

There are many design tradeoffs that can be made in the design of a pipelined
ADC, such as the number of stages, the number of bits per stage, number of correction
bits, etc. In order to ensure that the digital data from the individual stages corresponding
to a particular sample arrives at the error correction logic simultaneously, the appropriate
number of shift registers must be added to the outputs of the pipelined stagese.g., if the
first stage requires 7 shift register delays, the next stage will require 6, the next 5, etc.
This adds a digital pipeline delay to the final output data as shown in Figure 13.













Figure 13: Typical Pipelined ADC Timing for AD9235 12-Bit, 65-MSPS ADC

For the AD9235 12-bit, 65-MSPS ADC shown in Figure 13, there are seven clock
cycles of pipeline delay (sometimes referred to as latency). This latency may or may not
be a problem, depending upon the application. If the ADC is within a feedback control
loop, latency may be a problemthe successive approximation architecture would be a
better choice. Latency also makes pipelined ADCs difficult to use in multiplexed
applications. However, in the bulk of applications where pipelined ADCs are suitable, the
latency issue is not a real problem.

A subtle issue relating to most CMOS pipelined ADCs is their performance at low
sampling rates. Because the internal timing generally is controlled by the external
sampling clock, very low sampling rates extend the hold times for the internal track-and-
holds to the point where excessive droop causes conversion errors. Therefore, most
SADC
N1 BITS
SDAC
N1 BITS
T/H
+

T/H
+

SADC
N2 BITS
SDAC
N2 BITS

+

TO ERROR CORRECTING LOGIC

T/H,
G
PIPELINE DELAY (LATENCY) = 7 CLOCK CYCLES
11
pipelined ADCs have a specification for minimum as well as maximum sampling rate.
Obviously, this precludes operation in single-shot or burst-mode applicationswhere the
SAR ADC architecture is more appropriate.

Finally, there is some confusion about the distinction between subranging and
pipelined ADCs. From the discussions above, it can be stated that although pipelined
ADCs are generally subranging (with error correction, of course), subranging ADCs are
not necessarily pipelined. In reality, however, the pipelined architecture is predominant
because of the demands for high sampling rates where internal settling time is of utmost
importance.

Pipelined ADCs are available today with resolutions up to 14 bits with sampling
rates over 100 MHz. They are ideal for many applications which require not only high
sampling rates but high signal-to-noise ratio (SNR) and spurious free dynamic range
(SFDR). A popular application for these converters today is in software defined radios
(SDR) used in modern cellular telephone basestations.

A simplified diagram of a generic software radio receiver and transmitter is
shown in Figure 14. Notice that rather than digitize each channel separately in the
receiver, the entire bandwidth containing many channels is digitized directly by the ADC.
The channel filtering, tuning, and separation is performed digitally in the receive signal
processor (RSP) by a high performance DSP. Digitizing the frequency band at a
relatively high intermediate frequency (IF) eliminates several stages of down conversion
and thereby leads to a lower cost, more flexible solutionmost of the signal processing
is performed digitally, rather than in more complex analog circuitry associated with
standard analog superheterodyne radio receivers. In addition, various air standards (GSM,
CDMA, EDGE, etc.) can be processed by the same hardware simply by making
appropriate changes in the software. Note that the transmitter in the software radio uses a
transmit signal processor (TSP) and DSP to format the individual channels for
transmission via the upstream DAC.













Figure 14: Generic IF Sampling Wideband Software Radio Receiver and Transmitter
ADC
RSP,
DSP
LO
IF
TSP,
DSP
DAC
IF
LO
LNA
PA
CHANNELS
CHANNELS
RECEIVER
TRANSMITTER
RF
RF
BPF BPF
BPF BPF
MIXER
MIXER
12
The basic concept of IF sampling is shown in Figure 15, where a 25-MHz band of
signals is digitized at a rate of 65 MSPS. The signal bandwidth of interest is centered in
the second Nyquist zone at an IF frequency of 48.75 MHz. Note that the numbers chosen
in this example are somewhat arbitrary, but they illustrate the concept of undersampling.
These applications place severe requirements on the ADC performance, especially with
respect to SNR and SFDR. This is because digitizing the entire bandwidth of signals
allows large amplitude "blockers" to be present along with the signals of interest. Any
distortion produced by these blockers limit the ability of the receiver to detect the lower
amplitude signals of interest.












Figure 15: Sampling a 25-MHz Bandwidth Signal:
IF Frequency = 48.75 MHz, f
s
= 65 MSPS

The specific requirements in terms of ADC sampling rate, SFDR and SNR for a
wideband receiver depend upon the particular air standards as shown in Figure 16. It
should be noted that ADCs are generally available for use in designing wideband
receivers for most of these standards.













Figure 16: Approximate Wideband ADC Requirements for Popular
Wireless Air Interface Standards

0
f
s
= 65MSPS
ZONE 1
IF = 48.75MHz
SIGNAL BW = 25MHz
32.5 65 97.5
f(MHz)
ZONE 2 ZONE 3
IF
MULTIPLE
ACCESS
METHOD
FDMA
TDMA/FDM
TDMA/FDM
TDMA/FDM
CDMA
CDMA
CDMA
CHANNEL
SPACING
(BW)
30kHz
30kHz
200kHz
200kHz
1.25MHz
1.25MHz
5MHz
TYPICAL
TOTAL
BW
12.5MHz
5-15MHz
5-15MHz
5-15MHz
5-15MHz
5-15MHz
5-20MHz
ADC
SAMPLING
RATE (TYP.)
61.44MSPS
61-92MSPS
61-92MSPS
61-92MSPS
61-92MSPS
61-92MSPS
61-92MSPS
ADC
SFDR
96dBc
88dBc
106dBc
93dBc
83dBc
79dBc
79dBc
ADC
SNR
72dBFS
68dBFS
85dBFS
75dBFS
74dBFS
74dBFS
69dBFS
AMPS
IS-136
GSM 900 MHz
GSM 1800/1900MHz, PCS
IS-95
CDMA2000
WCDMA (UMTS)
13
Evaluating ADCs for wideband applications such as software radios is much
easier because of the availability of evaluation boards and software from manufacturers
such as Analog Devices. Many times, the ac specifications for the specific sampling rate
and signal frequency is not directly given on the data sheet. The evaluation board allows
the user to evaluate the ADC under the precise system operating conditions. Figure 17
shows the Analog Devices' high speed ADC FIFO (first-in, first-out) evaluation kit. The
FIFO collects a record of data from the high speed ADC, and the data is then transferred
to the PC via the parallel or USB port. The ADC Analyzer software then calculates the
FFT, SFDR, SNR, etc., for display on the monitor.


















Figure 17: Analog Devices' High Speed ADC FIFO Evaluation Kit

In addition to a variety of evaluation boards, Analog Devices recently introduced
its ADIsimADC

evaluation software which models the performance of various

wideband ADCs. This software models the effects of converter nonlinearity, noise,
aperture jitter, etc. It is basically a virtual evaluation board which allows users to select a
particular ADC, insert the model into the software, and evaluate the ADC performance
on their PC.

SUMMARY

This paper has discussed the successive approximation, sigma-delta, and
pipelined architecturesby far the most popular in modern integrated circuit ADCs.
Successive approximation is the architecture of choice for nearly all multiplexed data
acquisition systems. The SAR ADC is relatively easy to use, has no pipeline delay, and is
available in resolutions to 18 bits and sampling rates up to 3 MSPS. For a wide variety of
industrial measurement applications, the sigma-delta ADC is ideal, and is available in
FFT DISPLAY
AND ANALYSIS
ADC Analyzer
Software
ADC
EVALUATION BOARD
FIFO BOARD
PC PARALLEL PORT
OR USB INTERFACE
14
resolutions from 12 to 24 bits. Sigma-delta ADCs are suitable for a wide variety of sensor
conditioning, energy monitoring, and motor control applications. The voiceband and
audio market is also dominated by the sigma-delta ADC and DAC, which are easily
integrated into ICs containing a high degree of digital functionality. For sampling rates
greater than approximately 5 MSPS, the pipelined architecture dominates. These
applications typically require high SFDR and SNR and resolutions up to 14 bits at
sampling frequencies ranging from 5 MSPS to greater than 100 MSPS.

The use of manufacturer's selection guides and parametric search engines,
coupled with a fundamental knowledge of the basic architectures, should help the
designer select the proper ADC for the application. The use of evaluation boards and
software, such as the ADIsimADC

models, can assist in the process. Designing the

proper input, output, and sampling clock interface circuitry is also a critical part of the
design, and data sheets and application notes should be consulted regarding this
important issue. Finally, probably the most important aspects of achieving a successful
mixed-signal design are layout, grounding, and decoupling. For a detailed treatment of
these and other design issues, the reader is encouraged to consult the two comprehensive
texts listed in the references as well as the Analog Devices' website.

REFERENCES

1. Walt Kester, Editor, Data Conversion Handbook, Published by Newnes, an
imprint of Elsevier, 2005, ISBN: 0-7506-7841-0.

2. Walt J ung, Editor, Op Amp Applications Handbook, Published by Newnes, an
imprint of Elsevier, 2005, ISBN: 0-7506-7844-5.

3. For more information on products or applications, please visit the Analog
Devices, Inc. website: http://www.analog.com