Electronics System Design Lab VII Sem ECE

EC 2404 ELECTRONICS SYSTEM DESIGN LAB

1. Design of a 4-20mA transmitter for a bridge type transducer.
Design the Instrumentation amplifier with the bridge type transducer (hermistor
or any resistance !ariation transducers" and con!ert the amplified !oltage from
the instrumentation amplifier to 4 # 20 mA current using op-amp. $lot the
!ariation of the temperature %s output current.
2. Design of A&'D& !oltage regulator using (&)
Design a phase controlled !oltage regulator using full wa!e rectifier and (&)*
!ary the conduction angle and plot the output !oltage.
+. Design of process control timer
Design a se,uential timer to switch on - off at least + relays in a particular
se,uence using timer I&.
4. Design of A. ' /. modulator ' demodulator
i. Design A. signal using multiplier I& for the gi!en carrier fre,uency and
modulation inde0 and demodulate the A. signal using en!elope detector.
ii. Design /. signal using %&1 I& 23455 for the gi!en carrier fre,uency and
demodulate the same using $66 23 454.
4. Design of 7ireless data modem.
Design a /(8 modulator using 444'9) 2205 and con!ert it to sine wa!e using
filter and transmit the same using I) 63D and demodulate the same $66 23
454'9) 2212.
5. $&: layout design using &AD
Drawing the schematic of simple electronic circuit and design of $&: layout
using &AD
;. .icrocontroller based systems design
Design of microcontroller based system for simple applications li<e security
systems combination loc<.
=. D($ based system design
Design a D($ based system for echo cancellation* using .('AD($ D($ <it.
>. $suedo-random (e,uence ?enerator
10. Arithmetic 6ogic @nit Design
2oteA 8its should not be used. Instead each e0periment may be gi!en as mini proBect.
1A6C 44 $3)I1D(
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Electronics System Design Lab VII Sem ECE
I2D39
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(.2o. 30periment 2ame
1 Design of a 4-20mA transmitter for a bridge type transducer
2 A&'D& !oltage regulator using (&)
+ Design of process control timer
4 a" Design of A. modulator ' demodulator
b" Design of /. modulator
4 Design a /(8 modulator using 9) 2205
5 $&: layout design using &AD
; $suedo-random (e,uence ?enerator
= Arithmetic 6ogic @nit Design
> .icrocontroller based systems design
10 D($ based system design
Electronics System Design Lab VII Sem ECE
1. DESIGN OF A 4-20mA TRANSMITTER FOR A BRIDGE TYPE
TRANSDUCER.
AIM:
o design the instrumentation amplifier with the bridge type transducer and con!ert the
amplified !oltage from the instrumentation amplifier to 4-20mA current using op-amp.
SOFTWARE REQUIRED:
1rcad
THEORY:
In a number of industrial and consumer applications physical ,uantities such as
temperature* pressure and light intensity are to be measured and controlled. hese physical
,uantities measured with the help of transducers ha!e to be amplified so that it can dri!e the
display system. his function is performed by an instrumentation amplifier.
he circuit uses a resisti!e transducer whose resistance changes as a function of the
physical ,uantity to be measured. he bridge is initially balanced by a dc supply so that %
1
C%
2
.
As the physical ,uantity changes* the resistance )

of the transducer also changes* causing an

unbalance in the bridge (%
1
D%
2
". his differential !oltage gets amplified by the three op-amp
differential instrumentation amplifier. he amplified !oltage is con!erted to current using %-I
con!erter.
he important features of instrumentation amplifier areA
1. Eigh ?ain Accuracy
2. Eigh &.))
+. Eigh ?ain (tability 7ith 6ow emperature &oefficient
4. 6ow Dc 1utput
4. Eigh 1utput Impedance
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Electronics System Design Lab VII Sem ECE
DESIGN:
A sensistor is a type of resistor whose resistance changes with temperature.
Instrumentation AmplifierA
6et %
1
C 2.+!
%
2
C 2.4!
%
0
C 4!
Assume )
F
C 44<
) C 10<
%
0
C )
2
')
1
(1G>0<'10<"(0.2!"
4! C )
2
')
1
(1G>0<'10<"(0.2!"
4 C 2)
2
')
1
)
2
')
1
C 2.
6et )
1
C 40<
)
2
C 100<
% - I &on!erterA
6et %
0
C 4!
I
0
C =mA
) C %
0
' I
0
) C 400H
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Electronics System Design Lab VII Sem ECE
CIRCUIT DIAGRAM:
U 5
u A 7 4 1
3
2
7
4
6
1
5
+
-
V
+
V
-
O U T
O S 1
O S 2 0
V 5
1 5 V d c
V 9
1 5 V d c
U 2
u A 7 4 1
3
2
7
4
6
1
5
+
-
V
+
V
-
O U T
O S 1
O S 2
U 3
u A 7 4 1
3
2
7
4
6
1
5
+
-
V
+
V
-
O U T
O S 1
O S 2
0
V
R 1 4 1
5 k
2
1
R 1 1
5 0 0
2 1
V 1 2
1 5 V d c
I
R 8
1 0 0 k
2 1
0
R 1 5 1
5 k
2
1
R 2 0
5 0 0
2 1 R 4
1 0 k
2
1
R 1 2 1
5 k
2 1
V 1 1 1
1 5 V d c
R 1 0
1 0 0 k
2 1
0
R 6
5 0 k
2 1
V
0
0
R 5
4 5 k
2
1
0
R 1 3 1
5 . 5 k
2 1
V 1 1 5
5 V d c
0
R 7
5 0 k
2 1
V
V 8
1 5 V d c
V 7
1 5 V d c
U 1 0
L M 7 4 1
3
2
7
4
6
1
5
+
-
V
+
V
-
O U T
O S 1
O S 2
0
V 3 0
1 5 V d c
0
R 3
4 5 k
2
1
V 4
1 5 V d c
0
0
PINDIAGRAM of IC4!:
PROCEDURE:
1. &onnections are gi!en as per the circuit diagram.
2. @se $($I&3 simulator and run.
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Electronics System Design Lab VII Sem ECE
3. 2ote down the input !oltages applied to the IA* output !oltage of IA and output current.
4. %ary the resistance !alue and note down the readings.
4. $lot the !ariation of resistance %s output current.
TABULATION:
(l.2o )esistance
(<H"
Input
%oltage
(%
1
" !olts
Input %oltage
(%
2
" !olts
1utput
%oltage
(%
0
"!olts
1utput
&urrent
(I
0
"mA
RESULT:
hus the instrumentation amplifier with the bridge type transducer was designed
and the amplified !oltage was con!erted to current.
"I"A QUESTIONS:
1. 7hat is Instrumentation AmplifierI
2. 30plain the wor<ing of the circuit.
+. 7hen will wheat stone bridge be balancedI
4. ?i!e the important features of IA.
4. 7hat is a transducerI
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Electronics System Design Lab VII Sem ECE
2. AC#DC "OLTAGE REGULATOR USING SCR
AIM:
o construct a phase controlled !oltage regulator using full wa!e rectifier and (&).
SOFTWARE:
1r&ad
THEORY:
In phase control the hyristors are used as switches to connect the load circuit to the
input ac supply* for a part of e!ery input cycle. hat is the ac supply !oltage is chopped using
hyristors during a part of each input cycle. he thyristor switch is turned on for a part of e!ery
half cycle* so that input supply !oltage appears across the load and then turned off during the
remaining part of input half cycle to disconnect the ac supply from the load. :y controlling the
phase angle or the trigger angle J K (delay angle"* the output ).( !oltage across the load can
be controlled. he trigger delay angle J K is defined as the phase angle (the !alue of t" at
which the thyristor turns on and the load current begins to flow.
CIRCUIT DIAGRAM:
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Electronics System Design Lab VII Sem ECE
R 1 0
1 k
2 1
I
X 3
2 N 1 5 9 5
0
R 7
1 k
2 1
V 1 2
5 V d c
V 1 0
F R E " 1 k
V A M # L " 5
V O F F " 0
R 9
1 k
2
1
$ 5
$ 1 N 4 0 0 7
X 2
2 N 1 5 9 5
V
0
V 8
F R E " 1 k
V A M # L " 5
V O F F " 0
0
V
GRAPH:
PROCEDURE:
1. &onnections are gi!en as per the circuit diagram.
2. @se $($I&3 simulator and run.
3. 2ote down the input !oltages applied to the (&)* output !oltage and current of (&).
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Electronics System Design Lab VII Sem ECE
4. $lot the ?raph.
RESULT:
hus the phase controlled !oltage regulator using full wa!e rectifier and (&) was
constructed and output was !erified.
"I"A QUESTIONS:
1. 7hat is meant by phase controlled !oltage regulatorI
2. 30plain the operation of the circuit.
+. 6ist the applications of (&).
4. 7hat is firing angleI
4. ?i!e the methods to trigger the (&)I
$. DESIGN OF PROCESS CONTROL TIMER
AIM:
Design a se,uential timer to switch on - off + relays in a particular
se,uence using timer I&.
SOFTWARE REQUIRED:
1r&ad
THEORY:
he process control is the acti!ities in!ol!ed in ensuring a process is predictable* stable
and consistently operating at a le!el(target" of performance with only normal !ariation. he I&
444 is highly stable de!ice for generating accurate time delay oscillations. he process control
timer designed using timer I&444 is operated in either astable or monostable mode. here are
three timers used to trigger the other timers through a switch control. he output of the ne0t
timer is obtained after a delay with respect to the delay in the triggering of the circuit.
DESIGN:
!
c
C %
cc
(1 # e
-t')&
"
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Electronics System Design Lab VII Sem ECE
At t C * !
c
C (2'+" %
cc
herefore* C1.1)&
Eere* C1.1 ms
Assume &C 0.1u/
) C
)C 108H
CIRCUIT DIAGRAM:
0
0
0
V
U 9
5 5 5 % & '
1
2
3
4
5
6
7
8
( N $
T R I ( ( E R
O U T # U T
R E S E T
) O N T R O L
T * R E S * O L $
$ I S ) * A R ( E
V ) )
1 0 k
2
1
R 5
1 k
2
1
1 2
. 1 u
1
2
1 k
2
1
5 V d c
0
) 4
. 1 u
1
2
. 1 u
1
2
0
0
0
1 2
0
1 2
U 3
5 5 5 % & '
1
2
3
4
5
6
7
8
( N $
T R I ( ( E R
O U T # U T
R E S E T
) O N T R O L
T * R E S * O L $
$ I S ) * A R ( E
V ) )
. 1 u 1
2
V
V
1 0 k
2
1
. 1 u
1
2
V
0
0
0
0
U 7
5 5 5 % & '
1
2
3
4
5
6
7
8
( N $
T R I ( ( E R
O U T # U T
R E S E T
) O N T R O L
T * R E S * O L $
$ I S ) * A R ( E
V ) )
. 1 u
1
2
. 1 u
1 2
. 1 u
1 2
1 0 k
2
1
5 V d c
0
0
1 k
2
1
V 6
T $ " 0
T F " 0
# + " 1 ,
# E R " 2 ,
V 1 " 5
T R " 0
V 2 " 0
5 V d c
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Electronics System Design Lab VII Sem ECE
TABULATION:
imer 1 ime* t C ms /re,uencyC EL
imer 2 ime* t C ms /re,uencyC EL
imer + ime* t C ms /re,uencyC EL
GRAPH:
PROCEDURE:
1. &onnections are gi!en as per the circuit diagram.
2. @se $($I&3 simulator and run.
3. 2ote down the input !oltages applied and the output at each stage.
4. $lot the ?raph.
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Electronics System Design Lab VII Sem ECE
RESULT:
hus a se,uential timer was designed to switch on - off + relays in a particular
se,uence using timer I&.
"I"A QUESTIONS:
1. 6ist the application of the imer.
2. 30plain the circuit operation
+. 7hat is a relay and gi!e its usesI
4. 7hat do you mean by a process control timerI
4. 7hy is monostable multi!ibrator used in the circuitI
4%& AM MODULATOR # DEMODULATOR
AIM:
o construct Amplitude .odulator circuit using multiplier I& and Demodulator circuit
using en!elop detector.
SOFTWARE REQUIRED:
1r&ad
THEORY:
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Electronics System Design Lab VII Sem ECE
.odulation is achie!ed by !arying one of the three parameters* amplitude* fre,uency and
phase in accordance with the message signal while <eeping the other two parameters as
constant. Eence the amplitude is !aried in accordance with the instantaneous !alues of the
low fre,uency signals. he fre,uency of the carrier is much greater than the amplitude of the
modulating signal to a!oid o!er modulation.
CIRCUIT DIAGRAM:
0
V 2
F R E " 1 0 k
V A M # L " 5
V O F F " 0
U 1
A $ 6 3 3 - A $
1
2
3
4
6
7
8
5
X 1
X 2
. 1
. 2
/
+
V
+
V
-
) 4
. 0 0 9 u 1
2
) 3
. 1 u
1 2
0
V 4
1 5 V d c
V 3
1 5 V d c
0
V 1
F R E " 1 k
V A M # L " 5
V O F F " 0
0
R 2
5 0 k
2 1
$ 2
$ 1 N 4 0 0 1
0
0
0
) 1
. 1 u
1 2
0
0
Mo'()%*+o, I,'-. /
GRAPH:
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Electronics System Design Lab VII Sem ECE
PROCEDURE:
1. &onnections are gi!en as per the circuit diagram.
2. @se $($I&3 simulator and run.
3. 2ote down the input !oltages applied and output !oltage
4. Also note down the demodulated output.
. $lot the ?raph and calculate the modulation inde0.
RESULT:
hus the message signal was modulated and demodulated. he modulation inde0 was
also calculated.
"I"A QUESTIONS:
1. 7hat is modulation and the need for itI ?i!e its types.
2. 7hat is an en!elope detectorI
+. 30plain the wor<ing of the circuit.
4. 7hat is demodulationI
4. 7hat is modulation inde0I
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Electronics System Design Lab VII Sem ECE
4.0 FREQUENCY MODULATION
AIM:
o perform the /re,uency modulation using I& 455 and to calculate the modulation
inde0 for !arious modulating !oltages.
HARDWARE REQUIRED:
/re,uency generator* I& 23455* )esistors* &apacitor* &)1* :read board and connecting
wires* )$(.
THEORY:
/re,uency modulation is a process of changing the fre,uency of a carrier wa!e in
accordance with the slowly !arying base band signal. he main ad!antage of this modulation
is that it can pro!ide better discrimination against noise.
F1-2(-,34 Mo'()%*+o, (5+,6 IC 788:
A %&1 is a circuit that pro!ides an oscillating signal whose fre,uency can be adBusted o!er a
control by Dc !oltage. %&1 can generate both s,uare and triangular wa!e signal whose
fre,uency is set by an e0ternal capacitor and resistor and then !aried by an applied D&
!oltage. I& 455 contains a current source to charge and discharge an e0ternal capacitor &
1
at a
rate set by an e0ternal resistor. )
1
and a modulating D& output !oltage. he (chmitt trigger
circuit present in the I& is used to switch the current source between charge and discharge
capacitor and triangular !oltage de!eloped across the capacitor and the s,uare wa!e from the
(chmitt trigger are pro!ide as the output of the buffer amplifier. he )2 and )+ combination
is a !oltage di!ider* the !oltage %& must be in the range +'4 %
&&
M %
&
M %
&&
. he
modulating !oltage must be less than +'4%
&&
the fre,uency fc can be calculated using the
formula f
o
C 2 (%
&&
-%c" )
1
&
1
%
&&.
/or a fi0ed !alue of %
&
and a constant &
1
the fre,uency can
be !aried at 10A1 similarly for a constant )
1
&
1
product !alue the fre,uency modulation can be
done at 10A1 ratio.
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Electronics System Design Lab VII Sem ECE
CIRCUIT DIAGRAM
pin diagram of 23455
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Electronics System Design Lab VII Sem ECE
GRAPH:
PROCEDURE:
1. he circuit connection is made as shown in the circuit diagram.
2. he modulating signal /. is gi!en from a /? (18EN"
+. /or !arious !alues of modulating !oltage %m the !alues of /ma0 and /min are
noted.
4. he !alues of the modulation inde0 are calculated.
RESULT:
hus the /. circuit using I&455 was performed and the modulation inde0 was found.
"I"A "OCE:
1. 7hat will be the changes in the wa!e under /. when the amplitude or fre,uency of the
modulating signal is increased I
2. he /. station ha!e less noise while recei!ing the signal. Oustify your answer.
+. 7hat happens when a stronger signal and a wea<er signal both o!erlap at the same
fre,uency in /.I
4. 2ame two applications of two way mobile radioI
4. 7hich mathematical e0pression is used to decide the side band amplitudes in a /.
signalI
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Electronics System Design Lab VII Sem ECE
7. DESIGN OF FS9 MODULATOR USING :R 2208
AIM:
o design a /(8 .odulator using 9) 2205.
COMPONENTS REQUIRED:
I& 9) 2205* )esistors* &apacitors.
THEORY:
In digital data communication* binary code is transmitted by shifting the carrier
fre,uency between two preset fre,uencies. his type of the transmission is called /re,uency
(hift 8eying. he standard digital data input fre,uency is 140EL.
.odem ta<es the digital electrical pulses from the terminal and con!erts it into the analog
signal that can be transmitted. he /(8 techni,ue is employed for the modulation of digital
(ignal.
CIRCUIT DIAGRAM:
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Electronics System Design Lab VII Sem ECE

GRAPH:
PROCEDURE:
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Electronics System Design Lab VII Sem ECE
1. &onnections are gi!en as per the circuit diagram.
2. ?i!e the message signal.
+. &hec< the output and !erify.
4. (witch off the input to find the carrier fre,uency.
. $lot the graph for input and output.
RESULT:
hus a /(8 was implemented using 9)2205 and !erified the results.
"I"A QUESTIONS:
1. 7hat is /(8I
2. Eow is timer used to modulate the signalI
+. ?i!e the pin details of 9)2205.
4. 6ist the applications of /(8.
4. 30plain the wor<ing of the circuit
8. PCB LAYOUT DESIGN USING CAD
AIM:
o draw the schematic of simple electronic circuit and design a $&: layout using &AD
SOFTWARE REQUIRED:
1r&ad
THEORY:
he &omputer Aided analysis is essential and can pro!ide information about the circuit
performances. It permits.
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Electronics System Design Lab VII Sem ECE
3!aluation of effects of !ariation in elements such as resistors* transistors etc.
he assessment of performance impro!ements or degradations.
3!aluation of the effects of noise and signal distortion without the need of
e0pensi!e measuring instruments.
(ensiti!ity analysis to determine the permissible bounds due to the tolerances on
each and e!ery element !alue or parameter of acti!e elements.
3!aluation of the effects of non-linear elements of the circuit performance.
1ptimiLation of the design of electronic circuits in terms of circuit parameters.
CIRCUIT DIAGRAM:
&ascode AmplifierA
0 ) 1 0 7 A
5 u
1 2
5 1 k
2
1
0
5 u
1 2
0
2 5 k
2
1
V 3
F R E " 1 k
V A M # L " 2 0 0 ,
V O F F " 0
2
0 ) 1 0 7 A
1 0 u
1 2
0
3 . 3 k
2
1
9 0 k
2
1
. 7 k
2
1
1 4 k
2
1
9 V d c
0
2 0 u
1
2
OUTPUT LAYERS:
?lobal 6ayer
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Electronics System Design Lab VII Sem ECE
op 6ayer
:ottom 6ayer
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Electronics System Design Lab VII Sem ECE
PROCEDURE:
1. Draw the circuit diagram using $spice and get the simulated output.
2. &reate .mnl file
(elect the re,uired file
?o to tools and select create netlist
&lic< 6ayout from the dialog bo0 appearing and gi!e 18.
2ote the path in which the .mnl file is created.
+. o create $&: Design
1pen 1r&ad 6ayout $lus
.a<e the data of 1r&ad 6ayout $lus to default
a<e the .mnl file and sa!e it.
(elect the obstacle from tools and select all the components.
Auto $lace :oard
Auto Auto route :oard
%iew the ?lobal 6ayer.
%iew the indi!idual layers by selecting tools* layer. ?i!e bac<space and select the
layers.

RESULT:
hus a schematic of cascode amplifier circuit was designed and a $&: layout
using &AD was obtained
"I"A QUESTIONS:
1. 7hat is netlistI
2. Define placement and routing.
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Electronics System Design Lab VII Sem ECE
+. 7hat is 6ayoutI 7hat is global layer
4. 7hat are the ad!antages of $&:I
. 30plain the procedure to bring out the 6ayout of any electronic circuit using &AD
. PSUEDO-RANDOM SEQUENCE GENERATOR
AIM:
o stimulate and implement a $):( ?enerator.
SOFTWARES REQUIRED:
$& with 9ilin0 I(3 (oftware >.1i
PROGRAM:
S+m()%*+o,
module prbs(rand*cl<*reset"P
input cl<*resetP
output randP
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Electronics System Design Lab VII Sem ECE
wire randP
reg Q+A0RtempP
always S (posedge reset"
begin
tempMC4KhfP
end
always S (posedge cl<"
begin
if(Treset"
begin
tempMCUtempQ0RVtempQ1R*tempQ+R*tempQ2R*tempQ1RWP
end
end
assign rand CtempQ0RP
endmodule
T-5* B-,3;
module prbstest("P
reg cl<*resetP
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Electronics System Design Lab VII Sem ECE
wire randP
prbs p1(rand*cl<*reset"P
initial
begin
fore!er begin
cl<MC0P
X4 cl<MC1P
X4 cl<MC0P
end
end
initial
begin
resetC1P
X12 resetC0P
X>0 resetC1P
X12 resetC0P
end
endmodule
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Electronics System Design Lab VII Sem ECE
PROCEDURE:
1. 7rite the coding.
2. @se 9ilin0 I(3 simulator and run.
+. 2ote the output and !erify.
RESULT:
hus a $):( ?enerator is simulated in %erilog and implemented using (partan+ /$?A
<it.
"I"A QUESTIONS:
Jerusalem College of Engineering Page 2"
Electronics System Design Lab VII Sem ECE
1. 7hat is $):( ?eneratorI
2. 30plain the program.
3. 7hat is ED6 and gi!e its typesI
4. 7hat is shift registerI
4. ?i!e the specifications of (partan+
<. SIMULATION OF ALU USING :ILIN:
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Electronics System Design Lab VII Sem ECE
AIM:
o stimulate and implement an A6@ using 9ilin0.
SOFTWARES REQUIRED:
$& with 9ilin0 I(3 (oftware >.1i *
PROGRAM:
module A6@(out*flag*sel*clear*a*b"P
output reg Q+A0Rout*flagP
input Q+A0Ra*b*selP
input clearP
reg Q4A0RtP
reg c*s*p*LP
always S (a or b or sel or clear"
begin
if(Tclear"
begin
tC0P
cC0P
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Electronics System Design Lab VII Sem ECE
sC0P
pC0P
LC0P
flagC0P
end
else
begin
if(selQ+RCC1Fb0"
begin
case(selQ2A0R"
+Fb000A begin tCaGbP if(tQ4RCC1" cC1P else cC0P end
+Fb001A begin tCa-bP if(tQ4RCC1" cC1P else cC0P end
+Fb010A tCaQ1A0RYbQ1A0RP
default tC>Fb0P
endcase
if(aQ+RVbQ+R" sC1P else sC0P end
else
begin case(selQ2A0R"
+Fb000AtCaZbP
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Electronics System Design Lab VII Sem ECE
+Fb001AtCa-bP
+Fb010AtCaVbP
+Fb011AtC(Ta"Z(Tb"P
+Fb100AtC(Ta"-(Tb"P
+Fb101AtCaTVbP
+Fb110AtCTaP
+Fb111AtCTbP
endcase
end
end
end
always S (a or b or sel or clear"
begin
outCtQ+A0RP
pCoutQ0RGoutQ1RGoutQ2RGoutQ+RP
if (tCC0" LC1P else LC0P
assign flagQ0RCpP
assign flagQ1RCsP
assign flagQ2RCcP
Jerusalem College of Engineering Page 31
Electronics System Design Lab VII Sem ECE
assign flagQ+RCLP
end
endmodule
PROCEDURE:
1. 7rite the coding.
2. @se 9ilin0 I(3 simulator and run.
+. 2ote the output and !erify.
RESULT:
hus a A6@ is simulated in %erilog and implemented using (partan+ /$?A <it
"I"A QUESTIONS:
1. 30plain the logic of the program.
2. 7hat is A6@I
+. 7hat is 9ilin0 I(3 (imulatorI
4. 7hat is the use of a simulatorI
4. 7rite a program to implement [C A: G &.
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