1. Motivation 2. Overview of HW design 3. FPGA design tools 4. Equipment 5. Demo 2007 R. Pellizzoni (Modified by O. Adekunle) 2 ! Goals: ! Prepare you to work on FPGA this semester. ! Make sure you have a good foundation. ! Question time! Raise your hand if you DONT know following: 1. Whats the difference between concurrent and sequential programming? 2. What ASIC and FPGA means? 3. What is an HDL? 2007 R. Pellizzoni (Modified by O. Adekunle) 3 1. Motivation 2. Overview of HW design 3. FPGA design tools 4. Equipment 5. Demo 2007 R. Pellizzoni (Modified by O. Adekunle) 4 ! HW can be designed a many levels ! Transistors ! Logic gates ! Register Transfer Level (RTL) ! Behavioral (algorithm) ! An HDL is used to describe the design. 2007 R. Pellizzoni (Modified by O. Adekunle) 5 Q D CLK ! HDL (as opposed to imperative lang. (ex: C)). ! Can be used for all levels; different constructs and styles for different levels. ! At behavioral level resembles C ! Language-level support for simulation ! Big difference between RTL level and C: HW is intrinsically concurrent. 2007 R. Pellizzoni (Modified by O. Adekunle) 6 ! Remember for this example ! Assignment is <= ! Logical and is and 2007 R. Pellizzoni (Modified by O. Adekunle) 7 ! Hardware design is inherently concurrent (in parallel) ! If A = 1, B = 1, D = 0, and E = 0 assigned ! What happens with HDL code below? ! (remember <= is assignment) C <= A and B C <= D and E 2007 R. Pellizzoni (Modified by O. Adekunle) 8 ! Hardware design is inherently concurrent (in parallel) ! If A = 1, B = 1, D = 0, and E = 0 assigned ! What happens with HDL code below? ! (remember <= is assignment) C <= A and B C <= D and E ! Error because you essential have: 2007 R. Pellizzoni (Modified by O. Adekunle) 9 and and A B D E C ! Main difference between C and an HDL ! C ! All code is sequential unless you explicitly use something (fork, etc.) to make code parallel/ concurrent ! HDL ! All code is concurrent unless you explicitly use something to make code sequential (process, etc.) 2007 R. Pellizzoni (Modified by O. Adekunle) 10 ! Different integrated circuit (IC)/fabrication models are available on the market (ASIC, PLD, etc). ! In this course we will use an Field Programmable Gate Array (FPGA) ! Write code in VHDL (VHSIC Hardware Description Language). ! VHSIC = Very High Speed Integrated Circuits, ! You get registers, small combinatorial networks, interconnection, RAM, and arithmetic ! You program the device by writing a bitstream to the configuration SRAM on the FPGA. ! These logic elements are still very low-level; we prefer to describe our design at a higher level. 2007 R. Pellizzoni (Modified by O. Adekunle) 11 1. Motivation 2. Overview of HW design 3. FPGA design tools 4. Equipment 5. Demo 2007 R. Pellizzoni (Modified by O. Adekunle) 12 ! We focus on Xilinx design tools since they have direct support for their FPGA families. ! Tools are generally pretty good. ! Xilinx ISE is used to synthesize RTL, perform timing analysis, simulation, generate bitstream and program the FPGA. ! Each function is actually performed by a different program. ! An integrated design environment provides access to all programs and file editing. ! Main tool we use in this course. 2007 R. Pellizzoni (Modified by O. Adekunle) 13 ! What Xilinx allows you to do: ! Write VHDL/RTL code. ! Simulate it. ! Synthesize it (you usually need to guide the synthesizer) ! Review timings. ! Simulate it with timings. ! Download to FPGA and test. 2007 R. Pellizzoni (Modified by O. Adekunle) 14 Q D CLK 2007 R. Pellizzoni (Modified by O. Adekunle) 15 RTL design (.vhd/.v) Synthesis (xst) Netlist (.ngc) Translation (ngdbuild) Translated file (.ngd) Mapping (map) Mapped file (.ncd) Place & route (par) Routed file (.ncd) Bitstream gen. (bitgen) Bitstream (.bit) Behavioral Simulation Timing Analysis Constraint file (.ucf) 1. Motivation 2. Overview of HW design 3. FPGA design tools 4. Equipment 5. Demo 2007 R. Pellizzoni (Modified by O. Adekunle) 16 ! Each PC in CS598 lab has all software installed under linux. ! CS598 TAs suggested that you request access to the lab and computer password if you need to use them. ! We have a lab license for the software, meaning we can install it on other computers in CS598 lab or any machine in the department. ! Software runs on unix, but its possible to download and run on a windows machine. ! We can also provide a development boards for each group. 2007 R. Pellizzoni (Modified by O. Adekunle) 17 ! 65 nm Virtex-5 FPGA (latest). ! Lots of connections, including RS232, video, audio, USB, ethernet, GPIO, SATA, and always useful leds and switches. ! Also provides 1xPCI-E lane. ! The bitstream can be loaded on either a flash memory or a compact flash card (after suitable conversion) for automatic programming on startup. 2007 R. Pellizzoni (Modified by O. Adekunle) 18 ! USB programming cable ! Unless you use a compact flash, you need it to program the FPGA. ! We will use Compact Flash Card to program 2007 R. Pellizzoni (Modified by O. Adekunle) 19 1. Motivation 2. Overview of HW design 3. FPGA design tools 4. Equipment 5. Demo 2007 R. Pellizzoni (Modified by O. Adekunle) 20 ! FPGA flip flop 2007 R. Pellizzoni (Modified by O. Adekunle) 21 Q D CLK RST 1. ISE tutorial using VHDL in lab. 2. Using Xilinx IPs: how to connect ML505 to the PCI-E bus and perform bus transactions. ! Available at: http://www.xilinx.com/products/boards/ml505/ pcie.htm 2007 R. Pellizzoni (Modified by O. Adekunle) 22