Proceedings of 2014 RAECS UIET Panjab University Chandigarh, 06 - 08 March, 2014

978-1-4799-2291-8/14/$31.00 2014 IEEE

A Digitally Controlled Floating Resistor Using
CMOS Translinear Cells
Priya Aggarwal
*
, Vandana mittal
*
, Mohammad A Maktoomi
*
, Mohammad S Hashmi
*

*Electronic Systems Group, IIIT Delhi, New Delhi, India
iRadio Lab, University of Calgary, Calgary, Alberta, Canada
Email: {priya13132, vandana13162, ayatullahm, mshashmi} @iiitd.ac.in


Abstract A CMOS based digitally controlled floating
resistor (DCFR) is proposed using translinear cells. The proposed
DCFR consists of two CMOS translinear cells along with a
CMOS current-division network (CDN). The proposed circuit is
designed in 0.35um technology and works at power supply of
1.6V. DCFR is analyzed as well as SPICE simulation along with
MATLAB is used to verify the proposed design. An application of
proposed DCFR is shown in a high pass filter.
Keywords CMOS; Floating resistance; Translinear
circuits; Current mode circuits; Current division network
I. INTRODUCTION
Passive resistor has high tolerance and large footprint on
chip; therefore there is lot of interest in their realization using
active elements [1]. Literature survey reveals that there are
two ways to realize such resistor: one is based on standard
blocks like operational trans-conductance amplifier (OTA),
current conveyor (CC) and differential difference current
conveyor (DDCC), etc [1-8], and other is their transistor level
design [9-14]. Making these resistors tunable adds flexibility
into the system employing them [1]. Since, in low voltage
design there is a limit on allowable tuning range; digital
control is a more attractive solution and is an active area of
research [15-19]. In this paper a new digitally controlled
CMOS floating resistor using two translinear cells is proposed.
A current division network (CDN) of [20] is used in
this paper to achieve digital control. It produces an output
current in accordance with the applied input bit pattern.
Translinear cell and current division network along with their
schematics are briefly discussed in Section II. In Section III,
the proposed DCFR is discussed. Results obtained using
LTspice and MATLAB appears in section IV.
II. BASIC CONCEPTS
A. CMOS Translinear Cell
Translinear circuit which was proposed by Barrie Gilbert
in 1975 [21], is one of the current mode circuits which is very
useful in analog circuits. It has been used in formation of
many circuits like in BJT based floating resistor [12], current
conveyor [2] etc. The current mode approach is frequently
used in many of the analog design.In translinear circuit
transconductance is linearly proportional to the external input
current [12]. This property has further been used to realize the
DCFR. Translinear circuit can be implemented with the help
of bipolar junction transistors [21] or CMOS [22]. A
simplified structure of a CMOS translinear cell is shown in
Fig.1.

Fig. 1. CMOS translinear circuit
In this circuit M3-M4 - PMOS transistors and M1-M2 -NMOS
transistors are matched individually. All the transistors are
biased in their saturation region. Reference current I
o

provides the drain current to transistors M1 and M3. Whereas
the drain current of M2 and M4 is varied by i
x
which in turn
depends on the input difference voltage, v
xy
.
Since, equal DC current flows into M1 and M3,
0
y
i = (1)
A KCL at node B yields:
4 2 x
i i i = (2)
Since all MOSFETs are biased in saturation,
x
i is given by
[22]:
2
0
2
2
p p p p ox n n n n
x xy xy ox
p n p n
W W
C W W
i V V I C
L L L L


= + +


(3)
Where
n
and
p
are the electron and hole mobility,
respectively. / p p W L and / n n W L are the aspect ratios of
PMOS and NMOS matched transistors.


To remove the second order term in Eq. (2), the condition is:
p p n n
p n
W W
L L

=

(4)

Due to condition in (4), Eq.(3) will reduced to

0
2
p p
n n
x xy ox
p n
W
W
i V I C
L L

= +



(5)

This shows I-V characteristics of translinear cell is linear and
the linearity constant is known as transconductance which can
be formulated as:-

0
2
p p
x n n
m ox
xy p n
W
i W
g I C
v L L

= = +



(6)
It is to be noted from (6) that transconductance varies with the
input reference current
o
I .
B. Current Division Network (CDN)
CDN is similar in function to an R/2R or capacitive ladder
which is used to obtain binary weighted currents[23]. A MOS
based CDN has advantage of lesser chip area. CDN from
[20] is shown in the Fig.2 for reference.


Fig. 2. A 3-bit CDN [20]
CDN of Fig. 2 accept an input current I
in
and provides binary
weighted currents I
o1
and I
o2
, given by


1 o in
I I = (7)

2
(1 )
o in
I I = (8)

0
1
2
2
n
i
i n
i
a
=
=

(9)
The current I
in
is equally divided

into two halves one going
into the next cell and other going into the parallel MOS which
are controlled by the digital bits applied. Finally, the current
controlled by the digital bits is combined which gives one
current output named I
01
and similarly the current controlled
by complemented bits is combined and named as I
02
.
III. PROPOSED CMOS BASED DCFR
The proposed floating resistor appears in Fig. 3. It is
MOS version of its bipolar counterpart reported in [12].
Transistors M4-M7 and M10-M14 are the part of translinear
circuits. All the other transistors are part of current mirrors
which helps in injecting bias current I
b
in the translinear
circuit pair. V
12
is the differential input voltage. All the
transistors are in the saturation region. From symmetry of the
circuit:

1 2
i i = (10)
Also, from (6)
1 0 1 2
2 ( )
p p
n n
ox
p n
W
W
i I C v v
L L

= +


(11)
Hence from (10) and (11), the equivalent differential input
resistance is given by:
0
1
2
eq
p p
n n
ox
p n
R
W
W
I C
L L
=

+


(12)

Fig. 3. Proposed floating current controlled positive resistance using two
mixed translinear cell
From (12) it is obvious that resistance value may be easily
tuned with input bias current.
In order to make the proposed CMOS floating resistor
digitally controlled, a CDN network discussed in the previous
section is used as shown in the block diagram of Fig. 4. Since,
CDN has two outputs I
o1
and I
o2
, one of the outputs is
connected with the bias current terminal of the floating resistor
and other output is connected to ground as shown in the Fig. 5.






Fig. 4. Block diagram of DCFR
Fig. 5. Complete diagram of DCFR
IV. SIMULATION RESULTS
Aspect ratios of transistors in Fig. 3 appear in Table 1.
First, the floating resistor of Fig.3 is simulated using LTspice-
IV, which is a SPICE simulator provided by Linear
Technology. A 0.35um CMOS technology file has been used
for the simulation purpose. The power supply voltage V
dd
and
V
ss
are 1.6V and -1.6V, respectively. Biasing current, I
b
is
swept from 35A to 200A with a step of 25A. Fig.6 shows
the corresponding output which verifies the claim that realized
impedance may be tuned using the bias current.
TABLE I. ASPECT RATIOS OF THE PROPOSED CMOS DCFR
W/L ratio ( m / m ) Corresponding transistors
10/2 M1,M2,M8,M15
60/0.35 M6,M7,M11,M14
20/0.35 M4,M5,M10,M13
30/2 M3, M9,M12

Line which cuts the y axis at the highest point (near -80uA
y-mark) corresponds to I
b
=35A. For this value
transconductance (slope) is lowest among all which is also
evident from the mathematical result given in (12).

Fig. 6. I-V characteristic of proposed floating resistor

In order to show the digital control of the floating resistor,
circuit of Fig. 5 is simulated by keeping a fixed bias current of
200A. For all the transistors in CDN aspect ratio is W/L= 2.8
/0.7 in m . Fig. 7 shows the LTspice generated plot when
imported in MATLAB. According to three input bit patterns
different value of transconductance ( slope) are obtained
which greatly matches with the analytical result of (12).
-0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05
-3
-2
-1
0
1
2
3
x 10
-4
Differential input , v
1
-v
2
(in volt)
C
u
r
r
e
n
t
,

i
1

(
i
n

A
m
p
)


001
010
011
100
101
110
111
Fig. 7.Simulation showing I-V characteristics of circuit in Fig. 5 .
In order to show utility of the proposed DCFR, a first order
high pass filter shown in Fig. 8 is simulated in LTspice and
Fig. 9 shows the exported plot in MATLAB for various input
bit combinations [10, 15].

Fig. 8. A first order HPF employing the proposed DCFR
v
1
-v
2
i
1
=-i
2
Decreasing I
b



10
3
10
4
10
5
10
6
10
7
10
8
10
9
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
Frequncy (in Hz)
G
a
i
n

(
i
n

d
B
s
)

Fig. 9 Response of the HPF containing DCFR

The value of C1=10pF and bias current I
b
is fixed at
200uA. It is seen from Fig. 9 that for different applied bit
pattern, the value of R
eq
is changing and thus the cut-off
frequency of the filter.
V. CONCLUSION
A digitally controlled CMOS based DCFR was proposed
in this paper .The proposed circuit was realized using cascade
connection of CMOS translinear cell and CMOS ladder
current division network.. The proposed DCFR produces
different values of resistance in accordance with the applied
bit pattern for a given value of bias current. The proposed
circuit was verified with the help of LTspice and MATLAB
software. Finally, to show usefulness of the proposed idea a
first order high pass filter employing the DCFR was design
and verified.

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