BALKAN PHYSICS LETTERS

c Bogazici University Press 30 March 2010

BPL, 18, 181048, pp. 360 - 367 (2010)
COMPARISON OF SEQUENTIAL AND SIMULTANEOUS
HIGH-LOW FREQUENCY CAPACITANCE-VOLTAGE METHOD ON
MOS STRUCTURE
Ayse Evrim SAATC

I and Orhan OZDEM

IR

Physics Department, Yildiz Technical University,

Davutpasa, Istanbul, TURKEY
Abstract. - Device based technique such as ac admittance measurement
was carried out on thermally grown silicon dioxide (SiO
2
) in the form of MOS
(Al/SiO
2
/silicon) structure. At the interface, inevitable local defects alter the
properties of MOS capacitor hence the precise determination of density of states
(DOS) is necessary. Here, the amount was determined by comparing the mea-
sured capacitance at low (10
2
Hz) and high (10
6
Hz) frequencies, so called the
high-low frequency capacitance method. Separate C-V measurement under low
and high frequency was a sequential method whereas measuring both high and
low frequency C-V curve in the same cycle was simultaneous one. The last one
seemed to be more convenient and more accurate since there is no voltage shift
between curves. Aforementioned methods were applied and gathered results
were compared on MOS structure.
Keywords: Admittance Measurement, MOS, high-low frequency.
* Corresponding author
Tel: +90 212 383 4279; Fax:+90 212449 1514
E-mail address: ozdemir@yildiz.edu.tr
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1. Introduction
Localized electronic states at the interface between silicon and its thermal oxide
(SiO
2
) have been a focus of intensive study over years. An accurate electrical char-
acterization at the interface trap (interface state) properties is essential both for
investigating their physical origins and predicting the performance of the resulting
metal/insulator/semiconductor (MIS) devices.
The MIS capacitor, which is the backbone of microelectronic industry, consists
of parallel plate capacitor with one electrode being a metallic plate, called gate elec-
trode and the other electrode, being a silicon. A thin insulating layer separates the
two electrodes which is one of the important material, constituents of thin lm tran-
sistor (TFT) and eld eect transistor (FET) devices. Thermally grown SiO
2
, at
high temperature oxidation processes (850-1000
0
C), has a property of high break-
down strength (greater than 10MV/cm), a low density of xed and mobile charge
in the oxide layer (10
11
cm
2
) and a low density of defects at Si/SiO
2
interface
(10
10
cm
2
eV
1
).
Various technological products which are strictly related to the MOS structure
include random access memory (RAM), erasable programmable read only memories
(EPROM) or charge coupled devices (CCD) and development of computers and in-
formation processing/control systems are tightly related to the achievements in MOS
technology. However, technological diculties such as insulator quality and interfaces
are the key issues to fabricate a working MOSFET.
Since the electrical properties of the interface traps are characterized by their
density (D
it
), their position in the energy gap of the silicon (E
t
) and their capture
cross section (), available parameters will be determined by a technique we employed.
Among the various measurement techniques, high-low frequency
capacitance-voltage technique will be utilized to characterize the interface traps in
MOS structure by performing (i) sequential and (ii)simultaneous measurements.
For the case of (i), Terman [1-2] developed and used the high frequency capaci-
tance method for determining interface trap capacitance. In there, high frequency is
intentionally selected so that neither inversion nor surface states charge can respond
to the excitation. Therefore, measured capacitance under high frequency (C
HF
) is
the series combination of oxide capacitance (C
ox
) and depletion capacitance (C
D
) of
the semiconductor
1
C
HF
=
1
C
ox
+
1
C
D
(1)
On the other hand, for a low frequency, the response is immediate and create addi-
tional capacitance (C
it
) to the low frequency C-V curves due to interface trap charges.
Hence, measured capacitance turns to be
1
C
LF
=
1
C
ox
+
1
C
D
+C
it
(2)
362 BALKAN PHYSICS LETTERS
Rearranging equation(2) yields C
it
as
C
it
= [
1
C
LF

1
C
ox
]
1
C
D
(3)
where C
ox
is determined from strong accumulation (piling of majority carriers at the
interface) regime. Combination of quasi-static C-V measurement (low frequency C-V)
with the one measured under high frequency cause to obtain interface state(or trap)
density (D
it
) in the energy range from accumulation to weak inversion as
C
it
= [
1
C
LF

1
C
ox
]
1
[
1
C
HF

1
C
ox
]
1
(4)
Interface trap capacitance is roughly proportional to interface state density through
C
it
qD
it
(5)
so,
D
it
=
1
qA
{[
1
C
LF

1
C
ox
]
1
[
1
C
HF

1
C
ox
]
1
} (6)
with q= elementary charge and A= electrode area. Additionally, low frequency C-
V measurement is also used to extract the semiconductor band bending (
s
) at the
interface as a function of gate bias voltage (V
G
) to obtain surface state energy distri-
bution. By numerical integration of C
LF
(V
G
) curve from accumulating bias voltage
(V
acc.
) to inverting bias voltage (V
inv.
),
s
distribution will be obtained as

s
=

V
inv.
V
acc.
(1
C
LF
C
ox
)dV
G
(7)
The energy distribution of D
it
(E) may be obtained by changing gate bias voltage along
the depletion region where the energy is scanned from the mid-gap to the valance band
edge of p-Si energy gap:
E
T
E
v
= q
s
+
kT
q
ln(
N
A
n
i
) (8)
where k= Boltzmann constant, T= temperature, N
A
= doping density of silicon and
n
i
=intrinsic carrier density in silicon, respectively.
Similar analysis could be carried out in simultaneously measured C-V curves as
in the case of sequential ones. The goal of this work in this view is the comparison of
sequentially and simultaneously measured C-V curves on MOS structure at hand to
extract the signature of traps.
2. Experimental
2. . 1 Film Fabrication
Typical MOS structure for the mentioned experiment consists of p-type silicon ranging
from 10 to 20 cm covered by 1390

A of oxide grown at 1050
0
C in one atmosphere of
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Figure 1: Capacitance as a function of gate bias at room temperature on Al/SiO
2
/p-
c-Si/Ohmic Al MIS structure under low (10
2
Hz) and high (10
6
Hz) frequency, mea-
sured by (a)sequentially and (b) simultaneously, respectively.
steam. Aluminum electrodes of 7.85x10
3
cm
2
area are evaporated onto the oxide.
For quantitative evaluations, a good ohmic contact has to be made to the silicon to
minimize series resistance. For this purpose, bare silicon wafers was cleaned rst by
RCA cleaning and then rear side of the wafer was coated with Al. Then it was heated
at 530
0
C for 30 minutes in nitrogen atmosphere, resulting the formation of ohmic
back contact.
2. . 2 Measuring System
For the sequential C-V measurement, both quasi-static C-V meter (Keithley 595) and
HP4192A LCR meter were used to measure the low frequency (10
1
Hz) and high
frequency (10
6
Hz) capacitances of MIS structure at hand. For the simultaneous C-V
measurement, on the other hand, NovoControl impedance analyser was used which
was capable of C-V measurements under frequency range of 10
6
Hz to 10
7
Hz.
3. Results and Discussion
Figure 1 depicts typical measured C-V curves. In there, a) report sequential and b)
posses simultaneous C-V results, where modulation frequency (10
1
and 10
6
Hz) is a
parameter. Note that in each case the specied voltage was applied to the top of the
Al electrode with respect to the back Al ohmic contact.
The capacitance curves, as shown in Figure 1, have three distinct regions, two
of high, nearly constant capacitance under low frequency C-V measurement and the
last one where the capacitance changes rapidly with gate bias and goes through a
364 BALKAN PHYSICS LETTERS
Figure 2: Evaluated doping density of p-c-Si semiconductor from the slope of
d
dV
G
(
1
C
m
)
2
relation along the depletion region at high frequency of C-V curves on
Al/SiO
2
/p-c-Si/Ohmic Al MIS structure measured by (a) HP4192A (b)Novocontrol
LCR meters, respectively.
minimum. Features of C-V behavior at high negative bias and the decrease towards
minimum are well understood [1-3] and can be explained as follows: at high negative
bias, piling of majority carriers (here holes) forms the accumulation layer. Since
this layer contain huge amount of charge, only the oxide capacitance is measured.
When bias is swept towards more positive side, initially, a charge in the accumulation
layer decreases causing a decrease in measure capacitance. With subsequent bias
reduction the accumulation layer turns into depletion layer, where the capacitance
is now a combination of oxide capacitance connected in series with that of the layer
capacitance (C
D
). The measured capacitance versus bias curve can go through a
minimum and rise to the oxide capacitance provided that the measuring frequency is
low enough (10
1
Hz). Otherwise, i.e., when frequency is high (10
6
Hz) compared
to the minority carrier (electrons) equilibration rate, the minority carrier under the
gate electrode can not contribute to the measured capacitance and stay constant to a
value designating oxide capacitance in series with C
D
for all values of inverting bias
voltages.
At the negative side of V
G
, a voltage/frequency independent capacitance is ob-
served at a value of 256 pF which is relevant to strong accumulation in the silicon
interface. This corresponds to the lm capacitance and oxide lm thickness as 1390

A
was determined from the relation C
ox
=

ox
A
x
ox
, where
ox
=5
0
with
0
is a permittivity
of free space.
Though, depletion should follow the accumulation as expected by MOS capacitor
analysis, the involvement of charges can modify the shape of C
m
-V
G
curve. A xed
or mobile charges residing in the insulator causes to shift the C
m
-V
G
curve along
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Figure 3: Extracted the semiconductor band bending (
s
) at the interface as a func-
tion of gate bias voltage (V
G
) by numerical integration of C
LF
(V
G
) curves measured
by (a) Keithley 595 Quasi static C-V Meter (b) Novocontrol LCR meter, respectively.
the voltage axis whereas interface charges caused to deviate the curves from the
ideal characteristic since the amount of charges in these state depend on the gate
voltage. These two eect can be understood from the at band voltage,V
FB
(zero
bias voltage where
s
=0); shifted magnitude of V
FB
from the ideal position (zero
bias) give a clue about the amount of density of charge located within the lm and/or
at insulator/semiconductor interface according to Gauss law as:
Q
it
+Q
f
V
FB
C
ox
(9)
Consequently, determination of V
FB
seems crucial for the overall evaluation of
local charges. This V
FB
value could be estimated from the at band capacitance,
C
FB
, as
1
C
FB
=
1
C
ox
+
1
C
D
(FB)
(10)
where C
D
(FB) =

s
A
L
D
with L
D
= Debye lenght =

kT
s
q
2
N
A
where
s
= silicon permit-
tivity. After determining N
A
from the slope of
d
dV
G
(
1
C
m
)
2
relation along the depletion
region at high frequency as 9x10
14
cm
3
( see Figure 2 a and b), L
D
was obtained
as 137 nm. Afterwards, C
FB
was calculated around 177 pF, corresponding to V
FB
as -4.54 V. The value denotes the actual starting point of depletion regime and the
amount of injected (or existent) charges in the oxide.
As V
G
surpass the V
FB
,
s
starts from zero (at band region) to 0.9 eV (strong
invertion region) and depict in Figure 3-a and b.
366 BALKAN PHYSICS LETTERS
Figure 4: D
it
distribution as a function of energy gap (E
T
E
v
) from the sequential
(a) and (b) simultaneous C-V curves on Al/SiO
2
/p-c-Si/Ohmic Al MIS structure,
respectively.
Meanwhile, due to the existence of interface states, dierence in capacitance mea-
sured at high frequency and low frequency C-V curves are eventual in both cases. For
a rough estimate of D
it
, relation (9) is applicable and Q
it
is calculated as 1.13x10
9
C which corresponds to 1.9x10
11
eV
1
cm
2
as D
it
. However, for a precise D
it
as well
as its distribution along the energy gap, relation (6) and (8) should be consulted.
Retrieved D
it
distribution as a function of energy gap are displayed in Figure 4-a and
b, respectively from the sequential and simultaneous C-V curves. Although, they are
consistent with each other, the value seems two decade higher than with conventional
MOS structure. The reason behind the dierence in between D
it
value is thought to
be due to self inversion charges located between insulator/semiconductor interface.
Once frequency is low enough, they contribute to the measured capacitance, leading
to overestimate the actual D
it
.
4. Conclusion
Sequential and simultaneous high-low frequency capacitance-voltage measurements
were carried out to extract the available signatures of interface defects which were
the amount of D
it
and its distribution along the energy band gap. Evaluated values
were consistent with each other but possessing a little bit higher D
it
value compared
to the conventional structure. The reason behind the dierence was speculated as self
inversion minority charges that they got involved in the measured capacitance as soon
as the modulation frequency was low enough to contribute, leading to overestimating
the D
it
value.
Ayse Evrim SAATC

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5. Acknowledgement
This work was carried out with the nancial support of Yildiz Technical University
Projects (BAPK Project No.: 28-01-01-02)
REFERENCES
[1] S.M. Sze, Physics of Semiconductor Devices Volume 2, John Wiley and Sons,
New York,1981.
[2] E. H. Nicollian, J.R. Brews, MOS(Metal Oxide Semiconductors)Physics and
Technology, John Wiley and Sons, London, 1982.
[3] O. Ozdemir, International Journal of Hydrogen Energy, 34(3),1468-1471, 2009.