LOW POWER MULTIPLIER USING

MODIFIED CARRY SELECT ADDER

P.shravan kumar babu
*1
, P.rudra narayana reddy
1
, ameenulla
1
, ravi
2

1
M.Tech Student, VIT University,Vellore Tamilnadu
2Assistan Professor, School of Electronics Engineering,VIT University, Vellore
*1
shravan.kumar1112@gmail.com;
1
rudrareddy434@gmail.com;
1
ameenulla903@gmail.com;
2
Abstract
Multiplier is the most basic block in any
computational circuit .It occupies and consumes
the largest power of all arithmetic circuits.In this
paper we implemented a low power multiplier
using booth radix 4 multiplication process and
then we add the partial products generated
with a modified csla which has very less delay
.prior to performing multiplication we use
dynamic range detection unit(DRD) to
determine which is multiplier and which is
multiplicand accordingly.We have implemented
all these circuits in Cadence 45nm library and
written the corresponding verilog codes and
synthesized it in nclaunch and for the backend
part we used ENCOUNTER tool of cadence.The
corresponding power and areas are calculated
using Cadence`s RC tool

Keywords
Booth, drd ,carry select adder ,backend

Introduction

Power consumption is the most basic criteria in
any application.optimizing the power consumed
without effecting the net performance of circuit
is of great need.Multiplier is one of the most
basic building block which is almost used in
many DSP applications,FILTERS,IMAGE
PROCESSING MECHANISMS.But this
multiplier consumes large area and also
consumes large amount of power. so there is a
great need for us to implement a multiplier
which has less delay along with low power
consumption.
There are many mechanism to perform
multiplication operation.They are shift and add
multiplier,Wallace tree multiplier,etc.There is a
special technique for performing multiplication
process it is booth encoding.In this booth
encoding process we encode our given bits and
follow necessary kind of rules for each encoded
bit and produce corresponding partial
products.This promotes low power by reducing
total number of operations.The booth encoding
radix value ranges from 2,4,8 etc. Each has its
own advantages and disadvantages.For our
project we are going to use booth 4 encoding
operation.Because it only uses only shift,
complement operation to perform appropriate
partial products .Appropriate dynamic range of
your given operands also plays a vital role in
your power consumption.So we need to
determine prior to multiplication which is
multiplier and which is multiplicand and
perform necessary sort f multiplication this is
done by dynamic range detection unit.Then
adding the partial products also plays a vital
role in your total power consumed.We generally
use full adder and half adder cells inorder to
perform necessary kind of addition
operation.There is a great need for us to use
higher end adders like csa,cla etc.So we need to
select a necessary kind of adders which
performs addition operation with a less delay
and optimum power consumption.this entire
paper is divided into following segments:
1)multiplication operation
2) DRD UNIT
3) booth encoder
4) carry select adder
5)evaluation and results
6)conclusion
7)acknowledgment
8)references

MULTIPLICATION OPERATION :
For multiplication operation you have two
operands :
1)multiplicand
2)multiplier
Multiplication= multiplicand * multiplier.
Multipliers each bit is multiplied with each and
every bit of a multiplicand and corresponding
partial products are generated.The efficiency of
a multiplier is dependant on how to multiply
these multiplier bits.We know that
multiplication operation is commutative.So
before multiplying we need to determine which
is multiplier and which is multiplicand.This
kind of determination is traditionally not
performed in multiplication operation.In our
modified multiplier we use a special unit which
is used to determine which is multiplier and
which is multiplicand.The flow chart of our
multiplication unit along with traditional
multiplication is shown below:

FIG1:TRADITIONAL MULTIPLIER
FIG2:MODIFIED MULTIPLIER
From the figure we see that the first unit is the
drd unit which determines multiplicand and
multiplier correspondingly.then we give to
booth multiplier which generates appropriate
partial products.Then we give to adder circuit
which adds our partial products and generates
appropriate outputs.for our project we are going
to use modified carry select adder(csla).
DRD UNIT:
It is most important unit in our
multiplication operation which is used to
determine the corresponding multiplier and
multiplicand from our given pair of
operands.The circuit diagram for our DRD unit
is shown below.


FIG 3:DRD UNIT
The drd unit does this by calculating there
dynamic ranges and then determing the one
with low dynamic range as your multiplier and
with more dynamic range as your
multiplicand.Because if we have more dynamic
range for your multiplier then we have more
amount of booth encoded bits which increases
the net computation of your multiplier for a
given set of operands there by increasing the
total power consumed.
BOOTH MULTIPLICATION:
Booths multiplication algorithm that multiplies
two signed binary numbers in twos
complement notation. It allows the
multiplication faster and smaller circuits, by
recoding the numbers that are to be multiplied.
It is the standard technique used in chip design,
and provides significant improvement over the
traditional multiplication technique
Traditional method of multiplication:-
A standard approach that is used to do
multiplication is shift and add method in this
the given two numbers are converted in to
binary form and we will take one of the operand
as multiplier and other operand as multiplier
.starting from lsb to msb based on the bit
weather 0 or 1 corresponding partial products
are generated and shifted on the number of
multiplier bit position and finally add the all
partial product bits to obtain result.
Following example shows the traditional
method of multiplication
0 0 1 0 1 1
0 1 0 0 1 1
0 0 1 0 1 1
0 0 1 0 1 1
0 0 0 0 0 0
0 0 0 0 0 0
0 0 1 0 1 1
0 0 1 1 0 1 0 0 0 1

In this system the no of partial products are
exactly same as the number of bits in multiplier
Radix-4 Booth Recoding
To booth recode the given operands first of all
decide which operand is multiplier and which
will be the multiplicand.Convert booth
operands to twos complement representation
using X bits and add 0 at lsb and now group
the three bits and leaving one bit at left side
group next three bits and so on and we will
recode the multiplier according to booth
recoding .based on the bit obtained
corresponding shift and multiplication done in
order to generate partial products.
Booth recoding strategy:
Block Partial Product
000 0
001
1 *
Multiplicand
010
1 *
Multiplicand
011
2 *
Multiplicand
100
-2 *
Multiplicand
101
-1 *
Multiplicand
110
-1 *
Multiplicand
111 0

TABLE 1:BOOTH ENCODING OPERATION
In order to get result the obtained partial
products are arranged in such a way that with
respect to first partial product second partial
product shifted two positions and third partial
product shifted four positions and so on then we
will add all the partial product to get the final
result.
Advantage of Modified PPS Unit :
X2AC9 0010101011001001
Y006A 0000000001101010
Y is having low dynamic range of data so we
select Y as multiplier and X as multiplicand. To
the multiplier we will add one extra 0 bit next to
lsb bit and we will recode the first three bits and
leaving one bit at lsb next three bits that means
one new right hand side bit and with the two
overlapped bits and so on. Depending on the
recoded bit we will perform corresponding
operation as shown in the above table and the
partial products are generated
0000000000000000 PP7
0000000000000000 PP6
0000000000000000 PP5
0000000000000000 PP4
00101010110010010 PP3
11101010100110111 PP2
11101010100110111 PP1
11010101001101110 PP0
000000000100011011011100111010 (11B73A)
CARRY SELECT ADDER:
Adders are the most important part of your
multiplication. They are the main components
which determine how speed your multiplier
works. Hence there is a great need for high
speed adder along with necessary area
optimization. Carry select adder (CSLA)is one of
the most high speed adders which is being used
in the present day. In general the efficiency of
an adder is determined how quickly we
generate carry bit and propagate it to the output
effectively .For a traditional ripple carry adder
we generate the carry bits sequentially and
propagate it from one stage to another stage. So
the final stage has to wait for a large amount of
time as all the successive bits must be computed
sequentially. The main advantage of carry select
adder is that it has very less delay. In this we
calculate all the bits parallel taking into
consideration of two scenarios:
1) carry(cin)=0
2)carry(cin)=1
The figure of a basic carry select adder is shown
below. There corresponding modules is also
shown below:

FIG 4: Traditional carry select adder
These are then feed to a multiplexer and the
output of previous stage(cout) is given as a
selection bit to your multiplexer which
determines which is the output. But the main
disadvantage is the circuit area is very large.
Therefore we need to optimize our carry select
adder to get optimum results. This is done by
using an excess three code converter instead of
your traditional ripple carry adder for your
Cin=1 scenario.Therefore by doing this we
reduce the area of carry select adder with a
slight amount of delay overhead as compared to
ordinary csla adder.For Cin=1 scenario we
convert our given output from cin=0 scenario
into excess 3 code conversion.because excess 3
code adds 1 bit to your output we get scenario of
cin=1.In order to convert our given number of
ubit into excess 3 bits we need u+1 bits. The
basic principle is to fit an excess 3 code
converter at the bottom of all variant size ripple
carry adder which are present at the bottom. The
basic modules of our csla and there
corresponding excess 3 carry code converter is
shown in the figure below:


FIG 5:MODIFIED CARRY SELECT ADDER

3 bit bec3 circuit:
s1out=~s1;
s2out=s1^s2;
ki=s1&s2;
c1out=c1^ki;
fin= {s2out,s1out};

4 bit bec circuit:
o1=~in1;
o2=in1^in2;
wi1=in1&in2;
o3=wi1^in3;
wi2=wi1&in3;
cout=in4^wi2;
fin1={o3,o2,o1};

5 bit bec3 circuit:
o1=~in1;
o2=in1^in2;
wi1=in1&in2;
o3=wi1^in3;
wi2=wi1&in3;
o4=in4^wi2;
wi3=wi2&in4;
cout=wi3^in5;
fin1={o4,o3,o2,o1};

6 bit bec:
o1=~in1;
o2=in1^in2;
wi1=in1&in2;
o3=wi1^in3;
wi2=wi1&in3;
o4=in4^wi2;
wi3=wi2&in4;
o5=wi3^in5;
wi4=wi3&in5;
cout=wi4^in6;
fin1={o5,o4,o3,o2,o1};


FIG 6:3 BIT BEC

FIG 7:4BIT BEC

FIG 8 5 BIT BEC

FIG 9 : 6 BIT BEC
The main gripe of our modified csla is that it has
a slight delay overhead but nevertheless it is
very fast and also consumes less power than our
traditional csla. Here we s1,s2,in1,in2,in3,in4,in5
are all input to your bec3 code converter.Now
we use these carry select adder cells to add our
partial products.For our case we use 32 bit
modified csla to add each pair of partial
products parallely and then we add again these
intermediate outputs to obtain our final
result.For our case we have 8 partial products
namely pp0,pp1,pp2,pp3,pp4,pp5,pp6,pp7.We
use a total of 7 modified csla cells in order to
find the final output.
Experimental Results
The output waveform of our multiplier is
shown below:

FIG 10.OUTPUT SIGNAL WAVEFORMS
The synthesizable architecture by using
ENCOUNTER cadence tool is shown below

FIG 11 :SYNTHESIZED ARCHITECTURE
COMPARISION TABLES :
In this we perform power ,area,delay
with certain set of exisisting multiplier like shift
and add multiply,vedic tree multiplier,Wallace
multiplier,array multiplier.The corresponding
tables are shown below.All the below results are
calculated by using Cadence tool nclaunch ,rc
tool, simvision,encounter tool.
Name of multiplier
Power consumed
Modified multiplier
using modified carry
select adder
1795291.232 nW
Shift and ahead
multiplier
74.30mW
Vedic multiplier 118mW
Wallace tree
multiplier using
compressors
94.80 mW
Array multiplier 256 mW

Table 2:POWER CALCULATION TABLES

Name of multiplier
AREA
Modified multiplier
using modified carry
select adder
27,767(um^2)
Shift and ahead
multiplier
15,256 um^2
Vedic multiplier 30,209(um^2)
Wallace tree
multiplier using
compressors
29,560 mW
Array multiplier 35,789(um^2)

Table 3:AREA CALCULATION TABLES

Name of multiplier
timing
Modified multiplier
using modified carry
select adder
1 ps
Shift and ahead
multiplier
5 ps
Vedic multiplier 12 ns
Wallace tree
multiplier using
compressors
8 ns
Array multiplier 10ns

TABLE 4: DELAY CALCULATION TABLE


BACKEND:
The backend for the design has
been shown below this is done by using
encounter tool .This is done by adding all pads
to our design .




Fig 12 :GDS 2 FILE OF MODIFIED CSLA
MULTIPLIER


CONCLUSION:
In this multiplier we have
introduced a low power csla which performs
addition very rapidly .But with a slight amount
of delay overhead in our circuit .And also we
reduced the switching activity so we are prone
to having low power.We can improve this
architecture by using BZFC CIRCUIT which by
passes zeros and performs even less amount of
computation than our implemented adder.


ACKNOWLEDGMENT:
We would like to thank Prof RAVI for
his excellent motivation and guidance in
completing this project. We also thank VIT in
providing excellent facilities for our research
based course
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