1 Introduction

TheUniversalVerificationMethodology(UVM)isastandardizedhybridmethodologyforverifyingcomplexdesigninthesemiconductor
industry.IthassupersededtheOpenVerificationMethodologywhichwasanOpenSourceverificationmethodologywassupportedbyboth
CadenceandMentor.UVMhasfullindustrywidesupportandstandardisedundertheAccelleraSystemsInitiative.
InthispaperTVSdescribesindetailthedifferencesbetweentheOpenVerificationMethodology(version2.1.2)andtheUniversalVerification
Methodology(version1.b).ItisintendedtohelpengineerstounderstandtheimplicationsofmovingfromOVMtoUVM.
ThepaperstartswithashorthistoryofOVMandUVMtosetthecontext.Adetailedcomparisonthenfollowslookingatphases,managingthe
endoftest,componentconfigurationandfinallyregistermodeling.

AbouttheAuthors:
SureshBabuhasbeeninvolvedinhardwareverificationfor10years.Currentlyheisaprojectlead@TVSwithresponsibilityforOVM,UVM
andeRMBasedtestbenchandVIPdevelopment,customersupportandmetricdrivenbasedverificationsignoffusingasureSign.
Dr.MikeBartleyfoundedTVSin2008afterspendingover20yearsworkinginbothhardwareverificationandsoftwaretesting.
AboutTestandVerificationSolutions
TVSdeliverstailoredsolutionsforhardwareverificationandsoftwaretesting.TVSisanindependentcompanyprovidingbothservicesand
products(VIP&asureSign)fromofficesaroundtheworld.TVSpridesitselfonhavingtheflexibilitytomeetdiverseclientrequirements.
Tolearnmoreaboutourofferings,visitwww.testandverification.comorwritetousatinfo@testandverification.com
2 OverviewofUVMHistory
UVMisbuiltonSystemVerilogandthehistoryofthatlanguageisshowninFigure1:HistoryofSystemVerilogbelow.

Figure1:HistoryofSystemVerilog
VerificationmethodologiescameintoexistencesoonafterthefirstdedicatedHVLs(HardwareVerificationLanguages)appeared(see.Themain
advantagesofadoptingamethodology(suchasUVM)are
ReusabilitythroughtestbenchreuseandverificationIPallowingplugandplay
Aprovenmethodologywithindustrywidesupportandavailabilityofengineerswithexistingknowledge/experience
Simulatorandvendorindependence
HiLo Verilog
1980 1990
2000 2005
e
C
Vera
System
Verilog
VHDL
SuperLog

Figure2:HistoryofVerificationMethodologies
2.1 OVMandUVMAvailability
Thefollowingreleasesareavailableinhttp://verificationacademy.com/verificationmethodology
UVM1.1b(tar.gz)Accellera
UVM1.1bUserGuideAccellera
UVM1.1a(tar.gz)Accellera
UVM1.0(tar.gz)Accellera
OVM2.1.2(.zip)
OVM2.1.2(tar.gz)
UVMRegisterKitforOVM2.1.2(tar.gz)
OVM<>VMMreferencelibrary,examplesanddocumentation

Vera RVM
VMM
AVM
URM
System
Verilog
OVM
VMM 1.2
UVM
e
eRM
OpenSource
3 OVMPhasesvs.UVMPhases
InthissectionwelookatthemainchangesinthewayphasesarehandledinUVM.Thereare2changesinthemethods(seesection3.1)and
changesintheactualnumbersofphases(seesection3.2).Notethatasthesechangesaresignificantandnotbackwardscompatiblethenthereis
awaytoinvokeOVMstylesemantics.

3.1 Changesinphasemethods
Thereare2changesintheinterfacetothephasemethods.ThesearesummarisedbelowwiththedetailinTable1:Summaryofthechangesin
phasemethods.
1. Methodnamechangedinto<phase_name>_phase.
2. Argumentaddedinallthephasemethods.
OVM UVM
classxbus_envextendsovm_env;

//VirtualInterfacevariable
protectedvirtualinterfacexbus_ifxi0;

functionvoidbuild();
stringinst_name;
super.build();
if(has_bus_monitor==1)begin
bus_monitor=xbus_bus_monitor::type_id::create("bus_monitor",
this);
end

Endfunction:build
classubus_envextendsuvm_env;

//VirtualInterfacevariable
protectedvirtualinterfaceubus_ifvif;

functionvoidbuild_phase(uvm_phasephase);
stringinst_name;
super.build_phase(phase);
if(!uvm_config_db#(virtualubus_if)::get(this,"","vif",vif))
`uvm_fatal("NOVIF",{"virtualinterfacemustbesetfor:
",get_full_name(),".vif"});

Endfunction:build_phase
Ifyouadd+UVM_USE_OVM_RUN_SEMANTICinthecommandlineitwillcausetherunphasetouseoldOVMstylerunsemantics.

//implementruntask
taskrun;
fork
update_vif_enables();
join
endtask:run

functionvoidend_of_elaboration();
$display("%0t:%0s:end_of_elaboration",$time,get_full_name());
endfunction
functionvoidstart_of_simulation();
$display("%0t:%0s:start_of_simulation",$time,get_full_name());
endfunction
functionvoidextract();
$display("%0t:%0s:extract",$time,get_full_name());
endfunction
functionvoidcheck();
$display("%0t:%0s:check",$time,get_full_name());
endfunction
functionvoidreport();
$display("%0t:%0s:report",$time,get_full_name());
Endfunction

//implementruntask
taskrun_phase(uvm_phasephase);
fork
update_vif_enables();
join
endtask:run_phase

functionvoidend_of_elaboration_phase(uvm_phasephase);
$display("%0t:%0s:end_of_elaboration",$time,get_full_name());
endfunction
functionvoidstart_of_simulation_phase(uvm_phasephase);
$display("%0t:%0s:start_of_simulation",$time,get_full_name());
endfunction
functionvoidextract_phase(uvm_phasephase);
$display("%0t:%0s:extract",$time,get_full_name());
endfunction
functionvoidcheck_phase(uvm_phasephase);
$display("%0t:%0s:check",$time,get_full_name());
endfunction

Table1:Summaryofthechangesinphasemethods
3.2 AdditionalphasesinUVM
UVMsawtheintroductionofalargenumberofnewphasestogivefinercontroloverthesimulation.ThesearesummarisedinError!Reference
sourcenotfound.below.

OVM UVM

Table2:AdditionalphasesinUVM
4 ManagingtheEndofTest
Moderntestbenchesprovideawayforcomponentsandobjectstosynchronizetheirtestingactivityandindicateitissafetoendthephaseand
thesimulation.UVM(andOVM)providesabuiltinobjectionforeachphasewhichallowsacomponenttoobjecttothephaseending.This
objectionmechanismgivesastructuredwayforhierarchicaltestbenchcomponentsstatustocommunicatetheirstatus.Forexample,a
componentmayraiseanobjectionwhenitstartsatransactionwiththeDUT(DesignUnderTest)andnotdropthatobjectionunderthe
transactioniscomplete.OracomponentexpectingaresponsefromtheDUTwillkeepanobjectionraiseduntiltheresponseisreceived.
Notethattheuvm_test_doneobjectionalsoworksinUVM,butitisnottherecommendedwayofmanagingtheendoftest.InUVMitis
recommendedtousetheavailabletimeconsumingphases,sousingaglobalvariableisnolongerarobustmechanism.
InOVM,callingglobal_stop_requestwasnotrecommendedbutitwasnotdeprecated.
OVM UVM

t ask r un( ) ;
seq. st ar t ( m_vi r t ual _sequencer ) ;
global_stop_request();
endt ask

t ask r un_phase( uvm_phase phase ) ;
phase.raise_objection( this );
seq. st ar t ( m_vi r t ual _sequencer ) ;
phase.lower_objection( this );

endt ask

t ask r un( ) ;
ovm_test_done.raise_objection( ) ;
seq. st ar t ( m_vi r t ual _sequencer ) ;
ovm_test_done.drop_objection( ) ;
endt ask

t ask r un_phase( uvm_phase phase ) ;
phase.raise_objection( t hi s , " st ar t ed sequence"
) ;
seq. st ar t ( m_vi r t ual _sequencer ) ;
phase.drop_objection( t hi s , " f i ni shed
sequence" ) ;

endt ask

Table3:ComparingendoftestinOVMandUVM

5 ConfiguringComponent
InUVMitisrecommendedtouseuvm_config_dbmethodforconfiguringcomponents.OVMusedthe[set,get]_config_[int,string,object]
methodsforconfiguringcomponents.TheUVMequivalentsofthesemethodsareavailable,butnotrecommended.
Theuvm_config_dbisparameterizedbythetypeofobjectthatisbeingconfigured.
OVM UVM
cl ass my_env ext ends ovm_env;
. . .
f unct i on voi d bui l d( ) ;
ahb_cf g = ahb_conf i g: : t ype_i d: : cr eat e( " ahb_cf g" ) ;
ahb_cf g. wi dt h = 16;
/ / set addi t i onal f i el ds
set_config_object("*","ahb_cfg",ahb_cfg);
endf unct i on
. . .
endcl ass

cl ass my_ahb_agent ext ends ovm_component ;
. . .
f unct i on voi d bui l d( ) ;
ovm_obj ect cf g;
ahb_conf i g my_cf g;
asser t ( get _conf i g_obj ect ( " ahb_cf g" , cf g, 0) ;
i f ( !$cast(my_cfg, cfg))
ovm_r epor t _er r or ( . . . ) ;
. . .
endf unct i on
. . .
endcl ass

cl ass my_env ext ends uvm_env;

. . .
f unct i on voi d bui l d( ) ;
ahb_cf g = ahb_conf i g: : t ype_i d: : cr eat e( " ahb_cf g" ) ;
ahb_cf g. wi dt h = 16;
/ / set addi t i onal f i el ds
uvm_conf i g_db#( ahb_conf i g) : : set (
t hi s, " ahb_agent " , " ahb_cf g" , ahb_cf g) ;
endf unct i on
. . .
endcl ass
cl ass my_ahb_agent ext ends uvm_component ;
. . .
f unct i on voi d bui l d( ) ;
ahb_conf i g my_cf g;
i f ( ! uvm_conf i g_db: : ahb_conf i g: : get (
t hi s, " " , " ahb_cf g" , my_cf g) ;
`uvm_er r or ( . . . )
. . .
endf unct i on
. . .
endcl ass
Table4:ConfiguringcomponentsinOVMandUVM

Itisrecommendedtoavoidusingassign_vifunctionthattakesavirtualinterfacehandleasanargumentandcallsanequivalentfunctionon
oneormorechildcomponent.Thisisrepeateddownuntilthelastcomponentreached.

Followingapproachisnotrecommended
XBUS ENV

function void assign_vi(virtual interface xbus_if xi);
xi0 = xi;
if( bus_monitor != null) begin
bus_monitor.assign_vi(xi);
end
for(int i = 0; i < num_masters; i++) begin
masters[i].assign_vi(xi);
end
for(int i = 0; i < num_slaves; i++) begin
slaves[i].assign_vi(xi);
end
endfunction : assign_vi

AGENT

function void assign_vi(virtual interface xbus_if xmi);
monitor.assign_vi(xmi);
if (is_active == UVM_ACTIVE) begin
sequencer.assign_vi(xmi);
driver.assign_vi(xmi);
end
endfunction : assign_vi
Table5:Avoidusingassign_vi
Figure3:Thestepsinvolvedinusingtheregistermodel

6 UVMRegisterlayer
ConstrainedrandomtestbenchesarerequiredtomodeltheDUTbehaviourtopredictexpectedbehaviours.Thisincludesmodelsofthe
registersand/ormemorieswithintheDUT.TheUVMprovidesregisterlayerclassestocreateahighlevel,objectorientedmodelformemory
mappedregistersandmemoriesinadesignunderverification.Thefollowingmethodologyfeaturesarekeytobuildingandusingsuchamodel.
CreateanabstractmodeloftheregistersandmemoriesinDUT
o TomaintainamirroroftheDUTregisters.
CreateahierarchythatisanalogoustotheDUThierarchy
o RegisterBlock
o RegisterFile
o Memory
o Register
o Field
ProvideaccesstotheregisterthroughadefinedAPI
o Addressindependentinstance/stringnames
Modeltheaddressmap
o Modelaccessviaspecificinterface
Figure3oppositeshowsthestepsinvolvedinusingtheregister
model.
6.1 AccessAPI
Table6:RegisteraccessAPIbelowgivesanoverviewoftheregisteraccessAPIandhowitshouldbeused.
Command Description
Read()/Write()

GeneratePhysicalReadfromtheDUT
GeneratephysicalWritetotheDUT
Peek()/poke()

Peek()orpoke()methodsRead/writedirectlytotheregister
Get()/set()

Get()orset()methodsread/writedirectlytothedesiredvalue
Update()

Update()theDUTwithdesiredvalueinthemodel
Mirror()

ReadtheDUTregisterandcheck/updatethemodelvalue
Table6:RegisteraccessAPI
7 Summary
Overtheyearsvariousverificationmethodologieshavebeenintroducedinordertooptimiseuseofscarceverificationresources.The
methodologieshavefollowedanevolutionthathasbroughtusnaturallytoUVManindustrywidemethodologybuiltonanopensource
languageandlibrary.
InthispaperwehaveshownwhatisrequiredinordertotransitionfromOVMtoUVM.