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The 8096 is a 16-bit microcontroller suited for embedded control applications. It has features of the 8051 microcontroller like a register file, arithmetic logic unit, and control unit. Additional features include an analog-to-digital converter, high-speed inputs/outputs, pulse-width modulation, and a watchdog timer. The 8096 architecture contains functional units connected by an 8-bit address bus and 16-bit data bus, including memory blocks, timers, serial ports, and an analog-to-digital converter.
The 8096 is a 16-bit microcontroller suited for embedded control applications. It has features of the 8051 microcontroller like a register file, arithmetic logic unit, and control unit. Additional features include an analog-to-digital converter, high-speed inputs/outputs, pulse-width modulation, and a watchdog timer. The 8096 architecture contains functional units connected by an 8-bit address bus and 16-bit data bus, including memory blocks, timers, serial ports, and an analog-to-digital converter.
The 8096 is a 16-bit microcontroller suited for embedded control applications. It has features of the 8051 microcontroller like a register file, arithmetic logic unit, and control unit. Additional features include an analog-to-digital converter, high-speed inputs/outputs, pulse-width modulation, and a watchdog timer. The 8096 architecture contains functional units connected by an 8-bit address bus and 16-bit data bus, including memory blocks, timers, serial ports, and an analog-to-digital converter.
The 8096 is a 16 bit microcontroller. It is specially suited for embedded control
applications. It has all the features of 8051, except bit addressing and bit manipulation. The additional features present in 8096 are !" con#erter, high speed inputs, and high speed outputs, generation of analog output analog #oltage and mechanism for self$chec%ing in runtime. It has a po&erful instruction set and addressing modes. Features of 8096 'i( It is a 16 bit microcontroller. 'ii( 8096 is been designed for high speed!high performance control applications. 'iii( It has 8 multiplexed input analog to digital con#erter &ith 10 bit resolution. 'i#( The high speed I!) section of 8096 comprises a 16 bit timer, a 16 bit counter and * input programmable edge detector, * soft&are timers and 6 output programmable e#ent generator. '#( Its serial port support different modes of operation &ith programmable baud rates. '#i( It supports register to register architecture &hich increases processing speed. '#ii( It is programmable pulse &idth modulation '+,-( output signals can be used as control signals to dri#e a motor or any other application. '#iii(It has 100 instructions that can operate on bit, byte, &ord, double &ords. 'ix( It consists of a complete set of 16 bit arithmetic instructions that include multiply and di#ide operations. 'x( It allo&s bit operations. They are done on any bit in the register file or in the special function register. 'xi( .ogical are arithmetic instructions support byte and &ord operations. 'xii( The &atchdog timer can be used to reset the system if soft&are fails to operate properly. Architecture The 8096 family of microcontrollers has se#eral sections, all of &hich &or% in an integrate manner to obtain high performance computing and control. The ma/or sections include a 16 bit 0+1, a programmable high speed input!output unit, on$chip 2-, on$chip 2)-, analog to digital con#erter, serial port and pulse$&idth modulated output for analog to digital con#erter. 3igure sho&s the internal architecture of 8096 microcontroller. It consists of se#eral functional units. They are. 'i( 0+1 &ith 454 byte register file and register .1. 'ii( 867 internal 2)-. 'iii( +rogrammable high speed I!) unit. 'i#( T&o 16 bit timers!counters. 8096 Microcontroller '#( 8erial ports. '#i( +ulse &idth modulator. '#ii( ,atchdog timer '#iii(-emory controller. 'ix( 9ight multiplexed inputs !" con#erter &ith 10 bit resolution. 8096 Architecture Block Diagram The t&o main buses address bus and data buses are used for inter$processor communication. The address bus is 8 bit and data bus is 16 bit. The data bus transfers data bet&een 2.1 and register file or special function registers. '832s(. The address bus pro#ides addresses for multiplexed address!data bus connecting to the memory controller. The memory controller pro#ides the addresses for the internal 2)- and external memory. Memory Organization The 8096 can access upto 6* 67 memory. The scratch pad register 'called as register file(, special function registers, on$chip 2-, on$chip 2)- and external memory space are the main constituents of memory. 3igure sho&s the map of 6*%7 addressable memory space. The basic bloc%s are: (i) Internal RAM containing 'a( 8pecial function registers '00 to 1;<(. 'b( 8tac% pointer '18< and 19 <( 'c( 2egister file '1< to 93<( 'd( +o&er do&n 2- '30< to 33<( This memory area is accessed as data memory. =o code can be executed from this area. The program memory area of 00 to 33< is reser#ed for internal use of Intel de#elopment systems. (ii) Internal ROM If the chip has on$chip 2)- then it has interrupt #ectors, factory test code, and internal program storage. It is a#ailable at addresses '4000< > 5333<(. If the chip does not contain 2)-, then these are defined in the external memory. (iii) !ternal memory or I"O are a#aila$le at addresses (0%00& ' %FF(&) and ()000& ' FFFF&)* (i#) +ort , and ) locations (%FF& and %FFF&) for the reconfiguration if they are not used as address"data lines* ,hen the 8096 is reset, address 4080< is loaded to the program counter to gi#e 8 67 of contiguous memory. Memory Map -+. /ection The central processing unit is responsible for processing arithmetic and logical operations and for generation of control signals. The different control signals are generated depending on the instruction being executed. The 0+1 comprises of the follo&ing : 'i( 2egister file 'ii( 2egister rithmetic and logic unit '2.1( 'iii( 0ontrol unit. Register File The follo&ing figure sho&s the complete internal 2- memory map. The 0+1 register file has 456 bytes of memory from location 00< to 33<. =o code can be executed from these 0+1 register file locations. If an attempt is made to execute instructions from these locations, the instructions &ill be automatically fetched from the external memory. T&o 8 bit temporary registers are pro#ided by 0+1 hard&are. They are used to access the locations from the 0+1 file. Internal Ram /tructure in 8096 )f the 456 locations, first 4* memory locations 00< > 1;< are special function registers '832s(. 832s are used to control the on$chip I!) section. The remaining 454 are 2- locations. These locations can be accessed as bytes, &ords or double &ords. 9ach of these 454 locations can be used by the 2.1. <ence, there are 454 accumulators. The first &ord in the 2- locations 18< and 19< is stac% pointer. They can be used as part of the register file if stac% operation is not done. The stoc% pointer must be initiali?ed by user program. It can point any&here in 6* 67 'external( memory space. The upper 16 bytes '030 > 033<( are %ept ali#e, e#en &hen the po&er fails. This feature is described under po&er do&n 2-. These locations recei#e their po&er from @ +" pin in po&er do&n mode. <ence, only in the po&er do&n mode these locations are ali#e. /0ecial Function Registers (/FRs) The 0+1 communicates &ith the other resources of 8096 through special function registers '832s( defined in the internal 2- space 00< > 19<. Through these 8328, the 0+1 controls the #arious timers, high speed I!) points, interrupts, "0, stac% and I!) ports. 3igure sho&s the locations and names of 832s. -any of the 832s ser#ice t&o functions, one if they are read and other if they are &ritten. -+. 1uses There are t&o buses 'address( and " 'data( bus. The different units of 0+1 interact &ith each other through these buses. The address bus is 8 bit &ide and data bus is 16 bit &ide. "ata bus is used for sending!recei#ing data information. The reason for ma%ing address bus 8 bit &ide is that internal on$chip 2- containing 832s and register file is 456 bytes long and can be directly addressed by using on 8 bit address. 3or 16 bit transfer t&o memory cycles &ill be needed. RA2. The register arithmetic and logic unit '2.1( contains : 'i( 1; bit .1 'ii( +rogram counter A incrementer. 'iii( +rogram status &ord. 'i#( .oop counter '5 bit(. '#( T&o shift registers '1; bit(. '#i( Temporary registers '1; bit(. 3or instruction reBuiring shift for execution, shift registers are pro#ided. e.g. : shift left, shift right, normali?e, multiply, di#ide etc. ,hen a 16 bit data is to be shifted, an upper &ord register!shifter is used. The lo&er &ord!shifter is used along &ith upper &ord register!shifter in case of 54 bit shift. 3or the instructions that reBuire repetiti#e shifts 'e.g. shift right by 5 bits(, a 5 bit loop counter is useful. 3or execution of t&o operand instructions, a temporary register is pro#ided. This temporary register stores the multiplier during the execution of multiplication instruction, or di#isor during execution of di#ision instruction. 3or the execution of increment!decrement instructions some constants are defined. The constants 0, 1, 4 are stored in 2.1 to execute the instruction faster. The bus 'address bus( is 8 bit &ide. It is used to transfer 16 bit address or data information to memory controller or other units. delay circuit is pro#ided. It facilitates transfer of lo&er byte follo&ed by delay follo&ed by upper byte to the memory controller. +rogram counter and incrementer are pro#ided in 2.1 to increment the +0 after execution of each instruction. Thus, it points to the next instruction to be executed. In case of /ump instructions being executed, the program counter is modified through .1. +rogram /tatus 3ord The program status &ord signifies the status of interrupt flags as &ell as condition flags at any instant. %4 %) %, %5 %% %0 9 8 6 6 4 ) , 5 % 0 C = @ @T 0 > I 8T Interrupt -as% 2egister +rogram /tatus 3ord (+/3) C: Indicates that the result of last arithmetic!logic instruction &as ?ero. =: Indicates that the last instruction generated negati#e result. @: 2esult generated in outside the range that can be expressed in the destination data type thus causing o#erflo&. @T: ,hen the @ flag is set, @T 'o#erflo& trap( is also set. <o&e#er, it can be reset by certain explicit instructions. It is useful in debugging the program. 0: Indicates that a bit is shifted out of -87 or I87 position because of arithmetic or shift operations. 8T: 0an be used for controlling rounding after right shift called Dstic%y bitE. It indicates that 1 has been shifted first to c flag and then out during right shift. I: It is set by 9I instruction and cleared by "I instruction. It indicates global interrupt enable!disable. These conditional flags 'except I( can be used in conditional /ump instructions. -ontrol .nit The control unit contains the instruction register, the decoder and timing unit to generate #arious control signals. The instruction is transferred to the control unit through bus and is stored in the instruction register. The instruction is decoded and the reBuired signals are generated for 2.1 control. Memory -ontroller The memory controller is used as the interface bet&een 2.1 and external memory or on$chip 2)-. The 8 bit &ide address bus is used to transfer the address and data bet&een 2.1 and memory controller. ,hene#er 2.1 &ants an instruction!data from memory it should send the lo&er byte of address on address bus follo&ed by the upper byte of address. The memory controller interacts &ith the external memory through an external address!data bus " 0 > " 15 'ports 5, *(. I"O /-7IO8 ll of the on$chip I!) feature of 8096 can be accessed through the special function registers. There are se#en ma/or I!) functions. Major I/O Functions I"O functions <igh speed input unit +ro#ides utomatic recording of e#ents. <igh speed output unit +ro#ides automatic triggering of e#ents and real time interrupts. +ulse &idth modulation )utput to dri#e motors or analog circuits. to " con#erter +ro#ides analog to digital con#ersion ,atchdog Timer 2esets 8096 if a malfunction occurs. 8erial port +ro#ides synchronous or asynchronous lin%. 8tandard I!) lines +ro#ide interface to external &orld. 7imers There are t&o 16 bit$timers: Timer 1 and Timer 4. Timer 1 is a 16 bit free running timer. It is used to synchroni?e e#ents to real time. Timer 4 can be cloc%ed externally. It synchroni?es e#ents to external occurrences. The high speed I!) unit is coupled to the timers. <8I records the #alue &hen transitions occurs on timer 1. <8) causes transitions to occur based on #alues of Timer 1 or Timer 4. 7imer % Timer 1 is used to pro#ide real time cloc% for external e#ents that are recorded on <igh 8peed Input '<8I( lines or &hich are generated on <igh 8peed )utput '<8)( lines of 8096. The input cloc% is i.e. it is cloc%ed once e#ery eight state times. 'e.g. : for a 14 -<?, the state time is 0.45 s. <ence period of Timer 1 cloc% is 4 s(. It can be reset only by executing a reset. The only other &ay to change its #alue is by &riting to 0000<. 7ut it is a test mode that sets both the timers to 0333F< and should not used in programs. 7imers 5 Timer 4 is an e#ent counter as if uses an external cloc% source. It can ha#e on of follo&ing sources as cloc% : 'i( Timer 4 cloc% 'port p 4.5( 'ii( <igh speed input line no. 1. The selection of cloc% source can be done by the user programming the bit ; of I!) control register 0. 'I)00.;(. Timer 4 is used for generating high speed outputs. The maximum speed of timer 4 is once per eight state times. Timer 4 is incremented by transitions 'one count by each falling edge or rising edge(. Timer 4 can be reset by the follo&ing methods. 'i( by executing a reset. 'ii( by setting I)00, 1 'iii( triggering the <8) channel 1* '09<(. 'i#( by setting <I8.0 G 1 or I)00.5 G 1 and pulling T28T. 3igure sho&s different methods of manipulating Timer 4. 7imer 5 -loc9 and Reset O0tions 7imer Interru0ts The t&o Timers 1 and Timer 4 can be used to trigger a timer o#erflo& interrupt and set a flag in the I!) status register 1 'I)81(. The interrupts are controlled by I)01.4 and I)01.5. The flags are set in I)81.5 and I)81.*. The enabling and disabling of timer interrupts are controlled by the interrupt mass register bit 0. In all cases, setting a bit enables a function &hile clearing a bit disables it. &igh /0eed In0uts (&/I) The <8I unit can be used to record the time at &hich an e#ent occurs &ith respect to Timer 1. There are * lines. '<8I.0, <8I.1, <8I.4 and <8I.5(. These are used in this mode to record up to 8 e#ents. <8I.4 and <8I.5 are bidirectional pins. They can be used as <8).* and <8).5. The I!) control registers I)00 and I)01 are used to determine the functions of these pins. 3ig. 15.6.4 sho&s <8I unit bloc% diagram. &/I .nit It can measure pulse &idths and record times of e#ents &ith a 4s resolution. &/I Modes 3or each <8I there are * modes of operation. The <8I mode register is used to control the pins that loo% for type of e#ents. 3ig. 15.6.5 sho&s the <8I mode register. ,here each 4$bit mode control field "efines one of * possible modes: 00 8 positi#e transitions 01 9ach positi#e transition 10 9ach negati#e transition 11 9#ery transition '+ositi#e and negati#e( &/I Mode Register The information is then stored in a se#el le#el 3I3) for later retrie#al. <igh and lo& le#els of inputs reBuire to be held for 1 state time to ensure proper operation. The maximum input speed is 1 e#ent e#ery 8 state times except &hen the 8 transition mode is used, is &hich one transition per state is allo&ed. The <8I lines can be enabled and disabled using bits I)00 at location 0015<. &/I FIFO ,hen an <8I e#ent occurs, a 8 40 3I3) stores the 16 bits of Timer 1 and * bits indicating the state of * <8I lines at the time the status is read. It can ta%e up to 8 state times for the information to reach the holding register. <ence, 8 state times are allo&ed bet&een consecuti#e reads of <8IHTI-9. ,hen the 3I3) is full, an additional e#ent for a total of 8 e#ents can be stored considering the holding register as a part of 3I3). If the 3I3) and holding register are full, any additional e#ent &ill not be recorded. It &ill cause an o#erflo& condition. &/I Interru0ts <8I unit generates interrupts in one of t&o methods determined by I)01.;. If a bit is 0, then an interrupt is generated each time a #alue is loaded in to the holding register. If bit is 1 an interrupt is generated &hen the 3I3) has six entries in it. ll the interrupts are rising edge triggered. <ence, if I)01.; G 1 then the processor &ill not be re$interrupted till the 3I3) contains 5 or less records. The interrupts can also be generated by <8I.0 pin that has its o&n interrupt #ector location 4008<. Thus, an <8I unit generates interrupts in 5 methods. &/I /tatus The status of <8I 3I3) is sho&n by bits 6 and ; of the I!) status register 1 'I)81(. If bit 6 is 1, the 3I3) contains at least 6 entries. If bit ; is 1, the 3I3) contains at least one entry and the holding register has been located. The 3I3) can be read after #erifying it contains #alid data. ,hile reading or testing bits in I)81 it is essential to store the byte and then test the stored #alue. The <8I can be read in t&o steps. Initially the <8I status register is read in order to obtain the current state of the <8I pins and &hich pins ha#e changed at the recorded time. 3igure sho&s the <8I status register. ,here for each 4 bit status field the lo& bit indicates &hether or not an e#en has occurred on this pin at the time in <8I time and the upper bit indicates the current status of the pin. Then the <8I time register is read. 2eading the time register unloads one &ord of the 3I3), so if the time register is read before the status register, the information in the status register is lost. It is at location 06 <. The <8I time registers are at located 0* and 05<. If the <8I time and status registers are read &ithout the holding register being loaded, the #alues read &ill be undeterminable. &/O -AM 3igure sho&s bloc% diagram of <8) unit. &igh /0eed Out0ut .nit content addressable memory file is the main component of the <8). It stores up to 8 e#ents that are pending to occur. 9#ery state time one location of 0- is compared &ith the t&o timers. fter 8 state times, the entire 0- is been searched for time matches. If a match occurs a specified e#ent &ill be triggered and that location of 0- &ill be made a#ailable for another pending e#ent. 9ach 0- register is 45 bits &ide. 3ig. 15.6.; sho&s the format of command to <8) unit. &/O -ommand 7ag Format To enter a command into 0- file, &rite ; bit command tag to location 0006< follo&ed by time at &hich action is to be carried into &ord address 000*<. It is essential to disable interrupts &hile &riting a command tag for <8). If an interrupt occurs during the time bet&een &riting the command tag and loading the time #alue, then the I82 &rites to <8) time register. The command tag is &ritten to 0-. The command tag from main program &ill not be executed. &/O Interru0ts The <8) unit can generate t&o type of interrupts. The <8) execution interrupts and the timer interrupt. The <8) execution interrupts '#ector G 4006 <( is generated &hen <8) commands operate one or more of six output pins. <o&e#er it is a mas%able interrupt. The soft&are timer interrupt is generated by any other <8) command li%e triggering the !", resetting Timer 4 or generating soft&are delay. &/O /tatus The holding register must be empty before &riting to <8). If the holding register is not empty, it &ill o#er&rite #alue in the holding register. The I!) status register 'I)80( bits 6 and ; indicted status of <8) unit. If I)80.6 G 0, holding register is empty and atleast one 0- register is empty. If I)80.; G 0, the holding resister is empty. -learing &/O ll 8 0- locations are compared before any action is ta%en. It allo&s a pending external e#ent to be cancelled by &riting the opposite e#ent to the 0-. <o&e#er, if an entry is placed in the 0- it cannot be remo#ed till either the specified timer matches the &ritten #alues or chip is reset. Internal e#ents are not synchroni?ed to timer 1. <ence they cannot be cleared. It includes e#ents on <8) channels 8 through 3 and all interrupts. The interrupts are not synchroni?ed. <ence, it is possible to ha#e multiple interrupts at same time. .sing 7imer 5 :ith &/O The timer 1 is incremented once e#ery 8 state times. If it is being used as a reference timer for the <8) action, then the comparator can obser#e all 8 0- registers before Timer 1 changes its #alue. Timer 4 is synchroni?ed to allo& it to change to a maximum rate of once per 8 state times. The Timer 4 increments on both the edges of the input signal. If Timer 4 is used as a reference, care must be ta%en that the Timer 4 is not reset prior to highest #alue for a Timer 4 match in the 0- because <8) 0- holds the pending e#ent till a time match occurs. If match is not reached then the e#ent remains pending in the 0- fill the 8096 is reset. ,hen Timer 4 is reset using <8) unit additional, care must be ta%en. This is because the <8) e#ent is an internal e#ent. It can happen at any time in the eight state time &indo&. If t&o e#ents are scheduled such that they must occur at the same time as the Timer 4 reset then they must be logged into the 0- &ith a Timer #alue of ?ero. If this method is used to design a programmable modulo counter, the count &ill remain at the maximum #alue of Timer 4 till a reset Timer 4 command is gi#en. The count remains ?ero for a transition that &ould change the count #alue from D=E to ?ero and then change on the next transition. /oft:are 7imers t present times the <8) can be programmed to generate interrupts. t a time four soft&are interrupts can be used. soft&are Timer flag is set by the <8) unit e#ery time a programmed time is reached. n interrupt &ill be generated if the interrupt bit in the command tag is set. The Interrupt 8er#ice 2outine 'I82( can then obser#e the contents of the I!) status register 1 'I)81( to tell &hich of the soft&are timers has expired and generated the interrupt. ,hen the <8) resets Timer 4 or starts an ! " con#ersion it can be programmed to generate a soft&are timer interrupt. There is no flag to indicate the occurrence of e#ent. -ultiple interrupts can also be generated. +ulse 3idth Modulation Out0ut 3igure sho&s the bloc% diagram of a pulse &idth modulation circuit. It comprises of +,- register, +,- counter and comparator. +ulse :idth modulated circuit The +,- output is set to one &hen the counter #alue is ?ero. The 8 bit is incremented e#ery state time. If the counter #alue matches &ith the #alue in the +,- register the output is s&itched lo&. Incase the counter o#erflo&s the output is again s&itched high. The output is lo& &hen the #alue of +,- register is 00. The output &a#eform is #ariable duty cycle pulse that repeats e#ery 456 state times. '6* s at 14 -<?(. 7y &riting the +,- register at location 1;<, changes are made in the duty cycle. =ormally motors need +,- &a#eform for efficient operation. If the +,- &a#eform is integrated it produces a "0 le#el that can be changed in 456 steps by modifying the duty cycle. +ort 4 pin5 is shared &ith the +,- output. <ence, both these features cannot be used at the same time. The +,- function is selected by I)001. 0 bit is set. +3M out0uts /erial +ort The 8096 has an on$chip serial port to minimi?e the number of chips needed in the system. It has one synchronous and three asynchronous modes. In the asynchronous modes baud rate of upto 18.5 6baud can be used &hile in asynchronous mode baud rates upto 1.5 -baud are a#ailable. The chip has a baud rate generator that is independent of Timer 1 and Timer 4. The asynchronous modes are full duplex i.e. they can simultaneously transmit and recei#e. lso they are double buffered i.e. they can begin reception of the second data byte before a pre#iously recei#ed byte has been read from the recei#e register. The serial port registers used for transmission and reception are 8713_Tx and 8713_2x. 7oth these registers share same address 0;<. They are physically separate. The 8713_Tx register hold data that is ready for transmission &hile 8713_2x register has data that is recei#ed by the serial port. 3igure sho&s the serial port status ! control register. 0ontrol of serial port is pro#ided through the 8+0)= ! 8+8TT register. 8ome bits are read only &hile some bits are &rite only. The four modes of serial port are modes 0, 1, 4 and 5. Mode 0 It is a synchronous mode. It is commonly used for interfacing to shift registers for I!) expansion. In this mode the port outputs a pulse train on the Tx" pin and either transmits or recei#es data on the 2x" pin. Mode % It is standard asynchronous modeI 8 bits plus a stop bit and start bit are sent or recei#ed. <ence, total frame si?e is of 10 bits. If parity is enabled '+9= G 1( then an e#en parity bit is transmitted instead of 8 th data bit. It is commonly used for 02T terminals. -ode 4 It is an asynchronous 9 th bit recognition mode. 11 bit frames are transmitted through the Tx" and are recei#ed through 2x" start bit 0, 8 data bits, a programmable 9 th bit and one stop bit. 0 or 1 can be assigned to the 9 th data bit using the 88 bit in control register before &riting to 8713_Tx. This bit can be used to pro#ide a selecti#e reception on the data lin%. The serial port interrupt and recei#e interrupt '2I( &ill not be acti#ated till the 9 th recei#ed bit is 1 during the reception of data. -ode 4 is used &ith 5 for multiprocessor communication. Mode , It is also an asynchronous 9 th bit mode. 11 bit frames a transmitted &ith one start bit, 8 data bits, a programmable 9 th bit and one stop bit. 11 bit data frame is identical to data frame of mode 4. The only difference is that the 9 th bit becomes a parity bit. If parity is not enabled '+9= G 0(, the T78 controls the status of ninth transmitted bit. It must be set before each transmission. )n reception, if +9= G 0, the 278 bit indicates the state of the ninth recei#ed bit. If the parity is enabled i.e. +9= G 1 then the same bit is called '2+9( recei#e parity error. It is used to indicate a parity error. Multi0rocessor -ommunication -odes 4 and 5 can be used for multiprocessor configuration. Multi0rocessor communication If the 9 th recei#ed bit is not set in mode 4 then the serial port interrupt is not acti#ated. This feature is used in multiprocessor systems. ,hen the master processor &ishes to transmit a bloc% of data to one of its se#eral sla#es then it first sends an address frame that identifies the target sla#e. n address frame &ill differ from the data frame by the 9 th data bit. If the 9 th data bit is 1 then it is an address frame, if bit is 0 then it is a data frame. data frame does not interrupt a sla#e in mode 4. <o&e#er an address frame interrupts all sla#es so that each sla#e can examine the recei#ed byte and obser#e if it is being addressed. The addressed sla#e &ill s&itch to mode 5 in order to recei#e the coming data frames. The sla#es that &ere unaddressed remain in mode 4 and do not recei#e any byte. (etermining 1aud Rates The baud rates for all the modes are controlled &ith the help of a baud rate register. It is a byte &ide register that is seBuentially loaded &ith t&o bytes. It internally stores the #alue as a &ord. The least significant byte is loaded to the register follo&ed by the most significant byte. The most significant byte of the baud #alue determines the cloc% source for the baud rate generator. If a bit is one, the FT.1 pin is used as source, if bit is ?ero, the T4 0.6 pin is used. The baud rate formulas are gi#en belo&: .sing ;7A2% -ode 0: 7aud rate G I 70 )thers: 7aud rate G .sing 75 -2< -ode 0: 7aud rate G I 70 )thers: 7aud rate G I 70 8ote= 7 cannot be eBual to 0, except &hen using FT.1 in other mode than mode 0. The #ariable D7E is used to represent the least significant 15 bits of the #alue loaded into the baud rate register. The maximum #alue of 7 is 54;6;. Table 15.6.4 gi#es baud rates for #alues 10, 11, 14 -<? I"O +orts 0> %> 5> , and ) 8096 has fi#e 8 bit I!) ports. 8ome of them are input ports &hile some of the ports are output ports and other ports are bidirectional and ha#e alternate functions. The input ports connect to the internal bus through an input buffer. The output ports connect through the output buffer to an internal register that holds the output bits. 7i$directional ports comprise of an internal register, an input buffer and an output buffer. ,hen an instruction accesses a bidirectional port as source register, the #alue comes from the port pins, not the internal register. +ort 0 +ort 0 is an input port. It shares its pins &ith the analog inputs to the !" con#erter. +ort % is a Buasi$bidirectional I!) port. The &ord DBuasi$bidirectionalE means that the port pin has a &ea% internal pull up that is al&ays acti#e and an internal pull$ do&n than can be on!off. The pinJs logic le#el can be controlled by an external pull$do&n if the internal pull$do&n is left off. 'i.e. a 1 is &ritten(. Buasi$bidirectional port &ill source current if externally held it. It &ill pull itself high if it is left unconnected. If the processor &rites to the pins of a Buasi$bidirectional port it actually &rites into the register that dri#es the port pin. If the port pin is to be used as an input then the soft&are must &rite a one to 832 bit. This causes the lo& impedance pull do&n de#ice to turn off and lea#e the pin pulled &ith a high impedance pull up de#ice that can be dri#en by the de#ice that dri#es the input. +ort 5 It is a multi$functional port. +ort 4 functions +ort Functio n Alternate Function -ontrolled $y +4.0 )utput Tx" '8erial +ort Transmit( I)01.5 +4.1 Input 2x" '8erial +ort 2ecei#e( in -odel $5 =! +4.1 )utput 2x" '8erial )utput +ort( in -ode 0 =! +4.4 Input 9xternal interrupt I)01.1 +4.5 Input T40.6 'Timer 4 input( I)01.; +4.* Input 2428T 'Timer 4 2eset( I)00.5 +4.5 )utput +,- '+ulse ,idth -odulation( I)01.0 +4.6 Kuasi$bidirectional =! +4.; Kuasi$bidirectional =! +orts , and )" A( 0 ' A( %4 These pins ser#e as bidirectional ports &ith open drain outputs or system bus pins used by memory controller &hen it accesses external memory. If the line is lo&, it ser#es as system bus. If line is set then they are used as +orts. A"( -on#erter The !" con#erter on 8096 pro#ides 8 input channels &ith a 10 bit digital output. The channels are multiplexed. 3or !" con#ersion successi#e approximation method is used. The digital output is eBui#alent to ratio of input #oltage di#ided by the analog supply #oltage. If ratio is unity then result is all ones. A"( -on#ersion 7ime and Formula )n 8096 each con#ersion need 168 state times '*4 s at 14 -<?( independent of accuracy of #alue of input #oltage. )n 8096 7< each con#ersion reBuires 88 state times '44 s at 14 -<?( independent of accuracy or #alue of input #oltage. The analog input #oltage should be in range of 0 to @ 233 !" result is calculated as, G The change in @ 293 or =L=" effects the output of the con#erter. It is ad#antageous if a radiometric sensor is used as these sensors ha#e an output that can be measured in proportion of @293. 3atchdog 7imer (3(7) The &atchdog timer is a method of reco#ery from soft&are upset. fter it is initialised, if the soft&are fails to reset the &atchdog at least e#ery 6* 6 state times, a hard&are reset &ill be initiated. The system &ill not restart. The &atchdog timer is a 16 bit counter. It is incremented each and e#ery state time. It is cleared by program after periodic inter#al. It is not allo&ed to o#erflo&. If a program does not properly progress then an o#erflo& occurs. s a result of o#erflo& the hard&are causes the system to restart and pre#ents the controller from causing a malfunction for longer than 16 ms in case a 14 -<? oscillator is used. In reset the &atchdog timer can be disabled. clear ,"T instruction enables it. 0ode is first &ritten to ,"T register. The timer is cleared by &ritting a D019<E follo&ed by D091<E to ,"T register at memory location 00<. fter ,"T in initiali?ed, it cannot be disabled by soft&are. The only method to disable ,"T is to hold the 2989T pin at 4 to 4.5 #olts. @oltage abo#e 4.5 @ on pin can damage the ,"T. <ence, this method is not recommended for normal operation. It is only used for debugging. A(?A8-( RI/- MA-&I8/ (ARM) +RO-//OR/ The 2-;T"-I$8 processor is a member of the 2- family of general$ purpose 54$bit microprocessors. The 2- family offers high 0erformance for #ery lo:@0o:er consum0tion and gate count. The 2-;T"-I$8 processor has ?on 8eumann architecture, &ith a single 54$bit data bus carrying both instructions and data. )nly load, store, and s&ap instructions can access data from memory. The 2-;T"-I$8 processor uses a three stage pipeline to increase the speed of the flo& of instructions to the processor. This enables se#eral operations to ta%e place simultaneously, and the processing, and memory systems to operate continuously. ARM67(MI/ stands for 7: T<1-7 ( for on$chip "ebug support, enabling the processor to halt in response to a debug reBuest, M: enhanced -ultiplier, yield a full 6*$bit result, high performance I: 9mbedded I09 hard&are 'In 0ircuit emulator( /= 8ynthesi?able FA7.R/ OF ARM +RO-//OR/ The 2- processors are based on 2I80 architectures and this architecture has pro#ided small implementations, and #ery lo& po&er consumption. Implementation si?e, performance, and #ery lo& po&er consumption remain the %ey features in the de#elopment of the 2- de#ices. The typical 2I80 architectural features of 2- are : large uniform register file. load!store architecture, &here data$processing operations only operate on register contents, not directly on memory contents. 8imple addressing modes, &ith all load!store addresses being determined from register contents and instruction fields only uniform and fixed$length instruction fields, to simplify instruction decode. 0ontrol o#er both the rithmetic .ogic 1nit '.1( and shifter in most data$ processing instructions to maximi?e the use of an .1 and a shifter uto$increment and auto$decrement addressing modes to optimi?e program loops .oad and 8tore -ultiple instructions to maximi?e data throughput 0onditional execution of almost all instructions to maximi?e execution throughput. 7here are three $asic instruction sets for ARM* 54$ bit 2- instruction set 16 >bit Thumb instruction set. The Thumb instruction set is a subset of the most commonly used54$bit 2- instructions. Thumb instructions operate &ith the standard 2- register configurations, enabling excellent interoperability bet&een 2- and Thumb states. This Thumb state is nearly 65M of the 2- code and can pro#ide 160Mof the performance of 2- code &hen &or%ing on a 16$bit memory system. This Thumb mode is used in embedded systems &here memory resources are limited. AR-&I7-7.R OF ARM +RO-//OR/= The 2- ; processor is based on @on =eman model &ith a single bus for both data and instructions 'The 2-9 uses <ar#ard model(.2- uses the d#anced -icrocontroller 7us rchitecture '-7( bus architecture. This -7 include t&o system buses: the -7 <igh$8peed 7us '<7( or the d#anced 8ystem 7us '87(, and the d#anced +eripheral 7us '+7(. The 2- processor consists of Arithmetic 2ogic .nit (,5@$it) One 1ooth multi0lier(,5@$it) One 1arrel shifter One -ontrol unit Register file of ,6 registers each of ,5 $its* In addition to this the 2- also consists of a +rogram status register of 54 bits, 8ome special registers li%e the instruction register, memory data read and &rite register and memory address register ,one +riority encoder &hich is used in the multiple load and store instruction to indicate &hich register in the register file to be loaded or stored and -ultiplexers etc. ARM Registers= 2- has a total of 5; registers .In &hich $ 51 are general$ purpose registers of 54$bits, and six status registers .7ut all these registers are not seen at once. The processor state and operating mode decide &hich registers are a#ailable to the programmer. t any time, among the 51 general purpose registers only 16 registers are a#ailable to the user. The remaining 15 registers are used to speed up exception processing. there are t&o program status registers: 0+82 and 8+82 'the current and sa#ed program status registers, respecti#ely In 2- state the registers r0 to r15 are orthogonalNany instruction that you can apply to r0 you can eBually &ell apply to any of the other registers. The main ban% of 16 registers is used by all unpri#ileged code. These are the 1ser mode registers. 1ser mode is different from all other modes as it is unpri#ileged. In addition to this register ban%, there is also one 54$bit 0urrent +rogram status 2egister '0+82(. In the 15 registers, the r15 acts as a stac% pointer register and r1* acts as a lin% register and r15 acts as a program counter register. 2egister r15 is the sp register, and it is used to store the address of the stac% top. 215 is used by the +18< and +)+ instructions in T #ariants, and by the 828 and 239 instructions from 2-#6. 2egister 1* is the .in% 2egister '.2(. This register holds the address of the next instruction after a 7ranch and .in% '7. or 7.F( instruction, &hich is the instruction used to ma%e a subroutine call. It is also used for return address information on entry to exception modes. t all other times, 21* can be used as a general$purpose register. 2egister 15 is the +rogram 0ounter '+0(. It can be used in most instructions as a pointer to the instruction &hich is t&o instructions after the instruction being executed. The remaining 15 registers ha#e no special hard&are purpose. -+/R: The 2- core uses the 0+82 register to monitor and control internal operations. The 0+82 is a dedicated 54$bit register and resides in the register file. The 0+82 is di#ided into four fields, each of 8 bits &ide: flags, status, extension, and control. The extension and status fields are reser#ed for future use. The control field contains the processor mode, state, and interrupt mas% bits. The flags field contains the condition flags. The 54$bit 0+82 register is sho&n belo&. +rocessor Modes= There are se#en processor modes .8ix pri#ileged modes abort, fast interrupt reBuest, interrupt reBuest, super#isor, system, and undefined and one non$pri#ileged mode called user mode. The processor enters abort mode &hen there is a failed attempt to access memory. 3ast interrupt reBuest and interrupt reBuest modes correspond to the t&o interrupt le#els a#ailable on the 2- processor. 8uper#isor mode is the mode that the processor is in after reset and is generally the mode that an operating system %ernel operates in. 8ystem mode is a special #ersion of user mode that allo&s full read$&rite access to the 0+82. 1ndefined mode is used &hen the processor encounters an instruction that is undefined or not supported by the implementation. 1ser mode is used for programs and applications. 1an9ed Registers= )ut of the 54 registers, 40 registers are hidden from a program at different times. These registers are called ban%ed registers and are identified by the shading in the diagram. They are a#ailable only &hen the processor is in a particular modeI for example, abort mode has ban%ed registers r15Habt, r1*Habt and spsr Habt. 7an%ed registers of a particular mode are denoted by an underline character post$fixed to the mode mnemonic or Hmode. ,hen the T bit is 1, then the processor is in Thumb state. To change states the core executes a speciali?ed branch instruction and &hen TG 0 the processor is in 2- state and executes 2- instructions. There are t&o interrupt reBuest le#els a#ailable on the 2- processor coreNinterrupt reBuest 'I2K( and fast interrupt reBuest '3IK(. @, 0, C , = are the 0ondition flags . @ 'o#erflo&( : 8et if the result causes a signed o#erflo& 0 '0arry( : Is set &hen the result causes an unsigned carry C 'Cero( : This bit is set &hen the result after an arithmetic operation is ?ero, freBuently used to indicate eBuality = '=egati#e( : This bit is set &hen the bit 51 of the result is a binary 1. +I+ 2I8= +ipeline is the mechanism used by the 2I80 processor to execute instructions at an increased speed. This pipeline speeds up execution by fetching the next instruction &hile other instructions are being decoded and executed. "uring the execution of an instruction, the processor 3etches the instruction .It means loads an instruction from memory. nd decodes the instruction i.e identifies the instruction to be executed and finally 9xecutes the instruction and &rites the result bac% to a register. ARM +rocessor Families There are #arious 2- processors a#ailable in the mar%et for different application .These are grouped into different families based on the core .These families are based on the 2-;, 2-9, 2-10, and 2-11 cores. The numbers ;, 9, 10, and 11 indicate different core designs. The ascending number indicates an increase in performance and sophistication. Though 2- 8 &as introduced during 1996, it is no more a#ailable in the mar%et. The follo&ing table gi#es a brief comparison of their performance and a#ailable resources. The 2-; core has a @on =eumann>style architecture, &here both data and instructions use the same bus. The core has a three$stage pipeline and executes the architecture 2-#*T instruction set. The 2-;T"-I &as introduced in 1995 by 2-. It is currently a #ery popular core and is used in many 54$bit embedded processors. The 2-9 family &as released in 199;. It has fi#e stage pipeline architecture. <ence, the 2-9 processor can run at higher cloc% freBuencies than the 2-; family. The extra stages impro#e the o#erall performance of the processor. The memory system has been redesigned to follo& the <ar#ard architecture, &ith separate data and instruction buses. The first processor in the 2-9 family &as the 2-940T, &hich includes a separate " A I cache and an --1. This processor can be used by operating systems reBuiring #irtual memory support. 2-944T is a #ariation on the 2-940T but &ith half the " AI cache si?e. The latest core in the 2-9 product line is the 2-9469O$8 synthesi?able processor core, announced in 4000. It is designed for use in small portable Oa#a$ enabled de#ices such as 5L phones and personal digital assistants '+"s(. The 2-10 &as released in 1999 . It extends the 2-9 pipeline to six stages. It also supports an optional #ector floating$point '@3+( unit, &hich adds a se#enth stage to the 2-10 pipeline. The @3+ significantly increases floating$point performance and is compliant &ith the I999 ;5*.1985 floating$point standard The 2-1156O$8 is the 2-11 processor released in the year 4005 and it is designed for high performance and po&er efficient applications. 2-1156O$8 &as the first processor implementation to execute architecture 2-#6 instructions. It incorporates an eight$stage pipeline &ith separate load store and arithmetic pipelines. A $rief com0arison of different ARM families is 0resented $elo:= ARM Family Aear of Release Architecture +i0eline O0erational FreBuency Multi0lier MI+/ 2-; 1995 @on =eumann 5 stage 80-<? 8x54 0.9; 2-9 199; <ar#ard 5 stage 150-<? 8x54 1.1 2-10 1999 <ar#ard 6 stage 460-<? 16x54 1.5 2-11 4005 <ar#ard 8 stage 555-<? 16x 54 1.4