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Reg. No. :


M.E./M.Tech. DEGREE EXAMINATION, JUNE 2011.
Common to M.E. Applied Electronics/M.E. VLSI design
First Semester
252101 DSP INTEGRATED CIRCUITS
(Regulation 2010)
Time : Three hours Maximum : 100 marks
Answer ALL questions.
PART A (10 2 = 20 marks)
1. Mention the advantages and disadvantages of ASIC implementation.
2. Draw the structural description of CMOS XOR gate.
3. What are the features of half-band FIR filter?
4. Draw the signal flow graph in time domain and frequency domain for the
signal equations : ( ) ( ) ( ) 1
2 1 3
+ = n v n av n v and ( ) ( ) n bv n v
3 4
= .
5. Mention the features of FIR filters.
6. What is the need for multirate signal processing?
7. Differentiate Von-Neumann architecture and Harvard architecture.
8. What are the typical applications of systolic and wave front arrays?
9. Represent the decimal number (15/32)10 in signed digit code.
10. How will you convert a twos complement number to CSDC numbers?
Question Paper Code : 31227
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31227 2
PART B (5 16 = 80 marks)
11. (a) (i) Describe briefly a systematic partitioning technique for the design
of a complex DSP system. (8)
(ii) Identify the logic style and determine the logic function that is
realized by the circuit shown in below figure. (8)

Or
(b) Write short notes on :
(i) Precharge-Evaluation logic
(ii) VLSI process technologies. (8 + 8 = 16)
12. (a) (i) Draw the block diagram for the RLS lattice filter for N = 4. (8)
(ii) State and explain the sampling process of analog signals. (8)
Or
(b) Derive the Cooley Tukey FFT Decimation in Time algorithm for N = 4.
(16)
13. (a) (i) Define Decimation and Interpolation (4)
(ii) Explain Interpolation with an integer factor L. (12)
Or
(b) (i) Explain in detail about Round-off noise. (10)
(ii) Determine the signal to noise ratio for the safely scaled, 16 point
FFT. (6)
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31227 3
14. (a) Explain in detail about shared memory architectures. (16)
Or
(b) (i) Differentiate multiprocessor architectures and multicomputer
architectures. (8)
(ii) Explain systolic and wave front arrays and its applications. (8)
15. (a) Explain in detail about basic shift accumulator with example. (16)
Or
(b) Simplify the basic serial/parallel multiplier in terms of the number of
D flip-flops and full adders for the coefficient (0.0101)2C.
(i) Draw the logic diagram for the minimized multiplier.
(ii) Determine the required control signals.
(iii) Determine the throughput when the data word length is 12 bits.
(iv) Validate the function of the minimized multiplier by performing a
multiplication with the value ( )
C
x
2
010 . 1 = . (4 + 4 + 4 + 4)