DSP Training Course Content

DSP CONCEPTS & REAL TIME IMPLEMENTATION
Trainer: Madhusudhana Rao.D ug.madhu.rao@gmail.com Mobile No: 9945219287

COURSE CONTENTS
UNIT 1
Analog Signals and Systems in Time and Frequency Domains
Review of Analog Concepts
Signal Parameters
Basic Operations on signals
Classification of signals
Basic Signal Examples
Complex Exponential
Phasor Representation of Complex Exponentials
Frequency domain representation of Complex Exponentials
Ortho-normality
Fourier Series Representation
Fourier Transform of non-periodic signals
Magnitude and Phase Spectra
Bandwidth of a Signal
Power and Energy Spectral Density
Auto Correlation and Cross Correlation of signals
Properties of Fourier Transform
Hilbert Transform
In-phase and Quadrature phase representation of signals
Bandpass Signals
Basic System Properties
Linear and Time Invariant Systems
Impulse Response and Its Significance
Input Output Relation: Convolution
Stability Criterion
Linear Constant Coefficient Differential Equations
First-order and Second-order systems
Frequency Response of a system
Magnitude and Phase Response of a system
Conditions for distortionless transmission through a system
Sinusoidal excitation of system
Classification of systems based on Magnitude Response
Butterworth and Chebyshev Low Pass Filters

Complex Domain Representation of Signals and Systems
Laplace Transform and Region of Convergence
Properties of Laplace Transform

UNIT 2
Signal Sampling and Quantization
Sampling Theorem for Bandlimited signals
Niquist Criterion
Reconstruction of a signal from its samples
Aliasing
Anti-Aliasing Filter
Sampling Theorem for Bandpass Signals
Quantization
Quantization Error
Analog to-Digital and Digital-to-Analog conversion
Binary Representation of Quantized Signal
Source Coding and Huffman Coding
Coding Efficiency

UNIT 3
Discrete Signals and Systems in Time and Frequency domains
Basic Digital Signals
Classification of Signals
Operations on Signals
Auto-Correlation and Cross-Correlation of Signals
Frequency variable for Discrete Signals
Fourier Transform of Discrete Signals
Magnitude and Phase Spectrum for Digital Signals
Basic System Properties
Systems connected in Parallel and Cascade
Linear and Time-Invariant Systems
Stability Criterion for an LTI System
Impulse Response
Frequency Response of a System
Magnitude and Phase Responses of System

Classification of Systems based on Magnitude and Phase Responses of a
system
Convolution
Conditions for Distortionless Transmission through a System
Sinusoidal Excitation of a System
IIR and FIR Systems
First-order Analog System and Its equivalent Discrete System
Realization of a Digital System using Direct Form-1 and Direct Form-2
methods.
FIR Symmetric System
Linear Constant Coefficient Difference Equation
Recursive and Non-Recursive Systems
Comb filter
Impulse Invariant Method and Bi-linear Transformation to transform a
signal from Laplace domain to Z-domain.
Frequency Transformations: LP to HP, BP, BS etc.

UNIT 4
Discrete Fourier Transform and Signal Spectrum
Discrete Fourier Series Coefficients
Discrete Fourier Transform
Amplitude Spectrum and Power Spectrum
Spectral Estimation using Window Functions
Fast Fourier Transforms (Decimation in Time and Decimation in Frequency)

UNIT 5
Complex Domain Representation of Digital Signals
Z-Transform
Properties of the Z-Transform
Region of Convergence in Z plane
Inverse Z-Transform
Solution of Difference Equations using Z Transform

UNIT 6
Digital Processing Systems and Digital Filter Realizations
Difference Equations and Transfer Function

System Function and Pole-Zero Diagram and Stability Criterion.
Digital Filter Frequency Response.
Classification of Digital Filters
Realization of Digital Filters
Tranformation of Analog Systems to Digital Systems
o Impulse Invariant Method
o Bilinear Transformation Method

UNIT 7
Finite Impulse Response Systems
FIR System: Definition and Difference Equation
FIR Filter Design:
o Fourier Transform Design & Window Method
o Frequency Sampling Method
Realizations of FIR Systems:
o Transversal Form
o Linear Phase Form
o Lattice Structure
Coefficient Accuracy Effects on FIR Filters

UNIT 8
Infinite Impulse Response Systems
IIR System: Definition and Difference Equation
Digital Butterworth and Chebyshev Filter Design
Higher order Infinite Impulse Response Filter Design using Cascade Method
Pole-Zero Placement Method for IIR Filters

UNIT 9
Adaptive Filters
Least Mean Square Adaptive Finite Impulse Response Filters
Basic Wiener Filter Theory
Applications of Adaptive Filtering
o Noise Cancellation
o System Modeling
o Canceling Periodic Interference Using Linear Prediction
o Echo Cancellation System


UNIT 10
Waveform Quantization and Compression
Quantization and Quantization Error
Mu Law Companding
Wavefoem Coding
o Differential Pulse Code Modulation
o Delta Modulation
o Adaptive Pulse Code Modulation
Discrete Cosine Transform

UNIT 11
Multirate Digital Signal Processing
Multirate Digital Signal Processing Basics
Decimation and Interpolation
Polyphase Filter Structure and Implementation
Over-sampling of Analog to Digital Converter
Under-sampling of Bandpass Signals

UNIT 12
Image Processing Basics
Image Data Formats
Image Histogram and Equalization
Image Level Adjustment and Contrast
Image Filtering Enhancement
Image Pseudo Color Generation
Image Spectra
Image Compression by DCT
Video Signal Basics
Motion Estimation in Video


UNIT 13
Digital Signal Processors
Introduction to Digital Signal Processors:
o Evolution of DSP Processors
o General purpose Microprocessors and DS Processors
Basic Architectural Features of DS Processors
o DSPs Computational Blocks
o Bus architecture and Memory
o Data Addressing Capabilities
o Address Generation Unit
o Speed Issues
Hardware Implementation
Basic Software Implementation
Design and Implementation of FIR Filters
Basic FIR Optimizations for DSP Devices
DSP Architecture Optimization for Filter Implementation
Butterfly Structure
Forms of FFT Algorithm
FFT Implementation Issues
DSP Architectures
Fast, Specialized Arithmetic
MAC Unit
Parallel ALUs
Numeric Representations
High Bandwidth Memory Architectures
Data and Instruction Memories
Memory Options
High Speed Registers
Memory Interleaving
Bank Switching
Caches for DSPs
Execution Time Predictability
Direct Access Memory (dMA)
DMA Example
Pipelined Processing
Limitations

Resource Conflicts
Pipeline Control
Specialized Instructions and Address Modes
Circular Addressing
Bit Reversed Addressing
Examples of DSP Architecture
Low Cost Accumulator Based Architecture
Low Power DSP Architectures
Event Driven Loop Applications
A DSP with Idle Modes
High Performance DSP
VLIW Load and Store DSP
TIs TMS320 Processors and their Features
Details of TMS320C55x

UNIT 14
Software Development Tools for C54x: Code Composer Studio (CCS)
Developing a Simple Program
o Create/Open a new project
o Adding the required files to the project
o Build, Load Program and Run the project
o Execution: Run, Halt, Step into, Step over etc
Debugging a project using CCS
o Add/remove Breakpoint
o Viewing variables and changing their values by using watch window
o View Memory and CPU Registers
o View Disassembly
o Viewing the Call Stack
Additional features of CCS
o Adding a probe point for File I/O
o Displaying Graphs
o Creating a Library Project
o Profiling the program


UNIT 15
Fixed Point and Floating Point Data Formats
Data Formats and Computational Accuracy in DSP Implementations
o Signed twos complement integer representation of data
o Fixed Point and Floating Point data formats
Fixed Point Arithmetic
o Fixed Point Addition (Numbers with same Q format)
o Fixed Point Subtraction (Numbers with same Q format)
o Fixed Point Addition (Numbers with same different format)
o Fixed Point Multiplication (Numbers with same Q format)
o Q Values in the Watch Window of CCS.
Fixed Point and Floating Point Processors
Dynamic Range and Precision
Quantization Errors
o Input Quantization Noise
o Coefficient Quantization Noise
o Round Off Noise
Overflow and Solutions
o Saturation and Arithmetic
o Overflow Handling
o Scaling of Signals
DSP Algorithms and their Fixed Point C Implementation
o Fixed Point C Coding and Issues
o To determine the impulse response of a system
o To implement difference Equations
o Convolution & Correlation
o DFT & FFT
o Decimation and Interpolation
o IIR and FIR Filters: Design (Using MATLAB and Fixed C
implementation).


UNIT 16
TMS320C55X Processors Architecture
TMS320C55x Architecture
o TMS320C55x CPU
o Memory Interface Unit
o Instruction Buffer Unit (I Unit)
o Instruction Buffer Queue
o Instruction Decoder
o Program Flow Unit (P Unit)
o Program-Address Generation and Program-Control Logic
o P-Unit Registers
o Address-Data Flow Unit (A Unit)
o Data Address Generation Unit
o A-Unit Arithmetic Logic Unit
o A-Unit Regitsers
o Data Computation Unit (D Unit)
o Shifter
o D-Unit Arithmetic Logic Unit
o Two Multiply and Accumulate Units
o D-Unit Registers
TMS320C55x Buses
TMS320C55x Memory Map
CPU Registers
o Memory Registers
o Accumulators
o Transition Registers
o Temporary Registers
o Registers used to Address Data Space and I/O Space
o Program Flow Registers
o Registers for Managing Interrupts
o Registers for Controlling Repeat Loops
o Status Registers
TMS320C55x Pipeline and Parallelism
o TMS320C55x Pipeline Phases
o Parallel Execution
o Pipeline Protection


UNIT 17
Addressing Modes
TMS320C55x Addressing Modes
o Direct Addressing Mode
o Indirect Addressing Mode
o Absolute Addressing Mode
o Memory-Mapped Register Addressing Mode
o Register Bits Addressing Mode
o Circular Addressing Mode

UNIT 18
Instruction Set
TMS320C55x Instruction Set
o Arithemetic Instructions
o Logic and Bits Manipulation Instructions
o Move Instructions
o Program Flow Control Instructions
Stack Operation
Interrupts and Reset Operations
Mixed C and Assembly Language Programming (Interfacing C with assembly
code)
Using TMS320C55x DSP Library

UNIT 19
LAB Experiments
Quantization of sinusoidal and speech signals
Overflow and saturation arithmetic
Quantization of coefficients
Synthesizing Sine Functions
Twiddle factor Generation
Complex Data Operation
Implementation of DFT
Experiment using Assembly Routines
Implementation of Block FIR filter
Implementation of Symmetric FIR filter
Implementation of FIR filter using Dual-MAC

Implementation of IIR filter using floating-point C, fixed-point C using
intrinsic functions and ASM programming.
Radix-2 Complex FFT (using C program)
Radix-2 Complex FFT using Assembly Language
FFT and IFFT
Fast Convolution

UNIT 20
LAB Experiments
Real Time DSP implementation using C5515 eZdsp USB Stick
o Interfacing with the on-board Audio Codec
o Interfacing with the on-board LED
o Interfacing with the on-board dip switches
o Interfacing with the on-board NOR flash
o Interfacing with the on-board SD card
o I2S interface between C5515 DSP processor and Audio Codec
Waveform Generation
Multitone Generation and FIR Filtering
Audio Effects
o Echo and Reverberation
o Upsampling and Down Sampling
o Flanging
Audio Filtering with FIR filters (Equalizers)
Acoustic Echo Cancellation


UNIT 21
Architectural Details, Addressing Modes and Instruction Set of TMS320C67xx
Introduction
TMS320C6x Architecture
Buses
On-Chip Memories
Interrupts and Interrupt Vector
TMS320C67x Peripherals
External Memory Interface
Direct Memory Access
Enhanced Host-Port Interface
Multi-Channel Buffered Serial Ports
Clock Generator and Timers
General Purpose Input/Output Port
Functional Units
Fetch and Execute Packets
Pipelining
Registers
Linear and Circular Addressing Modes
o Direct Addressing Modes
o Indirect Addressing Modes
o Absolute Addressing Modes
o Memory-Mapped Register Addressing Mode
o Register Bits Addressing Mode
o Circular Addressing Mode
TMS320C6x Instruction Set
o Assembly Code Format
o Types of Instructions
Assembler Directives
Linear Assembly
ASM Statement within C
C-Callable Assembly Function
Timers
Interrupts
o Interrupt Control Registers
o Interrupt Acknowledgement

Multichannel Buffered Serial Ports
Memory Considerations
o Data Allocation
o Data Alignment
o Pragma Directives
o Memory Models
Code Improvement
o Intrinsic Functions
o Trip Directive for Loop Count
o Cross Paths
o Software pipelining
Constraints
o Memory constraints
o Cross-Path Constraints
o Load/store Constraints
o Pipelining Effects with More Than One EP within an FP

UNIT 22
Introduction to DSP BIOS
Real-Time System Concepts
o Define the topology common to most DSP systems
o List factors involved in design of a real-time system
o Compare and contrast tradeoffs in R/T system design
o Identify where various BIOS elements apply to DSP systems
o Describe the startup sequence of a BIOS based system
Hardware Interrupts (HWI)
o Describe the concepts of foreground / background processing
o List details of the Idle (IDL) thread
o Compare Hardware Interrupts (HWI) to ISRs
o Demonstrate how to invoke Interrupt Preemption
o Describe the purpose of the Interrupt Monitor
o Create an HWI object using CCS Gconf tool
o Add an idle thread to a given CCS project
o Lab: Observe performance of HWI threads using CCS tools
Software Interrupts (SWI)
o Describe the basic concepts of SWIs

o Demonstrate how to post a SWI
o Describe the SWI object
o List several SWI posting options
o Define the benefit of each SWI posting method
o Lab: Add a SWI to an HWI-based system
Tasks and Semaphores (TSK, SEM)
o Describe the fundamental concepts of tasks
o Demonstrate the use of semaphores in tasks
o Author TSK code using simple data block pointers
o Create a TSK with the CCS GUI
o Describe the TSK object
o Explain the value of double buffers in DSP systems
o Lab: Modify SWI based code to employ TSK
Multi-Threaded Systems (CLK, PRD)
o Describe the way BIOS can implement a time base
o Setup a time base via the BIOS CLK module
o Describe the results of invoking various BIOS CLK API
o Set functions to run at a periodic rate via the PRD module
o Describe how to implement delayed one-shot functions
o Describe how the scheduler can be managed via BIOS API
o List various BIOS scheduler management API
o Lab: scheduler management API for system performance
Inter-Thread Communication (MSGQ ...)
o Become familiar with signaling/data transfer methods in DSP/BIOS:
o ATM Atomic Fxns
o SEM Semaphore
o LCK Lock
o MBX Mailbox
o QUE Queue
o SCOM Synchronized Comm.
o MSGQ Message Queue
BIOS Instrumentation (LOG, STS, SYS, TRC)
o Demonstrate statistical data on variables without halting the DSP
o Describe why printf() is unsuitable for real-time systems
o Describe how LOG_printf() overcomes this problem
o Demonstrate how to use LOG_printf() in debugging
o Describe how to implement trace control

o Demonstrate how to perform real-time graphing
o Describe the various API for responding to system errors
o Lab: Incorporate/ observe R/T instrumentation into lab solution

UNIT 23
Optimization Methods
Optimizing DSP Implementation
What is Optimization
The Process
Making the Common Case Fast
Make the Common Case Fast DSP Architectures
Make the Common Case Fast DSP Algorithms
Make the Common Case Fast DSP Compilers
DSP Optimization Techniques
Using DMA
Staging Data
Pending Vs Polling
Managing Internal Memory
Loop Unrolling
Filling The Execution Units
Reducing Loop Overhead
Fitting The Loop To Register Space
Trade-Off
Software Pipelining and an Example
A Serial Implementation
A Minimally Parallel Implementation
Compiler Generated Pipeline
An Implementation with Restrict Keyword
Enabling Software Pipelining
Interrupts and Pipelined Code
DSP Compilers and Optimization
Compiler Architecture and Flow
Compiler Optimizations
Instruction Selection
Latency and Instruction Scheduling

Register Allocation
Compiler Time Options
Programmer Helping Out the Compiler
Intrinsic functions
Keywords & In-lining
Reducing Stack Access Time
Compilers Helping Out the Programmer
Summary of Coding Guidelines
Profile based Compilation
Advantages
Issues with Debugging Optimized Code
Summary of the Code Optimization Process

UNIT 24
Lab Experiments : (Simple Programming Examples Using C and ASM Codes)
Sine generation using eight points with DIP switch control.
Generation of the sinusoid and plotting with CCS
Dot product of two arrays
Loop Program Using Interrupt
Loop Program Using Polling
Sine Generation Using Polling
Sine Generation with Two Sliders for Amplitude and Frequency Control
Loop Program with Input Data Stored in Memory Buffer
Loop with Data in Buffer Printed to File
Square-Wave Generation Using Lookup Table
Ramp Generation Using Lookup Table
Ramp Generation without a Lookup Table
Echo (echo)
Echo Using Two Interrupts with Control for Different Effects
Sine Generation with Table Values Generated within Program
Sine Generation with Table Created by MATLAB
Amplitude Modulation (AM)
Sweep Sinusoid Using Table with 8000 Points
Pseudorandom Noise Sequence Generation (noise_gen)
Efficient dot product
Sum of n + (n - 1) + (n - 2) + . . . + 1 Using C Calling Assembly Function

Factorial of a number using C program calling ASM function.
Dot product using assembly program calling assembly function
Dot product using C function calling linear assembly function
Factorial using C calling linear assembly function
FIR filter implementation: Bandstop and Bandpass
Effects on Voice using Three FIR Lowpass Filters
Implementation of four different filters: LPF, HPF, BPF and BSF.
FIR implementation with pseudorandom noise sequence as input to filter.
FIR filter with frequency response plot using CCS
FIR filter with internally generated pseudo random noise as input to filter
and output stored in memory.
Two notch filters to recover corrupted input voice
FIR implementation using four different methods
Voice scrambler using filtering and modulation
Illustration of Aliasing effects with downsampling
Implementation of an inverse FIR filter
FIR implementation using C calling ASM function
FIR implementation using C calling faster ASM function.
FIR implementation using C calling ASM function implementing circular
buffer.
FIR implementation using C calling ASM function implementing circular
buffer in external memory
IIR filter implementation using second order stages in cascade
Generation of two tones using two second order difference equations
Sine generation using a Difference equation.
generation of a swept sinusoid using a difference equation
IIR inverse filter
DFT of a sequence of real numbers with output from CCS window
FFT of a real time input signal using an FFT function in C
FFT of a sinusoidal signal from a table using TIs C callable FFT function.
Fast convolution with overlap-add for FIR implementation using TIs floating
point FFT functions
Graphic Equalizer
Adaptive Filter C implementation
Adaptive filter for noise cancellation
Adaptive FIR filter for system ID of Fixed FIR

Adaptive FIR filter for system ID of Fixed FIR with weights of adaptive filter
initialized as FIR bandpass.
Adaptive FIR for system identification of fixed IIR.
Adaptive predictor for cancellation of narrowband interference added to
desired wideband signal.
Sum of products with word-wide data access for fixed point
implementation using C code
Separate sum of products with C intrinsic functions using C code
Sum of products with word-wide data access for fixed point
implementation using linear ASM code
Sum of products with Double-Word load for floating point implementation
using linear ASM code
Dot product with no parallel instructions for fixed-point implementation
using ASM code.
Dot product with parallel instructions for Fixed-Point implementation using
ASM code.
Two Sums of Products with Word-Wide (32-bit) Data for Fixed-Point
Implementation Using ASM Code
Dot Product with No Parallel Instructions for Floating-Point Implementation
Using ASM Code
Dot Product with Parallel Instructions for Floating-Point Implementation
Using ASM Code
Two Sums of Products With Double-Word-Wide (64-bit) Data for Floating-
Point Implementation Using ASM Code
Dot Product Using Software Pipelining for a Fixed-Point Implementation
Dot Product Using Software Pipelining for a Floating-Point Implementation.

UNIT 25
Simple Project:
Acoustic Echo Cancellation using NLMS Algorithm
Background Noise Suppression using Spectral Subtraction Method

DSP Training Course Content

Încărcat de

Informații document

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

DSP Training Course Content

Încărcat de

Drepturi de autor:

Formate disponibile

DSP CONCEPTS & REAL TIME IMPLEMENTATION

Trainer: Madhusudhana Rao.D ug.madhu.rao@gmail.com Mobile No: 9945219287

S-ar putea să vă placă și