Lab 1.

Stimulus Modeling
1.1. Objectives
Use the UVM class library to:

Generate random stimulus and layer constraints

!"lore the UVM automation "rovided in the library
Use the UVM messaging ca"ability to control verbosity #rom the command$line
1.%. &nstalling Lab1
'o install lab1( do the #ollo)ing
* +SO,V-.&'-/OM0bin0install-uvm 1lab1
* cd lab1
2or this lab( you can )or3 in the #ollo)ing directory: lab1
Lab 1a: UVM 4utomation and Messaging
1. 5evie) the U45' #rame de#inition: uart-#rame.sv
6otes:
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uart-#rame is derived #rom the uvm-se7uence-item base class 8re# $ lab1-note19
:e#ault constraints are s"eci#ied 8lab1-note%9.
'he ;uvm-object-utils and ;uvm-#ield-< macros are used #or built$in automation 8lab1-note=9.
'he constructor( ne) 89( is included in the class de#inition 8lab1-note>9.
?arity is calculated in the "ost-randomi@e89 method 8not a random variable9 8lab1-noteA9.
%. 5evie) the sim"le #rame generator and to"$level module: lab1-to".sv
'his #ile instantiates a generator class that randomi@es #rames and sends them to the :U' via a
send-to-dut89 tas3.
6otes:

uvm-"3g::< is im"orted at the to" level to im"ort the UVM library 8lab1-note19.
uart-#rame.sv is included to im"ort the #rame de#inition 8lab1-note%9.
4 #rame-generator class loo"s through BcountC times to randomi@e a #rame and send it to the
:U'.
'he to" module instantiates the #rame-generator( constructs and randomi@es it and calls the
gen-and-"ush89 method to start generating stimulus.
&n the send-to-dut 89 tas3 8lab1-note=9 )e e!"lore the UVM built$in automation: co"y89( clone89(
s"rint89( set-name89.
=. 5un a simulation and revie) the results:
* irun 1# run.#
5evie) the results in the irun.log #ile.
>. Use the UVM messaging ca"ability:
'he de#ault UVM-V5DOS&'E value is LOF( so only UVM-LOF and UVM-6O6 messages are
"rinted.
* irun 1# run.# GUVM-V5DOS&'EHUVM-/&G/ 8lots o# data is dis"layed9
* irun 1# run.# GUVM-V5DOS&'EHUVM-6O6 8minimal data is dis"layed9
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6ote: &S$IL does not recom"ile0re$elaborate the design0testbench #or these changes.
A. 5un )ith multi"le random seeds to get di##erent results:
* irun 1# run.# GsvseedH546:OM
Lab 1b: ,onstraint Layering
1. 4dding constraints via layering: lab1b-to".sv
6ote:

,reate a test1-#rame class by e!tending #rom uart-#rame.

4dd a constraint to limit the "ayload value to less than JKh=2.
Modi#y the #rame-generator class to use test1-#rame.
5un a simulation and revie) the results:
* irun 1# run1b.#
Ma3e sure that the ne) constraint too3 e##ect and no #rames )ith "ayload LJKh=# are generated.
1.
8O"tional9 Use the random seed to get di##erent results:
* irun 1# run1b.# GsvseedH546:OM
Lab 1c: :e#ault 'ree ?rinter
!"lore built$in "rint o"tion: uvm-de#ault-tree-"rinter.
6ote:

5evie) the lab1c-to".sv #ile and loo3 #or lab1c-note1. Fhen "rinting the #rame data( the
de#ault tree "rinter #ormat is used 8instead o# the table "rinter9.
5un a simulation and revie) the results:
* irun 1# run1c.#
5evie) the irun.log #ile to see ho) the tree "rinter #ormats out"ut data.
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Lab %. UVM Se7uences
%.1. Objectives

!"lore the driver and se7uencer interaction

5evie) the se7uencer de#ault behavior
!ecute a s"eci#ic se7uence
Frite a ne) se7uence
%.%. &nstalling Lab%
'o install lab%( do the #ollo)ing:
* +SO,V-.&'-/OM0bin0install-uvm 1lab%
* cd lab%
2or this lab( )or3 in the #ollo)ing directory: lab%0
6ote: &n this lab( )e included the driver( se7uencer and to"$level module in the same #ile. &n a real
veri#ication environment these #iles )ould be se"arated out.
Lab %a: 'he :river and Se7uencer &nteraction
1. 5evie) the se7uencer: lab%-to".sv:

uart-se7uencer is derived #rom the uvm-se7uencer base class 8lab%-note19. 'his "rovides UVM
built$in #ields and automation.
uvm-com"onent-utils 8lab%-note%9 9 is a macro( used #or registering a uvm-com"onent or any o#
its sub$class.
%. 5evie) the :river:

uart-t!-driver is derived #rom uvm-driver 8lab%-note=9.

;uvm-com"onent-utils 8lab%-note>9 9 is a macro( used #or registering a uvm-com"onent or any
o# its sub$class.
run-"hase 89 tas3 1 called during simulation run time. Loo"s through and gets an item #rom the
se7uencer( sends the item to the :U' and calls se7uencer item-done89 method.
2or this lab( send-to-dut 89 delays "rints the data item #or this sim"le driver.
=. 5evie) the Sim"le Se7uence :e#inition: 8Starting at lab%-noteA9:

'his sim"le se7uence )ill generate random U45' #rames as they are re7uested #rom the driver.
'he "re-body89tas3 raises an objection #or the se7uence( the body89tas3 )ill e!ecute #ive
U45' #rames in a loo" 1 each #rame is generated )hen the driver re7uests through the
get-ne!t-item89call. 'he "ost-body89tas3 dro"s an objection #or the se7uence so that the
simulation can grace#ully end.
>. 5evie) the to"$level test: 8Starting at lab%-noteM9

De#ore creating the driver and se7uencer( the UVM con#iguration mechanism is used to s"eci#y
the se7uence to be e!ecuted in the run-"hase 8lab%-noteN9. 'his sets the de#ault se7uence to
the sim"le-se7uence.
'he se7uencer and driver are declared and created 8lab%-noteN9. 'hen they are connected using
a 'LM connection. 8lab%-noteJ9
2inally( a global run-test 89 tas3 is called to start the simulation. run-test89 is "art o# the UVM
library and )ill start the simulation 8lab%-noteO9
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A. 5un a simulation and revie) the results 8results are in the irun.log #ile9:
* irun 1# run.#
5evie) the #rame "rinted out by the driver:
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/o) many #rames )ere e!ecutedP
Fhich se7uence8s9 )ere e!ecuted during the simulationP 8hint: loo3 at the value o# B"arent
se7uenceC in each #rame9
/o) did the se7uencer 3no) )hat se7uence to e!ecuteP
M. 5un )ith di##erent random seeds and get di##erent results:
* irun 1# run.# GsvseedH546:OM
N. One )ay to vie) the transactions )as in the irun.log #ile. Fith built$in transaction recording(
SimVision
allo)s you to vie) the transactions gra"hically. &nvo3e Simvision and load u" the transaction
database:
* simvision 1in"ut lab%a.svc#
'he SimVision Fave#orm )indo) dis"lays the #ive transactions generated during the simulation
run. Eou should be able to see the transactions generated by the sim"le se7uence( and those
ca"tured in the driverKs send-to-dut89 tas3. 'he #ields o# the uart-#rame are ca"tured and the
timing o# the tas3 matches the delay value.
'he 'ransaction Stri"e ,hart )indo) dis"lays the same data in a di##erent #ormat. Eou can see
the #rame #ield values in either stri"e$chart or table #ormat.
Select a transaction in the stri"e chart 8or 'able9 and you )ill see the same transaction
highlighted in the )ave#orm )indo).
Lab %b: User$:e#ined Se7uences
1. 5evie) the se7uence library: uart-se7-lib.sv
4 base se7uence( uart-base-se7 8lab%-note%9 incor"orates the objection mechanism so any
4,'&V se7uences should e!tend #rom this class and )ill automatically incor"orate setting0dro""ing
objections.
2our user$de#ined se7uences are included: uart-incr-"ayload-se7( uart-bad-"arity-se7(
uart-transmit-se7( and uart-nested-se7 8hint: search #or SQU6, in the #ile9.
'he uart-nested-se7 8lab%-note=9 is a se7uence that e!ecutes other se7uences.
%. Modi#y the lab%-to".sv #ile to include the se7uence library 8lab%-note1R9
=. Modi#y the to"$level test: lab%-to".sv
S"eci#y the uart-nested -se7 as the ne) de#ault se7uence.
Uncomment the t)o lines containing lab%-note11 and comment out the lines above it.
>. 5un another simulation and revie) the results:
* irun 1# run.#
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Fhich se7uence8s9 )ere e!ecuted during the simulationP 8/int: loo3 at the value o# B"arent
se7uenceC in each #rame9. Decause this is a nested se7uence( you )ill see that the nested
se7uence e!ecuted multi"le sub$se7uences
:o the values loo3 correctP
/o) did the se7uencer 3no) )hat se7uence to e!ecuteP
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A. &nvo3e Simvision and load u" the ne) transaction database:
* simvision 1in"ut lab%b.svc#
'he SimVision Fave#orm )indo) dis"lays the se7uencer and driver transactions. &# you e!"and
the uart-nested-se7 8the SGT sign ne!t to the name in the Fave#orm9 it sho)s the to"$level
se7uence 8uart-nested-se79( the sub$se7uences 8incr-"ayload-se7( bad-"arity-se7( and
transmit$se79( and the individual uart #rame transactions 8re79 that )ere generated.
'he 'ransaction Stri"e ,hart )indo) can also e!"and0colla"se to sho) the se7uence and
transaction data.
Lab %c: ,reating Eour O)n Se7uence 8O?'&O64L9
1. Modi#y the se7uence library: uart-se7-lib.sv:

Go to line containing lab%-note= and add your o)n se7uence:

o
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Eou can do a decrementing "ayload se7uence
Eou can nest t)o o# the e!isting se7uences
Go )ildU
%. Modi#y lab%-to".sv to set your ne) se7uence as the de#ault se7uence.
=. 5un another simulation and revie) the results:
* irun 1# run.# GsvseedH546:OM
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Lab =. 5eusable nvironment 'o"ology
=.1. Objectives

5evie) and understand the correct structure o# a reusable com"onent.

=.%. &nstalling Lab=
'o install lab=( "lease do the #ollo)ing:
* +SO,V-.&'-/OM0bin0install-uvm 1lab=
* cd lab=
2or this lab( )or3 in the #ollo)ing directory: lab=0
1. 5evie) the #iles in the UV, directory: uart0
4ll o# the reusable #iles that com"rise the U45' UV, are located in the uart0sv directory. Loo3 at
some o# the #iles to understand the UV, com"onent architecture. 4 list o# these #iles is ;included into
uart-"3g.sv #ile )hich is im"orted into the to"$level module.
uart0sv0uart-t!-driver.sv:
o
uart-t!-driver e!tends #rom uvm-driver. 'he driver includes code to re"resent "rotocol #or
send-t!-#rame 89 tas3. 'he uart-t!-driver interacts )ith the :U' signals via a virtual
inter#ace.
uart0sv0uart-t!-agent.sv:
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uart-t!-agent e!tends #rom uvm-agent. 'he agent includes instances o# a monitor( driver
and se7uencer.
Loo3 at the build-"hase89 method

'he monitor is created 8lab=-note19. &ts build-"hase89 method )ill be automatically

called.
&# the is-active #lag is UVM-4,'&V( the driver and se7uencer are created and their
con#igurations are set to the uart-con#ig.
uart0sv0uart-env.sv:
o
uart-env e!tends #rom uvm-env. &t contains instances o# the 5! and '! agents. 'hese are
created in the envKs build-"hase89 method.
5evie) some o# the other #iles in this 8lab=9 directory i# you have time.
1. 5evie) the to"$level module: uart-to".sv:
4n instance o# the uart-env is "laced into the testbench 8lab=-note19( along )ith a con#iguration
class instance that s"eci#ies the :U'0test con#iguration.
'he test environment is created and invo3ed in an initial bloc3 8lab=-note%9
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2irst( the #actory is used to create the uart-env com"onent instance 8lab=-note=9
'he con#iguration is created( randomi@ed and assigned. 'his con#iguration is UV, s"eci#ic
8lab=-note>( lab=-noteA9
6e!t( the virtual inter#ace assignments are made( using the uvm-con#ig-db 8lab=-noteM9
'hen )e BinstructC the se7uencer in the 'I agent to e!ecute the uart-tra###ic-se7 in the
run-"hase 8lab=-noteN9
2inally( the global UVM tas3: run-test89 is called to start the test and run the simulation to
com"letion.
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%. 5un a simulation and revie) the irun.log #ile:
* irun 1# run.#
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Search #or SVS: in irun.log #ile
'he #irst thing you see "rinted in the log #ile is the U45' to"ology. 'his ca"ability is "rovided
)ith the UVM built$in automation )hen the test called uartR."rint89 in the second initial bloc3
8lab=-note=d9V note that the uart."rint89 )as called a#ter W1 to ensure that the build-"hase
has com"leted and the uart and all its sub$com"onents have been built.
6otice that the '! agent is UVM-4,'&V and 5! agent is UVM-?4SS&V. 'he '! agent
contains driver( monitor and se7uencer( )hile the 5! agent only contains a monitor.
=. 5evie)ing the results in SimVision:
* simvision 1in"ut lab=a.svc#
o 'his time( the transaction data is ca"tured along )ith the signal data. 'he t!d signal
transmits the "ayload( so you can easily see the "ayload because it is ca"tured in the
uart-#rame transaction. 'he 'ransaction Stri"e ,hart is also available #or e!"loring the
simulation results
>. ,ontrolling the 'o"ology: uart-to".sv:

6o) )e are going to see )hat ha""ens )hen )e ma3e a com"onent UVM-?4SS&V.
o
Modi#y the uart-to".sv #ile 1 go to line containing lab=-note> and uncomment the lines
that con#igure the '! 4gent as UVM-?4SS&V.
A. 5un a simulation and revie) the results:
* irun 1# run.#
6ote that the 5! and '! agents are no) UVM-?4SS&V( and no stimulus is generated or sent to the
:U'. 'his is ho) a UV, )ould be used as a monitoring device at the system level.
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Lab >. 'est ,reation Using 5eusable
,om"onents
>.1. Objectives

!"lore test creation and control using a UVM 'estbench

!amine an e!isting test and observe ho) it creates a veri#ication environment
,ontrol environment behavior #rom the testbench and the test
,ontrol test e!ecution and e!ecute multi"le tests )ithout recom"iling0re$elaborating the design
,ontrolling the test e!it using objection handling mechanism
>.%. &nstalling Lab>
'o install lab>( do the #ollo)ing:
* +SO,V-.&'-/OM0bin0install-uvm 1lab>
* cd lab>
2or this lab( )or3 in the #ollo)ing directory: lab>0
UVM 'estbench
Module UV,
Monitor
Scoreboard
&nter#ace X )hite$
bo! coverage
U45' :U' 8Verilog 5'L9
4?D
Veri#ication
,om"onent
4?D
&nter#ace
'! 'ransmitter
2&2O
5!
2&2O
4?D
5eceiver
,ontrol0Status
5egisters
t!d
Mode
S)itch
U45'
Serial
U45'
Veri#ication
,om"onent
r!d
,ontrol0&nterru"t
Logic
Virtual Se7uencer
'his lab is run on the #ull veri#ication environment and U45' :U'. &t includes:

'he Verilog 5'L #or the U45' :U'

4n instance o# the 4?D UV,
4n &nstance o# the U45' UV,
4 module UV, )hich includes a scoreboard and a monitor #or chec3ing and coverage collection
4 virtual se7uencer )hich controls multi"le UV,s
,overage is being collected
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'ransaction recording is also enabled

1. 5evie) the Simulation Veri#ication nvironment: uart-ctrl-tb.sv:
'his #ile contains the testbench class #or this design. uart-ctrl-tb e!tends #rom uvm-env 8lab>-note19.
&t contains instances o# the 4?D UV,( the U45' UV,( the module UV, and the virtual se7uencer.
'he build 89 method o# the sve is used to con#igure the veri#ication environment and create0build the
sub$com"onents o# the environment 8lab>-note%9
%. 5evie) a test class: tests0a"b-uart-r!-t!.sv:
&n UVM( tests are classes. u%a-a%u-#ull-rand-test e!tends #rom uvm-test.
&t contains an instance o# our sve: uart-ctrl-tb uart-ctrl-tbRV
'he build 89 method o# the test sets a de#ault se7uence #or the virtual se7uencer and then it
creates and builds the testbench 8uart-ctrl-tbR9
=. 5un a simulation and revie) the "rinted to"ology: 8irun.log9:
* irun 1# run1.#
'he run1.# #ile s"eci#ied GUVM-'S'64MHu%a-a%u-#ull-rand-test to tell the run-test89
method )hich UVM test class to e!ecute
Fhen revie)ing the results in the irun.log #ile( )e see the "rinted to"ology #or the #ull
veri#ication environment 8uart-ctrl-tbR( a"bR( uartR( uartR-ctrlR( and the virtual se7uencer9
6otice that the virtual se7uencer )as e!ecuting the Bconcurrent-u%a-a%u-rand-transC se7uence
8hint: search #or B!ecuting se7uenceC string9
Multi"le U45' and 4?D #rames )ere generated and sent during the simulation.
>. 5evie) the Virtual Se7uence Library: uart-ctrl-virtual-se7-lib.sv:
4 base-virtual-se7 se7uence is included to handle the objection mechanism. 8lab>-note19 4n
objection is raised in the "re-body89 tas3 and dro""ed in the "ost-body89 tas3. 4ll virtual
se7uences )ill e!tend #rom this base se7uence.
'he body89 o# the virtual se7uence begins at line mar3ed lab>-note% o# this #ile:
o
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&t starts by "rogramming the :U' by calling the "rogram-dut-csr-se7 se7uence 8con#ig-dut
instance9.
'hen it s"a)ns o## t)o di##erent threads 1 one #or sending a random number o# #rames #rom
the U45' to the 4?D and one sending trans#ers #rom 4?D to U45'.
2inally it calls another se7uence to read the U45' :U' 5! 2i#o #rom the 4?D UV,.
A. 5un the uart-incr-"ayload test:

'his se7uence "rograms the :U' via the 4?D bus( e!ecutes an incrementing "ayload se7uence
via the U45' inter#ace and then reads the 'I 2i#o via the 4?D bus.
* irun 1# run%.#
'he &US simulator should not recom"ile0re$elaborate the design because )e only changed the
UVM-'S'64M argument in the run%.# #ile.
M. 5un a simulation in GU& mode:

!"lore the SimVision debug ca"ability by running in GU& mode:

* irun 1# run%.# 1in"ut lab>.tcl
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Lab A. Using &ncisive Veri#ication Duilder
Objective

Use &VD to understand the necessary ste"s to im"lement a UV,

?er#orm sim"le simulation to chec3 the correctness o# generated code
A.1. &nstalling LabA
'o install labA( do the #ollo)ing:
* +SO,V-.&'-/OM0bin0install-uvm $labA
* cd labA
2or this lab( )or3 in the #ollo)ing directory: labA0
A.%. Duild a sim"le "oint$to$"oint UVM Veri#ication
,om"onent
&nvo3e the &ncisive Veri#ication Duilder 8done through the #ollo)ing scri"t9:
* .0run-ivb
M. On the main "age( clic3 to ,reate a ne) "roject. 4dd the "roject name Ymy-libY as sho)n in the
second )indo) belo) and then clic3 2inish:
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'he Fi@ard #lo) )indo) )ill be o"en( select ,reate UV,s L &nter#ace UV, Duilder.
N. Select 4ctions L 4ctivate Fi@ard #rom the "o"$u" menu:
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J. 'he &VD Duilding Fi@ard )ill start )ith the #ollo)ing )indo)s( 3ee" the de#ault values unless
other)ise indicated:
O. On General UV, O"tions )indo)( ty"e Zmy-uvcZ as "ac3age name and select ZSystemVerilog 1
4ccellera UVMZ.
1R. ,ontinue #illing in names #or the initiator( res"onder( and data item names say master( slave( and
transaction res"ectively.
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11. &nvo3e the UV, generation by selecting my-uvc and clic3ing the Generate button:
1%. ,lic3 O. on "o"$u" #orm and &VD )ill sho) the list o# generated #iles.
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1=. !it #rom &VD and cd to my-lib-lib0my-uvc0sv: 4naly@e:

my-uvc-transaction.sv $ #or data items generation

my-uvc-master-agent.sv( my-uvc-master-driver.sv( my-uvc-master-monitor.sv(
my-uvc-master-se7uencer.sv to understand the generated agent structure
1>. cd ..0e!am"les and revie) the #iles:

test-lib.sv( chec3 ho) test has been im"lemented

e!amine the se7uence lib
1A. cd ..0( e!ecute .0demo.sh( simulation )ill start )ith gra"hical inter#ace. 5un the simulation by
clic3ing
the run button:
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1M. 4naly@e the irun.log and loo3 #or the to"ology "rint$out.
1N. &n the :esign Dro)ser( you can vie) the to"ology by e!"anding the uvm-test-to" instance.
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Lab M. ,overage 4nalysis and 5an3ing
5uns
&n this section( )e use nter"rise Manager to vie) regression results and do test case ran3ing.
'o save time in this section )e load an already$e!ecuted regression result.
M.1. Objective

Use an e!ecutable veri#ication "lan to analy@e test runs.

4naly@e the relative contribution o# each run to the total coverage.
M.%. &nstalling LabM
'o install labM( do the #ollo)ing:
* +SO,V-.&'-/OM0bin0install-uvm 1labM
* cd labM
2or this lab( )or3 in the #ollo)ing directory: labM0
M.=. Loading 5egression Out"ut( Vie)ing ,overage
1. O"en the v"lan #ile and revie) its structure:
* acroread uart-a"b-v"lan."d# X
'he v?lan is a user readable #ile that )as created by the team( to list all the veri#ication #eatures that
need to be veri#ied.
%. &nvo3e nter"rise Manager 8done through the #ollo)ing scri"ts9:
* .0start-uart-emanager X
nter"rise Manager allo)s you to manage regression runs. 5egressions launched through nter"rise
Manager can collect and vie) coverage )ith multi"le ty"es o# metrics and ma" them into their related
#eatures. 2or e!am"le:

,ode ,overage 8branch and condition9

'oggle coverage
2SM coverage
2unctional coverage
4ssertion coverage
'his coverage data can be "rojected onto a user$de#ined v?lan structure that re#lects the veri#ication
goals. 'his allo)s #eature$#ocused revie) and analysis( and allo)s generating customi@ed re"orts.
6ote: 4ll #igures sho)n belo) are indicative. 4ll associated numbers sho)n in the #igures could
vary de"ending on the seed( B.vsi#C used to run regression or B.vso#C #ile being loaded.
1. 5ead the canned regression results:
On the &ncisive nter"rise Manager )indo) read the veri#ication session out"ut #ile 8vos#9
a. Select 2ile L 5ead-session.
'his o"ens the 5ead-session )indo).
b. 6avigate to o"en the vso# at the #ollo)ing location:
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+SO,V-.&'-/OM0i"-regression-data0uvm-class0uart-ctrl0vm-uart-ctrl-regression.user1.11<0<
.vso#
c.
,lic3 O"en.
'his o"ens the regression results
%. 'o vie) the coverage( clic3 the bo! v?lan in the &ncisive nter"rise Manager )indo).
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=. ,lic3 O. in the Dac3)ard ,om"atibility 6ote )indo) i# it "o"s u".
>. On the 4utomatic ,overage Merge )indo) that o"ens( select the
B& intend to "er#orm "er$run analysis 8do not merge9C o"tion and clic3 O3.
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'his sho)s you the ra) coverage as sho)n belo).
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Fe no) load the v?lan )e revie)ed in ste" 1 on to" o# this coverage:
1. ,lic3 5ead on the Veri#ication ?lan 'ree 8:e#ault9 )indo)
%. Load the uart-a"b-v"lan.!ml #iles( and clic3 O"en.
6ote: 5emember to change the 2iles o# ty"e to !ml #ile 8<.!ml9.
4 Veri#ication ?lan 'ree )indo) a""ears )ith the U45' v?lan annotated )ith coverage results.
'he cumulative coverage result o# each category o# #unctions a""ears.
Fe can see that not 1RR* o# the entire coverage goal )as achieved. Eou can e!"and each o# the sub$
categories and vie) their aggregated coverage results.
M.>. Vie)ing 5egression 5un 5esults
nter"rise Manager allo)s you to loo3 at results #or a s"eci#ic run. Eou can revie) the status 8#or
e!am"le( "assed( #ailed( and )aiting to be e!ecuted9. LetKs revie) the results #or the regression run )e
have just loaded.
1. Minimi@e the V"lan )indo)s until you #ind the main &ncisive nter"rise Manager )indo).
'he GU& dis"lays the results o# the loaded regression. 4ll the tests have "assed as #ollo)s:
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6ote that all the test cases in the regression 8t)elve tests as sho)n in the #igure above is just
indicative9 have "assed. Let us revie) the individual result log.
%. On the "assed column 8mar3ed as B?C9( clic3 the number 1% 8number 1% as sho)n in the #igure
above
is just indicative9
'his dis"lays a list o# the tests that "assed and the seed o# the tests. Eou can select one o# the runs
and get much in#ormation such as run$directory( log #ile( seed( and #ailure cause 8i# any9.
M.A. 5an3ing 5uns
5estore the Veri#ication ?lan tree )indo) that )e "reviously minimi@ed.
5an3ing 5egression 5uns to the v?lan:
'o im"rove the coverage e##iciency o# a session( you need to 3no) the relative contribution o# each run
related to the total coverage. 'he ran3ing #eature ran3s a set o# runs based on their coverage
contribution
and( by de#ault( adds a cumulative grade attribute.
1. &n the Veri#ication ?lan tree( select the section 'o" L U45' 4?D Veri#ication ?lan.
Fe no) ran3 the run on this section.
%. Select 4nalysis $ 5an3 5uns.
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=. ,lic3 O. on the 5an3ing "o" )indo) that a""ears.
>. ,lic3 O. on the 5eread ,overage )indo).
4 5uns )indo) o"ens( i# one is not already o"en. 4lternatively( the table in the 5uns )indo)
changes as sho)n belo):
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'he cumulative attribute is added to the table.
'he table is sorted according to the coverage e##iciency. 'he o"timum runs have a "ur"le
bac3ground( )hile redundant runs have blue.
A. ,lic3 the 2ilter 5adio button under v?lan button.
Fe use the general #iltering mechanism to remove runs that donKt contribute additional code or
#unctional coverage to)ards our "lan goals.
M. 2rom the "ull do)n menu on the le#t( select 5an3ing &d.
N. Select UH #rom the com"arison "ull$do)n( and enter $1 in the te!tbo!.
J. ,lic3 2ilter.
O. 'hese runs can be )ritten to a Session &n"ut 2ile 8VS&29 to launch a #ocused regression suite.
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M.M. 4naly@ing ,overage
5estore the Veri#ication ?lan 'ree )indo) that )e "reviously minimi@ed.
,orrelating 5egression 5uns to the v?lan:
Some tests contribute to s"eci#ic #eatureKs coverage( )hile others may #ocus on a di##erent area o#
interest. Eou may )ant to #ocus on a s"eci#ic #eature and rerun tests that contribute to its coverage.
Using
the correlate button( you can measure the contribution o# tests to a selected #eature or a sub$category
)ithin your "lan.
1. !"and the coverage tree do)n to 'o" $ U45' 4?D Veri#ication ?lan $ Dlac3 Do! Dehavior $ Serial
:ata 2&2O $ '! 2&2O $ '! 2&2O Level 1
U45'-4?D-MO6&'O5.monitor.uart-cover.dut-t!-#i#o-cg.t!-level
4t this "oint you can vie) the various 2&2O bins. 'he v?lan tree loo3s as sho)n belo).
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6otice that )e have only hit a very small subset o# the 'I 2&2O level coverage bins. 'his includes not
com"letely #illing the 'I 2&2O.
%. 'o create a correlation matri! #or the Serial :ata 2&2Os node select Serial :ata 2&2Os in the v?lan
by
clic3ing on it.
=. ,lic3 the ,orrelate button or select 4nalysis $ ,orrelation Matri! #rom the menu
>. ,lic3 O. )hen the #ollo)ing dialog bo! a""ears.
A. &# the 5eread ,overage dialog bo! a""ears ,lic3 O. in order to create the correlation matri!.
'he #ollo)ing 5uns )indo) o"ens( dis"laying the runs in the current conte!t. 4 coverage attribute
column is added to the 5uns table( dis"laying the contribution made by each run0seed o# runs.
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4ll simulations run so #ar are not able to contribute to 1RR* coverage to this #eature. Fe may need a
large number o# seed or bias constraints di##erently to increase coverage o# this section.
Fe have created a test that targets the 2&2O holes that addresses this coverage goal.
6e!t( )e run this test and loo3 at the cumulative coverage to determine i# )e are ma3ing "rogress
to)ards this #eature.
'o run this test )e start a ne) simulation session in &ncisive Manager by #ollo)ing the ste"s belo):
M. Go to the main &ncisive nter"rise Manager )indo).
N. ,lic3 Start.
'his launches a Start Session )indo).
J. Select uart-r!t!-#i#o-cov.vsi# and clic3 O"en.
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'he test case runs in a ne) !term.
O. Once the test case com"letes( 7uit the !term.
1R. 'o see the simulation result( clic3 5e#resh in the &ncisive Manager )indo).
11. 2ollo) the ste"s 1$= above to create a correlation matri! #or the Serial :ata 2&2Os node.
'he 5uns )indo) o"ens dis"laying the runs in the current conte!t.
6o) you can see that the ne) test case uart-t!r!-#i#o-cov test has 1RR* correlation #or the Serial :ata
2&2Os node. 'he total coverage has also increased #rom the "revious simulation.
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Summary
&ncisive nter"rise Manager automates the e!ecution o# multi"le random tests. &t allo)s intuitive
#eature$
based revie) o# multi"le coverage metrics( ran3 your regression suit to remove redundant test and
correlated simulation runs to e!ercise a desired #eature.