IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO.
6, DECEMBER 2006
Temperature-Dependence of Off-State Drain Leakage
in X-Ray Irradiated 130 nm CMOS Devices
Bongim Jun, Member, IEEE, Ryan M. Diestelhorst, Marco Bellini, Gustavo Espinel, Aravind Appaswamy,
A. P. Gnana Prakash, John D. Cressler, Fellow, IEEE, Dakai Chen, Ronald D. Schrimpf, Fellow, IEEE,
Daniel M. Fleetwood, Fellow, IEEE, Marek Turowski, Member, IEEE, and Ashok Raman
Abstract—The off-state drain current leakage characteristics of
130 nm CMOS technology are investigated using x-ray irradiation
and operating temperature as variables. Radiation-induced inter-
face traps in the gate oxide to gate-drain overlap region strongly
enhance the off-state leakage as a function of gate bias. Due to
the thin gate oxide in these 130 nm devices, we find that drain-
edge direct tunneling is more plausible than conventional gate-in-
duced-drain-leakage in explaining the observed increase in drain
leakage. Radiation-induced traps in the shallow trench isolation
oxide create parasitic channels in the p-well and produce another
source of off-state drain leakage with increasing total dose. The
drain current increase from both the gate overlap region and the
shallow trench edge are enhanced with increasing total dose and
suppressed by cooling.
Index Terms—CMOS, cryogenic, GIDL, off-state leakage cur-
rent, shallow trench isolation, STI, total dose radiation effects.
I. INTRODUCTION
U LTRA-THIN gate oxides employed in advanced CMOS
technology nodes are naturally tolerant to ionizing radia-
tion under typical doses and operating conditions, without addi-
tional hardening. However, radiation-induced oxide and inter-
face traps can enhance band-to-band off-state tunneling either
directly across the gate oxide and/or in the gate-to-drain overlap
region in the channel depletion or accumulation regimes [1]–[5].
Moreover, spatially-distributed radiation-induced charges in the
shallow trench isolation (STI) oxide can create parasitic inver-
sion channels in parallel with the gate at the STI oxide edge and
at the STI/body interface, resulting in unacceptably high off-
state leakage [1], [6]–[8]. Gate-induced drain leakage (GIDL)
has been a well-accepted mechanism for the explanation of off-
state drain leakage via a band-to-band tunneling process in the
gate to drain overlap region for devices operated in strong accu-
mulation mode [4]. However, more recent studies performed on
ultra-thin gate oxide devices instead attribute the off-state drain
leakage to edge direct tunneling (EDT) rather than to conven-
tional GIDL [9]. In the present investigation, we have compared
Manuscript received July 14, 2006; revised August 25, 2006. This work was
supported by the Air Force Office of Scientific Research (AFOSR) MURI, the
NASA SiGe ETDP Project, and the Georgia Electronic Design Center (GEDC)
at Georgia Tech.
B. Jun, R. M. Diestelhorst, M. Bellini, G. Espinel, A. Appaswamy,
A. P. G. Prakash, and J. D. Cressler are with the School of Electrical and
Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30308
USA (e-mail: junb@ece.gatech.edu).
D. Chen, R. D. Schrimpf, and D. M. Fleetwood are with the EECS Depart-
ment, Vanderbilt University, Nashville, TN 37235 USA.
M. Turowski and A. Raman are with CFD Research Corporation, Huntsville,
AL 35805 USA.
Digital Object Identifier 10.1109/TNS.2006.886230
0018-9499/$20.00 © 2006 IEEE
3203
the contributions of EDT, GIDL, and the STI parasitic channels
to the observed off-state drain leakage currents for the selected
130 nm node CMOS devices as a function of total ionizing ra-
diation dose and temperature.
It is also well-known that cooling CMOS devices to cryogenic
temperatures (e.g., 77 K) can provide considerable performance
advantages [10], [11]. Thus, cryogenic operation of advanced
CMOS technology is potentially interesting for a wide variety of
emerging space exploration missions (e.g., to the Moon and/or
Mars). However, the impact of ionizing radiation on the relia-
bility of such devices operating at cryogenic temperatures has
not been examined carefully to date, especially for aggressively
scaled technology nodes. We report here, for the first time, the
cryogenic characteristics of 130 nm CMOS devices irradiated
with x-rays at room temperature and subsequently cooled to
temperatures as low as 10 K. Three-dimensional (3D) TCAD
models were built to simulate radiation-induced STI leakage
contributions to the off-state -
room and cryogenic temperatures.
characteristics, at both
II. DEVICES AND TESTING DETAILS
The Si bulk CMOS devices used in study are from a 3rd gen-
eration, 130 nm, SiGe BiCMOS technology—IBM 8 HP [12].
The measured FETs have channel widths ranging from 10 m
to 0.16 m, and effective channel lengths ranging from 1.6 m
to 0.12 m, with a physical gate oxide thickness of 2.2 nm.
Prior to radiation exposure, the DC characteristics of the
devices were measured as a function of temperature using a
closed-cycle He cryotest system with a Lakeshore temperature
controller. This system allows device measurements at temper-
atures ranging from 300 K to 10 K, with a resolution of K.
The samples were wire-bonded into 28-pin DIP packages.
Total ionizing dose radiation tests were performed at room
temperature using 10 keV x-rays with dose rates of 3.2 and 32.4
krad(SiO )/min, to total doses as high as 11 Mrad(SiO ), under
four bias conditions: 1) all terminals grounded, 2) V
with the other terminals grounded, 3) V (the rated
of this technology) with the other terminals grounded,
and 4) V, V with the other terminals
grounded (for the pFETs, V and V).
The DC characteristics of the devices were measured in-situ,
immediately after each cumulative dose was reached. Currents
from all terminals of the devices were measured using an Agi-
lent 4155 C. Additional post-irradiation cryogenic temperature
data were measured approximately 60 hours after the radiation
tests were completed. To separate the radiation-induced effects
3204 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO. 6, DECEMBER 2006

Fig. 1. Schematic (a) cross-sectional diagram and (b) top view of nFET used
for this study. Each transistor is isolated by shallow trench isolation (STI).

Fig. 2(b) Off-state I and I characteristics corresponding to I shown in

Fig. 2(a). V are 50, 100, 150, and 200 mV.

0 V and transconductance characteristics of a device with

Fig. 2(a) I
W=L = 10=0:12 for various V .

on off-state drain leakage current from the STI effects, a para-

metric 3D model was built using CFDRC’s (Computational
Fluid Dynamics Research Corporation) NanoTCAD simulator
and optimized using various process details, including the
doping profiles and layout [13].

III. EXPERIMENTAL RESULTS AND DISCUSSION

A. Pre-Irradiation I—V Characteristics and Leakage Current

Mechanisms at Off-State Fig. 3. Band diagrams of (a) gate -substrate junction and (b) gate-drain edge
for an nFET accumulated channel. I DT and I DT represent hole and
Fig. 1(a) illustrates the schematic cross-section of the 130 nm electron direct tunneling currents, respectively while I and I represent
nFET, while Fig. 1(b) shows a schematic top-view, indicating edge direct tunneling, and gate induced drain leakage currents, respectively.
the potential STI and GIDL damage regions.
Fig. 2(a) shows the - and transconductance char-
acteristics of an nFET with a channel W/L of 10/0.12, for var- [9] and explained the off-state drain leakage primarily due to
ious values in the channel accumulation regime. The cor- edge direct tunneling (EDT) and the gate leakage due to direct
responding gate and substrate current in off-state is shown in tunneling under channel accumulation (DT).
Fig. 2(b). Observe that there is absolutely no dependence of The energy band diagrams in Fig. 3(a) and (b) illustrate the
the off-state drain leakage current, or the corresponding gate and tunneling that occurs at the gate-substrate and gate-drain edges,
substrate currents. This off-state insensitivity to con- respectively. Fig. 3(a) depicts the accumulation of holes in the
trasts with conventional GIDL physics, according to which substrate and electrons in the gate poly; these holes and elec-
shown be a strong function of [4]. Moreover, the off-state trons contribute gate-substrate direct tunneling current for a thin
is about three orders of magnitude higher than the gate oxide. Far from the gate-drain edge with its reverse-biased
corresponding at V, which makes any GIDL substrate-drain junction, is insensitive to . Fig. 3(b) de-
contribution a secondary tunneling mechanism, since is picts the band diagram in the gate-drain overlap region showing
typically much higher than and close to at . the edge direct current and GIDL current. From the pre-irradi-
Yang et al. also found a similar leakage current behavior, espe- ation characteristics shown in Fig. 2(a) and (b), should
cially for devices with gate oxide thickness thinner than 2 nm dominate for a thin gate oxide.
JUN et al.: TEMPERATURE-DEPENDENCE OF OFF-STATE DRAIN LEAKAGE 3205

Fig. 4. I 0 V and gm characteristics as a function of dose. Devices were

0
0
biased during irradiation at a substrate bias of 1:2 V and a gate bias of 1.2 V
Fig. 5(a) Off-state I V characteristics of an nFET (W=L = 10=0:12)
before (solid line) and after 540 krad(SiO ) (dashed line). The device was irra-
(other terminals grounded).
diated with V = 1:2 V.

B. Radiation Effects on Off-State I—V Characteristics

Fig. 4 shows the and characteristics as a func-
tion of dose for a device with width and length dimensions of
. The dose rate was 3.2 krad(SiO )/min and the
devices were biased during irradiation under worst case con-
ditions: gate bias of 1.2 V and substrate bias of V, with
the other terminals grounded. In channel depletion/accumula-
tion ( V), the drain current increases with dose up to
about 540 krad(SiO ), and then starts to saturate for further in-
creases in total dose. In the subthreshold region
there is a gradual increase in the subthreshold hump with dose
due to an increase in STI leakage current.
The radiation-induced STI drain-to-source leakage current
becomes significant when the oxide charges in the STI are large
enough to create a weak inversion channel along the STI edge,
effectively shunting the source and drain [1], [6]–[8]. Thus, if
Fig. 5(b) Off-state I -V characteristics of an nFET (W=L = 10=0:12)
large enough, the STI edge leakage can begin to overwhelm before and after 540 krad(SiO ). Dashed lines indicate the I -V character-
the off-state drain leakage current produced by EDT/GIDL at istics with source terminal opened. The device was irradiated at V = 1:2 V.
high doses at large gate bias. To extract the STI leakage con-
tribution to the drain leakage current, characteris-
tics were obtained by monitoring all terminal currents and re- The observed increasing drain leakage current with in-
peating the sweep, while keeping the gate terminal creasing dose is partially due to the increase in significance of
open (i.e., a physical disconnection of the gate), and the results the GIDL, which is now assisted by radiation-induced interface
are plotted in Fig. 5(a). In Fig 5(a), the drain current increase traps. Fig. 6 shows (a) the maximum gate current, (b) the max-
after 540 krad(SiO ) is nearly an order of magnitude larger than imum drain leakage current, and (c) the maximum substrate
when measured without a gate contact. Note that the source cur- leakage currents, extracted at V from a device
rent is positive when the trap assisted tunneling (TAT) dom- with gate width and length of 10 m and 1.6 m, irradiated
inates the STI leakage, while becomes negative when the under four different bias conditions: B1) V and
STI leakage dominates the TAT at V. To elimi- V; B2) V; B3) V, and B4)
nate the STI leakage contribution to the off-state drain current, all pins grounded.
the characteristics were measured while keeping the B1 represents the worst-case bias condition, where the larger
source terminal electrically open, as shown in Fig. 5(b). Note vertical field induces more oxide and interface traps, enhancing
that is plotted as a function of drain potential. As shown in the trap-assisted band-to-band tunneling. For B3 there is less
Fig. 5(b) with no source contact, one can see a smaller near leakage in and than for the other three bias conditions.
zero volts without a source contact, since there is then no STI We believe this is due to channel depletion during irradiation.
leakage contribution to . The difference in gate and substrate Note that radiation-induced traps assist gate-to-substrate direct
currents both with and without a source contact is negligible. tunneling; the correlation among the three currents,
3206
Fig. 6. (a) Gate, (b) drain and (c) substrate current as function of dose at four
different radiation bias conditions. Currents were extracted from I 0 V and
I 0 0
V characteristics at applied V of 0:5 V.
is shown clearly at each dose. A slight inequality indicates
that is now a net current after the STI leakage contribution
has been subtracted from the .
With a sufficiently large dose (e.g., after 1 Mrad(SiO )),
and saturate and eventually decrease at a negative gate
voltage of V, as shown in Figs. 6(a) and (b). As explained
in Fig. 5, the STI parasitic leakage current overwhelms the drain
leakage current, compensating the tunneling current from EDT/
GIDL. , on the other hand, continues to increase with dose,
as shown in (c), because the EDT/GIDL is proportional to dose.
The radiation induced STI parasitic leakage current con-
tribution to the off-state drain current can be separated using
NanoTCAD-generated 3D-structure of nFET and its sur-
rounding STI region. The gate oxide thickness, width, and
length of the device simulated are 2.2 nm, 1.0 m and 0.12 m,
respectively. Fig. 7 clearly shows the parasitic channel created
along the STI edge with sheet charges of /cm ,
which is roughly equivalent to the total dose of 1 Mrad(SiO )
in the radiation condition described in Fig. 4.
C. Cryogenic Characteristics of Radiation-Induced Off-State
Drain Leakage Current
Fig. 8 shows the and characteristics as a function
of temperature (T) for a device with a gate width and length of 10
m and 0.12 m, respectively. Note that for ( are caused by the radiation-induced trap-assisted direct tun-
is defined to be when the drain current is independent of T),
decreases with decreasing T due to the positive temperature
dependence of diffusive transport; whereas, for
increases with decreasing T due to the negative T dependence of
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO. 6, DECEMBER 2006
Fig. 7. Parasitic channels created along the STI edge, with sheet charge Qs =
1:3 2 10 /cm applied at the STI-silicon interfaces. The color map shows the
logarithm of electron density, n (log /cm ).
Fig. 8. I -V and gm characteristics as a function of measurement temper-
ature before irradiation. W=L = 10=0:12 and V = 50 mV.
the carrier mobility in inversion (i.e., the lower the T the higher
carrier mobility). is 0.66 V for this device. Prior to the
cryogenic measurements on the irradiated devices, all devices
were annealed at room temperature for 60 hours in a nitrogen
ambient to determine the possible room temperature annealing.
Fig. 9 shows the - characteristics for the device shown
in Fig. 8 as a function of temperature after 1.8 Mrad(SiO ). For
, the radiation-induced drain leakage current gradu-
ally decreases with decreasing T, since the trap-assisted band-to-
band tunneling and the parasitic channels at STI/p-well inter-
faces are negative functions of T.
Corresponding gate and substrate current characteristics are
shown in Figs. 10(a) and (b), respectively, as functions of tem-
perature, after irradiation to 1.8 Mrad(SiO ). The absolute value
of is compared with . Again, the decreases in and
neling in the gate and drain overlap region.
The maximum leakage currents for and for the
four devices ( , and ),
as shown in Figs. 11 and 12, respectively, are extracted from
JUN et al.: TEMPERATURE-DEPENDENCE OF OFF-STATE DRAIN LEAKAGE
Fig. 9. I -V characteristics as a function of temperature for a device after
1.8 Mrad(SiO ).
Fig. 10. (a) Substrate and (b) gate current characteristics as a function of tem-
perature after a total x-ray dose of 1.8 Mrad(SiO ).
Fig. 11. Drain leakage current characteristics in the accumulation regime
0
(V = 0:5 V) obtained from as functions of (a) dose and (b) measurement
temperature after a dose of 1.8 Mrad(SiO ). Devices were annealed for 60 h
at room temperature.
- and - , at the largest applied negative gate
voltage ( V). These are plotted as functions of
3207
Fig. 12. Substrate current characteristics in the accumulation regime
(V = 0 0:5 V) obtained from (a) x-ray irradiation and (b) low tem-
perature measurement after 60 h of room temperature annealing following
1.8 Mrad(SiO ) exposure.
(a) dose and (b) temperature after 60 h of room temperature an-
nealing in a nitrogen ambient. Both and increase with
dose, indicating that the device geometry is not strongly corre-
lated with the EDT/GIDL, which is consistent with published
results [9]–[11]. In addition, the low temperature characteristics
are repeatable, indicating that the radiation-induced oxide and
interface traps remain in place and active at low temperatures.
D. Total Ionizing Radiation and Cryogenic Temperature
Effects on the pFETs
It is also well-accepted that GIDL contributes to the off-state
drain leakage current in pFETs, in the same manner as in nFETs,
due to hot electron pile-up in the gate-drain overlap area when
the channel forms under strong accumulation [4].
GIDL is normally enhanced after ionizing radiation, which may
induce traps at the gate-to-drain overlap region in pFETs [14].
However, the pFETs used in our study did not show a drain
leakage current increase with either TID or , as shown in
Fig. 13(a), and the observed increases of off-state gate and sub-
strate current are very small, as shown in Fig. 13(b). We at-
tribute this TID insensitivity of the off-state pFET to the fol-
lowing reasons: 1) There is insignificant interface trap formation
in the gate-drain overlap region, and/or 2) the radiation-induced
traps may not assist direct tunneling of accumulated electrons
at the drain edge. Moreover, there is no contribution of radi-
ation-induced oxide traps in the STI oxide and at STI/n-well,
since the radiation induced positive charges in the STI oxide
cannot form leakage paths in the n-well. It indicates that no ra-
diation hardening process is required for pFETs in this tech-
nology for the dose and bias conditions examined in this study.
The - and characteristics of a cryogenically-oper-
ated pFET after 1.8 Mrad(SiO ) are shown
in Fig. 14. There is no sign of any change in the
and characteristics from irradiation and no significant in-
creases in off-state , and in the pFETs are observed,
regardless of channel length and , up to the maximum dose
3208 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 53, NO. 6, DECEMBER 2006

Fig. 13. I-V characteristics of pFET (W=L = 10=0:12) as a function of TID:

(a) drain current and (b) corresponding gate and substrate current in off-state of Fig. 15. Effective channel mobility ( ) and peak gm characteristics as a
the device (V 0
= 0:05 V). function of temperature after a total x-ray dose of 1.8 Mrad(SiO ).

is 4% and 13%, at 300 K and 10 K, respectively; whereas, the

decrease in peak is 4% and 9.5%, at 300 K and 10 K, respec-
tively. One possible explanation of this slightly larger degrada-
tion found in mobility at low temperatures after irradiation is
the possible increase of border and interface traps, which can
increase Coulomb scattering at the interface.

IV. SUMMARY
Off-state drain current leakage mechanisms for 130 nm
CMOS devices with ultrathin gate oxides are investigated using
x-ray irradiation and variable temperature operation as damage
and characterization methods, respectively. Direct tunneling
across the thin gate oxide is found to be a major source of gate
Fig. 14. I 0 V and gm characteristics of a pFET as a function of tempera- and drain leakage current, and dominates the gate-induced-
ture. The device was irradiated with x-rays up to a dose of 1.8 Mrad(SiO ) prior drain-leakage (GIDL). Radiation-induced traps assist direct
to the cryogenic characterization. tunneling and GIDL, which becomes a primary source of drain
leakage current after irradiation. Parasitic channel paths form
at the STI/substrate due to radiation induced traps in the STI
(1.8 Mrad(SiO )). The subthreshold slope and peak increase oxide and these currents compensate the off-state drain current.
with decreasing T due to the increase in hole mobility with de- The off-state drain leakage current is fully suppressed at tem-
creasing temperature. peratures lower than about 200 K. 3-D NanoTCAD simulation
E. Radiation Effects on Mobility and Threshold Voltage at results show good agreement with experimental results.
Both Room and Cryogenic Temperatures
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