Design of AFE and PWM drive for Lithium-ion battery management system for HEV/EV

system
Sudhakar singamala, Manfred brandl, Sandeep vernekar, Veereshbabu vulligaddala, Ravikumar adusumalli, Vijay ele
ams semiconductors India Pvt Ltd
1
sudhacr12001@yahoo.com
2
manfred.brndl@ams.com
3
sandeep.vernaker@ams.com

4
veereu_2@yahoo.com
5
ravi@gmail.com
6
vijay.ele@ams.com


Abstract This paper describes Analog-front-end (AFE) for
lithium-ion battery management system. It includes the design of
the differential clocked comparator which compares the cell
voltage and the external reference voltage in the cell voltage
domain to find if the cell voltage is within the safe operating
range. This also includes PWM drive for the external fly-back
dc-dc converter, the charge shuttling switches and control logic
for active cell balancing of Lithium-ion battery cells in 0.35um
high voltage (HV) CMOS technology. PWM drive circuit
generates programmable frequency and programmable duty
cycle to drive external low-side FET in the primary of the fly-
back dc-dc converter. Secondary of the fly-back converter is
connected to on-chip charge shuttling switches. Based on the
differential comparators decision for the set target cell balance
voltage, the digital finite state machine (FSM) generates control
signal to charge individual cells in the battery sequentially.
These circuits are part of lithium-ion battery cell balancer IC.
The IC is designed to support cell voltage monitoring and cell
balancing of a lithium-ion battery of seven cells.

Keywords active cell balancing, charge shuttling switches, clock
level shifter, differential comparator, fly-back dc-dc converter,
Lithium-ion battery management, PWM drive.
I. INTRODUCTION
Shortage of fossil fuel, rising energy prices and the growing
concern over carbon emissions has focused attention on
electrical and hybrid-electrical vehicles. For efficient
electrical vehicles (EV) and hybrid-electrical vehicles (HEV)
lithium-ion battery technology is useful as it offers high
energy density for the given weight. To get the required motor
drive power of Kwatts from batteries, it is required to stack
the battery cells in series to a higher voltage thereby reducing
the current requirements and reducing the wire harness
required in the vehicles [1]. Each lithium-ion cell is typically
3.7V and generally 100 cells are connected in series to get the
battery voltage to around 370V to 400V. When using a single
lithium-ion cell, it is required to monitor the cell voltage so
that the cell voltage is not out of safe operating voltage range
of the cell based on cell chemistry. Thus monitoring of the
limits is required because, if the cell is overcharged above
defined upper limit during charging of the cell, the cell
electrolytic breakdown happens, or sometimes cell may
explode, and if it is discharged to lower than lower limit it can
not supply any power to the system.
Battery cell voltage monitoring and cell-balancing is
mandatory for series connected lithium-ion battery cells,
because any capacity mismatch between series connected cells
reduces the over all pack capacity [1]. The combination of the
cell voltage limits and SoC (state of charge of cell) mismatch
limits the pack capacity to the capacity of the weakest cell.
Cell monitoring takes care of the cell overcharge and over-
discharge condition and cell balancing technique increases the
capacity, and system operating life time. Cell-balancing is
necessary for HEVs and EVs, where charging occurs
frequently, such as regenerative braking. For cell-balancing
and for monitoring it is required to compare each cell voltage
with the predefined voltage limits and required to compare
with the final target cell voltage. Based on the comparators
results individual cells are charged with external flyback
converter secondary by using the same stack as a supply for
the transformer primary. The fly-back PWM driver circuit,
charge shuttling switches, differential comparators and
required level shifter circuits are realised in 0.35um HV
CMOS technology.
This paper is organized as follows. In section II, system
architecture and implementation of high voltage switched
capacitor comparator is described. In section III, design of
trimmable fly-back PWM driver circuit, charge shuttling
switch design and control logic for cell balancing is described.
In section IV, charge balancing application circuit along with
the simulation results are given and finally conclusions are
drawn in section V.

II. PROPOSED ARCHITECTURE
To monitor each cell voltage individually in a battery stack
it is required to handle huge common mode voltage and
transient voltages. With the IC fabricated in 0.35um HV
CMOS process, a stack of seven cells can be monitored and
these ICs can be stacked to support upto 1000V stack made
of lithium-ion cells. Based on the result of the comparison
between the cell voltage and target voltage, and by using
external fly-back dc-dc converter cell-balancing can be
performed.

A. System architecture
The system consists of seven switched-capacitor (SC)
comparator circuits and corresponding clock level shifter
circuits, charge shuttling switches with level-shifters to level
shift switch control signals, PWM low side driver circuit to
drive external FET, 5V LDO as supply of internal circuits, 12-
bit DAC to set the cell thresholds, cell target voltage with SPI
and digital state machine for the control of IC functionality.
The block diagram of the system is shown in the Figure1.
2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems
1063-9667/14 $31.00 2014 IEEE
DOI 10.1109/VLSID.2014.39
186
C-GND
VCELL1
VCELL2
VCELL3
VCELL4
VCELL5
VCELL6
VCELL7
Cnt1H
Cnt2L
Cnt7H
Cnt1L
Cnt2H
Cnt3L
Cnt3H
Cnt4L
Cnt4H
Cnt5L
Cnt5H
Cnt6L
Cnt6H
Cnt7L
Cnt1
Cnt2
Cnt3
Cnt4
Cnt5
Cnt6
Cnt7
V5V
FD_OUT
RC
Osc
FSM,
DIGITAL12
bit_DAC
5V
5V
0V
0V
Pre_Reg,
POR,LDO
0V
VSUP
SDI
SDO
SCLK
CS
GND
VSUP
T
S
E
C
H
T
S
E
C
L
SSW
_LS
VCELL
Comp
5V
0V
SC_ckt
CLK_CELL
V_REF
VCELL6
VCELL7
Comp
5V
0V
SC_ckt
CLK_CELL
V_REF
VCELL5
VCELL6
Comp
5V
0V
SC_ckt
CLK_CELL
V_REF
VCELL4
VCELL5
Comp
5V
0V
SC_ckt
CLK_CELL
V_REF
VCELL3
VCELL4
Comp
5V
0V
SC_ckt
CLK_CELL
V_REF
VCELL2
VCELL3
Comp
5V
0V
SC_ckt
CLK_CELL
V_REF
VCELL1
VCELL2
Comp
5V
0V
SC_ckt
CLK_CELL
V_REF
C_GND
VCELL1
0V

Fig.1 Block diagram of lithium-ion battery cell balancing and monitoring
system
B. Differential circuit architecture
SC differential circuit is designed to handle the different
cell voltage levels of the battery and to generate the difference
of the cell voltage and the reference voltage which is set by
12-bit DAC. The generated difference signal is given to
comparator and the comparator generates logic high if cell
voltage is higher than reference voltage else it generates logic
low [2]. In this circuit 50V breakdown capacitors are used to
support high common mode cell voltages of the battery. The
switched capacitor differential circuit and the comparator are
shown in figure 2.
The functionality of the differential circuit as follows. It
samples the different cell and reference voltages. To sample
the different cell voltages, the system clock is level shifted to
cell voltage domain. The reference voltage is sampled with the
reference clock (5V) because the set threshold and target cell
voltage are always less than 5V. Clock level shifter and non-
overlapping clock generation circuit are shown in figure 3 and
in figure 4.
SC circuit consists of four sampling capacitors (CS1, CS2,
CS3, and CS4) and comparator gate capacitors act as load
capacitors. It consists of eleven switches for sampling the cell
voltage in one phase of the clock and for difference generation
in second phase of the clock. During first
phase(PhVin1,Phref1,Phref1d,Phrefdd) of the clock switches
sw1,sw3,sw5,sw7,sw9,sw10,sw11 are on and left side of the
sampling capacitor CS1 samples VCELL1P, CS2 samples
VREFN (0V), CS3 samples VCELLN1, CS4 samples VREFP
and the right side of the sampling capacitors samples to Vbias
(2.5V). During the second phase (PhVin1b, Phref1b) of the
clock the switches (sw2,sw4,sw6,sw8) parallel to sampling
switches turn on and left side of the sampling caps sampled to
different voltage and the right side of the sampling capacitors
are floating. By appling charge conservation to each capacitor,
the voltage on the right side of CS1 has to decrease by
(VCELL1P-VCELL1N), on CS2 has to decrease by (VREFN-
VREFP), on CS3 has to decrease by (VCELL1N-VCELL1P),
and on CS4 has to decrease by (VREFP-VREFN).

s
w
9
s
w
1
1
s
w
1
0

Fig.2 Comparator with SC differential circuit for comparison of cell voltage
with reference voltage

In phase two of the clock CS1 and CS2 are connected
together and CS3 and CS4 are connected together. Due to
charge sharing between sampling capacitor and load
capacitors the voltage Vout1 and Vout2 in phase two is given
by the following equations [3] if all the sampling capacitors
are same and equal to CS
( ) ( ) ( ) VREFN VREFP N VCELL P VCELL
Cload Cs
Cs
Vout
+

= 1 1
2
1


( ) ( ) ( ) VREFN VREFP N VCELL P VCELL
Cload Cs
Cs
Vout
+
= 1 1
2
2
By neglecting the parasitic load capacitor when compared to
the sampling capacitor, the differential output from the SC
circuit is the difference of the cell voltage and the reference
voltage. The output is give by the following equation.

( ) ( ) ( ) VREFN VREFP N VCELL P VCELL Vout Vout = 1 1 1 2

The generated difference is independent of the common
mode voltage of the cell and will be given to the comparator
which is working on the 5V supply. The comparator is
designed to resolve the signal different of 500uV between the
cell voltage and the reference voltage.
187
C. Implementation of the SC differential circuit:
The switches in the SC circuit are complementary CMOS
switches with dummies switches to avoid the charge injection
on to sampling capacitors. These switches are sized to have
low on resistance such that sufficient settling time is available
for SC circuit sampling. To sample the cell voltages the clocks
are level shifted to cell voltage domain and for sampling the
set reference voltage clocks in 5V domain are used. After
level shifting the clocks to cell voltage domain non-
overlapping clocks are generated in the cell voltage and 5V
domain to avoid clock feed through and signal dependent
offsets in the differential SC circuit when sampling cell
voltage and reference voltages. The functionality of the clock
level shifter to cell voltage domain as follows, low voltage
(5V) clock and the complement of the clock drives the diode
connected load differential pair and the current in the load is
mirrored into a resistor which is connected to different supply
domain. Voltage across the resistor used as input to the
inverter chain whose supply is the required cell voltage. For
example generating the clocks in the cell seven domains,
VCELL7 is connected to VCELLP and VCELL6 is connected
to VCELLN of the clock level shifter circuit. The output clock
from this circuit is in level shifted from 5V domain to cell7
voltage domain. The level shifted clock will be given to non-
overlapping clock circuit whose supply is VCELL7 and
VCELL6, shown in figure 4 to generate non overlapping
clocks in the cell voltage domain, these clocks are used to
sample the cell voltage. The reference sampling clock also
given to clock level shifter and non-overlapping clock
generation circuit with 5V as supply to have the same delay in
the cell voltage and reference voltage sampling clocks.


Ibias
5uA
IR=4V
5V
0V
VCELLP
VCELLN
CLK(5V) CLK1 CLK1b
0V
5V
CLK1b
CLK1
5V VCELLP
VCELLN
0V
Clock_level shifter


Fig.3 Clock level shifter circuit to level shift clocks to different cell voltage
domains
D. Differential circuit and results
The simulation results of the differential SC circuit and clock
level circuit are shown in figures 5, 6, 7.
Figure 5 shows the simulation results of the on resistance of
the switch in the differential circuit.
Figure 5 shows the simulation results of the SC differential
circuit with seven cell voltage as one input and reference
voltage as other input. For this simulation VCELLP is 28V
and VELLN is 24V, VREFP=4.005V and VREFN=0V. The
simulation results show the difference (approx 5mv) between
the cell voltage and reference voltage on Vbias (2.5V) in
phase once of the sampling clock and in the other phase it is
Vbias voltage
Figure 6 shows the level shifted non-overlapping clock in
clock in cell seven domain and 5V domain to sample cell
seven voltage and reference voltage and the output of the
comparator( logic low) showing that the cell voltage is lees
than and the reference voltage


Fig.4 Non-overlapping clock generation circuit in cell voltage domain


Fig.5 Simulation results of differential circuit switch on resistance

Fig.6 SC differential circuit output for VCELLP=28v, VCELLN=24v,
VREFP= 4.005v and VREFN=0v.
188

Fig.7 level shifter clock output and comparator output for VCELLP=28v
VCELLN=24v and VREFP=4.005v VREFN=0v.
III. DESIGN OF PWM DRIVE SIGNAL, CHARGE SHUTTLING
SWITCH AND CONTROL LOGIC
In this section the design of the PWM drive signal
generation circuit, design of the charge shuttling switches and
switch control logic are described.
A. Design of PWM drive signal and simulation results
Once the cell voltage is within the pre-defined limits all the
cells in the battery need to bring to same target voltage set by
12-bit DAC, to get the maximum power from the battery. For
cell balancing, lithium-ion cells are charged with fly-back dc-
dc converter based on the comparator decision. To generate
the PWM signal to drive primary of the fly-back converter a
relaxation RC oscillator is designed. The frequency and the
duty cycle of oscillator can be programmed based on the
charging current requirements and the transformer used in the
dc-dc converter. Process variation in the PWM frequcy can be
trimmed with trimmable charging current.
The oscillator generates a PWM frequency signal by
comparing the capacitor voltage with high precision band gap
reference voltage [4]. The capacitor is charged with a
constant current. Constant current is generated by adding
PTAT (proportional to absolute temperature) current and
CTAT current. Both the PWM circuit and constant current
generation circuit are shown in fig 8, 9.
The frequency of the oscillator is based on the charging
current, Capacitor, and the band gap reference voltage and is
given by the following equation.
C Vbg
Icont
fpwm
*
*
2
1
=


To generate different frequencies (200 kHz, 100 kHz, 50
kHz, 25 kHz) the charging constant current magnitude is
changed with two bits and the process variation is
compensated by adding timmable current by using 5 trim bits.
To generate different duty cycles on the PWM frequency, the
band gap reference voltage is divided into eight parts with a
resistive divider and the resistive divider output is compared
with the capacitor charged ramp voltage. The resistive divided
output is selected by using 8:1 multiplexer. Monto-carlo
process and mismatch simulation results of the 200 kHz PWM
signal and constant current are shown in the figure 10.

Comp Ckt Fout
5V
0V
BGR
R
e
s
_
d
i
v
Pwm_45%
Pwm_35%
Pwm_40%
Pwm_25%
Pwm_30%
Pwm_10%
Pwm_20%
Comp Ckt PWM_drive
5V
0V
Pwm_50%
Logic
Fout
5V
C
8
:
1

M
u
x

Fig.8 PWM signal generation circuit for external FET drive
Fig.9 Constant current generation circuit for charging the capacitor













Fig.10 Simulation results of 200 kHz PW and constant capacitor charging
current
B. Design of charge shuttling switches and control logic
For active cell balancing based on the comparator decision
the cell are charged with the secondary of transformer
sequentially if the particular cell voltage is lower than the
target cell voltage. The architecture shown in figure 11 is used
to connect the transformer secondary to individual cells.
The primary requirement in designing charge shuttling
switch is low on resistance of the switch to reduce the power
dissipation in the switch and the isolation between the cells
during charging i.e. when cell seven is charging with the
transformer secondary through pins TSECH, TSECL the other
189
cells should not be connected to cell seven. The switch is
sized to have low ON resistance and the isolation is achieved
with the parasitic diode available with 50V PMOS transistors
in 0.35um high voltage CMOS process. To turn on the charge
shuttling switch the control signal need to be level shifted to
that domain. For level shifter control signal of the each switch
is generated by the circuit shown in the figure 12. The supply
for the switch control block is the source node of the switch
transistors connected in series, this node voltage is
approximately VCELL voltage because of parasitic diode
between drain and source of the PMOS transistor and the
generated control signal is 3V lower than the cell voltage to
have VGS of the 3V for the shuttling switches. Based on the
control signal one pair of the shuttling switches are on and the
rest of the switches are off and the parasitic diodes provides
the isolation between cells.


F ig.11 Charge shuttling switches and control logic circuit


Fig 12. Shuttling switches control signal level shifter circuit
The simulation results of the charge shuttling switch is
shown in the figure 13 and the cell four control signal level
shifted signal is shown in figure 14 for each cell voltage of 4V.



Fig 13. Simulation results for on resistance of the charge shuttling switch


Fig 14. Simulation results of cell 4 control signal level shifted output with all
cell voltage s in the battery at 4V
IV. CELL BALANCING WITH THE DESIGNED CIRCUIT
A. Cell balancing with external flyback dc-dc converter
Schematic of active cell balancing is shown in the figure 15.
The functionality as follows, once the cell voltages are with
the pre-defined upper and lower limits the cell balancing is
performed. All cell voltages are compared with the target
voltage set by 12-bit DAC, based on the comparator decision
the cells whose voltage is lees than the cell target voltage
those cells are charged with the secondary of the transformer
sequentially. Once the charging is over for the battery again
all the cell voltages are compared with the target voltage,
based on the comparator decision required cells are charged.
This process continues until all the cells in the battery reaches
to same target voltage (cell balance voltage). This process is
supported by the digital state machine in the IC and once all
the cell are in with in the predefined accuracy of the reference
voltage, digital logic generates balance done signal. Time
required for balancing the cell is based on the PWM frequency,
duty cycle and inductances in the transformer. Figures 16, 17
Switch control
Level shifted
190
shows the transformer secondary voltages (TSECL, TSECH)
when cell are charged sequentially from cell one to cell 7.
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c
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p
p
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c
k
t

Fig 15. Active cell balancing circuit with external fly-back converter


Fig 16. Transformer secondary low side voltage for sequential cell balancing.
V. CONCLUSIONS
The switched capacitor differential comparator can be used
to find whether the lithium-ion cells voltages are with in the
safe operating range of the cell and by comparing each cell
voltage with the predefined upper and lower limits and by
comparing the with reference voltage (cell target voltage) the
comparator decision will be used for the active cell balancing.
The designed pulse width modulated signal drive the
external FET in the primary of the fly-back dc-dc and the
charge shuttling switches are used during cell balancing for
connecting the individual cell in the battery to secondary of
fly-back dc-dc converter and also provide isolation between
cell during cell balancing..


Fig 17. Transformer secondary high side voltage for sequential cell balancing

ACKNOWLEDGMENT
We are very thankful to review team of this project and the
head of the design center for supporting throughout the design
phase and lab evaluation phase of the IC.
REFERENCES
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Amplifier,IEEE J. Solid-State Circuits,, vol.SC-17,pp.1008-
1013,December,1982.
[3] L. Der, S.H. Lewis and P.J. Hurst, A Switched-Capacitor Differencing
Circuit with Common-Mode Rejection for Fully Differential
comparators, Midwest Symp. on Circuits and Systems, Detroit, pp.
911-914, August 1993.
[4] Olmos A, A temperature Compensated Fully Trimmable on-Chip IC
Oscillator, in Proc. SBCCI, 2003, pp.181-186.
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