Chapter13

Intel8086Microprocessorarchitecture,features,andsignals

Think & Answer type Questions:
1. How much memory in terms of bytes can be interfaced with 8086? Why?
Memory with a capacity of 1 MB can be interfaced with 8086 as it has 20 address
lines (since 2
20
=1 MB).

2. What is the minimum and maximum size of a segment in terms of bytes? Why?
The minimum size of a segment can be one byte. The maximum size of a segment
is 64 KB as the offset address size is 16 bits (since 2
16
=64KB).

3. Why memory is divided into segments in 8086? What are its advantages?
The 8086 accesses each memory location using the content of a segment register
which indicates the base address of a memory segment and an offset register
which indicates the offset within the memory segment from where the data or
instruction is accessed. Hence the memory is divided into segments.

The memory segmentation allows us to write relocatable program and data, by
which the program and data to be executed by the 8086, can be placed anywhere
in the memory map of 8086 (i.e from the address 00000H to FFFFFH), and can be
executed without any modification in the program and data. It also leads to good
data structure since the program, data and stack are kept in separate segments.

4. How many 8K x 8 memory chips are required to construct 1 MB memory?
1 MB =2
20
bytes =2
20
x 8 bits
Each 8K x 8 memory chip can store 2
13
x 8 bits.
Therefore, Number of 8K x 8 memory chips needed =(2
20
x 8) / (2
13
x 8) =2
7
=128

5. Which pin of 8086 determines mode of operation? How?
The MN/ MX pin of 8086 determines the mode of operation of 8086. If it is
connected to +5V, 8086 operates in minimum mode and if it is connected to 0V
(i.e. Ground), 8086 operates in maximum mode.

6. What are the differences between NMI and INTR interrupts in 8086?
The NMI interrupt is a non-maskable interrupt and it can not be disabled by
software. The NMI interrupt has higher priority over INTR interrupt. The NMI
interrupt is a vectored interrupt as it has a specific interrupt type number allotted
to it, which is type 02H.

The INTR interrupt is a maskable interrupt and it can be enabled or disabled by
setting or clearing the I flag in the flag register respectively. The INTR interrupt
has lower priority over NMI interrupt. The INTR interrupt is a non-vectored
interrupt as it has no specific interrupt type number allotted to it by default.


Microprocessors and Microcontrollers Kumar, Saravanan & Jeevananthan
Oxford University Press 2011
7. Which pin of 8086 is used to synchronize the slowly operating peripherals with
8086? How?
The READY pin of 8086 is used to synchronize the slowly operating peripherals
with 8086. Each bus cycle of 8086 contains four T-states namely T1 to T4 when
the READY pin remains high throughout the bus cycle. If the READY pin is
made low during the T3 state of a bus cycle, wait states (Tw) are introduced in the
same bus cycle after T3 state, as long as READY is kept low and the logic state of
different control signals of 8086 such as RD, WR, and M/ IO, etc. are maintained
at the same level. Once the READY pin is made high, the T4 state appears next
and the current bus cycle ends.

8. Is it possible for a segment to begin at a memory address that is not divisible by
16 (i.e. address that does not end with the digit 0H) in 8086? Why?
No. The reason is that the base address of a segment in 8086 is always obtained
by appending four binary zeros (i.e a single hexadecimal digit 0H) to the value
contained in the segment register. Hence a segment always begins at a memory
address that is divisible by 16 (i.e. address that ends with the digit 0H).

9. Is it possible for two segments to get overlap in 8086? How?
Yes. When the size of a segment is less than 64 KB, another segment can start in
the next immediate memory address that is present after the first segments ending
address and having the hexadecimal digit 0H (i.e. 0000 in binary) as its last digit.

For example, if a data segment begins at address 20000H in memory (with DS
register having the value of 2000H) and ends at the address 25005H in memory
due to its size being 6 bytes only (i.e. less than 64KB), then the next segment (say
stack segment) can begin at the next immediate memory address that ends with
the hexadecimal digit 0H, which is the address 25010H. Note that if the same data
segment has a size of 64KB (maximum size of a segment), its ending address will
be 2FFFFH. Since the next segment (i.e. stack segment) starts within the address
2FFFFH which is the maximum allowable address for data segment in this
example, the data segment and stack segment are said to be overlapping.

10. Why is the stack segment said to be growing downwards in 8086?
During every push operation of a word into stack, the stack pointer (SP) gets
decremented by 2. Hence, stack segment said to be growing downwards in 8086.
Due to this fact, while using stack segment in a program, at the beginning of the
program itself, the SS register is initialized with the base address of stack segment
and the SP is initialized with a value that is equal to the maximum number of
bytes which will be present in the stack at any instant of time during the program
execution.

11. Mention the differences between 8085 and 8086 Microprocessors.

Sl.No. 8085 8086
1. 8 bit processor 16 bit processor
Microprocessors and Microcontrollers Kumar, Saravanan & Jeevananthan
Oxford University Press 2011
2. Has 8 data lines and 16 address lines Has 16 data lines and 20 address
lines
3. Memory is accessed by absolute
address
Memory is accessed by segment
and offset address
4. A serial port is available Serial port is not available
5. 5 hardware interrupts are present 2 hardware interrupts are present
6. 8 software interrupts (RST0 to
RST7) are present
229 software interrupts (INT n)
are present since the remaining 27
interrupts are reserved out of 256
interrupt types.
6. Operates in only one mode Operates in any one of the two
modes namely minimum and
maximum mode
7. Instruction queue is not present Instruction queue is present

Microprocessors and Microcontrollers Kumar, Saravanan & Jeevananthan

Oxford University Press 2011