Dr. Ing.

Luigi Vanfretti,
Rujiroj Leelaruji, Wei Li, and Tetiana Bogodorova

Docent and Assistant Professor
Smart Transmission Systems Lab.
Electric Power Systems Department
KTH Royal Institute of Technology, Sweden
E-mail: luigiv@kth.se
Web: http://www.vanfretti.com
Simulation Studies and Experiences of the preliminary
CIGRE DC Grid Test System with EMTP-RV, PSCAD and
Opal-RT
Acknowledgement

The work presented here was carried out by three different
PhD students:
- Wei Li (PSCAD)
- Tetiana Bogodorova (EMTP-RV)
- Rujiroj Leelaruji (Opal-RT Model: Matlab/Simulink/SPS + Lib.)
- They worked very hard for several weeks!

We would like to thank the following persons for their
support in using the models:
- Luc-Andre Gregoire (Opal-RT)
- Sebastien Dennetiere (RTE)
- Juan Carlos Garcia Alonso (Manitoba HVDC Research Center)
To start
Be nice : No one loves the messenger who brings bad
news
About the test systems:
- The specifications used in this work have been proposed by B4-57.
- The specifications used to define the test system are preliminary and
will be reviewed by the B4 WGs.

Exercise judgment
- Comparisons of highly detailed and complex models in three
completely different software environments are difficult
- A one-to-one agreement should not be expected
- All models can be improved, this study aims to show where
improvement is needed
- We make no statements of what is right or wrong, we just
present the results
- Even with the limitations of each of the current models, they are
actually quite detailed and of high quality.
To start
Be nice : No one loves the messenger who brings bad
news
About the test systems:
- The specifications used in this work have been proposed by B4-57.
- The specifications used to define the test system are preliminary and
will be reviewed by the B4 WGs.

Exercise judgment
- Comparisons of highly detailed and complex models in three
completely different software environments are difficult
- A one-to-one agreement should not be expected
- All models can be improved, this study aims to show where
improvement is needed
- We make no statements of what is right or wrong, we just
present the results
- Even with the limitations of each of the current models, they are
actually quite detailed and of high quality.
Outline
Brief description of the models
- Opal-RT (Matlab/Simulink + SimPowerSystems and eMegaSim from
Opal-RT)
- PSCAD from Manitoba HVDC Research Center
- EMTP-RV from PowerSys and EMTP DCG

Models differences

Simulation Studies
- Description and aim of the simulation studies
- Selected results (all results available for scrutiny)

General simulation challenges when using the
benchmark models

Recommendations and Further Work
Brief Description of the Models
Cigre DC Grid Test System
Types of Conv. Controls
Droop Cntrl
Droop Cntrl
P Cntrl
VF Cntrl
Not Specified
DC-DC Conv.
P Cntrl
Droop Cntrl
Test System in Opal-RT
(Layout from Hypersim)
No DC/DC converter
Embedded VBE
model means that
the detail MMC cell
model is
implemented but
without the cell
capacitor balancing
control (see the
OPAL-RT
presentation)
Test System in Opal-RT
(Top level model)
Subsystem of A1
MMC Converter
Subsystem A0 to A1
Test System in Opal-RT
(Subsystems)
Test System in PSCAD

Test System in PSCAD
Converter A1
Converter controller
VSC control MMC PWM
Test System in EMTP-RV
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
I
I
J
J
K
K
L
L
M
M
N
N
O
O
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
1 1
0 0
500 MW
100 MW
1000 MW
400 MW
600 MW
500 MW
1700 MW
1300 MW
1100 MW
1700 MW
600 MW
100 MW
1500 MW
1500 MW
CIGRE DC Grid test system - August 2012
Notes :
Every converters are configured as bipoles with earth return
Mixed configurations (monopole and bipole) can be used
Converter models : Detailed Equivalent - Type5 - 21 levels
Average value model is used for DC-DC converter B5


Converters Controls :
A1, B1, B2, B3 : P/Vdc droop control and Q control on AC side
C1, C2, D1, F1 : P control and Q control on AC side
E1 : V/f control
Double click to select the test case
1. Steady state solution
2. Steady State Power Through Converters
3. Fault on AC grid
3.1. Line opening
3.1.1. Trip and reclose of Line 1: A0_A1_2 A1_A0_2
3.1.2. Trip and reclose of Line 2: B0_B3 B3_B0
3.1.3. Trip and reclose of Line 3: C2_C1
3.2. Balanced 3 phase faults:
3.2.1. Fault on Line 1: A0_A1_2 A1_A0_2
3.2.2. Fault on Line 2: B0_B3 B3_B0
3.2.3. Fault on Line 3: C2_C1
3.3. Unbalanced 3 phase faults:
3.3.1. Fault on Line 1: A0_A1_2 A1_A0_2
3.3.2. Fault on Line 2: B0_B3 B3_B0
3.3.3. Fault on Line 3: C2_C1
4. Response due to reference changes:
4.1. Change in Pref at VSC_A1 (Droop Control): from 0.73 to 0.63
4.2. Change in Pref at VSC_B2 (Droop Control): form -1 to -0.9
4.3. Change in Pref at VSC_C1 (P control): from 1 to 0.9
4.4. Change in Pref at VSC_F1 (P control): from 1 to 0.9
4.5. Change in Pref at VSC_E1 (VF control): from -1 to -0.9
4.6. Change in Vref at B2 (Vf control): from 1 to 1.02
5. DC Faults
5.1. Trip and reclose of Line 1: A1_B1_1 B1_A1_1
5.2. Trip and reclose of Line 2: B5_B1 B1_B5
5.3. Trip and reclose of Line 3: B2_B3 B3_B2
5.4. Trip and reclose of Line 4: A1_C2 C2_A1


+
AC_C1
+
AC_C2
+
AC_D1
+
B0
+
AC_F1
DCline_2X1780MCM_200km
D
C
l i n
e
_
2
X
1
7
8
0
M
C
M
_
5
0
0
k
m
D
C
l i n
e
_
2
X
2
3
1
2
M
C
M
_
3
0
0
k
m
D
C
l i n
e
_
2
X
1
7
8
0
M
C
M
_
4
0
0
k
m
D
C
l i n
e
_
2
X
1
7
8
0
M
C
M
_
4
0
0
k
m
DCline_2X1780MCM_100km
ACline_3X795MCM_200km
ACline_3X795MCM_200km
P Q Load_E1
155kVRMSLL
100MW
0.1MVAR
ACline_3X795MCM_300km
ACline_3X795MCM_300km
PQ_C2
PQ_C1 PQ_A1
PQ_B3
PQ_B1
P Q Load_B1
380kVRMSLL
900MW
0.1MVAR
PQ_B3_B2_1
PQ_B3_B2_2
PQ_B3_B0
PQ_B2_B0
PQ_B1_B0_1
A
C
l i n
e
_
3
X
7
9
5
M
C
M
_
2
0
0
k
m
B
R
K
_
A
1
_
B
4
D
C
D
C
_
B
5
B
R
K
_
B
4
_
A
1
B
R
K
_
A
1
_
B
1
_
1
B
R
K
_
A
1
_
B
1
_
2
B
R
K
_
B
1
_
A
1
_
1
BRK_B5_B1
BRK_B1_B5
BRK_B1 BRK_B1_E1
B
R
K
_
B
1
_
A
1
_
2
BRK_E1_B1 BRK_E1
B
R
K
_
E
1
_
F
1
B
R
K
_
E
1
_
D
1
BRK_F1 BRK_B3
B
R
K
_
F
1
_
E
1
BRK_D1
BRK_C2
BRK_C1 BRK_A1
BRK_B3_B2 BRK_B2_B3
BRK_B2
PQ_LoadB3
PQ_B3_B1
PQ_B1_B3
PQ_LoadB1
PQ_LoadB2
PQ_B2
PQ_B2_B3_1
PQ_B2_B3_2
PQ_B0_B1_1
PQ_B0_B2
PQ_B0_B3
PQ_AC_C1
P
Q
_
C
2
_
C
1
PQ_A1_A0_2
PQ_A0_A1_1
PQ_A0_A1_2
BRK_C2_A1
BRK_A1_C2
B
R
K
_
D
1
_
C
2
B
R
K
_
D
1
_
E
1
PQ_B0_B1_2
PQ_B1_B0_2
A1_C1_800MM2_200KM
A1_C2_800MM2_200KM
B1_E1_800MM2_200KM
B6_F1_800MM2_100KM
C
2
_
D
1
_
6
3
0
M
M
2
_
3
0
0
K
M
D
1
_
E
1
_
1
0
0
0
M
M
2
_
2
0
0
K
M
E
1
_
F
1
_
6
3
0
M
M
2
_
2
0
0
K
M
B2_B3_630MM2_200KM
ACline_3X795MCM_400km
A
C
l i n
e
_
3
X
7
9
5
M
C
M
_
3
0
0
k
m
P Q
Load_B3
P Q
Load_B2
ACline_3X795MCM_200km
ACline_3X795MCM_200km
MMC
bipole
type4
20 SM
VSC_A1
MMC
bipole
type4
20 SM
VSC_C1
MMC
bipole
type4
20 SM
VSC_C2
MMC
bipole
type4
20 SM
VSC_D1
MMC
bipole
type4
20 SM
VSC_E1
MMC
bipole
type4
20 SM
VSC_F1
MMC
bipole
type4
20 SM
VSC_B1
MMC
bipole
type4
20 SM
VSC_B3
MMC
bipole
type4
20 SM
VSC_B2
A
C
c
a
b
l e
_
3
X
1
8
5
m
m
2
_
5
0
k
m
V
Vmeter_A1
Test case selection
Test cases 1 &2
V
Vmeter_C1
V
Vmeter_C2
V
Vmeter_D1
V
Vmeter_E1
V
Vmeter_F1
V
Vmeter_B3
V
Vmeter_B2
V
Vmeter_B1
V
Vmeter_B0
PQ_B0
PQ_A0_A1
PQ_AC1_A1
+
A0
+
AC2
V
Vmeter_A0
PQ_A1_A0_1
B
R
K
_
C
2
_
D
1
P Q
Load_E1_b
155kVRMSLL
10MW
0.1MVAR
PQ_AC_C2
PQ_AC_D1
PQ_AC_F1
PQ_E1_a
PQ_E1_b
PQ_D1
P
Q
_
C
1
_
C
2
PQ_E1
PQ_F1
B
R
K
_
B
5
_
2
BRK_B5_1
Test System in EMTP-RV
Converter A1
VSC_1
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
5 5
Start point reactors are disconnected in converters
AC
DC_pl us
DC_mi nus
MMC
monopol e
type4
20 SM
VSC_1
MMC
monopol e
type4
20 SM
VSC_2
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
I
I
J
J
K
K
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
1 1
0 0
Scope:
These devices are Exported Masks, do not modify
AC
1 2
- 30
Conv erter_Tfos
1/1
Ex ported Mas k
p
n
+
4
k
, 6
5
0
0
S
t a
r _
p
o
i n
t _
r e
a
c
t o
r
Page
1-B4
Vdc
scope
Vc 1_up_phA
scope
I_c i rc ul ar_phA
f ( u)
1
2
(u[1]+u[2])/2
P
a
g
e
1
- B
4
V
_
S
e
c
o
n
d
a
r y
_
T
r a
n
s
f o
P
a
g
e
1
- B
4
, 1
- J
4
I _
S
e
c
o
n
d
a
r y
_
T
r a
n
s
f o
P
a
g
e
1
- B
4
, 1
- H
3
V
_
P
r i m
a
r y
_
T
r a
n
s
f o
P
a
g
e
1
- B
4
, 1
- H
4
I _
P
r i m
a
r y
_
T
r a
n
s
f o
scope
Vc 20_up_phA
scope
Vc 1_l ow_phA
scope
Vc 20_l ow_phA
scope
Vref_phA
Va_ref
Vb_ref
Vc _ref
Page V_Sec ondary _Trans fo
Page
1-B4, 1-C1
I_Sec ondary _Trans fo
Page
1-B4, 1-B1
V_Pri mary _Trans fo
Page
1-B4, 1-B1
I_Pri mary _Trans fo
i a
v a
v a
i a
scope
V_Pri mary _phA
scope
I_Pri mary _phA
scope
V_Sec ondary _phA
scope
I_Sec ondary _phA
Page Vdc scope
Vdc
Va_ref
Vb_ref
Vc _ref
+
-
Vdc _meas
Page
1-J 4
Vabc _ref Page
1-B1, 1-H3 V_Pri mary _Trans fo
Page
1-B1, 1-H4 I_Pri mary _Trans fo
Page
1-C1 V_Sec ondary _Trans fo
Page
1-C1, 1-J 4 I_Sec ondary _Trans fo
Page
S_up_A
Page i _up_A
Page i _l ow_A
Page i _up_B
Page i _l ow_B
Page i _up_C
Page i _l ow_C
Page S_l ow_A
Page S_up_B
Page S_l ow_B
Page S_up_C
Page S_l ow_C
Page Vc _up_A
Page Vc _l ow_A
Page
1-D4
Vabc _ref
Page i _up_A
Page i _l ow_A
Page Vc _up_C
Page Vc _up_B
Page Vc _up_A
Page Vc _l ow_C
Page Vc _l ow_B
Page Vc _l ow_A
Page Vc _up_C
Page Vc _up_B
Page Vc _up_A
Page Vc _l ow_C
Page Vc _l ow_B
Page Vc _l ow_A
MMC Control
CCSC+CBA
Gate
signals
Va_ref
Vb_ref
Vc_ref
Vc_low_A
Vc_up_A
Vc_up_B
S_up_A
Vc_low_B
Vc_up_C S_up_C
Vc_low_C S_low_C
S_up_B
S_low_B
S_low_A
theta
i_up_C
i_up_B
i_low_C
i_low_B
i_up_A
i_low_A
Capa.
Voltages
Current
Arms
MMC_Control
Page i _up_A
Page i _l ow_A
Page i _up_B
Page i _l ow_B
Page i _up_C
Page i _l ow_C
Page S_up_A
Page S_l ow_A
Page S_up_B
Page S_l ow_B
Page S_up_C
Page S_l ow_C
Vc 1
Vc 20
Vc 1
Vc 20
Page
1-H4
P_meas
Page
1-H4
Q_meas
scope
P_meas
scope
Q_meas
Page
1-D4
P_meas
Page
1-D4
Q_meas
Page 1-H2 Vdc
i_up_A
P
i_up_B
i_up_C
i_low_A
i_low_B
N
i_low_C
AC
S_up_B
S_up_A Vc_up_A
Vc_up_B
Vc_up_C
Vc_low_C
Vc_low_B
Vc_low_A S_low_A
S_low_B
S_low_C
S_up_C
Capa.
Voltages
Gate
signals
Input Ouput
Current
Arms
Equivalent Equation Model (EEM)
MMC 21Levels
in DLL
NB:
This DLL works for a step time >1us
EEM_MMC_21L
MMC_20SM
vi
Sec ondary 1
vi
Pri mary 1
VSC Control
V_Secondary_Transfo
I_Secondary_Transfo
Vabc_ref
V_Primary_Transfo
I_Primary_Transfo
Vdc_meas Vdc
theta
P_meas
Q_meas
VSC_Control
AC_Conv erter
Main Model Differences
Opal-RT Model (Matlab/Simulink/SPS + Opal-RT Libraries)
- Developed by Opal-RT (Luc-Angre Gregoire)
- Embedded VBE for VSCs (Type 5 see Opal-RT presentation)
- No. of sub-modules per valve: two type of converters, 400 (for on-shore) and 20 (for offshore grid)
- DC-DC Converter Model not included (B5 Converter)
- 11 cores running in real-time with the eMegaSim simulator.
PSCAD Model
- Developed by Manitoba HVDC Research Center.
- Detailed (equivalent Norton) models of VSC (Type 4 all gate signals).
- No. of sub-modules per valve: Two type of converters, one is 38 (MMC PWM) and the other is 98 (MMC)
- DC-DC Converter Model not included (B5 Converter)
EMTP-RV Model
- Developed by RTE (Sebastien Dennetiere)
- Detailed (equivalent Norton) models of VSCs (Type 4 all gate signals).
- No. of sub-modules per valve: 21
- Type 2 (DM) also available.
- Simplified DC-DC Converter included
- Documented modification from specification: Parameters are modified in the AC side B0 and B1 line length
is 200 km, 2 circuit lines (instead of 1 line of 400 km)
Type 4 Definition
- Reduction in each arm to limit the number of electrical nodes (based on the integration method 1 arm, 1
equivalent)
Simulation Studies:
Steady State and Time Domain
Simulation goals:
- Determine the steady state performance of the test systems
- Determine the dynamic performance of the test systems and
terminals due to small perturbations, switching events (at DC), and
faults (at AC)
Simulation studies proposed (22):
- Steady State Analysis (3)
- Faults on AC Systems:
Line opening (3)
Balanced 3-phase faults (3)
Unbalanced 3-phase faults (3)
- Response due to control reference changes
Perturbation in Pref at all controllers (5), Vref (1)
- DC Faults: DC Line switching
DC line openings (4)
Studies carried out: Opal-RT (21), PSCAD (16), EMTP-RV (22)
Count: 59 simulations 3 steady state, 56 time domain


Model/User Limitations:
Simulations that could not be carried out
Opal-RT
- Change in Vref at DCDC_B5 (Simulation 4) Response due to
reference changes
PSCAD
- Change in Pref at VSC_E1 (Simulation 4) Response due to
reference changes
Model needs to be modified by adding a load at E1.
We ran out of time to do this.
- Change in Vref at DCDC_B5 (Simulation 4) Response due to
reference changes
Converter B5 is an empty block
- All DC Faults
Could not figure out how to disable some internal breakers in
the converters.
EMTP-RV
- All simulations were be executed.



Requirements to
run the models
Opal-RT
- OPAL-RT real-time simulator OR license to run the
compiled model in the PC (localhost license)
- RT-Lab version 10.4.4.130, MATLAB Simulink 2011b
(32-bit).
- MMC libraries from Opal-RT
- 11 processors
(eMegaSim simulator at KTH SmarTS Lab has 24).
PSCAD
- Compiler: PSCAD requires a FORTRAN compiler. In these simulation we use Intel Visual
Fortran Composer XE 2011 (v12) compiler (trial license).
- Version of the software: PSCAD X4 (4.5.0.0) Professional edition (trial license).
- Third party tools: If having the error of WSock32.lib file missing, the Windows platform
headers and libraries need to be installed by the users.
- A VSC_MMC_lib file comes together with the model.
EMTP-RV
- EMTP-RV V2.4
- MMC Toolbox
FOR ALL OF THE ABOVE: PATIENCE!!! (and money)

Steady State Analysis
We consider the harmonic steady state, not power flow
solution.
Procedure: -run the simulation until it reaches a steady state
Opal-RT and PSCAD models offer a meter.
For EMTP-RV:
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-1
-0.5
0
0.5
1
1.5
2
x 10
9
time (s)
y
PLOT
BRK_B2_B3/p1/p_t@control@1
Steady
State
EMTP-RV
SPS Meters
0,8
0,9
1
1,1
A0 A1 B0 B1 B2 B3 B4 B5 B6 C1 C2 D1 E1 F1
A
C

V
o
l
t
a
g
e

(
p
u
)

AC Bus
Design Specification Opal-RT PSCAD EMTP-RV
Steady State Solutions AC and DC Bus Voltages
DC Buses
AC Bus AC Bus
0,8
0,9
1
1,1
A0 A1 B0 B1 B2 B3 B4 B5 B6 C1 C2 D1 E1 F1
D
C

V
o
l
t
a
g
e

(
p
u
)

DC Bus
Design Specification Opal-RT PSCAD EMTP-RV
Steady State Power Through Converters
Steady State Power through
Converters
1100
600
400
1000
100
500
1700
500
1300
1100
P
AC_A1

P
AC_C1

P
AC_D1

P
AC_C2

P
AC_E1

P
AC_F1

P
AC_B3

P
AC_B1

P
AC_B2

P
DC_B5_out

P
DC_B5_in

Comparison of Desired Flows:
Design spec. with actual power through converters
(max. value between input and output)
The Opal-RT model matches the specification with no differences.
There is a very reasonable agreement between the design specification EMTP-
RV. Differences are likely due to tuning of model parameters.

Difference with
the Spec.
0
200
400
600
800
1000
1200
1400
1600
1800
A1 B1 B2 B3 B5 C1 C2 D1 E1 F1
P
o
w
e
r

(
M
W
)

Converter
Opal-RT PSCAD EMTP-RV Design Specification (Desired Flow)
Models
need to be
verified
Steady State Solutions
(Harmonic Steady State) AC and DC Flows
Steady State Solns.
AC Flows
DC Flows
Design Spec.
PSCAD
EMTP-RV
Opal-RT
AC and DC Flows
0,00
500,00
1000,00
1500,00
2000,00
2500,00
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Design Spec. Opal-RT PSCAD EMTP-RV
Results
Absolute Values Shown
Line no. From Bus To Bus
Design
Spec.
1 A1ac A0ac 600,00
2 A1dc B1dc 1500,00
3 A1dc B4dc 800,00
4 C1dc A1dc 600,00
5 C2dc A1dc 600,00
6 B0ac B1ac 400,00
7 B0ac B2ac 400,00
8 B0ac B3ac 400,00
9 B1ac B3ac 400,00
10 B4dc B1dc 300,00
11 B1dc E1dc 500,00
12 B2ac B3ac 200,00
13 B3dc B2dc 200,00
14 B5dc B2dc 1100,00
15 B6dc B3dc 700,00
16 F1dc B6dc 700,00
17 C1ac C2ac 100,00
18 C2dc D1dc 200,00
19 D1dc E1dc 800,00
20 E1dc F1dc 200,00
Directly
Connected to
Slack Bus
600
577
279,80
609
1500
1194,90
340,60
1127,20
800
199,61
320,50
530,40
600
4,40
277,80
595,90
600
5,90
158,50
250,40
400
- 434,10
13,70
622,70
400
1017
422,90
486,20
400
772
377,60
2436
400
741,30
688,80
834,60
300
- 198,34
120,30
1251,00
500
104,38
321,00
316,60
200
58,64
176,50
34,35
200
836,80
153,29
1886
1100
0
433
720,20
700
841,47
217,60
2301
700
887,98
245,40
2301
100
- 10,47
137,28
149
200
- 64,27
4,60
151,20
800
586,83
524
836
200
432,12
138
1805
Flow from B2
to F1
In some of the AC measurement, the output was filtered after power
computation. For the DC case, only the instantaneous power without
filtering was used.







Source of errors in power
measurements in Opal-RT model
Also, the power in each AC line
was deducted from the
measurement of each converter.
There is a lot of room for error in
doing this way. Next version of
the model should include more
measurement to avoid such error.

In some of the AC measurement, the output was filtered after power
computation. For the DC case, only the instantaneous power without
filtering was used.







Source of errors in power
measurements in Opal-RT model
Also, the power in each AC line
was deducted from the
measurement of each converter.
There is a lot of room for error in
doing this way. Next version of
the model should include more
measurement to avoid such error.

Faults on AC Systems
AC Faults
Line 1
Line 2
Line 3
Faults on AC Systems
AC Faults
Line 1
Line 2
Line 3
All changes applied at t=1 sec after harmonic steady state
soln.


Balanced (3 phase) [or unbalanced] fault is applied at left-
hand (or upper) side bus of the line.

Ideal AC breakers are placed on each side of the line.


The line is opened after 2 cycles (0.04sec), after this to
cycles the fault is cleared by opening the breakers on left
hand side and right hand side simultaneously, and closing
them simultaneously after 2 cycles.
Balanced Fault on Line 3:
C1_C2
0 0.2 0.4 0.6 0.8 1
0
0.5
1
A
C
V
o
l
t
a
g
e
B
u
s
C
1


Opal-RT PSCAD EMTP-RV
0 0.2 0.4 0.6 0.8 1
0.9
1
1.1
1.2
D
C
V
o
l
t
a
g
e
B
u
s
C
1
0 0.2 0.4 0.6 0.8 1
0.7
0.8
0.9
1
1.1
A
C
V
o
l
t
a
g
e
B
u
s
C
2
0 0.2 0.4 0.6 0.8 1
0.8
1
D
C
V
o
l
t
a
g
e
B
u
s
C
2
Time - (sec)
0 0.2 0.4 0.6 0.8 1
0
500
1000
P
.
t
o
C
o
n
.
C
1


Opal-RT PSCAD EMTP-RV
0 0.2 0.4 0.6 0.8 1
-2000
0
2000
P
.
f
r
o
m
C
o
n
v
.
C
1
0 0.2 0.4 0.6 0.8 1
0
500
1000
P
.
t
o
C
o
n
.
C
2
0 0.2 0.4 0.6 0.8 1
-1500
-1000
-500
0
500
P
.
f
r
o
m
C
o
n
v
.
C
2
Time - (sec)
Response Due to Reference Changes
Response to Ref.
Changes
Pref=-0.1
Droop Cntrl
Pref=-0.1
Droop Cntrl
Pref=-0.1
P Cntrl
Pref=-0.1
P Cntrl
Pref=+0.1
VF Cntrl
Vref=+0.02
Const. V
Faults on DC Grid
DC Faults
Line 1
Line 2
Line 3
Line 4
General Simulation Challenges
Opal-RT
- Separate subsystems in order to run in real-time
- Need a model compiler for the specific architecture of the system
and software configuration.
- Model modifications during real-time simuation
Con.: No possibilities of modifying the circuit model for real-
time simulation, but ok for off-line (although this takes out the
advantage of having an RT simulator)
Pros.:
Control parameters can be modified while real-time simulation is running.
RT simulator can be used in Simulation Accelerator mode when no I/O is used
(faster than real-time)
- Capacitor Balancing:
Detailed MMC cell model was used.
However, the DC voltage of each capacitor is adjusted to the
average value of the sum of the cell capacitor voltage.
The capacitor voltage balancing control system is therefor not
implemented (but available).

General Simulation Challenges

PSCAD
- Errors that are difficult to figure out:
Example1:Component *** does not have a corresponding
definition.
Solution: loading the library has to do before loading the
model.
Example2: ***No rule to make target ***.mak. Stop
Solution: install suitable compiler (GNU Fortran compiler is
not suitable)
PSCAD
- Aspects not documented that make it difficult to use the
model
In link tab of project setting, the user must manually add these
sub-directories to the directory specied by the User Library Path
input in the Workspace dialog. In this simulation, we need to
choose if12 (Intel Visual Fortran compiler versions 12).
De-blocking the converter control for several seconds at the
beginning of the simulation, which is not indicated when providing
this model.





Some newly developed components do not have help information.
For example, the DC breaker.


General Performance Observed
(ONE Specific Case)
Opal-RT (50 sec time step)
A. Approximately 1 sec
B. Simulation time: Real time. (1 sec. = 1 sec.)

PSCAD (20 sec time step)
A. Approximately 5 sec
B. Simulation time: about 1 hr for a 15s simulation
(Initialization Work Around - if system is left unchanged: start from a
snapshot (snapshot for initialization)

EMTP-RV (40 sec time step)
A. Approximately 0.5 sec.
B. Simulation time: 258.625 sec for 2 second simulation.
A. Simulation t to reach a steady state
B. Time effort to carry out one simulation

Recommendations and Further Work
The three models simulated are very complex and detailed, and will
certainly be useful for DC Grid studies.
We make the following recommendations for improvements on the
current models!
Documentation:
- Currently the EMTP-RV and SPS models are designed only for the
scenarios presented.
- Documentation on the models (details) are needed for preparing other
studies.
Model Harmonization:
- The DC Grid benchmark models need to:
Be harmonized in terms of steady state solution
Controller implementation should be identical
- For large DC Grid studies, the focus is not on converter performance, and
detailed representation of the VSCs might be unnecessary
The use of a common average value model for the VSC is recommended,
but this must be validated with detailed models
(Detailed models are only necessary for internal protection and
performance analysis)
Recommendations and Further Work
Validation:
- Component validation
Validation across different simulation environments should
start at the component level for comparison studies to be
meaningful:
Controller validation should be first (check controller response to
isolated inputs compare outputs)
VSC validation (for AVM), DC Line models and breaker models
Independent validation of AC grid portions
Component level validation with real measurements
would be AWESOME!
Some suppliers and R&D centers have comparisons with actual
hardware or analog set ups, but it is not public.
- Point-to-point DC Link:
Validation is recommended to establish the core differences
of a simple DC Grid operation under different control modes
in the three different environments.
Recommendations
Looking into the Future: Avoid Modeling Ambiguity
Modeling and Simulation without Ambiguity!
The efforts in developing these benchmark models is of great value for DC
Grid development.

However, DC Grid development will be hindered due to a lack of ability:
- To share (validated) models across different simulation environments.
- Which in turns requires the re-implementation of models in different tolls (very costly!).
- In this case models need to be validated.

This study has shown that there is a clear need for unambiguous model
exchange
- Model exchange not referring only to parameter data
- Actual model implementations differ: whats inside the box? is not transparent to the user
- Challenge for users without access to all software (economically prohibitive)

This problem has existed since about 40 years for conventional AC/DC
system design! (J. Belanger)
- DC Grid development should strive to tackle this attitude for common benefit.
Recommendations Looking into the
Future: Avoid Modeling Ambiguity
Possible solutions to ambiguity
Modelica-based models:
- Modelica is an OOP modeling language for complex systems
- Modelica models allow the specification of both the model equations and
parameters
- A DC Grid model could be entirely defined, without ambiguity, and shared.
- Files could be packaged so that the model inside remains closed.

- Caveat: Each simulation environment needs to translate from Modelica to
their internal definition (which requires validation). Mapping to GUI, etc

- However:
- The use of Modelica language for very large AC/DC networks still need to
be demonstrated. FP7 Pegase project had very promising results for
moderate size networks.
- Usually, network solution used specialized circuit solvers (nodal ) with
system topologies and component parameters. Are topology-based
specialized solvers available in Modelica?
Proof of concept:
Sharing Modelica Power System Models in two
different simulation environments
Simulation results in Scilab/Xcos and Dymola, respectively. They are
absolutely the same.
Courtesy of Wei Li (KTH), Angela Chie and Patrik Panciatici (RTE)
Proof of concept:
Sharing Modelica Power System Models in two
different simulation environments
Simulation results in Scilab/Xcos and Dymola, respectively. They are
absolutely the same.
Courtesy of Wei Li (KTH), Angela Chie and Patrik Panciatici (RTE)
Recommendations Looking into the
Future: Avoid Modeling Ambiguity
Possible solutions to ambiguity (contd)
FMI
- Automotive industry has used the Flexible Mock-up Interface approach. Models
are exported in a FMU (Functional Mock-up Unit).
- FMUs can be imported in another environment and executed.
- FMUs from different sources can cooperate at runtime in a co-simulation
environment. FMI defines the interfaces for this to happen.
- Caveat: co-simulation environment is needed. Would be difficult to do real-time
simulation (in the case of Opal-RT Models).

- OPAL-RT already support co-simulation for loosely coupled systems.
- But
Co-Simulation is very difficult for tightly coupled system such as AC/DC
circuit due to delays since simultaneous solution is required. OPAL-RT has
developed SSN for this purpose.
The use of FMI for electrical network simulation still need to me demonstrated
and it may happen that FMI is a good approach for loosely coupled simulation
only (control systems and plant models with very different time constants).
Recommendations Looking into the
Future: Avoid Modeling Ambiguity
Possible solutions to ambiguity (Contd)
CIM-for-EMT
- Would be similar to the Modelica approach, but it would be
more difficult to share exact equations (or package them so
that they are closed).
- As of now, CIM only defines the topology and system
parameters, not the model equations
Thank you!
luigiv@kth.se
http://www.vanfretti.com