DIGITAL SYSTEMS

COURSE SUMMARY
-EE Placement Team 2013-14
COUNTERS AND REGISTERS
Register consists of a group of flip-flops with a common clock input.They are used to store
and shift binary data.
Counter is constructed from two or more flip-flops which change states in a prescribed
sequence when input pulses are received.
Counters and registers are sequential circuits.


DESIGN OF BINARY COUNTERS

D=
!
T= "
!
#$or%
&$ample'


CLOCED SE!UENTIAL CIRCUITS
E"am#le1$Anal%&'&()(or the following sequential circuit)find the ne$t state equation or map for each flip-
flop.*sing these construct a state graph and a state table.+hat is the output sequence when the input
sequence is ,=-..--/ Draw the timing diagram.
0olution'


E"am#le 2)$De*'+a't,n ,- &tate .*a#/& an0 ta1le&( '1 sequential circuit has two inputs#,. and ,2% and
one output#3%.The output begins as - and remains a constant value unless one of the following input
sequences occurs.#a% The input sequence ,.,2=-.)-- causes the output to become -)#b% The input
sequence ,.,2=..)-- causes the ouput to become . #c% The input sequence ,.,2=.-)-- causes the
output to toggle.Derive a moore state table.
0olution )
1ssign a state to each possible input#--)-.)..).-% with an output of -)and another state to each input with
an output of ..This gives eight states.
The state table with 4 states to this 5-state table using the state reduction methods.
STATE REDUCTION )
E"am#le)

STATE ASSIGN2ENT )+e try to satisfy as many conditions as possible from the following'
DESIGN OF SE!UENTIAL CIRCUITS



*sing 617#6rogrammable 1rrray 7ogic%
ALGORIT32IC STATE 2AC3INE)
1n 108 chart is a method of describing the sequential operations of a digital system.The chart is
composed of three basic elements'
..0tate bo$'9ndicates a state in the Control 0equence and is rectangular in shape.
2.Decision bo$'Descibes the effect of an input on the control subsystem and has diamond shape.
:.Conditional bo$'The register operations or outputs listed inside the conditional bo$ are generated during
a given state provided the input condition is satisfied.9t has an oval shape.
E"am#le) AS2 BLOC



State 0'a.*am e45'+alent ,- t/e AS2 Bl,c6
ASYNC3RONOUS SE!UENTIAL CIRCUITS
1synchronous sequential circuits donot use clock pulses.The change of internal state occurs when there
is a change in the input variables.
1nalysis &$ample'

Fl,7 Ta1le)
.
;
Race conditions: 1 race condition is said to e$ist in an 1synchronous sequential circuit when two or
more binary state variables change value in response to change in an input variable.9f the final stable
state that the circuit reaches does not depend on the order in which the state variables change)the race is
called a noncritical race.9f it is possible to end up in two or more different stable states)depending on the
order in which the state variables change)then it is a critical race.

+hen a circuit goes through a unique sequence of unstable states)it is said to have a cycle.
P,'nt t, *emem1e* 7/en 0e&'.n'n. A&%nc/*,n,5& &e45ent'al c'*c5't&)
The circuit must be operated in fundamental mode with only one input changing at a time and must be
free of critical races.
Sta1'l't%) The values of < that are equal to y represent stable states .

&$ample of an unstable circuit.
Design example for Asynchronous Sequential Circuit:To design a negative edge triggered T (lip-
(lop.
Ste#& 'n+,l+e0 'n t/e 0e&'.n #*,ce&&)
..De&'.n &#ec'-'cat',n&'The circuit has 2 inputs)T#Toggle% and C #Clock% and one output .The output
state is complemented if T=. and the clock C changes from . to -.&lse the output remains unchanged.
28 P*'m't'+e Fl,7 Ta1le

2
.
:.2e*.'n. ,- t/e Fl,7ta1le
5.Race-F*ee State A&&'.nment'
9.T*an&'t',n Ta1le an0 O5t#5t 2a#'
:.O1ta'n t/e L,.'c D'a.*am'
3a;a*0&'*nwanted switching transients that appear at the output of a circuit because different paths
e$hibit different propagation delays.
3a;a*0& 'n C,m1'nat,*'al C'*c5't&)Condition where a single variable change produces a momentary
output change when no output change should occur.
3a;a*0& 'n Se45ent'al C'*c5't&'9f a momentary incorrect signal is fed back in an 1synchronous
0equential Circuit)it may cause the circuit to go into the wrong stable state.
T%#e& ,- 3a;a*0&'


E"am#le'
Detect',n'+henever the circuit must move from one product term to the other)there is a possibility of a
momentary interval when neither term is equal to .)giving rise to an undesirable - output.
C,**ect',n'
Removed by covering any two minterms that may produce a ha=ard with a product term common
to both.


+hen a Combinatorial circuit is implemented in 0>6 form with 1?D->R or ?1?D gates)the
removal of static-. ha=ard guarantees the removal of static-- ha=ard and dynamic ha=ards.
1nother way to avoid static ha=ards in 1synchronous 0equential Circuits is to implement the
circuit with 0-R 7atches.1 momentary - signal applied to the 0 or R inputs of a ?>R latch will
have no effect on the state of the circuit.
3a;a*0 'n an A&%nc/*,n,5& Se45ent'al C'*c5't8
E&&ent'al /a;a*0&'
Caused by unequal delays along two or more paths that originate from the same input.
>ccurs in asynchronous sequential circuits.
Cannot be corrected by adding redundant gates.
Corrected by ad@usting the amount of delay in the affected path.
EE Placement Team 2013-14
References :
..(undamentals of 7ogic Design by C/a*le& R,t/.
2.Digital Design by 2,**'& 2an,8