Title: Top-Down Design of VLSI Circuits using Schematic Entry and Electronic

Design AutomationPart-IIALUs
Abstract:
This experiment continues the hierarchical design process of VLSI Circuits utilizing Electronic Design
Automation (EDA) tools such as DSCH and MICROWIND. The students will get to design larger designs,
such as a 4-bit, 4-operation ALU, as compared to previous experiments. The concept of design re-use
will be emphasized with DSCH symbols.
Introduction:
Full adders are one of the most widely used design blocks in digital circuits. They are used as basic
building blocks for large adders as well as multipliers. This experiment shows students how they can be
used as a building block of Arithmetic and Logic Unit (ALU) as well.
Theory And Methodology:
Any digital circuit can be designed using dedicated devices or re-using common blocks with dedicated
hardware minimized. For example, an adder-subtracter can be designed using an adder and a
subtracter. Here, each task or application is realized through specific hardware. This would be a design
process using only dedicated devices.
The other approach to design an adder-subtracter would be to use adders for both addition and
subtraction utilizing 2s compliment algorithm. This design process that maximizes usage of common
blocks and minimizes custom hardware meant for specific tasks/application is what is referred to as
design re-use.
Note that for adder-subtracter, XOR gates would be needed for selectively passing one of the inputs or
its 1s compliment (depending on the control signal Add_Sub). The extra 1 needed for 2s compliment is
added by connecting the control signal (Add_Sub) to the carryin port of the full adder associated with
the least significant bits of the inputs. In other words, if an ALU performs only addition and subtraction,
the adder-subtractor designed in Lab7 would be sufficient for it.
To extend the ALUs operation to AND and OR operation, one can add AND and OR gates to the design,
selectively pass both the inputs to the adder-subtractor, the AND gate or the OR gate as needed through
the two demultiplexers and then finally pass the result of one of these 3 computing elements to the ALU
output through a mux, as displayed below.
An alternative approach to design this ALU involves utilizing the adder to implement AND and OR
operation in addition to addition and subtraction. This approach would save a lot of hardware (reduce
number of gates). VLSI designers are always looking for reusing a device for performing multiple
operations to reduce area and cost. This also simplifies the (physical) layout design process as well.
In this approach, the sum ports of the adders will displays addition and subtraction results, while the
carryout ports will display the AND and OR results.

To implement the AND and OR operation in the above-mentioned approach, the designer needs to
develop a logic circuit that would send 0s to carryin ports of full adders for AND operation, 1s to these
ports for AND operation and keep the carryin bits unmodified for addition and subtraction. In other
words, for addition and subtraction, carryout outputs of one stage would become carryin inputs of next
stage; however, for AND and OR operation, the Next-CarryIn logic circuit would send 0s or 1s
unconditionally to the carryin inputs of the next stage regardless of the carryout values of the previous
stage so that these operations can be implemented. Note that for subtraction, the initial carryin signal
(Cin0) needs to receive a 1 so that 2s complement of one of the inputs can be sent to the adders.
Utilize the symbols for 1-bit full adder and 2-bit, 2-input XOR gate designed in Lab7 to complete this
design. You should also generate a symbol for the Next-CarryIn logic circuit developed from the above
truth-table. The general hardware architecture is shown below.

To implement the AND and OR operation in the above-mentioned approach, the designer needs to
develop a logic circuit that would send 0s to carryin ports of full adders for AND operation, 1s to these
ports for AND operation and keep the carryin bits unmodified for addition and subtraction. In other
words, for addition and subtraction, carryout outputs of one stage would become carryin inputs of next
stage; however, for AND and OR operation, the Next-CarryIn logic circuit would send 0s or 1s
unconditionally to the carryin inputs of the next stage regardless of the carryout values of the previous
stage so that these operations can be implemented. Note that for subtraction, the initial carryin signal
(Cin0) needs to receive a 1 so that 2s complement of one of the inputs can be sent to the adders.

Apparatus:
1. A Windows-based (XP or 7) PC with standard word processors (i.e. Microsoft Office) and PDF readers
(i.e. Adobe Acrobat Reader/Writer, Foxit Reader/Phantom) installed. 2. A PSPICE simulator, preferably
ORCAD PSpice Student 9.1 Student from Cadence

Precautions:
1. A PC with a standard Anti-Virus program installed should be used.










SIMULATION:
A 2-bit 4-operation ALU:





4 BIT 4 Operation ALU:








4 BIT 4 OPERATION ALU (WITHOUT DEMUX)

Discussion And Conclusion:
1. All the results matched the theoretical data from the tables constructed beforehand.
2. All the results for all the operations were checked repeatedly and no mistakes were found.
3. The ALU was designed very carefully and no mistakes were found with wiring or any of the
symbols used.
REFERENCES:
1. Lab manual provided in class.
2. http://en.wikipedia.org/wiki/Arithmetic_logic_unit
3. http://whatis.techtarget.com/definition/arithmetic-logic-unit-ALU
4. http://www.computerhope.com/jargon/a/alu.htm
5. http://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder