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New Low-Power Reversible Logic Gates Using Gate Diffusion

Input Technique
R. Uma
1,
, P. Vigneshwarababu
2,
, R. Nakkeeran
2
and P. Dhavachelvan
1
1
Department of Computer Science, School of Engineering, Pondicherry University, Pondicherry 605 014, India.
2
Department of Electronics Engineering, School of Engineering, Pondicherry University, Pondicherry 605 014, India.
e-mail: uma.ramadass1@gmail.com; vickeybabu@gmail.com
Abstract. Reversible computation received signicant attention in low power dissipating circuit design in the
past fewyears. Classical computation involves irreversible logic gates which inevitably generate heat. To achieve
low power consumption reversible logic becomes a competent technology that have both forward and backward
deterministic. This paper focuses two main design approaches. The former presents the implementation of two
Modied Toffoli Reversible gate (MTGDI) namely MTGDI gate1 and MTGDI gate2. The implementation of
these logic gates into electronic circuitry is based on Gate Diffusion Input Technique. The latter presents the
realization of full adder circuit using the proposed MTGDI gate1 and MTGDI gate2. The performance of the
proposed adder is compared with the existing full adders in terms of power dissipation, garbage output, number
of stages and quantum cost. Delay and power has been evaluated by Tanner simulator using TSMC BSIM
0.250 m technologies.
Keywords: Reversible logic, Garbage output, Quantum computing, Bijective mapping, Logical reversibility.
1. Introduction
Reversible logic design is extensively motivated in recent years due to its energy and information lossless
design. Conventional irreversible logic gates dissipate heat for every single bit loss during their operation.
Based on R.Landauers theory in 1960, the loss of one bit information dissipates KTln2 joules of energy. where
K = 1.3806505 10 23 m
2
kg
2
K-1(joule/kelvin-1) is the Boltzmanns constant and T is absolute temperature at
which operation is occurred [1]. This loss cannot be avoided if the circuit comprises of irreversible logic gates. In 1973
C. H. Bennett demonstrated that this KTln2 joules dissipation can be avoided if the circuit is reversible. So this power
dissipation issue can be overcome by using reversible logic gates instead of conventional irreversible logic gates in a
circuit.
A gate or circuit is reversible if it does not lose any information and allows one to uniquely recover input vector from
the output vector and vice versa. In reversible logic gates there is one to one mapping between input and output i.e.
number of input lines equal to number of output lines. This bijective mapping prevents the loss of information which is
main reason for power dissipation in irreversible logic. The reversible gate output which is not used is called Garbage
output. Extra Inputs which are used in reversible gate to make it reversible is called Constant or Garbage input.
Performance and Complexity of reversible gate/circuits are depends on various parameters. Such as
Less number of reversible logic gates are used to design reversible circuit
Less number of constant or garbage input should be used to make the gate reversible
Garbage output should be minimum
Fan out is not allowed in reversible logic gate. The fan out of each gate is equal to one. A copying gate is used if
more fan out are required
The purpose of this paper is to propose new reversible gate using Gate Diffusion Input (GDI) Technique. The
primary objective of this proposed gate produces optimum power product (Product of power and delay PDP) and
quantum cost with compared to the existing counterpart. The proposed primitive structure is designed to operate in

Corresponding author
Elsevier Publications 2013.
R. Uma, et al.
Figure 1. Proposed MTGDI reversible gates.
the 3-5V range with 250 nm process parameter. The organization of the paper is as follows: The section II, describes
the design structure of Modied Toffoli gate MTGDI gate1 and MTGDI gate2 using Gate Diffusion Input Technique
[5,6]. Section III, presents the implementation of proposed full adder using MTGDI gate1 and MTGDI gate2.
Section IV presents the performance issues with respect to its counterpart. Section V presents the discussion. Finally
the conclusion is presented in section VI.
2. Proposed Primitive Reversible Primitive Cells
A reversible gate has equal number of inputs and outputs and one-to-one mappings between input vectors and output
vectors; so that, the input vector states can be always uniquely reconstructed from the output vector states. Several
reversible gates have been reported in [14,718]. Among them are Feynman Gate (FG), Toffoli Gate (TG), Fredkin
Gate (FRG), New Gate (NG) and New Toffoli Gate (NTG). The proposed reversible is a modied version of Toffoli
Gate (TG) using GDI (MTGDI). The proposed gate consists of 3 input and 3 output reversible blocks. The input vector
is I (A, B, C) and output vector is O(P, Q, R). The logic diagram and truth table of the proposed reversible gates are
shown in gure 1. Figure 1a shows the realization of MTGDI gate1 which denes the functionality of a buffer, 2-input
MUX and 2-input AND. The computation functions based on A, B, C are
If =

A = 0, P = 0, Q = AB, R = B : A = 1, C = 1, P = 1, Q = MUX, R = XOR


B = 0, P = A, Q = AC, R = 2 i nput AND; B = 1, P = A, Q = MUX, R = 2 i nput NAND
C = 0, P = A, Q = AB, R = B
Figure 1b shows the realization of MTGDI gate2 which denes the functionality of two buffers and 2-input XOR
gate. The computation functions based on A, B, C are
If =

A = 0, P = 0, Q = B, R = C; A = 1, P = 1, Q = B, R = C
B = 0, P = A, Q = A, R = C; B = 1, P = A, Q = A, R = C
C = 0, P = A, Q = 2 i nput XOR, R = 0; C = 1, P = A, Q = 2 i nput XOR, R = 1
3. Proposed Full Adder Cell using MTGDI
Addition is an indispensable operation for any high speed digital system, digital signal processing or control system.
The primary issues in the design of adder cells are area, delay and power dissipation. Several adder topologies
have been reported by [1018]. The proposed adder circuit realization is shown in gure 2. The proposed adder is
implemented with MTGDI gate1 and MTGDI gate2. Gate2 realizes the sum function and Gate1 realizes the carry
function. To test the performance of the proposed and existing reversible adders, detailed comparisons were performed.
32 Elsevier Publications 2013.
New Low-Power Reversible Logic Gates Using Gate Diffusion Input Technique
Figure 2. Proposed full adder circuit realization.
The simulations were run with the Tanner software. All the schematics are based on TSMC 0.250m technology with
supply voltage ranging from 1.2 V to 5 V in steps of 0.2 V. All the full adders are simulated with multiple design
corners (TT, FF, FS, and SS) to verify that operation across variations in device characteristics and environment. The
W/L ratios of both nMOS and pMOS transistors are taken as 2.5/0.25 m. The circuits are simulated with a 100 MHz
clock frequency. The delay parameter is calculated from all the transitions from an input combination to another, and
the delay at each transition has been measured from the time that clock signal reaches 50% of the supply level. Power
Delay Product (PDP) has been calculated by the taking the product term of delay and average power consumption.
The input/output waveform generated for proposed full adder with clock frequency of 100 MHz is shown in gure 3.
The waveform indicates the complete transition characteristics of proposed full adder with the three inputs A, B, C
having the bit patterns (000, 001, 010, 011, 100, 101, 110 and 111).
4. Performance Analysis of Proposed Full Adder Cell
The performance analysis of proposed full adder and existing [12,13,18] is depicted in Table 1. The comparison
parameters are the total delay incurred in the circuit, rise time (RT), fall time (FT), power dissipated, PDP (product of
delay and power), the total number of garbage output, critical path and quantumcost. It is observed that for the existing
[12,13,18] the delay, PDP and quantum cost are high. The quantum cost of the proposed MTGDI gates are calculated
using [7,8]. Quantumcost is the cost associated with designing reversible logic gate. It denotes number of 11 and 22
quantum logic gates used to design a reversible logic gate. NOT, controlled V, controlled V+ and CNOT(Feynman)
are basic quantum gates used to construct reversible logic gate. The quantum cost of proposed MTGDI gate1 is 5.
Elsevier Publications 2013. 33
R. Uma, et al.
Figure 3. Input/Output waveform of proposed full adder operating with clock frequency of 100 MHz.
Table 1. Performance analysis of proposed full adder with existing reversible full adders.
Figure 4. Quantum cost calculation for MTGDI gate1 and MTGDI gate2 using [7,8]
It requires 1 CNOT, 2 controlled V and 2 controlled V+ gates. Quantum cost of the proposed MTGDI gate2 is 1.
It needs 1 CNOT gate. The calculation of quantum cost of MTGDI gate1 and MTGDI gate2 is shown in gure 4.
From the performance evaluation it has been observed that the adder in [18] implemented with MKG gate exhibits
the maximum power dissipation of 1.72 mW. While the adder in [13,17] implemented with DKG and Toffoli-Feyman
has maximum quantum cost of 11. Maximum delay of 69.57ns has been observed for adder in [13] implemented with
TOFFOLI and FEYNMAN. The critical path delay is high for the reversible adder in [13]. From this analysis it has
34 Elsevier Publications 2013.
New Low-Power Reversible Logic Gates Using Gate Diffusion Input Technique
Table 2. Performance analysis of proposed full adder with existing reversible
full adders.
% Improvement % Improvement % Improvement
Reversible adder in power in PDP in quantum cost
Existing [13 ] 16.52 22.53 36.364
Existing[17] 54.55 54.608 36.364
Existing[18] 57.99 57.99 22.222
Figure 5. Performance comparison of reversible full adder in terms of power, PDP and quantum cost.
been noticed that for the proposed reversible adder using MTGDI gate1 and gate2 exhibits less delay, power, critical
path and quantum cost when compared to the existing reversible adders. But only deciency in the proposed adder is
the garbage output is slightly higher when compared to its counterpart.
5. Discussion
A new modied reversible logic cells (MTGDI) using Gate Diffusion Input Technique has been presented in section 2.
A new low-power and low quantum cost reversible full adder is proposed using proposed MTGDI gate1 and MTGDI
gate2. Its performances have been analyzed and reported in section 4. Table 2 presents the performance of proposed
reversible full adder and the existing counterpart in terms of percentage improvement in power, PDP and quantum
cost. Figure 5 shows the percentage graph of proposed and existing reversible full adder. From this it is elucidated that
the maximum percentage of improvement in power is 58% and minimum of 17%. While comparing the percentage
improvement for PDP the maximum improvement is 58% and minimum is 23%. Similarly for the quantum cost
maximum of 36% and minimum of 22% improvement are obtained for the proposed reversible full adder circuit.
6. Conclusion
A new modied reversible logic cells (MTGDI) using Gate Diffusion Input Technique has been presented. The
functionality realization and performances are reported in section 2 and 3. Using the proposed MTGDI cells a new
reversible full adder circuit has been implemented and its performance has been evaluated in terms of delay, power,
PDP, garbage output, critical path and quantum cost. From the performance evaluation it is observed that the proposed
full adder using MTGDI is superior in terms of delay, PDP, power and quantum cost with respect to its counterpart.
Nearly 58% of power, Maximum PDP with 58% and maximum cost of 36% are obtained for the proposed reversible
full adder circuit using MTGDI gates.
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