MAHATMA GANDHI UNIVERSITY

SCHEME AND SYLLABI

FOR
M. Tech. DEGREE PROGRAMME
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
WITH SPECIALIZATION IN
VLSI & EMBEDDED SYSTEM

(20! ADMISSION ONWARDS"
SCHEME AND SYLLABI FOR M. Tech. DEGREE PROGRAMME IN
ELECTRONICS AND COMMUNICATION ENGINEERING WITH
SPECIALIZATION IN VLSI & EMBEDDED SYSTEMS
SEMESTER # I
S$.
N%.
C%&'(e N%. S&)*ec+
H'( , Wee- E./$&/+0%1 Sche2e (M/'-("
C'e30+(
(C"
L T P
Se((0%1/$
ESE T%+/$
TA CT
S&)
T%+/$
1 MECVE 101
Semiconductor Devices Physics
& Modeling
3 1 0 25 25 50 100 150
2 MECVE 102 CM!S "n#log Design $% 3 1 0 25 25 50 100 150
3 MECVE 103 CM!S Digit#l Design $% 3 1 0 25 25 50 100 150
MECVE 10
Em&edded System '#rd(#re
"rchitecture $%
3 1 0 25 25 50 100 150
5 MECVE 105 Elective % 3 0 0 25 25 50 100 150 3
) MECVE 10) Elective %% 3 0 0 25 25 50 100 150 3
* MECVE 10* V+S% Design +#& 0 0 3 25 25 50 100 150 2
, MECVE 10, Semin#r % 0 0 2 25 25 50 0 50 1
T%+/$ 4 5 6 200 200 500 700 00 26
E$ec+0.e # I (MEC VE 06" E$ec+0.e # II (MEC VE 08"
MEC VE 105 $ 1 "dv#nced Digit#l Design MEC VE 10) $ 1 V+S% C"D
MEC VE 105 $ 2 V+S% Process -echnology MEC VE 10) $ 2 .#nom#teri#ls/ Structures #nd Devices
MEC VE 105 $ 3
System %denti0ic#tion #nd System
Simul#tion
MEC VE 10) $ 3 12 %C -echnology
MEC VE 105 $ Electronic System Design MEC VE 10) $ Modeling o0 Em&edded Systems
L +ecture/ T -utori#l/ P Pr#ctic#l
TA -e#cher3s "ssessment 4"ssignments/ #ttend#nce/ grou5 discussion/ 6ui7/ tutori#ls/ semin#rs/
etc89
CT Cl#ss -est 4Minimum o0 t(o tests to &e conducted &y the %nstitute9
ESE End Semester E:#min#tion to &e conducted &y the ;niversity
E$ec+0.e(9 .e( Electives m#y &e #dded &y the de5#rtment #ccording to the needs o0 emerging
0ields o0 technology8 -he n#me o0 the elective #nd its syll#&us should &e su&mitted to the ;niversity
&e0ore the course is o00ered8
2
MECVE 0
SEMICONDUCTOR DEVICE PHYSICS AND
MODELLING
L T P C
! 0 5
M%3&$e
Se20c%13&c+%'( F&13/2e1+/$(: M%(;e+ O.e'.0e< /13 MOS C/=/c0+%'9 Semiconductors9
%ntrinsic Semiconductors/ 2ree Electrons/ #nd 'oles/ E:trinsic Semiconductors/ E<uili&rium in
the "&sence o0 Electric 2ield/ E<uili&rium in the Presence o0 Electric 2ield/ .one<uili&rium=
6u#si$2ermi +evels/ 1el#tions &et(een Ch#rge Density/ Electric 2ield/ #nd Potenti#ls= Poisson>s
E<u#tion8 Conduction? -r#nsit -ime/ Dri0t/ Di00usion/ -ot#l Current8 Cont#ct Potenti#ls:
The pn >&1c+0%19 !vervie( o0 the M!S -r#nsistor9 @#sic Structure/ " 6u#lit#tive Descri5tion
o0 M!S -r#nsistor !5er#tion/ M!S -r#nsistor Ch#r#cteristics8 -he Mos C#5#citor? -he
2l#t&#nd Volt#ge/ Potenti#l @#l#nce #nd Ch#rge @#l#nce/ E00ect o0 A#te$@ody Volt#ge on
Sur0#ce Condition? 2l#t&#nd Condition/ "ccumul#tion/ De5letion/ "n#lysis/ %nversion? Aener#l
1el#tions #nd 1egions o0 %nversion/ Strong %nversion/ Be#C %nversion/ Moder#te %nversion
M%3&$e 2
The Th'ee?Te'201/$ M%( S+'&c+&'e9 Cont#cting the %nversion +#yer/ -he @ody E00ect/
1egions o0 %nversion? "55ro:im#te +imits/ Strong %nversion/ Be#C %nversion/ Moder#te
%nversion/ " "Vnullnull ControlD Point o0 Vie(9 2und#ment#ls/ -he DPincho00E Volt#ge
-he 2our$-ermin#l Mos -r#nsistor? -r#nsistor 1egions o0 !5er#tion/ Com5lete "ll$1egion
Model/ Sim5li0ied "ll$1egion Models? +ine#ri7ing the De5letion 1egion Ch#rge/ @ody$
1e0erenced Sim5li0ied "ll$1egion Models/ Source$1e0erenced Sim5li0ied "ll$1egion Models/
Ch#rge 2ormul#tion o0 Sim5li0ied "ll$1egion Models
M%3e$( B/(e3 %1 @&/(0?Fe'20 P%+e1+0/$(: ReA0%1( %; I1.e'(0%1 01 Te'2( %; Te'201/$
V%$+/Ae(9 Strong %nversion? Com5lete Strong$%nversion Model/ @ody$1e0erenced Sim5li0ied
Strong$%nversion Model/ Source$1e0erenced Sim5li0ied Strong$%nversion Model
Moder#te$%nversion #nd Single$Piece Models/ Source$1e0erenced vs8 @ody$1e0erenced
Modeling/ E00ective Mo&ility/ E00ect o0 E:trinsic Source #nd Dr#in Series 1esist#nces/
-em5er#ture E00ects/ @re#Cdo(n/ -he p-Ch#nnel M!S -r#nsistor/ Enh#ncement$Mode #nd
De5letion$Mode -r#nsistors/ Model P#r#meter V#lues/ Model "ccur#cy/ #nd Model
Com5#rison
M%3&$e !
S2/$$?Ch/11e$ A13 Th01 OB03e E;;ec+(? C#rrier Velocity S#tur#tion/ Ch#nnel +ength
Modul#tion/ Ch#rge Sh#ring? Short$Ch#nnel Devices/ .#rro($Ch#nnel Devices/ +imit#tions o0
3
Ch#rge$Sh#ring Models/ Dr#in$%nduced @#rrier +o(ering/ Punchthrough/ 'ot C#rrier E00ects=
%m5#ct %oni7#tion8 Sc#ling? Cl#ssic#l Sc#ling/ Modern Sc#ling
L/'Ae?S0A1/$ M%3e$01A O; The M%( T'/1(0(+%' I1 T'/1(0e1+ O=e'/+0%19 6u#si$St#tic
!5er#tion/ Ev#lu#tion o0 %ntrinsic Ch#rgers in 6u#si$St#tic !5er#tion? Strong %nversion/
Moder#te %nversion/ Be#C %nversion/ "ll$1egion Model/ De5letion #nd "ccumul#tion8-r#nsit
-ime under DC Conditions/ +imit#tions o0 the 6u#si$St#tic Model
.on$6u#si$St#tic Modeling? -he Continuity E<u#tion/ .on$6u#si$St#tic "n#lysis8 E:trinsic
P#r#sitics? E:trinsic C#5#cit#nces/ E:trinsic 1esist#nce/ -em5er#ture De5endence/ Sim5li0ied
Models
M%3&$e 5
S2/$$?S0A1/$ M%3e$01A F%' L%< A13 Me30&2 F'eC&e1c0e(9
+o($2re<uency Sm#ll$Sign#l Model 0or the %ntrinsic P#rt? Sm#ll$Sign#l Model 0or the Dr#in$
to$Source Current/ Sm#ll$Sign#l Model 0or the A#te #nd @ody Currents/ Com5lete +o($
2re<uency Sm#ll$Sign#l Model 0or the %ntrinsic P#rt/ Strong %nversion/ Be#C %nversion/
Moder#te %nversion/ "ll$1egion Models8 " Medium$2re<uency Sm#ll$Sign#l Model 0or the
%ntrinsic P#rt? %ntrinsic C#5#cit#nces8 %ncluding the E:trinsic P#rt
.oise? Bhite .oise/ 2licCer .oise/ .oise in E:trinsic 1esist#nces/ %ncluding .oise in Sm#ll$
Sign#l Circuits8 "ll$1egion Models
M%3e$01A F%' C0'c&0+ S02&$/+0%19 -y5es o0 Models: Models 0or Device "n#lysis #nd Design/
Device Models 0or Circuit Simul#tion/ "ttri&utes o0 Aood Com5#ct Models/ Model
2ormul#tion? Aener#l Consider#tion #nd Choices8 Common M!S2E- Models "v#il#&le in
Circuit Simul#tors? @S%M/ EFV/ PSP/ !ther Models
Re;e'e1ce(9
. G#nnis -sividis #nd Colin Mc"ndre( / H!5er#tion #nd Modeling o0 the M!S
-r#nsistorE/ 3Ie/ 2010/ !;P
2. -8 Gtterd#l/ G8 Cheng #nd -8 "8 2Jeldly / HDevice Modeling 0or "n#log #nd 12 CM!S
Circuit DesignE/ / Kohn Biley & Sons/ 2003
!. .#r#in "ror# / HM!S2E- Modeling 2or V+S% Simul#tion? -heory "nd Pr#cticeE/ /
Borld Scienti0ic/ 200*

MECVE 02
CMOS ANALOG IC I
L T P C
! 0 5
M%3&$e
B/(0c( %; MOSFET 2%3e$01A/ Current Mirrors $ Sim5le CM!S current mirror Sensitivity
#n#lysis $ -em5er#ture #n#lysis $-r#nsient res5onse $ C#scode current mirror $ Bilson current
mirror/ Volt#ge 1e0erences $ Volt#ge dividers $ Current Source Sel0$@i#sing $ "dv#nced volt#ge
re0erences $ &#nd$g#5 #nd &et# multi5lier re0erenced circuits
M%3&$e 2
Single st#ge #m5li0iers ? @#sic con0igur#tions9 common source $ common dr#in $ common g#te
circuits/ "ctive +o#ds/ C#scode #m5li0iers9 0olded c#scode #m5li0iers/ Push$Pull #m5li0iers:
CM!S Cl#ss "@ #m5li0iers
M%3&$e !
D0;;e'e1+0/$ /2=$0;0e'( ? Source cou5led 5#ir? current source lo#d CM11 M#tching
consider#tions/ Source cross cou5led 5#ir/ c#scode lo#ds: Bide s(ing di00erenti#l #m5li0iers?
Current di00erenti#l #m5li0ier const#nt tr#nsconduct#nce di00erenti#l #m5li0ier/ !ut5ut st#ges 9
source 0ollo(er #s #n out5ut st#ge/ CM!S Cl#ss "@ out5ut st#ges
M%3&$e 5
F'eC&e1cD 'e(=%1(e %; A2=$0;0e'( Aener#l Consider#tions # Miller e00ect "ssoci#tion o0
Poles (ith .odes/ Common source/ Source 0ollo(ers / Common g#te / C#scode st#ge/
Di00erenti#l P#ir8
N%0(e ? St#tistic#l Ch#r#cteristics o0 .oise $ .oise S5ectrum $ "m5litude Distri&ution $
Correl#ted #nd ;ncorrel#ted Sources/ -y5es o0 .oise ? -herm#l .oise $ 2licCer .oise shot
noise/ 1e5resent#tion o0 .oise in Circuits/ .oise in Single$St#ge "m5li0iers $ Common$Source
St#ge $ Common$A#te St#ge $ Source 2ollo(ers $ C#scode St#ge/ .oise in Di00erenti#l P#irs/
.oise @#nd(idth
Re;e'e1ce(9
18 18 K#co& @#Cer/ '#rry B +i/ D#vid E @oyce/ H CM!S Circuit Design/ +#yout/ #nd
Simul#tionE/3
rd
Edition/ 1LL,
28 @eh7#d 1#7#vi / HDesign o0 "n#log CM!S %ntegr#ted CircuitsE/ -#t# McAr#( 'ill
200,
5
38 Ar#y/ 'urst/ +e(is/ Meyer/ H"n#lysis #nd Design o0 "n#log %ntegr#ted CircuitsE/ 5
th
Edition/ Biely %ndi#/2010
8 Phili5 E "llen/ Dougl#s 1 'ol&erg/ HCM!S "n#log Circuit DesignE/ %ntern#tion#l
Student4Second9 Edition/ 2irst %ndi#n Edition 2010
C% 'eC&0(0+e 'e/301A9 M!S2E- modeling in strong inversion $ l#rge sign#l model/ lo($
0re<uency sm#ll$sign#l model/ high$0re<uency sm#ll$sign#l model/ &ody e00ect/ e00ect o0
v#ri#tions in the 0#&ric#tion 5rocess8
)
MECVE 0!
CMOS DIGITAL DESIGN I
L T P C
! 0 5
M%3&$e .
St#tic CM!S %nverter9 DC Ch#r#cteristics/ @et# 1#tio E00ects/ .oise M#rgin/ P#ss -r#nsistor
DC Ch#r#cteristics8 Del#y Models9 %ntroduction/ De0initions/ -iming !5timi7#tion/ -r#nsiet
1es5onse8
1C Del#y Model9 E00ective 1esist#nce/ A#te #nd Di00usion C#5#cit#nce/ E<uiv#lent 1C
Circuits/ -r#nsient 1es5onse/ Elmore Del#y/ +#yout De5endence o0 C#5cit#nce/ Determining
E00ective 1esist#nce8
+ine#r Del#y Model9 +ogic#l E00ort/ P#r#sistic Del#y/ Del#y in # +ogic A#te/ Drive/ E:tr#cting
+ogic#l E00ort 0rom D#t#sheets/ +imit#tions to the +ine#r Del#y Model8 +ogic#l E00ort o0
P#ths? Del#y in Multist#ge +ogic .et(orCs/ Choosing the @est .um&er o0 St#ges/ E:#m5le/
+imit#tions o0 +ogic#l E00ort/ %ter#tive Solutions 0or Si7ing8
M%3&$e 2.
%nterconnect e00ects #nd 5o(er #n#lysis9%ntroduction/ Bire Aeometry/ %ntel Met#l St#cCs
%nterconnect Modeling? 1esist#nce/ C#5#cit#nce/ %nduct#nce/ SCin E00ect/ -em5er#ture
De5endence8 %nterconnect %m5#ct? Del#y/ Energy/ Crosst#lC/ %nductive E00ects/ E00ective
1esist#nce #nd Elmore Del#y8 %nterconnect Engineering? Bidth/ S5#cing #nd +#yer/ 1e5e#ters/
Crosst#lC Control/ +o($S(ing Sign#ling/ 1egener#tors/ +ogic#l E00ort (ith Bires8
M%3&$e !.
S+/+0c /13 DD1/20c c0'c&0+(9 CM!S %nverter? trist#te inverter/ !ther st#tic CM!S logic g#tes/
st#tic 5ro5erties42 in5ut .".D/ .!19/ Com&in#tion#l logic circuits8 +#yout$e:#m5les8
2und#ment#ls o0 dyn#mic logic?/ Dyn#mic 5#ss tr#nsistor circuits/ CM!S circuits/ 'igh
5er0orm#nce dyn#mic circuits$Domino CM!S/ Multi !ut5ut Domino +ogic/ Du#l$r#il Domino
+ogic/ .P Domino logic4.!1"9/ -rue$Single$Ph#se$ClocC4-SPC9 CM!S logic/ Po(er
dissi5#tion in CM!S circuits8 @iCM!S logic g#tes/ st#tic &eh#vior/ s(itching del#y8 Silicon$
!n$%nsul#tor Circuit Design? 2lo#ting @ody Volt#ge/ S!% "dv#nt#ges/ Dis#dv#nt#ges
M%3&$e 5.
SD(+e2 3e(0A19 %ntroduction/ Structured Design methodology9 Conce5ts o0 'ier#rchy/
1egul#rity / Modul#rity/ +oc#lity e:5l#ined through # suit#&le c#se study 40or e:#m5le? "
So0t(#re 1#dio$" System E:#m5le9 %m5lement#tion methods 0or digit#l %Cs? 2ull custom/
Semi$custom/ cell &#sed #nd "rr#y &#sed methods8 Custom Design 0lo($System 5#rtitioning $
*
0loor 5l#nning 5l#cement glo&#l routing det#iled routing $ circuit e:tr#ction D1C +VS8
Design 0or m#nu0#ctur#&ility/ Design 0or -est#&ility.
Re;e'e1ce(9
18 Beste #nd '#rris/ H %ntegr#ted Circuit DesignE/ Ie/ 2011/ Pe#rson Educ#tion8
28 Sung$Mo F#ng/ Gusu0 +e&le&ici/ H CM!S Digit#l %ntegr#ted Circuits/ 3Ie/ -#t#
McAr#($'ill Educ#tion/ 20038
38 1#&#ey/ Ch#ndr#C#s#n #nd .iColic/ HDigit#l %ntegr#ted Circuits " Design
Pers5ectiveE/ 2Ie/ Pe#rson Educ#tion8
8 18 K#co& @#Cer/ '#rry B8 +i/ D#vid E8 @oyce: HCM!S/ Circuit Design/ +#yout/ #nd
Simul#tionE: 3Ie/ Biley %nterscience8
C%'eC&0(0+e 'e/301A9 MOS I1+'%3&c+0%1 /13 M%3e$(9 +ong$Ch#nnel %$V Ch#r#cteristics/ C$V
Ch#r#cteristics/ Sim5le M!S C#5#cit#nce Models/ Det#iled M!S A#te C#5#cit#nce Model/
Det#iled M!S Di00usion C#5#cit#nce Model
,
MECVE 05
EMBEDDED SYSTEM HARDWARE
ARCHITECTURE I
L T P C
! 0 5
M%3&$e
I1+'%3&c+0%1 +% E2)e33e3 SD(+e2( /13 E2)e33e3 h/'3</'e9 " system engineering
#55ro#ch to em&edded systems ? %ntroduction #nd de0inition o0 Em&edded Systems/ Em&edded
System Design/ %ntroduction #nd im5ort#nce o0 em&edded systems #rchitecture/ -he em&edded
systems Model8
@#sics o0 com5uter #rchitecture #nd &in#ry num&er systems8 %ntroduction to Em&edded
Systems$ "55lic#tion dom#in/ 2e#tures #nd Aener#l ch#r#cteristics o0 em&edded systems/
Micro5rocessor vs microcontroller/ 2igure o0 merits/ Cl#ssi0ic#tion o0 MC;s8 Em&edded
systems -he h#rd(#re 5oint o0 vie(? MC;/ memory/ lo( 5o(er design/ 5ullu5 #nd 5ull do(n
resistors 8 Sensors/ "DCs #nd #ctu#tors . Some e:#m5les o0 em&edded systems $ Mo&ile Phone/
"utomotive Electronics/ 1#dio 2re<uency %denti0ic#tion 412%D9 Bireless Sensor .et(orCs
4B%SE.E-9/ 1o&otics/ @iomedic#l "55lic#tions/ @r#in M#chine %nter0#ce etc
M%3&$e 2
E2)e33e3 H/'3</'e9 @uilding @locCs #nd the Em&edded @o#rd ? %m5ort#nce o0 re#ding #
Schem#tic/ M#Jor com5onents o0 #n em&edded &o#rd/ 2#ctors th#t #llo( #n em&edded device to
(orC/ -he Em&edded @o#rd #nd the von .eum#nn Model/ Po(ering the '#rd(#re8 E2)e33e3
P'%ce((%'( $ %S" "rchitecture Models / %ntern#l Processor / Processor Per0orm#nce$ @ench
m#rCs / 1e#ding # Processor3s D#t#sheet 4 E:#m5le 5rocessor$ MPC ,)09 P'%ce(%' De(0A1
c/(e (+&3D # " Sm#ll$Sc#le E:5eriment#l M#chine (SSEM) 0or e:#m5le/ the M;0 5rocessor
M%3&$e !
Me2%'0e(: Me2%'D 2/1/Ae2e1+ &B%/'3 Me2%'D
Memory Systems %ntroduction/ Memory S5#ces / C#che !vervie( /E:tern#l Memory/ Direct
Memory "ccess8 @o#rd Memory $ Memory M#n#gement o0 E:tern#l Memory/ @o#rd Memory
#nd Per0orm#nce8
M%3&$e 5
B%/'3 I,O & B%/'3 B&(e(
B%/'3 I,O (I1=&+,O&+=&+" $ M#n#ging D#t#= Seri#l vs8 P#r#llel %I!? Seri#l %I! E:#m5le$
.et(orCing #nd Communic#tions? 1S$232 & %EEE ,02811 Bireless +"./ P#r#llel %I!
e:#m5le?$ P#r#llel !ut5ut #nd Ar#5hics P#r#llel #nd Seri#l %I!? E:#m5le? .et(orCing #nd
communic#tionsMEthernet8 %nter0#cing the %I! Com5onents/ %I! 5er0orm#nce8 @o#rd @uses?
L
@us "r&itr#tion #nd -iming/ %ntegr#ting the @us (ith !ther @o#rd Com5onents/ @us
Per0orm#nce
Re;e'e1ce(9
18 -#mmy .oerg##rd/ HEm&edded Systems "rchitecture/ " Com5rehensive Auide 0or
Engineers #nd Progr#mmersE/ .e(ness/ Elseiver/ 2012
28 +yl# @ D#s / HEm&edded systems$"n integr#ted #55ro#chE/ Pe#rson Educ#tion/ 2013
38 Steve 2ur&er / H"1M System$on$chi5 #rchitectureE/ 2Ie/ Pe#rson Educ#tion
8 K#cC A#nssle/ -#mmy .oerg##rd/2red E#dy/+e(in Ed(#rds/D#vid K8 F#t7/ 1icCAentile/
Fen "rnold/ F#m#l 'yder/ @o& Perrin/ Creed 'uddleston/ HEm&edded '#rd(#re Fno(
%t #llE/ .e(ness/ Elseiver/ 200,
58 B#yne Bol0 / HCom5uters #s Com5onents$5rinci5les o0 Em&edded com5uter system
designE/ Elseveir/ 2005
)8 Fen "rnold/ HEm&edded Controller '#rd(#re DesignE/ ++' -echnology 5u&lishing/
2001
*8 Peter M#r(edel/ HEm&edded System DesignE/ S5ringer/ 200)
,8 2r#nC V#hid #nd -ony D8 Aiv#rgis/ HEm&edded System Design? " ;ni0ied '#rd(#re I
So0t(#re %ntroductionE/ 20008
L8 Kerr#y#/ "8 H+ong -erm -rends 0or Em&edded System Design8E
108 S8 E8 Deren7o/ HPr#ctic#l %nter0#cing in the +#&or#tory? ;sing # PC 0or %nstrument#tion/
D#t# "n#lysis #nd ControlE/ C#m&ridge/ 20038
118 E8 "8 +ee #nd S8 "8 Seshi# / H%ntroduction to Em&edded SystemsE/ 2011$2012
10
MECVE 06 ?
ADVANCED DIGITAL DESIGN
L T P C
! 0 0 !
M%3&$e ?
Com&in#tion#l +ogic? S(itching "lge&r#8 Com&in#tion#l$Circuit "n#lysis8 Com&in#tion#l$
Circuit Synthesis8 Progr#mmed Minimi7#tion Methods8 -iming '#7#rds/ Com&in#tion#l +ogic
Descri5tion ;sing '#rd(#re Descri5tion +#ngu#ges8 Se<uenti#l +ogic Design? +#tches/ 0li5
0lo5s/ timing/ #nd glitches/ 2inite St#te M#chines? #n#lysis/ 2inite St#te M#chines? design$St#te
di#gr#ms #nd "SM ch#rts/ -r#nsistion +ists8 Decom5osing St#te M#chines8 2eed&#cC
Se<uenti#l Circuits8 2eed&#cC Se<uenti#l$Circuit Design8 Se<uenti#l +ogic Descri5tion ;sing
'#rd(#re Descri5tion +#ngu#ges
M%3&$e 2?
Com&in#tion#l #nd Se<uenti#l$Circuit Document#tion St#nd#rds8 D#t#5#th Design? D#t#5#th
Com5onents? 1egisters/ "dder/ Com5#r#tors/ Multi5lierM"rr#y$Style/ Su&tr#ctors #nd Signed
.um&er/ "rithmetic$+ogic ;nitsM"+;s/ Shi0ters/ Counters #nd -imers/ 1egister 2iles8
D#t#5#th Com5onent Descri5tion ;sing '#rd(#re Descri5tion +#ngu#ges8 Synchronous Design
Methodology: %ter#tive versus Se<uenti#l Circuits %m5ediments to Synchronous Design8
Synchroni7er 2#ilure #nd Met#st#&ility8 Controller Design #nd%m5lement#tion? 1#ndom +ogic/
-ime St#te 4Divide #nd Con<uer9/ Kum5 Counter/ @r#nch Se<uencers/ Micro5rogr#mming/
Control 5#r#llelism/ 5i5elining
M%3&$e !?
1egister$-r#ns0er +evel 41-+9 Design? 'igh$+evel St#te M#chine/ 1-+ Design Process/
Determining ClocC 2re<uency/ @eh#vior#l$+evel Design? C to A#tes/ Memory Com5onents/
6ueues 42%2!s/ Multi5le Processors/ 'ier#rchyM" Fey Design Conce5t8 1-+ Design ;sing
'#rd(#re Descri5tion +#ngu#ges8
M%3&$e 5
!5timi7#tions #nd -r#deo00s? Com&in#tion#l +ogic !5timi7#tions #nd -r#deo00s/ Se<uenti#l
+ogic !5timi7#tions #nd -r#deo00s/ D#t# 5#th Com5onent -r#deo00s/ 1-+ Design
!5timi7#tions #nd -r#deo00s/ -r#deo00s in Design? " c#se study 40or e:#m5le Digit#l Video
Pl#yerI1ecorder89
Re;e'e1ce(9
18 2r#nC V#hid / HDigit#l Design (ith 1-+ Design/ V'D+ #nd VerilogE/ 2Ie/ Biley/ 2010
11
28 '#rris & '#rris/ HDigit#l Design #nd Com5uter "rchitectureE/ 2Ie/ Morg#n
F#u0m#nn/ 2012
38 Kohn 28 B#Cerly : HDigit#l Design Princi5les #nd Pr#cticesE/ Ie/ Prentice '#ll/ 2005
8 Billi#m K#mes D#lly / 18 Curtis '#rting/ HDigit#l Design? " Systems "55ro#chE/
C#m&ridge ;niversity Press/ 2012
58 1#ndy '8 F#t7 #nd A#et#no @orriello : HContem5or#ry +ogic DesignE/ 2IE/ Prentice
'#ll %ndi#/ 200L
12
MECVE 06 ? 2
VLSI PROCESS TECHNOLOGY
L T P C
! 0 0 !
M%3&$e
!vervie( "nd M#teri#ls? "n %ntroduction to Microelectronic 2#&ric#tion/ Moore3s +#(/ %-1S8
Semiconductor Su&str#tes8 'ot Processing? Di00usion? Do5#nt di00usivities/ ch#nneling/ 2icC>s
1st #nd 2nd l#( o0 di00usion/ di00erent do5#nt 5ro0ile study/ Electric 0ield e00ects/ Segreg#tion/
microsco5ic model/ v#c#ncy #nd interstiti#l de5endence8 -herm#l !:id#tion? -y5es o0 o:ides/
0urn#ce design/ De#l Arove Model (et #nd dry o:id#tion/ thin o:ide gro(th 4devi#tion 0rom
De#l Arove9/ 1#5id -herm#l !:id#tion8
M%3&$e 2
De5osition #nd Aro(th? Physic#l De5osition? Ev#5or#tion #nd S5uttering? DC/ 12/ 5l#sm#/
Chemic#l V#5or De5osition/ E5it#:i#l Aro(th? M@E/ Aro(th Finetics? "+D/ M!CVD/
+PCVD/ "PCVD/ PECVD etc8%on %m5l#nt#tion? %m5l#nt#tion Modeling/ Electronic #nd nucle#r
sto55ing/ Ch#nneling/ D#m#ge "nne#ling/ -r#nsient enh#nced diusion 4-ED9
M%3&$e !
P#ttern -r#ns0er? !5tic#l +ithogr#5hy/ .on o5tic#l +ithogr#5hic -echni<ues/ Photoresists/
E:5osure? Systems? o5tics/ #dv#nced lithogr#5hy techni<ues/ E:5osure Develo5ment/
Enh#ncement techni<ues? 5ro:imity correction/ 5h#se shi0t m#sCs8 Etching? %sotro5ic I
#nisotro5ic/ selectivity/ Bet #nd dry etch8 1e#ctive ion etching 41%E9/ Chemic#l$mech#nic#l
5olishing 4CMP9
M%3&$e 5
Process %ntegr#tion? Device %sol#tion/ Cont#cts/ #nd Met#lli7#tion8 CM!S -echni<ues/ A#"s
-echnologies/ Silicon @i5ol#r -echnologies/ MEMS8
Re;e'e1ce(9
. -he Science #nd Engineering o0 Microelectronic 2#&ric#tion/ S8"8 C#m5&ell/ 2Ie/ !;P/
%ndi#/ 20128
2. K8D8 Plummer/ M8D8 De#l/ P8A8 Ari00in/ Silicon V+S% -echnology/ Pe#rson Educ#tion/
2001
!. S8F8 Ah#ndhi/ V+S% 2#&ric#tion Princi5les Silicon #nd A#llium "rsenide/ Kohn Biley
#nd Sons
MECVE 06 ? !
SYSTEM IDENTIFICATION AND SYSTEM
SIMULATION
L T P C
! 0 0 !
13
M%3&$e
I1+'%3&c+0%1? Systems #nd Models/ -erminology/ @#sic Pro&lems/ M#them#tic#l Models
Pro5erties/ Structur#l Model 1e5resent#tions/ System %dentiNc#tion Procedure/ -ime %nv#ri#nt
+ine#r Systems/ Simul#tion #nd Prediction/ Models o0 +ine#r -ime %nv#ri#nt Systems/ Models
0or -ime v#rying #nd .online#r Systems8
Re.0e< %; SD(+e2 Re(=%1(e Me+h%3(?
T02e D%2/019 %m5ulse 1es5onse Model 1e5resent#tion/ -r#ns0er 2unction Model
1e5resent#tion/ Direct %m5ulse 1es5onse %dentiNc#tion/ Direct Ste5 1es5onse %dentiNc#tion/
%m5ulse 1es5onse %dentiNc#tion ;sing Ste5 1es5onses/ 2re<uency -r#ns0er 2unction/ Sine$
(#ve 1es5onse %dentiNc#tion8
F'eC&e1cD Re(=%1(e Me+h%3(? Em5iric#l -r#ns0er$0unction %dentiNc#tion/ Em5iric#l -r#ns0er$
0unction Estim#te/ Critic#l Point %dentiNc#tion/ %m5ulse 1es5onse %dentiNc#tion ;sing %n5ut
out5ut D#t#/ Discrete$time Delt# !5er#tor8
M%3&$e 2
T02e?01./'0/1+ SD(+e2 I3e1+0Fc/+0%1 I9
S+/+0c SD(+e2 I3e1+0Fc/+0%1: +ine#r St#tic Systems? +ine#r 1egression/ +e#st$s<u#res
Estim#tion/ %nter5ret#tion o0 +e#st$s<u#res Method/ @i#s/ "ccur#cy / %dentiN#&ility8
.online#r St#tic Systems? .online#r 1egression/ .online#r +e#st$s<u#res Estim#tion/ %ter#tive
Solutions/ "ccur#cy/ Model 1e5#r#meteri7#tion? St#tic C#se/ M#:imum +iCelihood Estim#tion8
C#se Studies 0or Electric#l #nd Electronic Systems8
M%3&$e !
T02e?01./'0/1+ SD(+e2 I3e1+0Fc/+0%1 II9
DD1/20c SD(+e2 I3e1+0Fc/+0%1? +ine#r Dyn#mic Systems? -r#ns0er 2unction Models/
E<u#tion Error %dentiNc#tion/ !ut5ut Error %dentiNc#tion/ Prediction Error %dentiNc#tion / Model
Structure %dentiNc#tion/ Su&s5#ce %dentiNc#tion/ +ine#r P#r#meter$v#rying Model
%dentiNc#tion/ !rthogon#l @#sis 2unctions8 C#se Studies 0or Electric#l #nd Electronic Systems8
M%3&$e 5
S02&$/+0%1 %; S+/+0c /13 DD1/20c SD(+e2(9
Pro&#&ility Models? %ntroduction to Pro&#&ility Models/ Discrete Pro&#&ility Models/
Continuous Pro&#&ility Models/ Stoch#stic Models? M#rCov Ch#ins/ M#rCov Processes/ +ine#r
1egression/ -ime Series8 Simul#tion o0 Dyn#mic Models? %ntroduction to Simul#tion/
1
Continuous$-ime Models/ -he Euler Method8 Simul#tion o0 Pro&#&ility Models? Monte C#rlo
Simul#tion/ -he M#rCov Pro5erty/ "n#lytic Simul#tion8
Re;e'e1ce(9
1. G/'e$ >. Gee(2/1 / HSD(+e2 I3e1+0;0c/+0%1? A1 I1+'%3&c+0%1E: S5ringer/ 2011
28 M#rC M8 Meersch#ert / HM#them#tic#l ModelingE/ "c#demic Press/ 2013
38 +enn#rt +Jung / HSystem %denti0ic#tion? -heory 0or the ;serE/ / 2Ie/ Pe#rson Educ#tion/
1LL,
8 1iC Pintelon / Koh#n SchouCens/ HSystem %denti0ic#tion? " 2re<uency Dom#in
"55ro#chE/ Kohn Biley & Sons/ 200
58 KOn MiCleP / Mirosl#v 2iC#r/ HProcess Modelling/ %denti0ic#tion/ #nd ControlE/ S5ringer/
200*
15
MECVE 06 ? 5
ELECTRONIC SYSTEM DESIGN
L T P C
! 0 0 !
M%3&$e
P'%3&c+ De(0A1 /13 De.e$%=2e1+
Em&edded System 5roduct Develo5ment +i0e cycle 4ED+C9/ !&Jectives o0 ED+C/ Ph#ses o0
ED+C/ modeling the ED+C/ Com5onent selection/ Schem#tic Design/ PC@ l#yout/ 0#&ric#tion
#nd #ssem&ly8 Product enclosure Design #nd Develo5ment8 Po(er su55ly Design8
Em&edded System Develo5ment Environment %DE/ Cross com5il#tion/ Simul#torsIEmul#tors/
'#rd(#re De&ugging8 '#rd(#re testing methods liCe @ound#ry Sc#n/ %n Circuit -esting 4%C-9
etc8
M%3&$e 2
E$ec+'%2/A1e+0c C%2=/+0)0$0+D (EMC"9
Designing 0or EMC/ EMC regul#tions/ ty5ic#l noise 5#th/ methods o0 noise cou5ling/ methods
o0 reducing inter0erence in electronic system8
C/)$01A %; E$ec+'%10c SD(+e2($C#5#citive cou5ling/ e00ect o0 shield on c#5#citive cou5ling/
inductive cou5ling/ e00ect o0 shield on inductive cou5ling/ e00ect o0 shield on m#gnetic cou5ling/
m#gnetic cou5ling &et(een shield #nd inner conductor/ shielding to 5revent m#gnetic r#di#tion/
shielding # rece5tor #g#inst m#gnetic 0ields/ %nductive cou5ling$shielding 5ro5erties o0 v#rious
c#&le con0igur#tions/ co#:i#l c#&le versus shielded t(isted 5#ir/ &r#ided shields/ ri&&on c#&les8
M%3&$e !
G'%&1301A /13 Sh0e$301A
S#0ety grounds/ sign#l grounds/ single$5oint #nd multi5oint$5oint ground systems/ hy&rid
grounds/ 0unction#l ground l#yout/ 5r#ctic#l lo( 0re<uency grounding/ h#rd(#re grounds/
grounding o0 c#&le shields/ ground loo5s/ Common Mode ChoCe $ shield grounding #t high
0re<uencies/ gu#rded instruments8
.e#r 0ields #nd 0#r 0ields/ ch#r#cteristic #nd (#ve im5ed#nces/ shielding e00ectiveness/
#&sor5tion #nd re0lection loss/ shielding (ith m#gnetic m#teri#l/ #5ertures/ conductive g#sCets/
conductive (indo(s/ conductive co#ting/ grounding o0 shields
M%3&$e 5
C%13&c+e3 E20((0%1(? 5o(er line %m5ed#nce$S(itched Mode Po(er su55lies$ Po(er line
2ilters$ 5o(er su55ly %nst#&ility$M#gnetic 0ield Emissions
1)
SD(+e2 De(0A1 ;%' EMC PC@ l#yout #nd st#cC u5$ Aener#l Printed Circuit @o#rd Design
consider#tions PC@ ch#ssis #nd Around connection/ 1eturn P#th Discontinuities$ PC@ l#yer
St#cC u5
E$ec+'%(+/+0c D0(ch/'Ae (ESD" ? St#tic gener#tion/ hum#n &ody model/ st#tic disch#rge/ ESD
5rotection in e<ui5ment design/ -r#nsient #nd Surge Protection Devices/ so0t(#re #nd ESD
5rotection/ ESD versus EMC/ ESD -esting
Re;e'e1ce(9
18 Shi&u F8V / H%ntroduction to Em&edded SystemsE/ -#t# McAr#( 'ill/ 200L
28 'enry B8!tt/ HElectrom#gnetic Com5#ti&ility EngineeringE: Biley %nterscience/200L
38 'enry B8!tt/ H.oise 1eduction -echni<ues in Electronic SystemsE/ 2Ie/ Biley
%nterscience8
8 Cl#yton 18P#ul / H%ntroduction to Electrom#gnetic Com5#ti&ilityE/ 2Ie
58 Soni# @en Dhi# / Moh#med 1#md#ni/ Etienne Sic#rd/ HElectrom#gnetic Com5#ti&ility
o0 %ntegr#ted Circuits -echni<ues 0or lo( emission #nd susce5ti&ilityE/ S5ringer/ 200)
)8 D#vid Morg#n/ H" '#nd&ooC 0or EMC -esting #nd Me#surementE/ 1Ie/ %E- Electric#l
Me#surement Series ,/
1*
MECVE 08 ?
VLSI CAD
L T P C
! 0 0 !
M%3&$e
%ntroduction to V+S% Physic#l Design?Physic#l Design "utom#tion/ V+S% Design Cycle/ .e(
-rends in V+S% Design Cycles/ Design Styles8 V+S% Physic#l Design "utom#tion? Physic#l
Design/ Physic#l Design Cycle/ V+S% Design "utom#tion8
+#yout Com5#ction? Design 1ules/ Sym&olic +#yout/ Pro&lem 2ormul#tion? "55lic#tions o0
Com5#ction/ %n0orm#l Pro&lem 2ormul#tion/ Ar#5h$theoretic#l 2ormul#tion/ M#:imum$dist#nce
Constr#ints8 "lgorithms 0or Constr#int$gr#5h Com5#ction? " +ongest$5#th "lgorithm 0or
D"As/ -he +ongest P#th in Ar#5hs (ith Cycles/ -he @ellm#n$2ord "lgorithm / Discussion?
Shortest P#ths/ +ongest P#ths #nd -ime Com5le:ity
M%3&$e 2
Pl#cement #nd P#rtitioning? Circuit 1e5resent#tion/ Bire$length Estim#tion/ -y5es o0 Pl#cement
Pro&lem/ Pl#cement #t V#rious levels/ Design$Style S5eci0ic Pl#cement/ Pl#cement "lgorithms?
Constructive Pl#cement/ %ter#tive %m5rovement8 P#rtitioning? Circuit P#rtitioning/ 'ier#rchic#l
P#rtitioning/ P#rtition +evels/ Pro&lem 2ormul#tion/ Cl#ssi0ic#tion o0 P#rtitioning "lgorithms
-he Fernigh#n$+in P#rtitioning "lgorithm
M%3&$e !
2loor5l#nning? 2loor5l#nning Conce5ts/ -erminology #nd 2loor5l#n 1e5resent#tion/
'ier#rchic#l Design/ De#ds5#ces/ Design$Style S5eci0ic 2loor5l#nning !5timi7#tion Pro&lems
in 2loor5l#nning/ Slicing #nd .on$Slicing 2loor5l#ns Sh#5e 2unctions #nd 2loor5l#n Si7ing
M%3&$e 5
1outing? -y5es o0 +oc#l 1outing Pro&lems/ "re# 1outing/ Ch#nnel 1outing? Ch#nnel 1outing
Models/ -he Vertic#l Constr#int Ar#5h/ 'ori7ont#l Constr#ints #nd the +e0t$edge "lgorithm/
Ch#nnel 1outing "lgorithms8 Alo&#l 1outing? St#nd#rd$cell +#yout/ @uilding$&locC +#yout #nd
Ch#nnel !rdering/ "lgorithms 0or Alo&#l 1outing? -#:onomy o0 V+S% 1outers/ Design$Style
S5eci0ic 1outing
Re;e'e1ce9
. Aere7/ H"lgorithms 0or V+S% Design "utom#tionE/ Kohn Biley & Sons/ 200)
2. .8 Sher(#ni/ H"lgorithms 0or V+S% Physic#l Design "utom#tionE/ Flu(er "c#demic
Pu&lishers/ 1LLL8
1,
!. S#di< M8 S#it #nd '8 Gousse0/ HV+S% Physic#l Design "utom#tion? -heory #nd
Pr#cticeE/ Borld Scienti0ic/ 1LLL8
5. Ch#rles K8 "l5ert= Dinesh P8 Meht#= S#chin S/ H'#nd&ooC o0 "lgorithms 0or Physic#l
Design "utom#tionE/ S#5#tneC#r "uer&#ch Pu&lic#tions/ 200,
1L
MECVE 08 ? 2
NANOMATERIALS:STRUCTURES AND DEVICES
L T P C
! 0 0 !
M%3&$e
De0inition o0 -echnology node8 M!S Sc#ling theory/ %ssues in sc#ling M!S tr#nsistors ? Short
ch#nnel e00ects/ Descri5tion o0 # ty5ic#l CM!S technology8
1e<uirements 0or .on cl#ssic#l M!S tr#nsistor8 M!S c#5#citor/ 1ole o0 inter0#ce <u#lity #nd
rel#ted 5rocess techni<ues/ A#te o:ide thicCness sc#ling trend/ Si!2 vs 'igh$C g#te dielectrics8
%ntegr#tion issues o0 high$C8 %nter0#ce st#tes/ &ulC ch#rge/ &#nd o00set/ st#&ility/ reli#&ility
6@D high 0ield/ 5ossi&le c#ndid#tes/ CV #nd %V techni<ues8
M%3&$e 2
Met#l g#te tr#nsistor ? Motiv#tion/ re<uirements/ %ntegr#tion %ssues8 -r#ns5ort in .#no
M!S2E-/ velocity s#tur#tion/ &#llistic tr#ns5ort/ inJection velocity/ velocity overshoot8 S!% $
PDS!% #nd 2DS!%8 ;ltr#thin &ody S!% $ dou&le g#te tr#nsistors/ integr#tion issues8 Vertic#l
tr#nsistors $ 2in2E- #nd Surround g#te 2E-
M%3&$e !
Met#l sourceIdr#in Junctions $ Pro5erties o0 schotCy Junctions on Silicon/ Aerm#nium #nd
com5ound semiconductors $BorC0unction 5inning8 Aerm#nium .#no M!S2E-s ? str#in /
<u#nti7#tion / "dv#nt#ges o0 Aerm#nium over Silicon / PM!S versus .M!S8
Com5ound semiconductors $ m#teri#l 5ro5erties/ MES2E-s Com5ound semicocnductors
M!S2E-s in the conte:t o0 ch#nnel <u#nti7#tion #nd str#in / 'etero structure M!S2E-s
e:5loiting novel m#teri#ls/ str#in/ <u#nti7#tion8
M%3&$e 5
Synthesis o0 .#nom#teri#ls ? CVD/ .ucle#tion #nd Aro(th/ "+D/ E5it#:y/ M@E
Ch#r#cteri7#tion techni<ues 0or n#nom#teri#ls? 2-%1/ Q1D/ "2M/ SEM/ -EM/ ED"Q etc
Emerging n#no m#teri#ls ? .#notu&es/ n#norods #nd other n#no structures/ +@ techni<ue/ So0t
lithogr#5hy etc8 Micro(#ve #ssisted synthesis/ Sel0 #ssem&ly etc8
Re;e'e1ce(9
18 G8 -#ur #nd -8 .ing / H2und#ment#ls o0 Modern V+S% DevicesE/ C#m&ridge ;niversity
Press8
28 Plummer/ De#l/ Ari00in / HSilicon V+S% -echnologyE/ Pe#rson Educ#tion %ndi#8
38 @rundle/ C81ich#rd= Ev#ns/ Ch#rles "8 Kr8= Bilson/ Sh#un/ H Encyclo5edi# o0 M#teri#ls
Ch#r#cteri7#tionE/ Elsevier8
20
8 D#niel 1#tner / H.#notechnology? " Aentle %ntroduction -o -he .e:t @ig %de#E/
Pe#rson Educ#tion %ndi#/ 2003
21
MECVE 08 ? !
RF IC TECHNOLOGY
L T P C
! 0 0 !
M%3&$e 9 E$e2e1+( %; M0c'%</.e I1+eA'/+e3 C0'c&0+( (MIC"
%ntroduction to Pl#n#r -r#nsmission +ine/ V#rious ty5es o0 5l#n#r tr#nsmission lines8 "n#lysis
o0 Microstri5 +ines? Method o0 Con0orm#l -r#ns0orm#tion/ V#ri#tion#l method/ .umeric#l
#n#lysis8 +osses in microstri5 lines/ %ntroduction to Slotline #nd Cou5led lines8
M%3&$e 29 MIC P/((0.e C%2=%1e1+( 9
%ntroduction/ %nductors/ resistors/ c#5#citors/ Vi# holes #nd grounding/ Microstri5 Com5onents/
Co5l#n#r circuits/ Multi +#yer techni<ues/ Micro m#chined 5#ssive com5onents8
M%3&$e !9 M0c'%</.e I1+eA'/+e3 C0'c&0+?;/)'0c/+0%1 +ech1%$%AD
S#lient 2e#tures o0 M%Cs/ Ch#r#cteristics #nd Pro5erties o0 Su&str#te/ Conductor/ Dielectric #nd
1esistive M#teri#ls/ MM%C 2#&ric#tion -echni<ues/ Di00usion #nd %on %m5l#nt#tion/ !:id#tion
#nd 2ilm De5osition/ E5it#:i#l Aro(th/ +ithogr#5hy/ Etching #nd Photo 1esist/ De5osition
Methods/ Ste5s %nvolved in the 2#&ric#tion o0 M!S2E-
M%3&$e 59 RF IC De(0A1 F$%<
System Design #nd @eh#vior#l Modelling/ Schem#tic Entry #nd Design Environment/ -ime #nd
2re<uency Dom#in Circuit Simul#tion/ +#yout/ Electrom#gnetic E:tr#ction/ P#r#sitic
E:tr#ction/ D1C #nd +VS/ Veri0ic#tion in System @ench8
12%C +#yout/ 12%C P#cC#ging #nd System %ntegr#tion/ System Design Consider#tions?
P#cC#ging/ Po(er/ 'e#t Dissi5#tion/ P#r#meter -r#deo00s8
Re;e'e1ce(9
18 2r#nC Ellinger/ H1#dio 2re<uency %ntegr#ted Circuits #nd -echnologiesE/ S5ringer/ 200*8
28 Au5t# F8 C8 & "m#rJit Singh/ HMicro(#ve %ntegr#ted CircuitsD Kohn Biley & Sons/ 1L*58
38 'o00m#n 18 F8/ H'#nd&ooC o0 Micro(#ve %ntegr#ted CircuitsE/ "rtech 'ouse Pu&lishers/
1L,*8
8 %8D 1o&ertson/C 8+ucys7yn8/ H 12%C #nd MM%C Design #nd -echnologyE/ -he %nstitution
o0 Engineering #nd -echnology/20018
58 +eo A8 M#lor#tsCy/ HP#ssive 12 & Micro(#ve %ntegr#ted CircuitsE/ Elsevier/ 2008
22
)8 Kose5h K8 C#rr/ H12 Com5onents #nd CircuitsE/ .e(nes/ 20028
*8 %nder K @#hl/ H+um5ed Elements 0or 12 #nd Micro(#ve CircuitsE/ "rtech 'ouse/ 20038
MECVE 08 ? 5
MODELLING OF EMBEDDED SYSTEMS
L T P C
! 0 0 !
M%3&$e
I1+'%3&c+0%1: SD(+e2 De(0A1 Me+h%3%$%A0e( & M%3e$(9 $ System$Design Ch#llenges
"&str#ction +evels /System Design Methodology/ System$+evel Models Pl#t0orm Design
System Design -ools8 System Design Methodologies$ @ottom$u5 Methodology/-o5$do(n
Methodology/ Meet$in$the$middle Methodology Pl#t0orm Methodology 2ield Progr#mm#&le
A#te "rr#y4 2PA"9 Methodology System$level Synthesis Processor Synthesis8 Models$Models
o0 Com5ut#tion/ System Design +#ngu#ges/ System Modeling/ Processor Modeling/
Communic#tion Modeling/ System Models
M%3&$e 2
SD(+e2 SD1+he(0(?$System Design -rends/ -r#ns#ction +evel Model4-+M9 @#sed Design/
"utom#tic -+M Aener#tion/ "utom#tic M#55ing Pl#t0orm Synthesis/ So0t(#re synthesis?
Prelimin#ries/ So0t(#re Synthesis !vervie(/ Code Aener#tion/ Multi$-#sC Synthesis/ %ntern#l
Communic#tion/ E:tern#l Communic#tion/ St#rtu5 Code/ @in#ry %m#ge Aener#tion E:ecution
M%3&$e !
H/'3</'e (D1+he(0(9$ 1egister -r#ns0er +ogic41-+9 "rchitecture/ %n5ut Models Estim#tion
#nd !5timi7#tion/ 1egister Sh#ring/ 2unction#l ;nit Sh#ring/ Connection Sh#ring/ 1egister
Merging/ Ch#ining #nd Multi$Cycling/ 2unction#l$;nit Pi5elining/ D#t#5#th Pi5elining/
Control #nd D#t#5#th Pi5elining/ Scheduling %nter0#ce Synthesis
M%3&$e 5
Ve'0;0c/+0%19$ Simul#tion @#sed Methods/ 2orm#l Veri0ic#tion Methods/ Com5#r#tive
"n#lysis o0 Veri0ic#tion Methods/ System +evel Veri0ic#tion 8 Em&edded Design Pr#ctise
?System +evel Design -ools/ Em&edded So0t(#re Design -ools/ '#rd(#re Design -ools/ C#se
Study
Re;e'e1ce(
18 D#niel D8 A#JsCi / S#m#r "&di "ndre#s #nd Aerstl#uer Aun#r Schirner / HEm&edded
System Design Modeling/ Synthesis & Veri0ic#tionE/ S5ringer/ 200L
23
28 "8 K#ntsch/ Morg#n / HModeling Em&edded Systems #nd SoCs $ Concurrency #nd
-ime in Models o0 Com5ut#tionE/ F#u0m#nn/ 20038
38 Aom## / HSo0t(#re Design Methods 0or Concurrent #nd 1e#l$time SystemsE/
"ddison$Besley/ 1LL3
8 -he Disci5line o0 Em&edded System Design/ 'en7inger/ -8/ Si0#Cis/ K/
58 Em&edded System Design? " ;ni0ied '#rd(#reISo0t(#re %ntroduction/ 2r#nC V#hid
#nd -ony D8 Aiv#rgis/ / 2000
)8 Com5uters #s Com5onents$5rinci5les o0 Em&edded com5uter system design/ B#yne
Bol0 / Elseveir/ 2005
*8 Discrete$Event System Simul#tion/ K8 @#nCs/ K8 S8 C#rson %%/ @8 +8 .elson/ #nd D8 M8
.icol/ Prentice$'#ll/ 20018
2
MECVE 07
VLSI DESIGN LAB
L T P C
0 0 ! 2
VLSI
"n#logIDigit#l @#sed E:5eriments using #55ro5ri#te Simul#tion -ool 4su& micron technology9
I. P/'+ A (A1/$%A VLSI De(0A1"
M!S2E- Device Ch#r#cteri7#tion 0or Sm#ll Sign#l Device P#r#meters #nd P#r#sitics
Design 4Schem#tic #nd +#yout9/ Simul#tion #nd Ch#r#cteri7#tion o0 the 0ollo(ing "n#log
Circuits
Current Mirrors
Volt#ge 1e0erence
Single St#ge #m5li0ier con0igur#tions
18 CS
28 CA
38 CD
Di00erenti#l "m5li0ier
I. P/'+ B (D0A0+/$ VLSI De(0A1"
Design 4Schem#tic #nd +#yout9/ Simul#tion #nd Ch#r#cteri7#tion o0 the 0ollo(ing CM!S +ogic
Circuits
@#sic A#tes 4using CM!S/ Domino CM!S logics9
18 %nverter
28 .".D
38 .!1
"dders 4'#l0 #dder/ 2ull #dder9
2li5$2lo5 4M#ster$ Sl#ve9
Com&in#tion#l com5onents 4 Encoders/ Decoders & Multi5le:ers9
Bith the 0ollo(ing re<uirements ?
CM!S %nverter 0or S5eci0ied Drive Strength/ S(itching Potenti#l #nd Per0orm#nce
CM!S @u00er 0or S5eci0ied Drive Strength/ S(itching Potenti#l #nd Per0orm#nce
CM!S .".D2 #nd .".D3 g#tes 0or s5eci0ied drive strengths
CM!S .!12 #nd .!13 g#tes 0or s5eci0ied drive strengths
CM!S "!%221 g#te 42R 4"8@ S C8D9>9 0or s5eci0ied drive strengths
CM!S !"%221 g#te 42R T4"S@984CSD9U> 0or s5eci0ied drive strengths
II. E2)e33e3 EB=e'02e1+(
25
II. P/'+ A # HDL B/(e3 eB=e'02e1+( ( A$$ eB=e'02e1+( +% )e 3%1e /+ RTL $e.e$"
Digit#l Com5onents inside # micro5rocessor #nd integr#tion o0 these com5onents
#9 Shi0ters
&9 St#te m#chine &#sed controllers
c9 %nstruction decoder
d9 "+;
II. P/'+ B # E2)e33e3 P'%ce((%' ,C%1+'%$$e' )/(e3 eB=e'02e1+( +% )e 3%1e %1 / 8,!2
)0+ P'%ce((%',C%1+'%$$e' )/(e3 )%/'3(
#9 Memory inter0#cing &#sed e:5eriments
&9 Peri5her#l %nter0#cing &#sed e:5eriments 4seri#lI5#r#llel 5ort &#sed9
c9 @us #r&itr#tion &#sed e:5eriments
EB/2 3&'/+0%1 %; ! h'( (h%&$3 )e (=$0+ 01+% +<% ($%+( %; .6 h%&'( e/ch
S$%+ # A1/$%A,D0A0+/$ VLSI 3e(0A1 )/(e3 C&e(+0%1( (/( =e' +he (D$$/)&( /)%.e"
S$%+ 2 # E2)e33e3 )/(e3 C&e(+0%1( (/ =e' +he (D$$/)&( /)%.e"
MECVE 04
SEMINAR? I
L T P C
0 0 2
2)
E#ch student sh#ll 5resent # semin#r on #ny to5ic o0 interest rel#ted to the core I elective courses
o00ered in the 0irst semester o0 the M8 -ech8 Progr#mme8 'e I she sh#ll select the to5ic &#sed on
the re0erences 0rom intern#tion#l Journ#ls o0 re5ute/ 5re0er#&ly %EEE Journ#ls8 -hey should get
the 5#5er #55roved &y the Progr#mme Co$ordin#tor I 2#culty mem&er in ch#rge o0 the semin#r
#nd sh#ll 5resent it in the cl#ss8 Every student sh#ll 5#rtici5#te in the semin#r8 -he students
should undert#Ce # det#iled study on the to5ic #nd su&mit # re5ort #t the end o0 the semester8
M#rCs (ill &e #(#rded &#sed on the to5ic/ 5resent#tion/ 5#rtici5#tion in the semin#r #nd the
re5ort su&mitted8
2*