COEN 3137

Advanced Logic Circuits Design

EXPERIMENT NO.
7
SYNCHRONOUS BINARY COUNTERS

Group #N (your group number)
(list all team members and affix signatures)

Team Members Signature







Republic of the Philippines
POLYTECHNIC UNIVERSITY OF THE PHILIPPINES
COLLEGE OF ENGINEERING
COMPUTER ENGINEERING DEPARTMENT

LAB 7 : Synchronous Binary Counters

Duration: 3 Hours

OBJECTIVES:

a. ) To construct a sequential circuit using 74LS76 ICs.
b. ) To verify the state table of the experimental circuit.
c.) To demonstrate the behavior of the circuit.
d.) To design and implement a sequential circuit 74LS76 ICs.
e.) To verify the state diagram to ensure that the circuit will work in accordance
with the design problem.

BASIC INFORMATION:

A synchronous sequential circuit employ signals that affect the memory
elements only at a discrete instants of time. This is achieved by using pulses of
limited duration throughout the system so that one pulse amplitude represents
logic 1 and another pulse amplitude represents logic 0.

Practical logic systems use fixed amplitudes such as voltage levels for the
binary signals. Synchronization is achieved by a timing device called a master-
clock generator, which generates a periodic train of clock pulses. The clock
pulses are distributed throughout the system in such a way that memory
elements are affected only with the arrival of the synchronization pulse.


DESIGNING SEQUENTIAL CIRCUITS.

We can construct the sequential circuits by following this step-by-step
procedure.

a. From the given information about the circuit, obtain state diagram and circuit
excitation table.

b. Determine the number flip-flops needed and assign a letter symbol to each.

c. Choose the type FF to be used.

d. Using the K-map, derive the circuit output functions and the flip-flop input
functions.

e. Draw the logic diagram.


MATERIALS REQUIRED :

3 LED 1 Breadboard
1 Power supply 1 Cutter plier
1 Long nose plier 1 Wire Stripper
3 150 2 74LS76 IC
1 74LS14 1 NO switch
4 10K

PROCEDURES:

Mod 4 Binary Up/Down Counter:

Design a circuit to build a Mod 4, two bit binary up/down counter.
The counter cycles from 012301... when X=0
or: 321032... when X=1
This circuit can be represented by the State Transition Diagram in
fig.1 below.

The STATES (binary number) are
represented using 2 flip-flops; each
flip-flop represents 1 binary digit. The
flip-flops can remember what has
happened in the past, or what value
has been stored in them.

There will be one external input, X
which controls the direction of the
count: UP for X=0, and DOWN for X=1.
The state of the flip-flops,
representing the 2-bit binary number
(the count) will be the only circuit
output.


We could design this circuit using JK, D or T flip-flops, but in this example well
use D flip-flops. When we are finished the circuit will look something like this
incomplete circuit:

Construct the State Transition Diagram
for Counter Circuit

lights
I. X

D
B
Q
B






Clc
k



Q
B















D
A
Q
A






Clc
k



Q
A





clock

Our task is to design the circuit, such that the flip flop inputs will
produce the current Next State outputs. The design procedure we
will follow for this problem will be:

Design Procedure:
1. Obtain the State Table from the problem statement of from the
State Transition Diagram.
2. Derive the flip-flop input equations from the next state conditions
in the state table.
3. Use K-maps to simplify the flip-flop input equations.
4. Draw the logic diagram with flip-flops and combinational gates as
specified by the flip-flop input equations.

We will illustrate the solution using both D flip flops and JK flip flops. Starting
with D flip flop solution.









Present
StateState
Input Next State Flip Flop
Inputs
Q
A

Q
B
X Q
A
+
Q
B
+
D
A
D
B










Derive the next-state equation using the K-mapping method:

Q
A
Q
B

X


0 0


0 1


1 1


1 0
0
1

D
A
=


Q
A
Q
B

X


0 0


0 1


1 1


1 0
0
1

D
B
=












Draw the logic diagram for this counter circuit:

lights
II. X

D
B
Q
B






Clc
k



Q
B















D
A
Q
A






Clc
k



Q
A





clock



Complete the solution using JK flip flops is shown on the following
page.
Present
State
Inpu
t
Next State Flip Flop Inputs
Q
A
Q
B
X Q
A
+

Q
B
+
J
A
K
A
J
B
K
B

0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1






JK FLIP FLOP #1 corresponds to most significant bit of the 2 bit
binary number, while flip flop #2 represents the least significant bit.
Deriving the next-state equations using K-mapping:

JK FLIP FLOP #1



Q
A
Q
B

Q
C
X


0 0


0 1


1 1


1 0


Q
A
Q
B

Q
C
X


0 0


0 1


1 1


1 0
0 0 0 0
0 1 0 1
1 1 1 1
1 0 1 0

J
A
=

K
A

=


JK FLIP FLOP #2



Q
A
Q
B

Q
C
X


0 0


0 1


1 1


1 0


Q
A
Q
B

Q
C
X


0 0


0 1


1 1


1 0
0 0 0 0
0 1 0 1
1 1 1 1
1 0 1 0

J
B
=

K
B

=







Draw the logic diagram for circuit implementation:





















































Problem #2: Design a circuit that cycle through the numbers:
13452134....
Your counter for the sequence of numbers should advance up or
down based on a control variable input. When control variable C=1,
advance forward, while a control input of C=0 should cause a
backward move in the sequence. Assume the sequence wraps
around at both ends. For example, if you have selected sequence
13452 and the counter started up at 1, with control input at one
(C=1), seven clock pulses should cause the following transitions:

13452134....








1. Draw the State Transition Diagram:

















2. Fill in the State Table below, for your sequence, using the
completed JK excitation values in the small table below.










For now leave the rows associated with the unused numbers
empty for now. Later after we fill in the K-maps we will come
back and explore what happens if the circuit ever gets into one of
these states.
Present State
input
Next State Flip Flop Inputs
Q
A

Q
B

Q
C
E Q
A
+
Q
B
+
Q
C
+

J
A
K
A
J
B
K
B
J
C
K
C

#
0 0 0 0

0
0 0 0 1
0



0 1 0

1
0 0 1 1
0 1 0 0

2
0 1 0 1
0 1 1 0

3
0 1 1 1
1 0 0 0

4
1 0 0 1
1 0 1 0

5
1 0 1 1
1 1 0 0

6
1 1 0 1
1 1 1 0

7
1 1 1 1



JK FLIP FLOP #1



Q
A
Q
B

Q
C
E


0 0


0 1


1 1


1 0


Q
A
Q
B

Q
C
E


0 0


0 1


1 1


1 0
0 0 0 0
0 1 0 1
1 1 1 1
1 0 1 0

J
A
=

K
A

=



JK FLIP FLOP #2

Q
A
Q
B

Q
C
E


0 0


0 1


1 1


1 0


Q
A
Q
B

Q
C
E


0 0


0 1


1 1


1 0
0 0 0 0
0 1 0 1
1 1 1 1
1 0 1 0

J
B

=

K
B


=


JK FLIP FLOP #3



Q
A
Q
B

Q
C
E


0 0


0 1


1 1


1 0

Q
A
Q
B

Q
C
E


0 0


0 1


1 1


1 0
0 0

0 0
0 1

0 1
1 1

1 1
1 0

1 0

J
C

=

K
C

=




Circuit Diagram

Control Input

E________________________________________________________

















J
A
Q
A



__
K
A
Q
A

J
B
Q
B



__
K
B
Q
B

J
C
Q
C



__
K
C
Q
C








74LS76A
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16
FIGURE 6. Dual JK Flip-Flop with Set and Clear
K
CP
J
Q
S
D
C
D
Q
16
1
4 14
15
2
3
K
CP
J
Q
S
D
C
D
Q
12
6
9 10
11
7
8
V
CC
=PIN 5
GND=PIN 13
LOGIC SYMBOL PIN CONFIGURATION
330
K
CP
J
Q
S
D
C
D
Q
16
1
4
14
15
2
3
V
CC
K
CP
J
Q
S
D
C
D
Q
12
6
9
10
11
7
8
V
CC
330
330
P O
T
10K
5V
s
RA
7
6
2 1
5
3
8 4
555
IC
RB
C
VCC
5V
OUT
0.01
10uF
+
+
10K
100K
Figure 6-1 Synchronous Sequential Circuit
DATA and RESULTS

PART 1. Synchronous Sequential Circuit Analysis.

Control Input Equations
















0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
P
state
In FF Inputs
N
state
O
P
state
Next state
= 0 = 1
OUT
=0 =1
TRUTH TABLE
TRANSITION TABLE
STATE DIAGRAM
PART II. Synchronous Sequential Circuit Design.








0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Present
state
FF Inputs
FF Excitation Table
STATE DIAGRAM
Next
state
0
1
00 01 11 10
0
1
00 01 11 10
0
1
00 01 11 10
0
1
00 01 11 10
0
1
00 01 11 10
0
1
00 01 11 10
Design Circuit.


























QUESTIONS :

a.) Does the actual output of Figure 6-1 agree with theoritical value?
Explain the reason of discrepancy, if any.

_________________________________________________________________

_________________________________________________________________


b.) Does the actual output of your design circuit agree with theoritical
value? Explain the reason of discrepancy, if any.

_________________________________________________________________

_________________________________________________________________


c.) In the circuit of Figure 6-2, the inputs A, B, and C are all initially
LOW. Output Y is suppose to go HIGH only when A, B, and C go to
HIGH in a certain sequence.
Determine the sequence that will make Y go HIGH.
Explain why the START pulse is needed.

_________________________________________________________________

_________________________________________________________________

_________________________________________________________________

_________________________________________________________________

_________________________________________________________________
A
Y
J
Q
Q
K
SET
CLR
X
J
Q
Q
K
SET
CLR
Figure 6-2.
B
C
Start

d.) Refer to the circuit in Figure 6-3. Assume that all asynchronous
inputs are connected to V
CC
. When tested, the circuit waveforms
appear as shown in Figure 6-3. Consider the following list of
possible faults. For each one indicate "YES" or "NO" as to whether
it could cause the observed results. Explain each response.

a.) CLR input Y
2
is open.

___________________________________________________________________________
___________________________________________________________________________

b.) Y
1
output's transition times are too long, possibly due to
loading.
__________________________________________________________________________
__________________________________________________________________________

c. Y
2
output shorted to ground.
______________________________________________________________________________
______________________________________________________________________________


d. Y
2
's hold-time requirement is not being met.
______________________________________________________________________________
______________________________________________________________________________




CONCLUSION:

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Clock
Y
2
Y
1
Y
0
Y
2
J
Q
Q
K
SET
CLR
Y
1
J
Q
Q
K
SET
CLR
Y
0
J
Q
Q
K
SET
CLR
Input Clock Pulses
Figure 6-3. JK FF wired as a 3-bit counter
1
1
1
1
1
1
Figure 6-4. Waveforms of the circuit in Figure 6-3.