OptiX OSN 3500 Intelligent Optical Transmission System

V200R011
Hardware Description
Issue 01
Date 2010-01-15
Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
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Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Contents
About This Document.....................................................................................................................1
1 Equipment Structure.................................................................................................................1-1
2 Cabinet.........................................................................................................................................2-1
2.1 Types of Cabinets............................................................................................................................................2-2
2.2 Configuration of the Cabinet...........................................................................................................................2-6
2.2.1 Indicators................................................................................................................................................2-7
2.2.2 DC Power Distribution Unit...................................................................................................................2-8
2.2.3 Other Configurations............................................................................................................................2-10
2.3 Technical Specifications...............................................................................................................................2-10
3 Subrack.........................................................................................................................................3-1
3.1 Structure..........................................................................................................................................................3-3
3.2 Slot Allocation.................................................................................................................................................3-4
3.3 Slot Access Capacity On The Packet Mode....................................................................................................3-6
3.4 Slot Access Capacity On The TDM Mode......................................................................................................3-8
3.5 Ventilation Mode.............................................................................................................................................3-9
3.6 Cable Management........................................................................................................................................3-10
3.7 Mapping Policies of Power Consumption.....................................................................................................3-12
3.8 Technical Specifications...............................................................................................................................3-13
4 Board List and Classification...................................................................................................4-1
4.1 Appearances and Dimensions of the Boards...................................................................................................4-2
4.2 Bar Codes of the Boards..................................................................................................................................4-3
4.3 Classification of the Boards............................................................................................................................4-4
5 Cross-Connect Boards and System Control Boards.............................................................5-1
5.1 PSXCS(A).......................................................................................................................................................5-2
5.1.1 Version Description................................................................................................................................5-2
5.1.2 Application.............................................................................................................................................5-3
5.1.3 Functions and Features...........................................................................................................................5-3
5.1.4 Working Principle and Signal Flow.......................................................................................................5-5
5.1.5 Front Panel.............................................................................................................................................5-6
5.1.6 Jumpers and DIP Switches.....................................................................................................................5-8
5.1.7 Valid Slots..............................................................................................................................................5-8
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description Contents
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i
5.1.8 Feature Code..........................................................................................................................................5-8
5.1.9 Parameter Settings..................................................................................................................................5-8
5.1.10 Technical Specifications......................................................................................................................5-8
5.2 GSCC..............................................................................................................................................................5-9
5.2.1 Version Description..............................................................................................................................5-10
5.2.2 Application...........................................................................................................................................5-10
5.2.3 Functions and Features.........................................................................................................................5-11
5.2.4 Working Principle and Signal Flow.....................................................................................................5-12
5.2.5 Front Panel...........................................................................................................................................5-15
5.2.6 Jumpers and DIP Switches...................................................................................................................5-16
5.2.7 Valid Slots............................................................................................................................................5-20
5.2.8 Feature Code........................................................................................................................................5-21
5.2.9 Parameter Settings................................................................................................................................5-21
5.2.10 Technical Specifications....................................................................................................................5-21
6 Packet Boards..............................................................................................................................6-1
6.1 PEX1...............................................................................................................................................................6-2
6.1.1 Version Description................................................................................................................................6-2
6.1.2 Application.............................................................................................................................................6-3
6.1.3 Functions and Features...........................................................................................................................6-3
6.1.4 Working Principle and Signal Flow.......................................................................................................6-7
6.1.5 Front Panel.............................................................................................................................................6-9
6.1.6 Jumpers and DIP Switches...................................................................................................................6-12
6.1.7 Valid Slots............................................................................................................................................6-12
6.1.8 Feature Code........................................................................................................................................6-13
6.1.9 Parameter Settings................................................................................................................................6-13
6.1.10 Technical Specifications....................................................................................................................6-13
6.2 PEX2.............................................................................................................................................................6-16
6.2.1 Version Description..............................................................................................................................6-17
6.2.2 Application...........................................................................................................................................6-17
6.2.3 Functions and Features.........................................................................................................................6-17
6.2.4 Working Principle and Signal Flow.....................................................................................................6-21
6.2.5 Front Panel...........................................................................................................................................6-23
6.2.6 Jumpers and DIP Switches...................................................................................................................6-25
6.2.7 Valid Slots............................................................................................................................................6-25
6.2.8 Feature Code........................................................................................................................................6-25
6.2.9 Parameter Settings................................................................................................................................6-25
6.2.10 Technical Specifications....................................................................................................................6-25
6.3 PEG8.............................................................................................................................................................6-27
6.3.1 Version Description..............................................................................................................................6-28
6.3.2 Application...........................................................................................................................................6-28
6.3.3 Functions and Features.........................................................................................................................6-29
6.3.4 Working Principle and Signal Flow.....................................................................................................6-32
Contents
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
ii Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
6.3.5 Front Panel...........................................................................................................................................6-34
6.3.6 Jumpers and DIP Switches...................................................................................................................6-36
6.3.7 Valid Slots............................................................................................................................................6-36
6.3.8 Feature Code........................................................................................................................................6-37
6.3.9 Parameter Settings................................................................................................................................6-37
6.3.10 Technical Specifications....................................................................................................................6-37
6.4 PEG16...........................................................................................................................................................6-38
6.4.1 Version Description..............................................................................................................................6-39
6.4.2 Application...........................................................................................................................................6-39
6.4.3 Functions and Features.........................................................................................................................6-40
6.4.4 Working Principle and Signal Flow.....................................................................................................6-43
6.4.5 Front Panel...........................................................................................................................................6-45
6.4.6 Jumpers and DIP Switches...................................................................................................................6-46
6.4.7 Valid Slots............................................................................................................................................6-46
6.4.8 Feature Code........................................................................................................................................6-47
6.4.9 Parameter Settings................................................................................................................................6-47
6.4.10 Technical Specifications....................................................................................................................6-47
6.5 PETF8............................................................................................................................................................6-49
6.5.1 Version Description..............................................................................................................................6-49
6.5.2 Application...........................................................................................................................................6-50
6.5.3 Functions and Features.........................................................................................................................6-50
6.5.4 Working Principle and Signal Flow.....................................................................................................6-52
6.5.5 Front Panel...........................................................................................................................................6-53
6.5.6 Jumpers and DIP Switches...................................................................................................................6-55
6.5.7 Valid Slots............................................................................................................................................6-55
6.5.8 Feature Code........................................................................................................................................6-55
6.5.9 Parameter Settings................................................................................................................................6-55
6.5.10 Technical Specifications....................................................................................................................6-55
6.6 PEFF8............................................................................................................................................................6-56
6.6.1 Version Description..............................................................................................................................6-57
6.6.2 Application...........................................................................................................................................6-57
6.6.3 Functions and Features.........................................................................................................................6-58
6.6.4 Working Principle and Signal Flow.....................................................................................................6-59
6.6.5 Front Panel...........................................................................................................................................6-61
6.6.6 Valid Slots............................................................................................................................................6-63
6.6.7 Feature Code........................................................................................................................................6-63
6.6.8 Parameter Settings................................................................................................................................6-63
6.6.9 Technical Specifications......................................................................................................................6-63
7 Dual-Plane Bridging Boards....................................................................................................7-1
7.1 EDQ41.............................................................................................................................................................7-2
7.1.1 Version Description................................................................................................................................7-2
7.1.2 Application.............................................................................................................................................7-2
OptiX OSN 3500 Intelligent Optical Transmission System
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7.1.3 Functions and Features...........................................................................................................................7-4
7.1.4 Working Principle and Signal Flow.......................................................................................................7-7
7.1.5 Front Panel...........................................................................................................................................7-10
7.1.6 Jumpers and DIP Switches...................................................................................................................7-11
7.1.7 Valid Slots............................................................................................................................................7-11
7.1.8 Feature Code........................................................................................................................................7-11
7.1.9 Parameter Settings................................................................................................................................7-12
7.1.10 Technical Specifications....................................................................................................................7-12
8 CES Boards..................................................................................................................................8-1
8.1 CQ1................................................................................................................................................................. 8-2
8.1.1 Version Description................................................................................................................................8-2
8.1.2 Application.............................................................................................................................................8-2
8.1.3 Functions and Features...........................................................................................................................8-3
8.1.4 Working Principle and Signal Flow.......................................................................................................8-4
8.1.5 Front Panel............................................................................................................................................. 8-6
8.1.6 Jumpers and DIP Switches.....................................................................................................................8-8
8.1.7 Valid Slots..............................................................................................................................................8-8
8.1.8 Feature Code.......................................................................................................................................... 8-8
8.1.9 Parameter Settings..................................................................................................................................8-8
8.1.10 Technical Specifications...................................................................................................................... 8-9
8.2 MD12............................................................................................................................................................8-10
8.2.1 Version Description..............................................................................................................................8-11
8.2.2 Application...........................................................................................................................................8-11
8.2.3 Functions and Features.........................................................................................................................8-12
8.2.4 Working Principle and Signal Flow.....................................................................................................8-13
8.2.5 Front Panel...........................................................................................................................................8-15
8.2.6 Jumpers and DIP Switches...................................................................................................................8-17
8.2.7 Valid Slots............................................................................................................................................8-17
8.2.8 Feature Code........................................................................................................................................8-17
8.2.9 Parameter Settings................................................................................................................................8-17
8.2.10 Technical Specifications....................................................................................................................8-18
8.3 MD75............................................................................................................................................................8-18
8.3.1 Version Description..............................................................................................................................8-19
8.3.2 Application...........................................................................................................................................8-19
8.3.3 Functions and Features.........................................................................................................................8-20
8.3.4 Working Principle and Signal Flow.....................................................................................................8-21
8.3.5 Front Panel...........................................................................................................................................8-23
8.3.6 Jumpers and DIP Switches...................................................................................................................8-25
8.3.7 Valid Slots............................................................................................................................................8-25
8.3.8 Feature Code........................................................................................................................................8-25
8.3.9 Parameter Settings................................................................................................................................8-25
8.3.10 Technical Specifications....................................................................................................................8-26
Contents
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
iv Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
9 SDH Boards................................................................................................................................. 9-1
9.1 SL1..................................................................................................................................................................9-4
9.1.1 Version Description................................................................................................................................9-4
9.1.2 Application.............................................................................................................................................9-5
9.1.3 Functions and Features...........................................................................................................................9-6
9.1.4 Working Principle and Signal Flow.......................................................................................................9-7
9.1.5 Front Panel.............................................................................................................................................9-9
9.1.6 Jumpers and DIP Switches...................................................................................................................9-11
9.1.7 Valid Slots............................................................................................................................................9-11
9.1.8 Feature Code........................................................................................................................................9-11
9.1.9 Parameter Settings................................................................................................................................9-12
9.1.10 Technical Specifications....................................................................................................................9-12
9.2 SL1A.............................................................................................................................................................9-13
9.2.1 Version Description..............................................................................................................................9-14
9.2.2 Application...........................................................................................................................................9-14
9.2.3 Functions and Features.........................................................................................................................9-15
9.2.4 Working Principle and Signal Flow.....................................................................................................9-16
9.2.5 Front Panel...........................................................................................................................................9-18
9.2.6 Valid Slots............................................................................................................................................9-20
9.2.7 Feature Code........................................................................................................................................9-20
9.2.8 Parameter Settings................................................................................................................................9-20
9.2.9 Technical Specifications......................................................................................................................9-21
9.3 SLQ1.............................................................................................................................................................9-22
9.3.1 Version Description..............................................................................................................................9-23
9.3.2 Application...........................................................................................................................................9-23
9.3.3 Functions and Features.........................................................................................................................9-24
9.3.4 Working Principle and Signal Flow.....................................................................................................9-25
9.3.5 Front Panel...........................................................................................................................................9-27
9.3.6 Valid Slots............................................................................................................................................9-29
9.3.7 Feature Code........................................................................................................................................9-29
9.3.8 Parameter Settings................................................................................................................................9-30
9.3.9 Technical Specifications......................................................................................................................9-30
9.4 SLQ1A..........................................................................................................................................................9-31
9.4.1 Version Description..............................................................................................................................9-32
9.4.2 Application...........................................................................................................................................9-32
9.4.3 Functions and Features.........................................................................................................................9-32
9.4.4 Working Principle and Signal Flow.....................................................................................................9-34
9.4.5 Front Panel...........................................................................................................................................9-36
9.4.6 Valid Slots............................................................................................................................................9-37
9.4.7 Feature Code........................................................................................................................................9-37
9.4.8 Parameter Settings................................................................................................................................9-38
9.4.9 Technical Specifications......................................................................................................................9-38
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description Contents
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Copyright Huawei Technologies Co., Ltd.
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9.5 SLO1.............................................................................................................................................................9-39
9.5.1 Version Description..............................................................................................................................9-40
9.5.2 Application...........................................................................................................................................9-41
9.5.3 Functions and Features.........................................................................................................................9-41
9.5.4 Working Principle and Signal Flow.....................................................................................................9-42
9.5.5 Front Panel...........................................................................................................................................9-44
9.5.6 Valid Slots............................................................................................................................................9-46
9.5.7 Feature Code........................................................................................................................................9-46
9.5.8 Parameter Settings................................................................................................................................9-47
9.5.9 Technical Specifications......................................................................................................................9-47
9.6 SLT1..............................................................................................................................................................9-48
9.6.1 Version Description..............................................................................................................................9-49
9.6.2 Application...........................................................................................................................................9-49
9.6.3 Functions and Features.........................................................................................................................9-50
9.6.4 Working Principle and Signal Flow.....................................................................................................9-51
9.6.5 Front Panel...........................................................................................................................................9-53
9.6.6 Valid Slots............................................................................................................................................9-55
9.6.7 Feature Code........................................................................................................................................9-55
9.6.8 Parameter Settings................................................................................................................................9-56
9.6.9 Technical Specifications......................................................................................................................9-56
9.7 SLH1.............................................................................................................................................................9-57
9.7.1 Version Description..............................................................................................................................9-58
9.7.2 Application...........................................................................................................................................9-58
9.7.3 Functions and Features.........................................................................................................................9-58
9.7.4 Working Principle and Signal Flow.....................................................................................................9-60
9.7.5 Front Panel...........................................................................................................................................9-62
9.7.6 Jumpers and DIP Switches...................................................................................................................9-63
9.7.7 Valid Slots............................................................................................................................................9-64
9.7.8 Board Protection...................................................................................................................................9-64
9.7.9 Parameter Settings................................................................................................................................9-66
9.7.10 Technical Specifications....................................................................................................................9-66
9.8 SEP1..............................................................................................................................................................9-67
9.8.1 Version Description..............................................................................................................................9-68
9.8.2 Application...........................................................................................................................................9-68
9.8.3 Functions and Features.........................................................................................................................9-68
9.8.4 Working Principle and Signal Flow.....................................................................................................9-71
9.8.5 Front Panel...........................................................................................................................................9-74
9.8.6 Jumpers and DIP Switches...................................................................................................................9-76
9.8.7 Valid Slots............................................................................................................................................9-76
9.8.8 Board Protection...................................................................................................................................9-76
9.8.9 Feature Code........................................................................................................................................9-79
9.8.10 Parameter Settings..............................................................................................................................9-79
Contents
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
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Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
9.8.11 Technical Specifications....................................................................................................................9-79
9.9 SL4................................................................................................................................................................9-79
9.9.1 Version Description..............................................................................................................................9-80
9.9.2 Application...........................................................................................................................................9-81
9.9.3 Functions and Features.........................................................................................................................9-81
9.9.4 Working Principle and Signal Flow.....................................................................................................9-83
9.9.5 Front Panel...........................................................................................................................................9-85
9.9.6 Valid Slots............................................................................................................................................9-87
9.9.7 Feature Code........................................................................................................................................9-87
9.9.8 Parameter Settings................................................................................................................................9-88
9.9.9 Technical Specifications......................................................................................................................9-88
9.10 SL4A...........................................................................................................................................................9-89
9.10.1 Version Description............................................................................................................................9-90
9.10.2 Application.........................................................................................................................................9-90
9.10.3 Functions and Features.......................................................................................................................9-90
9.10.4 Working Principle and Signal Flow...................................................................................................9-92
9.10.5 Front Panel.........................................................................................................................................9-94
9.10.6 Valid Slots..........................................................................................................................................9-95
9.10.7 Feature Code......................................................................................................................................9-95
9.10.8 Parameter Settings..............................................................................................................................9-96
9.10.9 Technical Specifications....................................................................................................................9-96
9.11 SLD4...........................................................................................................................................................9-97
9.11.1 Version Description............................................................................................................................9-98
9.11.2 Application.........................................................................................................................................9-98
9.11.3 Functions and Features.......................................................................................................................9-99
9.11.4 Working Principle and Signal Flow.................................................................................................9-100
9.11.5 Front Panel.......................................................................................................................................9-102
9.11.6 Valid Slots........................................................................................................................................9-104
9.11.7 Feature Code....................................................................................................................................9-104
9.11.8 Parameter Settings............................................................................................................................9-105
9.11.9 Technical Specifications..................................................................................................................9-105
9.12 SLD4A......................................................................................................................................................9-106
9.12.1 Version Description..........................................................................................................................9-107
9.12.2 Application.......................................................................................................................................9-107
9.12.3 Functions and Features.....................................................................................................................9-108
9.12.4 Working Principle and Signal Flow.................................................................................................9-109
9.12.5 Front Panel.......................................................................................................................................9-111
9.12.6 Valid Slots........................................................................................................................................9-113
9.12.7 Feature Code....................................................................................................................................9-113
9.12.8 Parameter Settings............................................................................................................................9-113
9.12.9 Technical Specifications..................................................................................................................9-114
9.13 SLQ4.........................................................................................................................................................9-115
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description Contents
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Copyright Huawei Technologies Co., Ltd.
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9.13.1 Version Description..........................................................................................................................9-116
9.13.2 Application.......................................................................................................................................9-116
9.13.3 Functions and Features.....................................................................................................................9-117
9.13.4 Working Principle and Signal Flow.................................................................................................9-118
9.13.5 Front Panel.......................................................................................................................................9-120
9.13.6 Valid Slots........................................................................................................................................9-122
9.13.7 Feature Code....................................................................................................................................9-122
9.13.8 Parameter Settings............................................................................................................................9-123
9.13.9 Technical Specifications..................................................................................................................9-123
9.14 SLQ4A......................................................................................................................................................9-124
9.14.1 Version Description..........................................................................................................................9-125
9.14.2 Application.......................................................................................................................................9-125
9.14.3 Functions and Features.....................................................................................................................9-125
9.14.4 Working Principle and Signal Flow.................................................................................................9-127
9.14.5 Front Panel.......................................................................................................................................9-129
9.14.6 Valid Slots........................................................................................................................................9-131
9.14.7 Feature Code....................................................................................................................................9-131
9.14.8 Parameter Settings............................................................................................................................9-131
9.14.9 Technical Specifications..................................................................................................................9-132
9.15 SL16..........................................................................................................................................................9-133
9.15.1 Version Description..........................................................................................................................9-134
9.15.2 Application.......................................................................................................................................9-134
9.15.3 Functions and Features.....................................................................................................................9-135
9.15.4 Working Principle and Signal Flow.................................................................................................9-136
9.15.5 Front Panel.......................................................................................................................................9-138
9.15.6 Valid Slots........................................................................................................................................9-140
9.15.7 Feature Code....................................................................................................................................9-140
9.15.8 Parameter Settings............................................................................................................................9-140
9.15.9 Technical Specifications..................................................................................................................9-141
9.16 SL16A.......................................................................................................................................................9-143
9.16.1 Version Description..........................................................................................................................9-144
9.16.2 Application.......................................................................................................................................9-144
9.16.3 Functions and Features.....................................................................................................................9-145
9.16.4 Working Principle and Signal Flow.................................................................................................9-146
9.16.5 Front Panel.......................................................................................................................................9-148
9.16.6 Jumpers and DIP Switches...............................................................................................................9-150
9.16.7 Valid Slots........................................................................................................................................9-150
9.16.8 Feature Code....................................................................................................................................9-150
9.16.9 Parameter Settings............................................................................................................................9-151
9.16.10 Technical Specifications................................................................................................................9-151
9.17 SLD16.......................................................................................................................................................9-153
9.17.1 Version Description..........................................................................................................................9-153
Contents
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9.17.2 Application.......................................................................................................................................9-153
9.17.3 Functions and Features.....................................................................................................................9-154
9.17.4 Working Principle and Signal Flow.................................................................................................9-155
9.17.5 Front Panel.......................................................................................................................................9-157
9.17.6 Jumpers and DIP Switches...............................................................................................................9-159
9.17.7 Valid Slots........................................................................................................................................9-159
9.17.8 Feature Code....................................................................................................................................9-159
9.17.9 Parameter Settings............................................................................................................................9-160
9.17.10 Technical Specifications................................................................................................................9-160
9.18 SLQ16.......................................................................................................................................................9-161
9.18.1 Version Description..........................................................................................................................9-162
9.18.2 Application.......................................................................................................................................9-163
9.18.3 Functions and Features.....................................................................................................................9-163
9.18.4 Working Principle and Signal Flow.................................................................................................9-165
9.18.5 Front Panel.......................................................................................................................................9-167
9.18.6 Jumpers and DIP Switches...............................................................................................................9-170
9.18.7 Valid Slots........................................................................................................................................9-170
9.18.8 Feature Code....................................................................................................................................9-170
9.18.9 Parameter Settings............................................................................................................................9-171
9.18.10 Technical Specifications................................................................................................................9-171
9.19 SLO16.......................................................................................................................................................9-172
9.19.1 Version Description..........................................................................................................................9-173
9.19.2 Application.......................................................................................................................................9-173
9.19.3 Functions and Features.....................................................................................................................9-174
9.19.4 Working Principle and Signal Flow.................................................................................................9-175
9.19.5 Front Panel.......................................................................................................................................9-177
9.19.6 Jumpers and DIP Switches...............................................................................................................9-179
9.19.7 Valid Slots........................................................................................................................................9-179
9.19.8 Feature Code....................................................................................................................................9-179
9.19.9 Parameter Settings............................................................................................................................9-180
9.19.10 Technical Specifications................................................................................................................9-180
9.20 SF16..........................................................................................................................................................9-181
9.20.1 Version Description..........................................................................................................................9-182
9.20.2 Application.......................................................................................................................................9-182
9.20.3 Functions and Features.....................................................................................................................9-182
9.20.4 Working Principle and Signal Flow.................................................................................................9-184
9.20.5 Front Panel.......................................................................................................................................9-186
9.20.6 Valid Slots........................................................................................................................................9-188
9.20.7 Feature Code....................................................................................................................................9-188
9.20.8 Parameter Settings............................................................................................................................9-188
9.20.9 Technical Specifications..................................................................................................................9-189
9.21 SL64..........................................................................................................................................................9-191
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description Contents
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ix
9.21.1 Version Description..........................................................................................................................9-191
9.21.2 Application.......................................................................................................................................9-192
9.21.3 Functions and Features.....................................................................................................................9-193
9.21.4 Working Principle and Signal Flow.................................................................................................9-194
9.21.5 Front Panel.......................................................................................................................................9-197
9.21.6 Jumpers and DIP Switches...............................................................................................................9-198
9.21.7 Valid Slots........................................................................................................................................9-198
9.21.8 Feature Code....................................................................................................................................9-198
9.21.9 Parameter Settings............................................................................................................................9-199
9.21.10 Technical Specifications................................................................................................................9-199
9.22 SLD64.......................................................................................................................................................9-201
9.22.1 Version Description..........................................................................................................................9-202
9.22.2 Application.......................................................................................................................................9-202
9.22.3 Functions and Features.....................................................................................................................9-203
9.22.4 Working Principle and Signal Flow.................................................................................................9-204
9.22.5 Front Panel.......................................................................................................................................9-206
9.22.6 Jumpers and DIP Switches...............................................................................................................9-208
9.22.7 Valid Slots........................................................................................................................................9-208
9.22.8 Feature Code....................................................................................................................................9-208
9.22.9 Parameter Settings............................................................................................................................9-209
9.22.10 Technical Specifications................................................................................................................9-209
9.23 SF64..........................................................................................................................................................9-210
9.23.1 Version Description..........................................................................................................................9-211
9.23.2 Application.......................................................................................................................................9-211
9.23.3 Functions and Features.....................................................................................................................9-211
9.23.4 Working Principle and Signal Flow.................................................................................................9-213
9.23.5 Front Panel.......................................................................................................................................9-215
9.23.6 Jumpers and DIP Switches...............................................................................................................9-217
9.23.7 Valid Slots........................................................................................................................................9-217
9.23.8 Feature Code....................................................................................................................................9-217
9.23.9 Parameter Settings............................................................................................................................9-217
9.23.10 Technical Specifications................................................................................................................9-218
9.24 SF64A........................................................................................................................................................9-219
9.24.1 Version Description..........................................................................................................................9-220
9.24.2 Application.......................................................................................................................................9-220
9.24.3 Functions and Features.....................................................................................................................9-221
9.24.4 Working Principle and Signal Flow.................................................................................................9-222
9.24.5 Front Panel.......................................................................................................................................9-224
9.24.6 Valid Slots........................................................................................................................................9-226
9.24.7 Parameter Settings............................................................................................................................9-226
9.24.8 Technical Specifications..................................................................................................................9-226
9.25 SLQ41.......................................................................................................................................................9-228
Contents
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
x Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
9.25.1 Version Description..........................................................................................................................9-229
9.25.2 Application.......................................................................................................................................9-229
9.25.3 Functions and Features.....................................................................................................................9-230
9.25.4 Working Principle and Signal Flow.................................................................................................9-231
9.25.5 Front Panel.......................................................................................................................................9-233
9.25.6 Jumpers and DIP Switches...............................................................................................................9-235
9.25.7 Valid Slots........................................................................................................................................9-235
9.25.8 Feature Code....................................................................................................................................9-235
9.25.9 Parameter Settings............................................................................................................................9-236
9.25.10 Technical Specifications................................................................................................................9-236
9.26 EU04..........................................................................................................................................................9-238
9.26.1 Version Description..........................................................................................................................9-239
9.26.2 Application.......................................................................................................................................9-239
9.26.3 Functions and Features.....................................................................................................................9-239
9.26.4 Working Principle and Signal Flow.................................................................................................9-239
9.26.5 Front Panel.......................................................................................................................................9-240
9.26.6 Valid Slots........................................................................................................................................9-241
9.26.7 Technical Specifications..................................................................................................................9-241
9.27 EU08..........................................................................................................................................................9-242
9.27.1 Version Description..........................................................................................................................9-243
9.27.2 Application.......................................................................................................................................9-243
9.27.3 Functions and Features.....................................................................................................................9-243
9.27.4 Working Principle and Signal Flow.................................................................................................9-243
9.27.5 Front Panel.......................................................................................................................................9-244
9.27.6 Valid Slots........................................................................................................................................9-245
9.27.7 Technical Specifications..................................................................................................................9-246
9.28 OU08.........................................................................................................................................................9-247
9.28.1 Version Description..........................................................................................................................9-247
9.28.2 Application.......................................................................................................................................9-248
9.28.3 Functions and Features.....................................................................................................................9-248
9.28.4 Working Principle and Signal Flow.................................................................................................9-248
9.28.5 Front Panel.......................................................................................................................................9-249
9.28.6 Valid Slots........................................................................................................................................9-251
9.28.7 Technical Specifications..................................................................................................................9-252
10 PDH Boards.............................................................................................................................10-1
10.1 PQ1..............................................................................................................................................................10-3
10.1.1 Version Description............................................................................................................................10-3
10.1.2 Application.........................................................................................................................................10-4
10.1.3 Functions and Features.......................................................................................................................10-5
10.1.4 Working Principle and Signal Flow...................................................................................................10-5
10.1.5 Front Panel.........................................................................................................................................10-8
10.1.6 Jumpers and DIP Switches.................................................................................................................10-9
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10.1.7 Valid Slots..........................................................................................................................................10-9
10.1.8 Feature Code....................................................................................................................................10-10
10.1.9 Board Protection...............................................................................................................................10-10
10.1.10 Parameter Settings..........................................................................................................................10-12
10.1.11 Technical Specifications................................................................................................................10-12
10.2 PQM..........................................................................................................................................................10-13
10.2.1 Version Description..........................................................................................................................10-14
10.2.2 Application.......................................................................................................................................10-14
10.2.3 Functions and Features.....................................................................................................................10-14
10.2.4 Working Principle and Signal Flow.................................................................................................10-15
10.2.5 Front Panel.......................................................................................................................................10-18
10.2.6 Jumpers and DIP Switches...............................................................................................................10-19
10.2.7 Valid Slots........................................................................................................................................10-19
10.2.8 Feature Code....................................................................................................................................10-20
10.2.9 Board Protection...............................................................................................................................10-20
10.2.10 Parameter Settings..........................................................................................................................10-22
10.2.11 Technical Specifications................................................................................................................10-22
10.3 PL3............................................................................................................................................................10-22
10.3.1 Version Description..........................................................................................................................10-23
10.3.2 Application.......................................................................................................................................10-23
10.3.3 Functions and Features.....................................................................................................................10-24
10.3.4 Working Principle and Signal Flow.................................................................................................10-25
10.3.5 Front Panel.......................................................................................................................................10-27
10.3.6 Jumpers and DIP Switches...............................................................................................................10-29
10.3.7 Valid Slots........................................................................................................................................10-29
10.3.8 Feature Code....................................................................................................................................10-29
10.3.9 Board Protection...............................................................................................................................10-29
10.3.10 Parameter Settings..........................................................................................................................10-32
10.3.11 Technical Specifications................................................................................................................10-32
10.4 PL3A.........................................................................................................................................................10-32
10.4.1 Version Description..........................................................................................................................10-33
10.4.2 Application.......................................................................................................................................10-34
10.4.3 Functions and Features.....................................................................................................................10-34
10.4.4 Working Principle and Signal Flow.................................................................................................10-35
10.4.5 Front Panel.......................................................................................................................................10-38
10.4.6 Jumpers and DIP Switches...............................................................................................................10-39
10.4.7 Valid Slots........................................................................................................................................10-39
10.4.8 Feature Code....................................................................................................................................10-39
10.4.9 Parameter Settings............................................................................................................................10-39
10.4.10 Technical Specifications................................................................................................................10-40
10.5 PD3............................................................................................................................................................10-40
10.5.1 Version Description..........................................................................................................................10-41
Contents
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
xii Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
10.5.2 Application.......................................................................................................................................10-41
10.5.3 Functions and Features.....................................................................................................................10-42
10.5.4 Working Principle and Signal Flow.................................................................................................10-43
10.5.5 Front Panel.......................................................................................................................................10-45
10.5.6 Valid Slots........................................................................................................................................10-47
10.5.7 Board Protection...............................................................................................................................10-47
10.5.8 Parameter Settings............................................................................................................................10-50
10.5.9 Technical Specifications..................................................................................................................10-50
10.6 PQ3............................................................................................................................................................10-50
10.6.1 Version Description..........................................................................................................................10-51
10.6.2 Application.......................................................................................................................................10-51
10.6.3 Functions and Features.....................................................................................................................10-52
10.6.4 Working Principle and Signal Flow.................................................................................................10-52
10.6.5 Front Panel.......................................................................................................................................10-55
10.6.6 Valid Slots........................................................................................................................................10-56
10.6.7 Board Protection...............................................................................................................................10-56
10.6.8 Parameter Settings............................................................................................................................10-59
10.6.9 Technical Specifications..................................................................................................................10-59
10.7 DX1...........................................................................................................................................................10-59
10.7.1 Version Description..........................................................................................................................10-60
10.7.2 Application.......................................................................................................................................10-60
10.7.3 Functions and Features.....................................................................................................................10-61
10.7.4 Working Principle and Signal Flow.................................................................................................10-62
10.7.5 Front Panel.......................................................................................................................................10-63
10.7.6 Jumpers and DIP Switches...............................................................................................................10-65
10.7.7 Valid Slots........................................................................................................................................10-65
10.7.8 Feature Code....................................................................................................................................10-65
10.7.9 Board Protection...............................................................................................................................10-66
10.7.10 Parameter Settings..........................................................................................................................10-67
10.7.11 Technical Specifications................................................................................................................10-68
10.8 DXA..........................................................................................................................................................10-68
10.8.1 Version Description..........................................................................................................................10-69
10.8.2 Application.......................................................................................................................................10-69
10.8.3 Functions and Features.....................................................................................................................10-69
10.8.4 Working Principle and Signal Flow.................................................................................................10-70
10.8.5 Front Panel.......................................................................................................................................10-71
10.8.6 Valid Slots........................................................................................................................................10-73
10.8.7 Parameter Settings............................................................................................................................10-73
10.8.8 Technical Specifications..................................................................................................................10-73
10.9 SPQ4..........................................................................................................................................................10-73
10.9.1 Version Description..........................................................................................................................10-74
10.9.2 Application.......................................................................................................................................10-74
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Hardware Description Contents
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10.9.3 Functions and Features.....................................................................................................................10-75
10.9.4 Working Principle and Signal Flow.................................................................................................10-76
10.9.5 Front Panel.......................................................................................................................................10-80
10.9.6 Jumpers and DIP Switches...............................................................................................................10-82
10.9.7 Valid Slots........................................................................................................................................10-82
10.9.8 Feature Code....................................................................................................................................10-82
10.9.9 Board Protection...............................................................................................................................10-82
10.9.10 Parameter Settings..........................................................................................................................10-85
10.9.11 Technical Specifications................................................................................................................10-85
10.10 D12B.......................................................................................................................................................10-85
10.10.1 Version Description........................................................................................................................10-86
10.10.2 Application.....................................................................................................................................10-86
10.10.3 Functions and Features...................................................................................................................10-86
10.10.4 Working Principle and Signal Flow...............................................................................................10-86
10.10.5 Front Panel.....................................................................................................................................10-86
10.10.6 Valid Slots......................................................................................................................................10-89
10.10.7 Technical Specifications................................................................................................................10-89
10.11 D12S........................................................................................................................................................10-90
10.11.1 Version Description........................................................................................................................10-90
10.11.2 Application.....................................................................................................................................10-91
10.11.3 Functions and Features...................................................................................................................10-91
10.11.4 Working Principle and Signal Flow...............................................................................................10-91
10.11.5 Front Panel.....................................................................................................................................10-92
10.11.6 Valid Slots......................................................................................................................................10-94
10.11.7 Technical Specifications................................................................................................................10-94
10.12 D75S........................................................................................................................................................10-95
10.12.1 Version Description........................................................................................................................10-95
10.12.2 Application.....................................................................................................................................10-96
10.12.3 Functions and Features...................................................................................................................10-96
10.12.4 Working Principle and Signal Flow...............................................................................................10-96
10.12.5 Front Panel.....................................................................................................................................10-97
10.12.6 Valid Slots......................................................................................................................................10-99
10.12.7 Technical Specifications................................................................................................................10-99
10.13 D34S......................................................................................................................................................10-100
10.13.1 Version Description......................................................................................................................10-100
10.13.2 Application...................................................................................................................................10-101
10.13.3 Functions and Features.................................................................................................................10-101
10.13.4 Working Principle and Signal Flow.............................................................................................10-101
10.13.5 Front Panel...................................................................................................................................10-102
10.13.6 Valid Slots....................................................................................................................................10-103
10.13.7 Technical Specifications..............................................................................................................10-103
10.14 C34S......................................................................................................................................................10-104
Contents
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Hardware Description
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Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
10.14.1 Version Description......................................................................................................................10-104
10.14.2 Application...................................................................................................................................10-104
10.14.3 Functions and Features.................................................................................................................10-104
10.14.4 Working Principle and Signal Flow.............................................................................................10-104
10.14.5 Front Panel...................................................................................................................................10-105
10.14.6 Valid Slots....................................................................................................................................10-107
10.14.7 Technical Specifications..............................................................................................................10-107
10.15 MU04....................................................................................................................................................10-108
10.15.1 Version Description......................................................................................................................10-108
10.15.2 Application...................................................................................................................................10-108
10.15.3 Functions and Features.................................................................................................................10-108
10.15.4 Working Principle and Signal Flow.............................................................................................10-109
10.15.5 Front Panel...................................................................................................................................10-109
10.15.6 Valid Slots....................................................................................................................................10-111
10.15.7 Technical Specifications..............................................................................................................10-111
10.16 DM12....................................................................................................................................................10-112
10.16.1 Version Description......................................................................................................................10-112
10.16.2 Application...................................................................................................................................10-112
10.16.3 Functions and Features.................................................................................................................10-112
10.16.4 Working Principle and Signal Flow.............................................................................................10-113
10.16.5 Front Panel...................................................................................................................................10-113
10.16.6 Valid Slots....................................................................................................................................10-116
10.16.7 Technical Specifications..............................................................................................................10-117
10.17 TSB4......................................................................................................................................................10-118
10.17.1 Version Description......................................................................................................................10-118
10.17.2 Application...................................................................................................................................10-118
10.17.3 Functions and Features.................................................................................................................10-118
10.17.4 Working Principle and Signal Flow.............................................................................................10-118
10.17.5 Front Panel...................................................................................................................................10-119
10.17.6 Valid Slots....................................................................................................................................10-120
10.17.7 Technical Specifications..............................................................................................................10-122
10.18 TSB8......................................................................................................................................................10-122
10.18.1 Version Description......................................................................................................................10-123
10.18.2 Application...................................................................................................................................10-123
10.18.3 Functions and Features.................................................................................................................10-123
10.18.4 Working Principle and Signal Flow.............................................................................................10-123
10.18.5 Front Panel...................................................................................................................................10-124
10.18.6 Valid Slots....................................................................................................................................10-125
10.18.7 Technical Specifications..............................................................................................................10-128
11 EoS Boards............................................................................................................................... 11-1
11.1 EFT8............................................................................................................................................................11-3
11.1.1 Version Description............................................................................................................................11-3
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description Contents
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11.1.2 Application.........................................................................................................................................11-3
11.1.3 Functions and Features.......................................................................................................................11-4
11.1.4 Working Principle and Signal Flow...................................................................................................11-6
11.1.5 Front Panel......................................................................................................................................... 11-8
11.1.6 Jumpers and DIP Switches...............................................................................................................11-11
11.1.7 Valid Slots........................................................................................................................................11-11
11.1.8 Feature Code....................................................................................................................................11-11
11.1.9 Parameter Settings............................................................................................................................11-11
11.1.10 Technical Specifications................................................................................................................11-12
11.2 EFT8A.......................................................................................................................................................11-16
11.2.1 Version Description..........................................................................................................................11-16
11.2.2 Application.......................................................................................................................................11-16
11.2.3 Functions and Features.....................................................................................................................11-17
11.2.4 Working Principle and Signal Flow.................................................................................................11-19
11.2.5 Front Panel.......................................................................................................................................11-21
11.2.6 Jumpers and DIP Switches...............................................................................................................11-24
11.2.7 Valid Slots........................................................................................................................................11-24
11.2.8 Feature Code....................................................................................................................................11-24
11.2.9 Parameter Settings............................................................................................................................11-24
11.2.10 Technical Specifications................................................................................................................11-24
11.3 EGT2.........................................................................................................................................................11-28
11.3.1 Version Description..........................................................................................................................11-29
11.3.2 Application.......................................................................................................................................11-29
11.3.3 Functions and Features.....................................................................................................................11-30
11.3.4 Working Principle and Signal Flow.................................................................................................11-32
11.3.5 Front Panel.......................................................................................................................................11-34
11.3.6 Jumpers and DIP Switches...............................................................................................................11-37
11.3.7 Valid Slots........................................................................................................................................11-38
11.3.8 Feature Code....................................................................................................................................11-38
11.3.9 Parameter Settings............................................................................................................................11-38
11.3.10 Technical Specifications................................................................................................................11-39
11.4 EFS0..........................................................................................................................................................11-47
11.4.1 Version Description..........................................................................................................................11-48
11.4.2 Application.......................................................................................................................................11-49
11.4.3 Functions and Features.....................................................................................................................11-50
11.4.4 Working Principle and Signal Flow.................................................................................................11-54
11.4.5 Front Panel.......................................................................................................................................11-56
11.4.6 Jumpers and DIP Switches...............................................................................................................11-58
11.4.7 Valid Slots........................................................................................................................................11-58
11.4.8 Feature Code....................................................................................................................................11-59
11.4.9 Board Protection...............................................................................................................................11-59
11.4.10 Parameter Settings..........................................................................................................................11-60
Contents
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
xvi Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
11.4.11 Technical Specifications................................................................................................................11-60
11.5 EFS0A.......................................................................................................................................................11-69
11.5.1 Version Description..........................................................................................................................11-69
11.5.2 Application.......................................................................................................................................11-69
11.5.3 Functions and Features.....................................................................................................................11-70
11.5.4 Working Principle and Signal Flow.................................................................................................11-73
11.5.5 Front Panel.......................................................................................................................................11-76
11.5.6 Jumpers and DIP Switches...............................................................................................................11-77
11.5.7 Valid Slots........................................................................................................................................11-77
11.5.8 Feature Code....................................................................................................................................11-78
11.5.9 Board Protection...............................................................................................................................11-78
11.5.10 Parameter Settings..........................................................................................................................11-80
11.5.11 Technical Specifications................................................................................................................11-80
11.6 EFS4..........................................................................................................................................................11-84
11.6.1 Version Description..........................................................................................................................11-85
11.6.2 Application.......................................................................................................................................11-85
11.6.3 Functions and Features.....................................................................................................................11-86
11.6.4 Working Principle and Signal Flow.................................................................................................11-89
11.6.5 Front Panel.......................................................................................................................................11-91
11.6.6 Jumpers and DIP Switches...............................................................................................................11-93
11.6.7 Valid Slots........................................................................................................................................11-93
11.6.8 Feature Code....................................................................................................................................11-94
11.6.9 Parameter Settings............................................................................................................................11-94
11.6.10 Technical Specifications................................................................................................................11-94
11.7 EGS2.......................................................................................................................................................11-102
11.7.1 Version Description........................................................................................................................11-103
11.7.2 Application.....................................................................................................................................11-104
11.7.3 Functions and Features...................................................................................................................11-104
11.7.4 Working Principle and Signal Flow...............................................................................................11-107
11.7.5 Front Panel.....................................................................................................................................11-110
11.7.6 Jumpers and DIP Switches.............................................................................................................11-113
11.7.7 Valid Slots......................................................................................................................................11-113
11.7.8 Feature Code..................................................................................................................................11-113
11.7.9 Parameter Settings..........................................................................................................................11-114
11.7.10 Technical Specifications..............................................................................................................11-114
11.8 EMS2.......................................................................................................................................................11-123
11.8.1 Version Description........................................................................................................................11-124
11.8.2 Application.....................................................................................................................................11-124
11.8.3 Functions and Features...................................................................................................................11-125
11.8.4 Working Principle and Signal Flow...............................................................................................11-128
11.8.5 Front Panel.....................................................................................................................................11-131
11.8.6 Jumpers and DIP Switches.............................................................................................................11-134
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description Contents
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11.8.7 Valid Slots......................................................................................................................................11-134
11.8.8 Feature Code..................................................................................................................................11-134
11.8.9 Parameter Settings..........................................................................................................................11-135
11.8.10 Technical Specifications..............................................................................................................11-135
11.9 EMS4.......................................................................................................................................................11-144
11.9.1 Version Description........................................................................................................................11-145
11.9.2 Application.....................................................................................................................................11-145
11.9.3 Functions and Features...................................................................................................................11-145
11.9.4 Working Principle and Signal Flow...............................................................................................11-149
11.9.5 Front Panel.....................................................................................................................................11-151
11.9.6 Jumpers and DIP Switches.............................................................................................................11-155
11.9.7 Valid Slots......................................................................................................................................11-155
11.9.8 Feature Code..................................................................................................................................11-156
11.9.9 Board Protection.............................................................................................................................11-156
11.9.10 Parameter Settings........................................................................................................................11-160
11.9.11 Technical Specifications..............................................................................................................11-161
11.10 EGS4.....................................................................................................................................................11-169
11.10.1 Version Description......................................................................................................................11-170
11.10.2 Application...................................................................................................................................11-170
11.10.3 Functions and Features.................................................................................................................11-171
11.10.4 Working Principle and Signal Flow.............................................................................................11-174
11.10.5 Front Panel...................................................................................................................................11-177
11.10.6 Jumpers and DIP Switches...........................................................................................................11-180
11.10.7 Valid Slots....................................................................................................................................11-180
11.10.8 Feature Code................................................................................................................................11-180
11.10.9 Board Protection...........................................................................................................................11-181
11.10.10 Parameter Settings......................................................................................................................11-184
11.10.11 Technical Specifications............................................................................................................11-185
11.11 EAS2.....................................................................................................................................................11-194
11.11.1 Version Description......................................................................................................................11-195
11.11.2 Application...................................................................................................................................11-195
11.11.3 Functions and Features.................................................................................................................11-196
11.11.4 Working Principle and Signal Flow.............................................................................................11-198
11.11.5 Front Panel...................................................................................................................................11-200
11.11.6 Jumpers and DIP Switches...........................................................................................................11-201
11.11.7 Valid Slots....................................................................................................................................11-201
11.11.8 Feature Code................................................................................................................................11-201
11.11.9 Parameter Settings........................................................................................................................11-201
11.11.10 Technical Specifications............................................................................................................11-202
11.12 EFF8......................................................................................................................................................11-205
11.12.1 Version Description......................................................................................................................11-205
11.12.2 Application...................................................................................................................................11-205
Contents
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Hardware Description
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Issue 01 (2010-01-15)
11.12.3 Functions and Features.................................................................................................................11-206
11.12.4 Working Principle and Signal Flow.............................................................................................11-206
11.12.5 Front Panel...................................................................................................................................11-206
11.12.6 Valid Slots....................................................................................................................................11-208
11.12.7 Technical Specifications..............................................................................................................11-209
11.13 EFF8A...................................................................................................................................................11-210
11.13.1 Version Description......................................................................................................................11-210
11.13.2 Application...................................................................................................................................11-210
11.13.3 Functions and Features.................................................................................................................11-211
11.13.4 Working Principle and Signal Flow.............................................................................................11-211
11.13.5 Front Panel...................................................................................................................................11-211
11.13.6 Valid Slots....................................................................................................................................11-213
11.13.7 Technical Specifications..............................................................................................................11-213
11.14 ETF8......................................................................................................................................................11-214
11.14.1 Version Description......................................................................................................................11-215
11.14.2 Application...................................................................................................................................11-215
11.14.3 Functions and Features.................................................................................................................11-215
11.14.4 Working Principle and Signal Flow.............................................................................................11-215
11.14.5 Front Panel...................................................................................................................................11-216
11.14.6 Valid Slots....................................................................................................................................11-218
11.14.7 Technical Specifications..............................................................................................................11-219
11.15 ETF8A...................................................................................................................................................11-220
11.15.1 Version Description......................................................................................................................11-220
11.15.2 Application...................................................................................................................................11-220
11.15.3 Functions and Features.................................................................................................................11-220
11.15.4 Working Principle and Signal Flow.............................................................................................11-220
11.15.5 Front Panel...................................................................................................................................11-221
11.15.6 Valid Slots....................................................................................................................................11-223
11.15.7 Technical Specifications..............................................................................................................11-223
11.16 ETS8......................................................................................................................................................11-224
11.16.1 Version Description......................................................................................................................11-225
11.16.2 Application...................................................................................................................................11-225
11.16.3 Functions and Features.................................................................................................................11-225
11.16.4 Working Principle and Signal Flow.............................................................................................11-225
11.16.5 Front Panel...................................................................................................................................11-226
11.16.6 Valid Slots....................................................................................................................................11-227
11.16.7 Technical Specifications..............................................................................................................11-228
12 ATM Boards............................................................................................................................12-1
12.1 ADL4...........................................................................................................................................................12-2
12.1.1 Version Description............................................................................................................................12-2
12.1.2 Application.........................................................................................................................................12-2
12.1.3 Functions and Features.......................................................................................................................12-4
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Hardware Description Contents
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12.1.4 Working Principle and Signal Flow...................................................................................................12-5
12.1.5 Front Panel.........................................................................................................................................12-7
12.1.6 Jumpers and DIP Switches.................................................................................................................12-9
12.1.7 Valid Slots..........................................................................................................................................12-9
12.1.8 Feature Code......................................................................................................................................12-9
12.1.9 Parameter Settings............................................................................................................................12-10
12.1.10 Technical Specifications................................................................................................................12-10
12.2 ADQ1........................................................................................................................................................12-11
12.2.1 Version Description..........................................................................................................................12-12
12.2.2 Application.......................................................................................................................................12-12
12.2.3 Functions and Features.....................................................................................................................12-13
12.2.4 Working Principle and Signal Flow.................................................................................................12-15
12.2.5 Front Panel.......................................................................................................................................12-16
12.2.6 Jumpers and DIP Switches...............................................................................................................12-18
12.2.7 Valid Slots........................................................................................................................................12-18
12.2.8 Feature Code....................................................................................................................................12-18
12.2.9 Parameter Settings............................................................................................................................12-19
12.2.10 Technical Specifications................................................................................................................12-19
12.3 IDL4..........................................................................................................................................................12-20
12.3.1 Version Description..........................................................................................................................12-21
12.3.2 Application.......................................................................................................................................12-21
12.3.3 Functions and Features.....................................................................................................................12-22
12.3.4 Working Principle and Signal Flow.................................................................................................12-23
12.3.5 Front Panel.......................................................................................................................................12-25
12.3.6 Jumpers and DIP Switches...............................................................................................................12-27
12.3.7 Valid Slots........................................................................................................................................12-27
12.3.8 Feature Code....................................................................................................................................12-27
12.3.9 Board Protection...............................................................................................................................12-28
12.3.10 Parameter Settings..........................................................................................................................12-28
12.3.11 Technical Specifications................................................................................................................12-28
12.4 IDQ1..........................................................................................................................................................12-29
12.4.1 Version Description..........................................................................................................................12-30
12.4.2 Application.......................................................................................................................................12-30
12.4.3 Functions and Features.....................................................................................................................12-31
12.4.4 Working Principle and Signal Flow.................................................................................................12-32
12.4.5 Front Panel.......................................................................................................................................12-34
12.4.6 Jumpers and DIP Switches...............................................................................................................12-36
12.4.7 Valid Slots........................................................................................................................................12-36
12.4.8 Feature Code....................................................................................................................................12-36
12.4.9 Board Protection...............................................................................................................................12-37
12.4.10 Parameter Settings..........................................................................................................................12-37
12.4.11 Technical Specifications................................................................................................................12-37
Contents
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
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Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
13 RPR Boards..............................................................................................................................13-1
13.1 EGR2...........................................................................................................................................................13-2
13.1.1 Version Description............................................................................................................................13-2
13.1.2 Application.........................................................................................................................................13-2
13.1.3 Functions and Features.......................................................................................................................13-3
13.1.4 Working Principle and Signal Flow...................................................................................................13-7
13.1.5 Front Panel......................................................................................................................................... 13-9
13.1.6 Jumpers and DIP Switches...............................................................................................................13-11
13.1.7 Valid Slots........................................................................................................................................13-11
13.1.8 Feature Code....................................................................................................................................13-11
13.1.9 Parameter Settings............................................................................................................................13-12
13.1.10 Technical Specifications................................................................................................................13-12
13.2 EMR0........................................................................................................................................................13-17
13.2.1 Version Description..........................................................................................................................13-18
13.2.2 Application.......................................................................................................................................13-18
13.2.3 Functions and Features.....................................................................................................................13-19
13.2.4 Working Principle and Signal Flow.................................................................................................13-22
13.2.5 Front Panel.......................................................................................................................................13-25
13.2.6 Jumpers and DIP Switches...............................................................................................................13-27
13.2.7 Valid Slots........................................................................................................................................13-27
13.2.8 Feature Code....................................................................................................................................13-28
13.2.9 Parameter Settings............................................................................................................................13-28
13.2.10 Technical Specifications................................................................................................................13-29
14 SAN Boards.............................................................................................................................14-1
14.1 MST4...........................................................................................................................................................14-2
14.1.1 Version Description............................................................................................................................14-2
14.1.2 Application.........................................................................................................................................14-2
14.1.3 Functions and Features.......................................................................................................................14-3
14.1.4 Working Principle and Signal Flow...................................................................................................14-4
14.1.5 Front Panel......................................................................................................................................... 14-7
14.1.6 Jumpers and DIP Switches.................................................................................................................14-8
14.1.7 Valid Slots..........................................................................................................................................14-8
14.1.8 Feature Code...................................................................................................................................... 14-8
14.1.9 Parameter Settings..............................................................................................................................14-9
14.1.10 Technical Specifications.................................................................................................................. 14-9
15 Microwave Boards..................................................................................................................15-1
15.1 IFSD1..........................................................................................................................................................15-2
15.1.1 Version Description............................................................................................................................15-2
15.1.2 Application.........................................................................................................................................15-2
15.1.3 Functions and Features.......................................................................................................................15-3
15.1.4 Working Principle and Signal Flow...................................................................................................15-5
15.1.5 Front Panel......................................................................................................................................... 15-6
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15.1.6 Jumpers and DIP Switches.................................................................................................................15-9
15.1.7 Valid Slots..........................................................................................................................................15-9
15.1.8 Feature Code......................................................................................................................................15-9
15.1.9 Board Protection.................................................................................................................................15-9
15.1.10 Parameter Settings............................................................................................................................15-9
15.1.11 Technical Specifications................................................................................................................15-11
15.2 RPWR........................................................................................................................................................15-12
15.2.1 Version Description..........................................................................................................................15-13
15.2.2 Application.......................................................................................................................................15-13
15.2.3 Functions and Features.....................................................................................................................15-14
15.2.4 Working Principle and Signal Flow.................................................................................................15-15
15.2.5 Front Panel.......................................................................................................................................15-16
15.2.6 Valid Slots........................................................................................................................................15-18
15.2.7 Feature Code....................................................................................................................................15-18
15.2.8 Technical Specifications..................................................................................................................15-18
15.3 ODU..........................................................................................................................................................15-19
16 WDM Boards...........................................................................................................................16-1
16.1 CMR2..........................................................................................................................................................16-2
16.1.1 Version Description............................................................................................................................16-2
16.1.2 Application.........................................................................................................................................16-2
16.1.3 Functions and Features.......................................................................................................................16-3
16.1.4 Working Principle and Signal Flow...................................................................................................16-3
16.1.5 Front Panel.........................................................................................................................................16-4
16.1.6 Valid Slots..........................................................................................................................................16-6
16.1.7 Feature Code......................................................................................................................................16-6
16.1.8 Technical Specifications....................................................................................................................16-7
16.2 CMR4..........................................................................................................................................................16-8
16.2.1 Version Description............................................................................................................................16-8
16.2.2 Application.........................................................................................................................................16-8
16.2.3 Functions and Features.......................................................................................................................16-9
16.2.4 Working Principle and Signal Flow...................................................................................................16-9
16.2.5 Front Panel.......................................................................................................................................16-11
16.2.6 Valid Slots........................................................................................................................................16-12
16.2.7 Feature Code....................................................................................................................................16-12
16.2.8 Technical Specifications..................................................................................................................16-13
16.3 MR2...........................................................................................................................................................16-14
16.3.1 Version Description..........................................................................................................................16-15
16.3.2 Application.......................................................................................................................................16-15
16.3.3 Functions and Features.....................................................................................................................16-16
16.3.4 Working Principle and Signal Flow.................................................................................................16-16
16.3.5 Front Panel.......................................................................................................................................16-17
16.3.6 Valid Slots........................................................................................................................................16-19
Contents
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Hardware Description
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Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
16.3.7 Feature Code....................................................................................................................................16-19
16.3.8 Technical Specifications..................................................................................................................16-20
16.4 MR2A........................................................................................................................................................16-21
16.4.1 Version Description..........................................................................................................................16-21
16.4.2 Application.......................................................................................................................................16-21
16.4.3 Functions and Features.....................................................................................................................16-22
16.4.4 Working Principle and Signal Flow.................................................................................................16-23
16.4.5 Front Panel.......................................................................................................................................16-24
16.4.6 Valid Slots........................................................................................................................................16-26
16.4.7 Technical Specifications..................................................................................................................16-26
16.5 MR2C........................................................................................................................................................16-27
16.5.1 Version Description..........................................................................................................................16-28
16.5.2 Application.......................................................................................................................................16-28
16.5.3 Functions and Features.....................................................................................................................16-28
16.5.4 Working Principle and Signal Flow.................................................................................................16-30
16.5.5 Front Panel.......................................................................................................................................16-30
16.5.6 Valid Slots........................................................................................................................................16-32
16.5.7 Technical Specifications..................................................................................................................16-32
16.6 MR4...........................................................................................................................................................16-33
16.6.1 Version Description..........................................................................................................................16-34
16.6.2 Application.......................................................................................................................................16-34
16.6.3 Functions and Features.....................................................................................................................16-34
16.6.4 Working Principle and Signal Flow.................................................................................................16-35
16.6.5 Front Panel.......................................................................................................................................16-36
16.6.6 Valid Slots........................................................................................................................................16-37
16.6.7 Feature Code....................................................................................................................................16-37
16.6.8 Technical Specifications..................................................................................................................16-38
16.7 LWX..........................................................................................................................................................16-39
16.7.1 Version Description..........................................................................................................................16-40
16.7.2 Application.......................................................................................................................................16-40
16.7.3 Functions and Features.....................................................................................................................16-40
16.7.4 Working Principle and Signal Flow.................................................................................................16-41
16.7.5 Front Panel.......................................................................................................................................16-43
16.7.6 Valid Slots........................................................................................................................................16-45
16.7.7 Feature Code....................................................................................................................................16-45
16.7.8 Parameter Settings............................................................................................................................16-45
16.7.9 Technical Specifications..................................................................................................................16-46
16.8 FIB.............................................................................................................................................................16-49
16.8.1 Version Description..........................................................................................................................16-49
16.8.2 Application.......................................................................................................................................16-49
16.8.3 Functions and Features.....................................................................................................................16-50
16.8.4 Working Principle and Signal Flow.................................................................................................16-50
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16.8.5 Front Panel.......................................................................................................................................16-50
16.8.6 Valid Slots........................................................................................................................................16-52
16.8.7 Technical Specifications.................................................................................................................. 16-52
17 Auxiliary Boards.....................................................................................................................17-1
17.1 AUX............................................................................................................................................................17-2
17.1.1 Version Description............................................................................................................................17-2
17.1.2 Application.........................................................................................................................................17-2
17.1.3 Functions and Features.......................................................................................................................17-2
17.1.4 Working Principle and Signal Flow...................................................................................................17-4
17.1.5 Jumpers...............................................................................................................................................17-5
17.1.6 Front Panel.........................................................................................................................................17-6
17.1.7 Valid Slots........................................................................................................................................17-15
17.1.8 Technical Specifications.................................................................................................................. 17-15
17.2 FAN...........................................................................................................................................................17-15
17.2.1 Version Description..........................................................................................................................17-16
17.2.2 Application.......................................................................................................................................17-16
17.2.3 Functions and Features.....................................................................................................................17-16
17.2.4 Working Principle and Signal Flow.................................................................................................17-17
17.2.5 Front Panel....................................................................................................................................... 17-18
17.2.6 Valid Slots........................................................................................................................................17-18
17.2.7 Technical Specifications.................................................................................................................. 17-19
18 Optical Amplifier Boards and Dispersion Compensation Boards...............................18-1
18.1 BA2.............................................................................................................................................................18-2
18.1.1 Version Description............................................................................................................................18-2
18.1.2 Application.........................................................................................................................................18-2
18.1.3 Functions and Features.......................................................................................................................18-3
18.1.4 Working Principle and Signal Flow...................................................................................................18-4
18.1.5 Front Panel.........................................................................................................................................18-5
18.1.6 Valid Slots..........................................................................................................................................18-8
18.1.7 Feature Code......................................................................................................................................18-9
18.1.8 Technical Specifications....................................................................................................................18-9
18.2 BPA...........................................................................................................................................................18-10
18.2.1 Version Description..........................................................................................................................18-11
18.2.2 Application.......................................................................................................................................18-11
18.2.3 Functions and Features.....................................................................................................................18-11
18.2.4 Working Principle and Signal Flow.................................................................................................18-12
18.2.5 Front Panel....................................................................................................................................... 18-14
18.2.6 Valid Slots........................................................................................................................................18-15
18.2.7 Feature Code.................................................................................................................................... 18-16
18.2.8 Technical Specifications.................................................................................................................. 18-16
18.3 COA.......................................................................................................................................................... 18-17
18.3.1 Version Description..........................................................................................................................18-18
Contents
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Hardware Description
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18.3.2 Application.......................................................................................................................................18-18
18.3.3 Functions and Features.....................................................................................................................18-19
18.3.4 Working Principle and Signal Flow.................................................................................................18-21
18.3.5 Front Panel.......................................................................................................................................18-23
18.3.6 Valid Slots........................................................................................................................................18-27
18.3.7 Feature Code....................................................................................................................................18-28
18.3.8 Technical Specifications..................................................................................................................18-28
18.4 RPC01.......................................................................................................................................................18-29
18.4.1 Version Description..........................................................................................................................18-30
18.4.2 Application.......................................................................................................................................18-30
18.4.3 Functions and Features.....................................................................................................................18-30
18.4.4 Working Principle and Signal Flow.................................................................................................18-31
18.4.5 Front Panel.......................................................................................................................................18-33
18.4.6 Valid Slots........................................................................................................................................18-34
18.4.7 Jumpers and DIP Switches...............................................................................................................18-34
18.4.8 Feature Code....................................................................................................................................18-35
18.4.9 Parameter Settings............................................................................................................................18-35
18.4.10 Technical Specifications................................................................................................................18-36
18.5 RPC02.......................................................................................................................................................18-37
18.5.1 Version Description..........................................................................................................................18-37
18.5.2 Application.......................................................................................................................................18-38
18.5.3 Functions and Features.....................................................................................................................18-38
18.5.4 Working Principle and Signal Flow.................................................................................................18-38
18.5.5 Front Panel.......................................................................................................................................18-40
18.5.6 Valid Slots........................................................................................................................................18-41
18.5.7 Jumpers and DIP Switches...............................................................................................................18-41
18.5.8 Feature Code....................................................................................................................................18-42
18.5.9 Parameter Settings............................................................................................................................18-42
18.5.10 Technical Specifications................................................................................................................18-43
18.6 OBU1........................................................................................................................................................18-44
18.6.1 Version Description..........................................................................................................................18-44
18.6.2 Application.......................................................................................................................................18-44
18.6.3 Functions and Features.....................................................................................................................18-45
18.6.4 Working Principle and Signal Flow.................................................................................................18-45
18.6.5 Front Panel.......................................................................................................................................18-47
18.6.6 Valid Slots........................................................................................................................................18-48
18.6.7 Feature Code....................................................................................................................................18-48
18.6.8 Parameter Settings............................................................................................................................18-49
18.6.9 Technical Specifications..................................................................................................................18-49
18.7 DCU..........................................................................................................................................................18-50
18.7.1 Version Description..........................................................................................................................18-51
18.7.2 Application.......................................................................................................................................18-51
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18.7.3 Functions and Features.....................................................................................................................18-52
18.7.4 Working Principle and Signal Flow.................................................................................................18-53
18.7.5 Front Panel....................................................................................................................................... 18-53
18.7.6 Valid Slots........................................................................................................................................18-56
18.7.7 Feature Code.................................................................................................................................... 18-56
18.7.8 Technical Specifications.................................................................................................................. 18-57
19 Power Boards...........................................................................................................................19-1
19.1 UPM............................................................................................................................................................19-2
19.1.1 Version Description............................................................................................................................19-2
19.1.2 Application.........................................................................................................................................19-2
19.1.3 Functions and Features.......................................................................................................................19-3
19.1.4 Working Principle and Signal Flow...................................................................................................19-5
19.1.5 Front Panel.........................................................................................................................................19-5
19.1.6 Valid Slots..........................................................................................................................................19-7
19.1.7 Technical Specifications....................................................................................................................19-8
19.2 PIU..............................................................................................................................................................19-9
19.2.1 Version Description............................................................................................................................19-9
19.2.2 Application.......................................................................................................................................19-10
19.2.3 Functions and Features.....................................................................................................................19-10
19.2.4 Working Principle and Signal Flow.................................................................................................19-11
19.2.5 Front Panel....................................................................................................................................... 19-11
19.2.6 Valid Slots........................................................................................................................................19-13
19.2.7 Technical Specifications.................................................................................................................. 19-13
19.3 PIUA..........................................................................................................................................................19-13
19.3.1 Version Description..........................................................................................................................19-14
19.3.2 Application.......................................................................................................................................19-14
19.3.3 Functions and Features.....................................................................................................................19-15
19.3.4 Working Principle and Signal Flow.................................................................................................19-15
19.3.5 Front Panel....................................................................................................................................... 19-16
19.3.6 Valid Slots........................................................................................................................................19-17
19.3.7 Technical Specifications.................................................................................................................. 19-17
19.4 PIUB..........................................................................................................................................................19-18
19.4.1 Version Description..........................................................................................................................19-18
19.4.2 Application.......................................................................................................................................19-18
19.4.3 Functions and Features.....................................................................................................................19-19
19.4.4 Working Principle and Signal Flow.................................................................................................19-19
19.4.5 Front Panel....................................................................................................................................... 19-20
19.4.6 Valid Slots........................................................................................................................................19-22
19.4.7 Technical Specifications.................................................................................................................. 19-22
20 Pluggable Optical Module...................................................................................................20-1
20.1 Overview.....................................................................................................................................................20-2
20.2 SFP/eSFP.....................................................................................................................................................20-3
Contents
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
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Issue 01 (2010-01-15)
20.3 XFP..............................................................................................................................................................20-7
20.4 CWDM/DWDM..........................................................................................................................................20-8
21 Cables.......................................................................................................................................21-1
21.1 Fiber Jumper................................................................................................................................................21-2
21.1.1 Categories of the Fiber Jumpers.........................................................................................................21-2
21.1.2 Connector...........................................................................................................................................21-2
21.2 Power Cable and Grounding Cable.............................................................................................................21-5
21.2.1 Power Cable of the Cabinet................................................................................................................21-5
21.2.2 Grounding Cable of the Cabinet Door...............................................................................................21-9
21.2.3 Subrack Power Cable.........................................................................................................................21-9
21.2.4 COA Power Cable............................................................................................................................21-11
21.3 Alarm Cable..............................................................................................................................................21-13
21.3.1 Cabinet Indicator Cable....................................................................................................................21-13
21.3.2 Indicator Cascading Cable Between Subracks or Alarm Cascading Cable Between the OptiX OSN
Equipment...................................................................................................................................................21-15
21.3.3 Alarm Cascading Cable Between the OptiX OSN Equipment and the Other Huawei Transmission
Equipment...................................................................................................................................................21-16
21.3.4 Alarm Input/Output Cable................................................................................................................21-18
21.4 Management Cable....................................................................................................................................21-19
21.4.1 OAM Serial Port Cable....................................................................................................................21-20
21.4.2 Serial 1 to 4/F1/F&f Serial Port Cable.............................................................................................21-21
21.4.3 RS-232/RS-422 Serial Port Cable....................................................................................................21-23
21.4.4 Ordinary Telephone Line.................................................................................................................21-24
21.4.5 COA Cascading Cable.....................................................................................................................21-25
21.4.6 Straight Through Cable....................................................................................................................21-27
21.4.7 Crossover Cable...............................................................................................................................21-28
21.5 Signal Cable..............................................................................................................................................21-29
21.5.1 75-ohm 8xE1 Cable..........................................................................................................................21-30
21.5.2 120-ohm 8xE1 Cable........................................................................................................................21-32
21.5.3 E3/T3/STM-1 Cable.........................................................................................................................21-34
21.5.4 Framed E1 Cable..............................................................................................................................21-36
21.5.5 Nx64 kbit/s Cable.............................................................................................................................21-36
21.6 Clock Cable...............................................................................................................................................21-54
21.6.1 Clock Cable......................................................................................................................................21-55
21.6.2 One-Channel Clock Transit Cable and Two-Channel Clock Transit Cable....................................21-56
22 Indicators.................................................................................................................................22-1
22.1 Indicators on the Cabinet.............................................................................................................................22-2
22.2 Alarm Indicators on the Boards..................................................................................................................22-2
23 Labels........................................................................................................................................23-1
23.1 Safety Labels...............................................................................................................................................23-2
23.1.1 Label Description...............................................................................................................................23-2
23.1.2 Label Position.....................................................................................................................................23-3
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23.2 Engineering Labels......................................................................................................................................23-6
24 Board Information Quick Reference..................................................................................24-1
24.1 Compatibility of Board Versions with the Products...................................................................................24-2
24.2 Quick Reference Table for Optical Interfaces.............................................................................................24-8
24.2.1 Common Parameters Specified for Optical Interfaces of SDH Boards.............................................24-8
24.2.2 Common Parameters Specified for Optical Interfaces of Packet Boards.........................................24-15
24.2.3 Common Parameters Specified for Optical Interfaces of Data Boards ...........................................24-17
24.3 Quick Reference of Board Functions........................................................................................................24-19
24.3.1 Information Quick Reference of SDH Boards.................................................................................24-19
24.3.2 Information Quick Reference of PDH Boards.................................................................................24-22
24.3.3 Information Quick Reference of Data Boards..................................................................................24-23
24.3.4 Information Quick Reference of Packet Boards...............................................................................24-25
24.4 Loopback Capability of the Boards...........................................................................................................24-28
24.5 Protection Schemes Supported by Each Board.........................................................................................24-37
24.6 Quick Reference of Power Consumption and Weight of Each Board......................................................24-44
25 Parameter Settings.................................................................................................................25-1
25.1 Packet Boards..............................................................................................................................................25-3
25.2 Dual-Plane Bridging Boards.......................................................................................................................25-4
25.3 CES Boards.................................................................................................................................................25-4
25.4 Data Boards.................................................................................................................................................25-6
25.4.1 SDH Parameters.................................................................................................................................25-6
25.4.2 Ethernet Parameters............................................................................................................................25-8
25.4.3 ATM Parameters................................................................................................................................25-9
25.5 SDH Processing Boards............................................................................................................................25-10
25.6 PDH Boards...............................................................................................................................................25-11
25.7 WDM Boards............................................................................................................................................25-13
25.8 Cross-Connect and Timing Units..............................................................................................................25-20
25.9 Optical Amplifier Boards..........................................................................................................................25-25
A Glossary.....................................................................................................................................A-1
B Acronyms and Abbreviations.................................................................................................B-1
Contents
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
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Issue 01 (2010-01-15)
Figures
Figure 1-1 Appearance of the OptiX OSN 3500 that is installed in the 300 mm ETSI cabinet...........................1-2
Figure 1-2 Appearance of the general OptiX OSN 3500 subrack and enhanced OptiX OSN 3500 subrack (1100
w)...........................................................................................................................................................................1-3
Figure 1-3 Appearance of the enhanced OptiX OSN 3500 subrack (2300 W)....................................................1-4
Figure 2-1 Appearances of the T63 cabinet and N63E cabinet............................................................................2-3
Figure 2-2 Locations of the cable holes at the top of the T63 cabinet.................................................................2-4
Figure 2-3 Locations of the cable holes at the bottom of the T63 cabinet...........................................................2-5
Figure 2-4 Locations of the cable holes at the top of the N63E cabinet..............................................................2-5
Figure 2-5 Locations of the cable holes at the bottom of the N63E cabinet........................................................2-6
Figure 2-6 ETSI cabinet.......................................................................................................................................2-7
Figure 2-7 Front panel of the N1PDU..................................................................................................................2-8
Figure 2-8 Front panel of the TN51PDU ..........................................................................................................2-10
Figure 3-1 Structure of the OptiX OSN 3500 subrack.........................................................................................3-3
Figure 3-2 Slot layout of the OptiX OSN 3500 subrack......................................................................................3-4
Figure 3-3 Dual-slot layout of the OptiX OSN 3500 subrack..............................................................................3-5
Figure 3-4 Slot access capacity when the N1PSXCS board is used....................................................................3-7
Figure 3-5 Slot access capacity when the N2PSXCSA board is used (single slots)............................................3-7
Figure 3-6 Slot access capacity when the N2PSXCSA board is used (double slots)...........................................3-8
Figure 3-7 Access capacity of each slot when the N1PSXCS board is used.......................................................3-8
Figure 3-8 Access capacity of slots when the N2PSXCSA is used.....................................................................3-9
Figure 3-9 Ventilation mode of the OptiX OSN 3500.......................................................................................3-10
Figure 3-10 Appearance of the cable distribution plate.....................................................................................3-11
Figure 3-11 Appearance of the fiber spool box..................................................................................................3-11
Figure 4-1 Bar code of a board.............................................................................................................................4-4
Figure 5-1 Position of the PSXCS(A) in the system............................................................................................5-3
Figure 5-2 Functional block diagram of the PSXCS(A)......................................................................................5-5
Figure 5-3 Front panel of the PSXCS(A).............................................................................................................5-7
Figure 5-4 Position of the GSCC in the system.................................................................................................5-11
Figure 5-5 Functional block diagram of the GSCC...........................................................................................5-13
Figure 5-6 Position of these orderwire bytes in the SDH frame........................................................................5-14
Figure 5-7 Front panel of the N4GSCC/N6GSCC.............................................................................................5-15
Figure 5-8 Position of the jumpers of the N4GSCC..........................................................................................5-17
Figure 5-9 Position of the jumpers of the N6GSCC..........................................................................................5-19
Figure 6-1 Networking and application of the PEX1...........................................................................................6-3
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description Figures
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Figure 6-2 Functional block diagram of the PEX1..............................................................................................6-8
Figure 6-3 Front panel of the N1PEX1..............................................................................................................6-10
Figure 6-4 Front panel of the N2PEX1..............................................................................................................6-11
Figure 6-5 Networking and application of the PEX2.........................................................................................6-17
Figure 6-6 Functional block diagram of the PEX2............................................................................................6-21
Figure 6-7 Front panel of the PEX2...................................................................................................................6-24
Figure 6-8 Networking and application of the PEG8.........................................................................................6-28
Figure 6-9 Functional block diagram of the PEG8............................................................................................6-32
Figure 6-10 Front panel of the PEG8.................................................................................................................6-35
Figure 6-11 Networking and application of the PEG16.....................................................................................6-40
Figure 6-12 Functional block diagram of the PEG16........................................................................................6-43
Figure 6-13 Front panel of the PEG16...............................................................................................................6-45
Figure 6-14 Networking and application of the PETF8.....................................................................................6-50
Figure 6-15 Functional block diagram of the PETF8.........................................................................................6-52
Figure 6-16 Front panel of the PETF8...............................................................................................................6-54
Figure 6-17 Networking and application of the PEFF8.....................................................................................6-57
Figure 6-18 Functional block diagram of the PEFF8.........................................................................................6-60
Figure 6-19 Front panel of the PEFF8................................................................................................................6-62
Figure 7-1 Networking and application of the EDQ41........................................................................................7-3
Figure 7-2 Functional block diagram of the EDQ41............................................................................................7-7
Figure 7-3 Front panel of the EDQ41................................................................................................................7-10
Figure 8-1 Networking and application of the CQ1.............................................................................................8-3
Figure 8-2 Functional block diagram of the CQ1 ...............................................................................................8-5
Figure 8-3 Front panel of the CQ1.......................................................................................................................8-7
Figure 8-4 Networking and application of the MD12........................................................................................8-12
Figure 8-5 Functional block diagram of the MD12 ..........................................................................................8-13
Figure 8-6 Front panel of the MD12..................................................................................................................8-15
Figure 8-7 Networking and application of the MD75........................................................................................8-20
Figure 8-8 Functional block diagram of the MD75 ..........................................................................................8-21
Figure 8-9 Front panel of the MD75..................................................................................................................8-23
Figure 9-1 Networking and application of the SL1..............................................................................................9-5
Figure 9-2 Functional block diagram of the SL1.................................................................................................9-7
Figure 9-3 Front panel of the SL1......................................................................................................................9-10
Figure 9-4 Networking and application of the SL1A.........................................................................................9-14
Figure 9-5 Functional block diagram of the SL1A............................................................................................9-16
Figure 9-6 Front panel of the SL1A...................................................................................................................9-19
Figure 9-7 Networking and application of the SLQ1.........................................................................................9-24
Figure 9-8 Functional block diagram of the SLQ1............................................................................................9-26
Figure 9-9 Front panel of the SLQ1...................................................................................................................9-28
Figure 9-10 Networking and application of the SLQ1A....................................................................................9-32
Figure 9-11 Functional block diagram of the SLQ1A.......................................................................................9-34
Figure 9-12 Front panel of the SLQ1A..............................................................................................................9-36
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Figure 9-13 Networking and application of the SLO1.......................................................................................9-41
Figure 9-14 Functional block diagram of the SLO1..........................................................................................9-43
Figure 9-15 Front panel of the SLO1.................................................................................................................9-45
Figure 9-16 Networking and application of the SLT1.......................................................................................9-49
Figure 9-17 Functional block diagram of the SLT1...........................................................................................9-51
Figure 9-18 Front panel of the SLT1..................................................................................................................9-54
Figure 9-19 Networking and application of the SLH1.......................................................................................9-58
Figure 9-20 Functional block diagram of the SLH1 when the SLH1 works with the EU08.............................9-60
Figure 9-21 Functional block diagram of the SLH1 when the SLH1 works with the OU08.............................9-61
Figure 9-22 Front panel of the SLH1.................................................................................................................9-63
Figure 9-23 TPS protection provided by the SLH1...........................................................................................9-64
Figure 9-24 Slot configuration for two 1:3 TPS protection groups of the SLH1...............................................9-65
Figure 9-25 Networking and application of the SEP1.......................................................................................9-68
Figure 9-26 Functional block diagram of the SEP1...........................................................................................9-71
Figure 9-27 Functional block diagram of the SEP when the SEP works with the EU08..................................9-72
Figure 9-28 Functional block diagram of the SEP when the SEP works with the OU08..................................9-73
Figure 9-29 Front panel of the SEP1..................................................................................................................9-75
Figure 9-30 TPS protection provided by the SEP..............................................................................................9-77
Figure 9-31 Slot configuration for the two 1:3 TPS protection groups of the SEP...........................................9-78
Figure 9-32 Networking and application of the SL4..........................................................................................9-81
Figure 9-33 Functional block diagram of the SL4.............................................................................................9-83
Figure 9-34 Front panel of the SL4....................................................................................................................9-86
Figure 9-35 Networking and application of the SL4A.......................................................................................9-90
Figure 9-36 Functional block diagram of the SL4A..........................................................................................9-92
Figure 9-37 Front panel of the SL4A.................................................................................................................9-94
Figure 9-38 Networking and application of the SLD4.......................................................................................9-99
Figure 9-39 Functional block diagram of the SLD4........................................................................................ 9-101
Figure 9-40 Front panel of the SLD4...............................................................................................................9-103
Figure 9-41 Networking and application of the SLD4A..................................................................................9-107
Figure 9-42 Functional block diagram of the SLD4A..................................................................................... 9-109
Figure 9-43 Front panel of the SLD4A............................................................................................................9-112
Figure 9-44 Networking and application of the SLQ4.....................................................................................9-117
Figure 9-45 Functional block diagram of the SLQ4........................................................................................ 9-119
Figure 9-46 Front panel of the SLQ4...............................................................................................................9-121
Figure 9-47 Networking and application of the SLQ4A..................................................................................9-125
Figure 9-48 Functional block diagram of the SLQ4A..................................................................................... 9-127
Figure 9-49 Front panel of the SLQ4A............................................................................................................9-130
Figure 9-50 Networking and application of the SL16......................................................................................9-135
Figure 9-51 Functional block diagram of the SL16.........................................................................................9-137
Figure 9-52 Front panel of the SL16................................................................................................................9-139
Figure 9-53 Networking and application of the SL16A...................................................................................9-145
Figure 9-54 Functional block diagram of the N1SL16A/N2SL16A/N3SL16A.............................................. 9-147
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Figure 9-55 Front panel of the SL16A.............................................................................................................9-149
Figure 9-56 Networking and application of the SLD16...................................................................................9-154
Figure 9-57 Functional block diagram of the SLD16......................................................................................9-156
Figure 9-58 Front panel of the SLD16.............................................................................................................9-158
Figure 9-59 Networking and application of the SLQ16...................................................................................9-163
Figure 9-60 Functional block diagram of the SLQ16......................................................................................9-165
Figure 9-61 Front panel of the N1SLQ16........................................................................................................9-168
Figure 9-62 Front panel of the N2SLQ16........................................................................................................9-169
Figure 9-63 Networking and application of the SLO16...................................................................................9-173
Figure 9-64 Functional block diagram of the SLO16......................................................................................9-176
Figure 9-65 Front panel of the SLO16.............................................................................................................9-178
Figure 9-66 Networking and application of the SF16......................................................................................9-182
Figure 9-67 Functional block diagram of the SF16.........................................................................................9-184
Figure 9-68 Front panel of the SF16................................................................................................................9-187
Figure 9-69 Networking and application of the SL64......................................................................................9-192
Figure 9-70 Functional block diagram of the N1SL64/N2SL64......................................................................9-195
Figure 9-71 Appearance of the front panel of the SL64...................................................................................9-197
Figure 9-72 Networking and application of the SLD64...................................................................................9-203
Figure 9-73 Functional block diagram of the SLD64......................................................................................9-205
Figure 9-74 Front panel of the SLD64.............................................................................................................9-207
Figure 9-75 Networking and application of the SF64......................................................................................9-211
Figure 9-76 Functional block diagram of the SF64.........................................................................................9-213
Figure 9-77 Front panel of the SF64................................................................................................................9-216
Figure 9-78 Networking and application of the SF64A...................................................................................9-220
Figure 9-79 Functional block diagram of the SF64A.......................................................................................9-222
Figure 9-80 Front panel of the SF64A.............................................................................................................9-225
Figure 9-81 Networking and application of the SLQ41...................................................................................9-229
Figure 9-82 Functional block diagram of the SLQ41......................................................................................9-232
Figure 9-83 Front panel of the SLQ41.............................................................................................................9-234
Figure 9-84 Functional block diagram of the EU04.........................................................................................9-239
Figure 9-85 Front panel of the EU04...............................................................................................................9-240
Figure 9-86 Functional block diagram of the EU08.........................................................................................9-243
Figure 9-87 Front panel of the EU08...............................................................................................................9-244
Figure 9-88 Functional block diagram of the OU08........................................................................................9-248
Figure 9-89 Front panel of the N1OU08..........................................................................................................9-249
Figure 9-90 Front panel of the N2OU08..........................................................................................................9-250
Figure 10-1 Networking and application of the PQ1.........................................................................................10-4
Figure 10-2 Functional block diagram of the PQ1.............................................................................................10-6
Figure 10-3 Functional block diagram of the mapping/demapping module......................................................10-6
Figure 10-4 Front panel of the PQ1....................................................................................................................10-8
Figure 10-5 TPS protection provided by the PQ1............................................................................................10-11
Figure 10-6 Slot configuration for the 1:8 TPS protection of the PQ1............................................................10-12
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Figure 10-7 Networking and application of the PQM......................................................................................10-14
Figure 10-8 Functional block diagram of the PQM.........................................................................................10-16
Figure 10-9 Functional block diagram of the mapping/demapping module....................................................10-16
Figure 10-10 Front panel of the PQM..............................................................................................................10-18
Figure 10-11 TPS protection provided by the PQM (E1 services are provided as an example)......................10-20
Figure 10-12 Slot configuration for the 1:8 TPS protection of the PQM.........................................................10-21
Figure 10-13 Networking and application of the PL3......................................................................................10-24
Figure 10-14 Functional block diagram of the PL3.........................................................................................10-25
Figure 10-15 Functional block diagram of the mapping/demapping module..................................................10-26
Figure 10-16 Front panel of the PL3................................................................................................................10-28
Figure 10-17 TPS protection provided by the PL3 in the OptiX OSN 1500B subrack...................................10-30
Figure 10-18 Slot configuration for the two 1:3 TPS protection groups of the PL3........................................10-31
Figure 10-19 Networking and application of the PL3A...................................................................................10-34
Figure 10-20 Functional block diagram of the PL3A......................................................................................10-36
Figure 10-21 Functional block diagram of the mapping/demapping module..................................................10-36
Figure 10-22 Front panel of the PL3A.............................................................................................................10-38
Figure 10-23 Networking and application of the PD3.....................................................................................10-42
Figure 10-24 Functional block diagram of the PD3.........................................................................................10-43
Figure 10-25 Functional block diagram of the E3/T3 mapping/demapping module.......................................10-44
Figure 10-26 Front panel of the PD3................................................................................................................10-46
Figure 10-27 TPS protection provided by the PD3..........................................................................................10-48
Figure 10-28 Slot configuration for the 1:3 TPS protection of the PD3..........................................................10-49
Figure 10-29 Networking and application of the PQ3.....................................................................................10-51
Figure 10-30 Functional block diagram of the PQ3.........................................................................................10-53
Figure 10-31 Functional block diagram of the E3/T3 mapping/demapping module.......................................10-53
Figure 10-32 Front panel of the PQ3................................................................................................................10-55
Figure 10-33 TPS protection provided by the PQ3..........................................................................................10-57
Figure 10-34 Slot configuration for the two 1:3 TPS protection groups of the PQ3.......................................10-58
Figure 10-35 Networking and application of the DX1.....................................................................................10-61
Figure 10-36 Functional block diagram of the DX1........................................................................................10-62
Figure 10-37 Front panel of the DX1...............................................................................................................10-64
Figure 10-38 TPS protection provided by the DX1.........................................................................................10-66
Figure 10-39 Slot configuration for the 1:8 TPS protection of the DX1.........................................................10-67
Figure 10-40 Networking and application of the DXA....................................................................................10-69
Figure 10-41 Functional block diagram of the DXA.......................................................................................10-70
Figure 10-42 Front panel of the DXA..............................................................................................................10-72
Figure 10-43 Networking and application of the SPQ4...................................................................................10-75
Figure 10-44 Functional block diagram of the SPQ4.......................................................................................10-77
Figure 10-45 Functional block diagram of the mapping/demapping module..................................................10-77
Figure 10-46 Functional block diagram of the SDH overhead processing module.........................................10-78
Figure 10-47 Front panel of the SPQ4.............................................................................................................10-81
Figure 10-48 TPS protection provided by the SPQ4........................................................................................10-83
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Figure 10-49 Slot configuration for the two 1:3 TPS protection groups of the SPQ4.....................................10-84
Figure 10-50 Functional block diagram of the D12B......................................................................................10-86
Figure 10-51 Front panel of the D12B.............................................................................................................10-87
Figure 10-52 Functional block diagram of the D12S.......................................................................................10-91
Figure 10-53 Front panel of the D12S..............................................................................................................10-92
Figure 10-54 Functional block diagram of the D75S.......................................................................................10-96
Figure 10-55 Front panel of the D75S..............................................................................................................10-97
Figure 10-56 Functional block diagram of the D34S.....................................................................................10-101
Figure 10-57 Front panel of the D34S............................................................................................................10-102
Figure 10-58 Functional block diagram of the C34S.....................................................................................10-105
Figure 10-59 Front panel of the C34S............................................................................................................10-106
Figure 10-60 Functional block diagram of the MU04................................................................................... 10-109
Figure 10-61 Front panel of the MU04..........................................................................................................10-110
Figure 10-62 Functional block diagram of the DM12................................................................................... 10-113
Figure 10-63 Front panel of the DM12..........................................................................................................10-114
Figure 10-64 Functional block diagram of the TSB4.....................................................................................10-119
Figure 10-65 Front panel of the TSB4........................................................................................................... 10-120
Figure 10-66 Functional block diagram of the TSB8.....................................................................................10-123
Figure 10-67 Front panel of the TSB8........................................................................................................... 10-124
Figure 11-1 Networking and application of the EFT8.......................................................................................11-4
Figure 11-2 Functional block diagram of the EFT8...........................................................................................11-7
Figure 11-3 Front panel of the EFT8..................................................................................................................11-9
Figure 11-4 Connection for testing the throughput specifications, packet loss ratio in the case of overloading, and
latency specifications........................................................................................................................................11-12
Figure 11-5 Connection for testing the back-to-back specifications................................................................11-12
Figure 11-6 Networking and application of the EFT8A..................................................................................11-17
Figure 11-7 Functional block diagram of the EFT8A......................................................................................11-20
Figure 11-8 Front panel of the EFT8A.............................................................................................................11-22
Figure 11-9 Connection for testing the throughput specifications, packet loss ratio in the case of overloading, and
latency specifications........................................................................................................................................11-25
Figure 11-10 Connection for testing the back-to-back specifications..............................................................11-25
Figure 11-11 Networking and application of the EGT2...................................................................................11-30
Figure 11-12 Functional block diagram of the EGT2......................................................................................11-33
Figure 11-13 Front panel of the N1EGT2/N2EGT2 that is installed with the GE optical interface................11-35
Figure 11-14 Front panel of the N2EGT2 that is installed with the GE electrical interface............................11-36
Figure 11-15 Connection for testing the throughput specifications, packet loss ratio in the case of overloading, and
latency specifications of the N1EGT2...............................................................................................................11-40
Figure 11-16 Connection for testing the back-to-back specifications of the N1EGT2....................................11-40
Figure 11-17 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications of the N2EGT2..........................................................11-43
Figure 11-18 Networking and application of the EFS0...................................................................................11-50
Figure 11-19 Functional block diagram of the EFS0.......................................................................................11-54
Figure 11-20 Front panel of the EFS0..............................................................................................................11-57
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Figure 11-21 Slot configuration for the 1:1 TPS protection for the EFS0.......................................................11-59
Figure 11-22 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications of the N4EFS0...........................................................11-60
Figure 11-23 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications of the N5EFS0...........................................................11-64
Figure 11-24 Networking and application of the EFS0A.................................................................................11-70
Figure 11-25 Functional block diagram of the EFS0A....................................................................................11-74
Figure 11-26 Front panel of the EFS0A...........................................................................................................11-76
Figure 11-27 Slot configuration for the 1:1 TPS protection for the EFS0A....................................................11-79
Figure 11-28 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications....................................................................................11-80
Figure 11-29 Networking and application of the EFS4...................................................................................11-86
Figure 11-30 Functional block diagram of the EFS4.......................................................................................11-89
Figure 11-31 Front panel of the EFS4..............................................................................................................11-92
Figure 11-32 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications of the N2EFS4...........................................................11-95
Figure 11-33 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications of the N3EFS4...........................................................11-98
Figure 11-34 Networking and application of the EGS2.................................................................................11-104
Figure 11-35 Functional block diagram of the EGS2....................................................................................11-108
Figure 11-36 Front panel of the N2EGS2/N3EGS2 that is installed with the GE optical interface..............11-110
Figure 11-37 Front panel of the N3EGS2 that is installed with the GE electrical interface..........................11-111
Figure 11-38 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications of the N2EGS2........................................................11-115
Figure 11-39 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications of the N3EGS2........................................................11-119
Figure 11-40 Networking and application of the EMS2................................................................................11-125
Figure 11-41 Functional block diagram of the EMS2....................................................................................11-129
Figure 11-42 Front panel of the EMS2 that is installed with the GE optical interface..................................11-131
Figure 11-43 Front panel of the EMS2 that is installed with the GE electrical interface..............................11-132
Figure 11-44 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications..................................................................................11-136
Figure 11-45 Networking and application of the EMS4................................................................................11-145
Figure 11-46 Functional block diagram of the EMS4....................................................................................11-149
Figure 11-47 Front panel of the EMS4 that is installed with the GE optical interface..................................11-152
Figure 11-48 Front panel of the EMS4 that is installed with the GE electrical interface..............................11-153
Figure 11-49 Normal working of the EMS4..................................................................................................11-157
Figure 11-50 Principle of the BPS protection for the EMS4.........................................................................11-158
Figure 11-51 Principle of the PPS protection for the EMS4..........................................................................11-159
Figure 11-52 Principle of the DLAG protection for the EMS4......................................................................11-160
Figure 11-53 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications..................................................................................11-162
Figure 11-54 Networking and application of the EGS4.................................................................................11-171
Figure 11-55 Functional block diagram of the EGS4....................................................................................11-175
Figure 11-56 Front panel of the N1EGS4/N3EGS4/N4EGS4 that is installed with the optical interface.....11-177
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Figure 11-57 front panel of the N1EGS4/N4EGS4 that is installed with the GE electrical interface........... 11-178
Figure 11-58 Normal working of the EGS4...................................................................................................11-181
Figure 11-59 Principle of the BPS protection for the EGS4..........................................................................11-182
Figure 11-60 Principle of the PPS protection for the EGS4...........................................................................11-183
Figure 11-61 Principle of the DLAG protection for the EGS4......................................................................11-184
Figure 11-62 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications of the N1EGS4........................................................11-186
Figure 11-63 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications of the N4EGS4........................................................11-190
Figure 11-64 Networking and application of the EAS2.................................................................................11-196
Figure 11-65 Functional block diagram of the EAS2.................................................................................... 11-199
Figure 11-66 Front panel of the EAS2...........................................................................................................11-200
Figure 11-67 Connection for testing the throughput specifications, packet loss ratio in the case of overloading and
latency specifications...................................................................................................................................... 11-203
Figure 11-68 Functional block diagram of the EFF8.....................................................................................11-206
Figure 11-69 Front panel of the EFF8............................................................................................................11-207
Figure 11-70 Functional block diagram of the EFF8A..................................................................................11-211
Figure 11-71 Front panel of the EFF8A.........................................................................................................11-212
Figure 11-72 Functional block diagram of the ETF8.....................................................................................11-215
Figure 11-73 Front panel of the ETF8............................................................................................................11-217
Figure 11-74 Functional block diagram of the ETF8A..................................................................................11-221
Figure 11-75 Front panel of the ETF8A.........................................................................................................11-222
Figure 11-76 Functional block diagram of the ETS8.....................................................................................11-225
Figure 11-77 Front panel of the ETS8............................................................................................................11-226
Figure 12-1 Networking and application of the ATM services that occupy bandwidths exclusively...............12-3
Figure 12-2 Networking and application of the ATM services that share bandwidths......................................12-4
Figure 12-3 Functional block diagram of the ADL4..........................................................................................12-6
Figure 12-4 Front panel of the ADL4................................................................................................................12-8
Figure 12-5 Networking and application of the ATM services that occupy bandwidths exclusively.............12-12
Figure 12-6 Networking and application of the ATM services that share bandwidths....................................12-13
Figure 12-7 Functional block diagram of the ADQ1.......................................................................................12-15
Figure 12-8 Front panel of the ADQ1..............................................................................................................12-17
Figure 12-9 Networking and application of the IMA services.........................................................................12-22
Figure 12-10 Functional block diagram of the IDL4.......................................................................................12-24
Figure 12-11 Front panel of the IDL4..............................................................................................................12-26
Figure 12-12 Networking and application of the IMA services.......................................................................12-30
Figure 12-13 Functional block diagram of the IDQ1.......................................................................................12-33
Figure 12-14 Front panel of the IDQ1..............................................................................................................12-35
Figure 13-1 Networking and application of the EGR2......................................................................................13-3
Figure 13-2 Functional block diagram of the EGR2..........................................................................................13-7
Figure 13-3 Front panel of the EGR2...............................................................................................................13-10
Figure 13-4 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications....................................................................................13-13
Figures
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Figure 13-5 Networking and application of the EMR0....................................................................................13-19
Figure 13-6 Functional block diagram of the EMR0.......................................................................................13-23
Figure 13-7 Front panel of the EMR0..............................................................................................................13-26
Figure 13-8 Connection for testing the throughput specifications, packet loss ratio in the case of overloading,
latency specifications, and back-to-back specifications....................................................................................13-30
Figure 14-1 Networking and application of the SAN services...........................................................................14-3
Figure 14-2 Functional block diagram of the MST4..........................................................................................14-5
Figure 14-3 Front panel of the MST4................................................................................................................14-7
Figure 15-1 Position of the OptiX OSN equipment that is configured with the IFSD1 in the network............15-3
Figure 15-2 Functional block diagram of the IFSD1.........................................................................................15-5
Figure 15-3 Front panel of the IFSD1................................................................................................................15-7
Figure 15-4 Position of the OptiX OSN equipment that is configured with the RPWR in the network..........15-14
Figure 15-5 Functional block diagram of the RPWR.......................................................................................15-15
Figure 15-6 Front panel of the RPWR.............................................................................................................15-17
Figure 16-1 Application of the CMR2 in the CWDM system...........................................................................16-2
Figure 16-2 Functional block diagram of the CMR2.........................................................................................16-3
Figure 16-3 Front panel of the CMR2................................................................................................................16-5
Figure 16-4 Application of the CMR4 in the CWDM system...........................................................................16-9
Figure 16-5 Functional block diagram of the CMR4.......................................................................................16-10
Figure 16-6 Front panel of the CMR4..............................................................................................................16-11
Figure 16-7 Application of the MR2 in the DWDM system............................................................................16-15
Figure 16-8 Functional block diagram of the MR2..........................................................................................16-16
Figure 16-9 Front panel of the MR2................................................................................................................16-18
Figure 16-10 Application of the MR2A in the DWDM system.......................................................................16-22
Figure 16-11 One MR2A board working as a two-channel add/drop OTM station........................................16-23
Figure 16-12 Two MR2A boards being cascaded to work as a four-channel add/drop OTM station.............16-23
Figure 16-13 MR2A and LWX working as a two-channel add/drop OADM station......................................16-23
Figure 16-14 Functional block diagram of the MR2A.....................................................................................16-24
Figure 16-15 Front panel of the MR2A............................................................................................................16-25
Figure 16-16 Application of the MR2C in the DWDM system.......................................................................16-28
Figure 16-17 One MR2C board working as a two-channel add/drop OTM station.........................................16-29
Figure 16-18 Two MR2C boards being cascaded to work as a four-channel add/drop OTM station.............16-29
Figure 16-19 MR2C and LWX working as a two-channel add/drop OADM station......................................16-29
Figure 16-20 Functional block diagram of the MR2C.....................................................................................16-30
Figure 16-21 Front panel of the MR2C............................................................................................................16-31
Figure 16-22 Application of the MR4 in the DWDM system..........................................................................16-34
Figure 16-23 Functional block diagram of the MR4........................................................................................16-35
Figure 16-24 Front panel of the MR4..............................................................................................................16-36
Figure 16-25 Application of the LWX in the DWDM system.........................................................................16-40
Figure 16-26 Functional block diagram of the LWX.......................................................................................16-42
Figure 16-27 Front panel of the LWX..............................................................................................................16-44
Figure 16-28 Position of the FIB in an optical transmission system................................................................16-49
Figure 16-29 Functional block diagram of the FIB..........................................................................................16-50
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Figure 16-30 Front panel of the FIB................................................................................................................16-51
Figure 17-1 Functional block diagram of the AUX...........................................................................................17-5
Figure 17-2 Position of the jumper J9 on the AUX...........................................................................................17-6
Figure 17-3 Front panel of the AUX..................................................................................................................17-7
Figure 17-4 Connections for alarm input, alarm cascading, and alarm output................................................17-14
Figure 17-5 Connections of cabinet alarm indicators.......................................................................................17-15
Figure 17-6 Functional block diagram of the XE1FAN...................................................................................17-17
Figure 17-7 Modular fan tray assembly...........................................................................................................17-18
Figure 18-1 Position of the BA in an optical transmission system....................................................................18-2
Figure 18-2 Functional block diagram of the BA2............................................................................................18-4
Figure 18-3 Front panel of the one-interface BA2.............................................................................................18-6
Figure 18-4 Front panel of the two-interface BA2.............................................................................................18-7
Figure 18-5 Position of the BA and PA in an optical transmission system.....................................................18-11
Figure 18-6 Functional block diagram of the N1BPA.....................................................................................18-13
Figure 18-7 Functional block diagram of the N2BPA.....................................................................................18-13
Figure 18-8 Front panel of the BPA.................................................................................................................18-14
Figure 18-9 Appearance of the 61COA/N1COA (PA)....................................................................................18-19
Figure 18-10 Appearance of the 62COA..........................................................................................................18-20
Figure 18-11 Application of the 62COA..........................................................................................................18-21
Figure 18-12 Functional block diagram of the 61COA/N1COA.....................................................................18-22
Figure 18-13 Front panel of the 61COA/N1COA............................................................................................18-23
Figure 18-14 Front panel of the 62COA..........................................................................................................18-24
Figure 18-15 SC/PC fiber connector................................................................................................................18-24
Figure 18-16 LSH flange and fiber connector..................................................................................................18-25
Figure 18-17 Position of the 61COA in the ETSI cabinet...............................................................................18-27
Figure 18-18 Position of the RPC01 in an optical transmission system..........................................................18-30
Figure 18-19 Functional block diagram of the RPC01 (forward pump)..........................................................18-32
Figure 18-20 Front panel of the RPC01...........................................................................................................18-33
Figure 18-21 Jumpers of the RPC01................................................................................................................18-35
Figure 18-22 Position of the RPC02 in an optical transmission system..........................................................18-38
Figure 18-23 Functional block diagram of the RPC02 (backward pump).......................................................18-39
Figure 18-24 Front panel of the RPC02...........................................................................................................18-40
Figure 18-25 Jumpers of the RPC02................................................................................................................18-41
Figure 18-26 Position of the OBU1 in an optical transmission system...........................................................18-44
Figure 18-27 Functional block diagram of the OBU1.....................................................................................18-46
Figure 18-28 Front panel of the OBU1............................................................................................................18-47
Figure 18-29 Position of the DCU in an optical transmission system.............................................................18-52
Figure 18-30 Functional block diagram of the DCU.......................................................................................18-53
Figure 18-31 Front panel of the one-interface DCU........................................................................................18-54
Figure 18-32 Front panel of the two-interface DCU........................................................................................18-55
Figure 19-1 Application of the UPM on the OptiX OSN equipment series.......................................................19-3
Figure 19-2 Appearance of the EPS75-4815AF power box...............................................................................19-4
Figures
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Figure 19-3 Front panel of the EPS75-4815AF.................................................................................................19-6
Figure 19-4 Application of the PIU on the OptiX OSN equipment series.......................................................19-10
Figure 19-5 Functional block diagram of the PIU...........................................................................................19-11
Figure 19-6 Front panel of the PIU..................................................................................................................19-12
Figure 19-7 Application of the PIUA on the OptiX OSN equipment series....................................................19-14
Figure 19-8 Functional block diagram of the PIUA.........................................................................................19-15
Figure 19-9 Front panel of the PIUA...............................................................................................................19-16
Figure 19-10 Application of the PIUB board in the OptiX OSN system.........................................................19-19
Figure 19-11 Functional block diagram of the PIUB.......................................................................................19-20
Figure 19-12 Front panel of the PIUB..............................................................................................................19-21
Figure 20-1 SFP/eSFP optical module...............................................................................................................20-2
Figure 20-2 XFP optical module........................................................................................................................20-2
Figure 20-3 Label of a pluggable optical module..............................................................................................20-3
Figure 21-1 Appearance of the LC/PC fiber connector......................................................................................21-3
Figure 21-2 Appearance of the SC/PC fiber connector......................................................................................21-4
Figure 21-3 Appearance of the FC/PC fiber connector......................................................................................21-4
Figure 21-4 Appearance of the LSH/APC fiber connector................................................................................21-4
Figure 21-5 Structure of the 48 V/BGND power cable of the cabinet for the N1PDU...................................21-6
Figure 21-6 Structure of the PGND power cable of the cabinet (JG2) for the N1PDU.....................................21-6
Figure 21-7 Structure of the PGND power cable of the cabinet (OT) for the N1PDU......................................21-6
Figure 21-8 Structure of the 48 V/BGND power cable of the cabinet for the TN51PDU...............................21-7
Figure 21-9 Structure of the PGND power cable of the cabinet for the TN51PDU..........................................21-7
Figure 21-10 Structure of the grounding cable of the cabinet door...................................................................21-9
Figure 21-11 Structure of the power cable for thegeneral and enhanced subrack (1100 W) subrack.............21-10
Figure 21-12 Structure of the power cable for the enhanced subrack (2300 W).............................................21-10
Figure 21-13 Structure of the COA power cable..............................................................................................21-12
Figure 21-14 Structure of the cabinet indicator cable......................................................................................21-14
Figure 21-15 Structure of the indicator cascading cable between subracks or the alarm cascading cable between
the OptiX OSN equipment................................................................................................................................21-15
Figure 21-16 Structure of the alarm cascading cable between the OptiX OSN equipment and the other Huawei
transmission equipment.....................................................................................................................................21-17
Figure 21-17 Structure of the alarm input/output cable...................................................................................21-18
Figure 21-18 Structure of the OAM serial port cable.......................................................................................21-20
Figure 21-19 Structure of the serial 14/F1/F&f serial port cable...................................................................21-22
Figure 21-20 Structure of the RS-232/RS-422 serial port cable......................................................................21-23
Figure 21-21 Structure of the ordinary telephone line.....................................................................................21-25
Figure 21-22 Structure of the COA cascading cable........................................................................................21-26
Figure 21-23 Structure of the straight through cable........................................................................................21-27
Figure 21-24 Structure of the crossover cable..................................................................................................21-28
Figure 21-25 Structure of the 75-ohm 8xE1 cable...........................................................................................21-30
Figure 21-26 Structure of the 120-ohm 8xE1 cable.........................................................................................21-33
Figure 21-27 Structure of the E3/T3/STM-1 cable..........................................................................................21-35
Figure 21-28 Structure of the V.35 DCE cable................................................................................................21-38
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Figure 21-29 Structure of the V.35 DTE cable................................................................................................21-39
Figure 21-30 Structure of the V.24 DCE cable................................................................................................21-41
Figure 21-31 Structure of the V.24 DTE cable................................................................................................21-43
Figure 21-32 Structure of the X.21 DCE cable................................................................................................21-44
Figure 21-33 Structure of the X.21 DTE cable................................................................................................21-46
Figure 21-34 Structure of the RS-449 DCE cable............................................................................................21-47
Figure 21-35 Structure of the RS-449 DTE cable............................................................................................21-49
Figure 21-36 Structure of the RS-530 DCE cable............................................................................................21-51
Figure 21-37 Structure of the RS-530 DTE cable............................................................................................21-53
Figure 21-38 Structure of the 75-ohm clock cable...........................................................................................21-55
Figure 21-39 Structure of the 120-ohm clock cable.........................................................................................21-55
Figure 21-40 Structure of the one-channel 75-ohm-to-120-ohm clock transit cable.......................................21-57
Figure 21-41 Structure of the two-channel 75-ohm-to-120-ohm clock transit cable.......................................21-57
Figure 23-1 Positions of the labels affixed to the OptiX OSN 3500 subrack (1)...............................................23-4
Figure 23-2 Positions of the labels affixed to the OptiX OSN 3500 subrack (2)...............................................23-5
Figure 23-3 Positions of the labels affixed to the board.....................................................................................23-6
Figures
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Tables
Table 2-1 Comparison between the specifications of the T63 cabinet and the specifications of the N63E cabinet
...............................................................................................................................................................................2-4
Table 2-2 Meanings of the status of the indicators...............................................................................................2-7
Table 2-3 Connections of the output terminal blocks on side A and side B........................................................2-9
Table 2-4 Technical specifications of the ETSI cabinet.....................................................................................2-11
Table 2-5 Technical specifications of the PDU..................................................................................................2-11
Table 3-1 Mapping relation between slots for the interface boards and slots for the processing boards.............3-6
Table 3-2 Paired slots...........................................................................................................................................3-6
Table 3-3 Mapping policies of power consumption on the OptiX OSN 3500...................................................3-12
Table 3-4 Dimensions and weight of the OptiX OSN 3500 subrack.................................................................3-13
Table 3-5 Maximum power consumption of the OptiX OSN 3500 subrack......................................................3-14
Table 4-1 Appearances and dimensions of the boards used on the OptiX OSN 3500.........................................4-2
Table 4-2 SDH boards that the OptiX OSN 3500 supports..................................................................................4-5
Table 4-3 PDH boards that the OptiX OSN 3500 supports..................................................................................4-6
Table 4-4 Packet boards that the OptiX OSN 3500 supports...............................................................................4-6
Table 4-5 Dual-mode bridging boards supported by the OptiX OSN 3500.........................................................4-7
Table 4-6 CES boards supported by the OptiX OSN 3500..................................................................................4-7
Table 4-7 Data boards that the OptiX OSN 3500 supports..................................................................................4-7
Table 4-8 Interface boards and switching and bridging boards that the OptiX OSN 3500 supports...................4-8
Table 4-9 Cross-connect boards and system control boards that the OptiX OSN 3500 supports........................4-9
Table 4-10 Auxiliary boards that the OptiX OSN 3500 supports........................................................................4-9
Table 4-11 WDM boards that the OptiX OSN 3500 supports...........................................................................4-10
Table 4-12 Microwave boards that the OptiX OSN 3500 supports...................................................................4-10
Table 4-13 Optical amplifier boards and dispersion compensation boards that the OptiX OSN 3500 supports
.............................................................................................................................................................................4-10
Table 4-14 Power boards that the OptiX OSN 3500 supports...........................................................................4-11
Table 5-1 Versions of the PSXCS board..............................................................................................................5-2
Table 5-2 Functions and features of the cross-connect unit of the PSXCS(A)....................................................5-4
Table 5-3 Functions and features of the clock unit of the PSXCS(A) board.......................................................5-4
Table 5-4 Versions of the GSCC........................................................................................................................5-10
Table 5-5 Functions and features of the GSCC..................................................................................................5-11
Table 5-6 Types and usage of the switches of the GSCC..................................................................................5-16
Table 5-7 Jumpers of the N4GSCC....................................................................................................................5-17
Table 5-8 Jumper J7100.....................................................................................................................................5-18
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Table 5-9 Jumpers of the N6GSCC....................................................................................................................5-19
Table 5-10 Jumper J11.......................................................................................................................................5-20
Table 6-1 Versions of the PEX1...........................................................................................................................6-2
Table 6-2 Functions and features of the PEX1.....................................................................................................6-4
Table 6-3 Optical interface of the PEX1............................................................................................................6-12
Table 6-4 Slots valid for the N1PEX1 and the corresponding logical slots of the N1PEX1 on the T2000.......6-12
Table 6-5 Parameters specified for the optical interfaces of the N1PEX1.........................................................6-14
Table 6-6 Parameters specified for the optical interfaces of the N2PEX1.........................................................6-14
Table 6-7 Parameters specified for the 10GE colored optical interfaces of the PEX1.......................................6-15
Table 6-8 Functions and features of the PEX2...................................................................................................6-18
Table 6-9 Optical interfaces of the PEX2...........................................................................................................6-25
Table 6-10 Parameters specified for the optical interfaces of the PEX2............................................................6-26
Table 6-11 Parameters specified for the 10GE colored optical interfaces of the PEX2.....................................6-26
Table 6-12 Functions and features of the PEG8.................................................................................................6-29
Table 6-13 Optical interfaces of the PEG8.........................................................................................................6-36
Table 6-14 Slots valid for the PEG8 and the corresponding slots for the PETF8/PEFF8..................................6-36
Table 6-15 Parameters specified for the optical interfaces of the PEG8............................................................6-37
Table 6-16 Parameters specified for the GE colored optical interfaces of the PEG8.........................................6-38
Table 6-17 Functions and features of the PEG16...............................................................................................6-40
Table 6-18 Optical interfaces of the PEG16.......................................................................................................6-46
Table 6-19 Slots valid for the PEG16 and the corresponding slots for the PETF8/PEFF8................................6-46
Table 6-20 Parameters specified for the optical interfaces of the PEG16..........................................................6-47
Table 6-21 Parameters specified for the GE colored optical interfaces of the PEG16.......................................6-48
Table 6-22 Functions and features of the PETF8...............................................................................................6-51
Table 6-23 Electrical interfaces of the PETF8...................................................................................................6-55
Table 6-24 Parameters specified for the electrical interfaces of the PETF8......................................................6-56
Table 6-25 Functions and features of the PEFF8...............................................................................................6-58
Table 6-26 Interfaces of the PEFF8....................................................................................................................6-63
Table 6-27 Specifications of the electrical interfaces.........................................................................................6-63
Table 7-1 Functions and features of the EDQ41..................................................................................................7-4
Table 7-2 Data features of the EDQ41.................................................................................................................7-5
Table 7-3 EoS data features of the EDQ41..........................................................................................................7-6
Table 7-4 Interfaces of the EDQ41.....................................................................................................................7-11
Table 7-5 Relationship between the feature code of the EDQ41 and types of optical interfaces......................7-11
Table 7-6 Specifications of the optical interfaces on the EDQ41......................................................................7-12
Table 7-7 Specifications of STM-4 optical interfaces on the EDQ41................................................................7-13
Table 8-1 Functions and features of the CQ1.......................................................................................................8-3
Table 8-2 Interfaces of the CQ1...........................................................................................................................8-8
Table 8-3 Slots valid for the PEG8 and the corresponding slots for the CQ1......................................................8-8
Table 8-4 Specifications of the optical interfaces on the CQ1.............................................................................8-9
Table 8-5 Functions and features of the MD12..................................................................................................8-12
Table 8-6 Interfaces of the MD12......................................................................................................................8-16
Tables
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Table 8-7 Pin description of the DB44 interfaces on the MD12........................................................................8-16
Table 8-8 Slots valid for the PEG8 and the corresponding slots for the MD12.................................................8-17
Table 8-9 Specifications of the electrical interfaces of the MD12.....................................................................8-18
Table 8-10 Functions and features of the MD75................................................................................................8-20
Table 8-11 Interfaces of the MD75....................................................................................................................8-24
Table 8-12 Pin description of the DB44 interfaces on the MD75......................................................................8-24
Table 8-13 Slots valid for the PEG8 and the corresponding slots for the MD75...............................................8-25
Table 8-14 Specifications of the electrical interfaces of the MD75...................................................................8-26
Table 9-1 Versions of the SL1..............................................................................................................................9-5
Table 9-2 Functions and features of the SL1........................................................................................................9-6
Table 9-3 Optical interfaces of the SL1..............................................................................................................9-11
Table 9-4 Relationship between the feature code of the SL1 and the type of optical interface.........................9-11
Table 9-5 Parameters specified for the optical interfaces of the SL1.................................................................9-12
Table 9-6 Functions and features of the SL1A...................................................................................................9-15
Table 9-7 Optical interfaces of the SL1A...........................................................................................................9-20
Table 9-8 Relationship between the feature code of the SL1A and the type of optical interface......................9-20
Table 9-9 Parameters specified for the optical interfaces of the SL1A..............................................................9-21
Table 9-10 Versions of the SLQ1.......................................................................................................................9-23
Table 9-11 Functions and features of the SLQ1.................................................................................................9-24
Table 9-12 Optical interfaces of the SLQ1.........................................................................................................9-29
Table 9-13 Relationship between the feature code of the SLQ1 and the type of optical interface....................9-29
Table 9-14 Parameters specified for the optical interfaces of the SLQ1............................................................9-30
Table 9-15 Functions and features of the SLQ1A..............................................................................................9-33
Table 9-16 Optical interfaces of the SLQ1A......................................................................................................9-37
Table 9-17 Relationship between the feature code of the SLQ1A and the type of optical interface.................9-37
Table 9-18 Parameters specified for the optical interfaces of the SLQ1A.........................................................9-38
Table 9-19 Versions of the SLO1.......................................................................................................................9-40
Table 9-20 Functions and features of the SLO1 board.......................................................................................9-41
Table 9-21 Optical interfaces of the SLO1.........................................................................................................9-46
Table 9-22 Relationship between the feature code of the SLO1 and the type of optical interface....................9-46
Table 9-23 Parameters specified for the optical interfaces of the SLO1............................................................9-47
Table 9-24 Functions and features of the SLT1.................................................................................................9-50
Table 9-25 Optical interfaces of the SLT1.........................................................................................................9-55
Table 9-26 Relationship between the feature code of the SLT1 and the type of optical interface.....................9-55
Table 9-27 Parameters specified for the optical interfaces of the SLT1............................................................9-56
Table 9-28 Functions and features of the SLH1.................................................................................................9-58
Table 9-29 Access capabilities of the SLH1 when the SLH1 works with different interface boards and electrical
interface switching boards...................................................................................................................................9-60
Table 9-30 Slots for the SLH1, EU08, and TSB8..............................................................................................9-66
Table 9-31 Technical specifications of the SLH1..............................................................................................9-66
Table 9-32 Functions and features of the SEP1.................................................................................................9-69
Table 9-33 Access capabilities of the SEP1 when the SEP1 works with different interface boards and electrical
interface switching boards...................................................................................................................................9-70
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Table 9-34 Electrical interfaces of the SEP1......................................................................................................9-76
Table 9-35 Slots for the SEP, EU08, and TSB8.................................................................................................9-78
Table 9-36 Parameters specified for the interfaces of the SEP1........................................................................9-79
Table 9-37 Versions of the SL4..........................................................................................................................9-80
Table 9-38 Functions and features of the SL4....................................................................................................9-82
Table 9-39 Optical interfaces of the SL4............................................................................................................9-87
Table 9-40 Relationship between the feature code of the SL4 and the type of optical interface.......................9-87
Table 9-41 Parameters specified for the optical interfaces of the SL4...............................................................9-88
Table 9-42 Functions and features of the SL4A.................................................................................................9-91
Table 9-43 Optical interfaces of the SL4A.........................................................................................................9-95
Table 9-44 Relationship between the feature code of the SL4A and the type of optical interface....................9-95
Table 9-45 Parameters specified for the optical interfaces of the SL4A............................................................9-96
Table 9-46 Versions of the SLD4.......................................................................................................................9-98
Table 9-47 Functions and features of the SLD4.................................................................................................9-99
Table 9-48 Optical interfaces of the SLD4.......................................................................................................9-104
Table 9-49 Relationship between the feature code of the SLD4 and the type of optical interface..................9-104
Table 9-50 Parameters specified for the optical interfaces of the SLD4..........................................................9-105
Table 9-51 Functions and features of the SLD4A............................................................................................9-108
Table 9-52 Optical interfaces of the SLD4A....................................................................................................9-113
Table 9-53 Relationship between the feature code of the SLD4A and the type of optical interface...............9-113
Table 9-54 Parameters specified for the optical interfaces of the SLD4A.......................................................9-114
Table 9-55 Versions of the SLQ4.....................................................................................................................9-116
Table 9-56 Functions and features of the SLQ4...............................................................................................9-117
Table 9-57 Optical interfaces of the SLQ4.......................................................................................................9-122
Table 9-58 Relationship between the feature code of the SLQ4 and the type of optical interface..................9-122
Table 9-59 Parameters specified for the optical interfaces of the SLQ4..........................................................9-123
Table 9-60 Functions and features of the SLQ4A............................................................................................9-126
Table 9-61 Optical interfaces of the SLQ4A....................................................................................................9-131
Table 9-62 Relationship between the feature code of the SLQ4A and the type of optical interface...............9-131
Table 9-63 Parameters specified for the optical interfaces of the SLQ4A.......................................................9-132
Table 9-64 Versions of the SL16......................................................................................................................9-134
Table 9-65 Functions and features of the SL16................................................................................................9-135
Table 9-66 Optical interfaces of the SL16........................................................................................................9-140
Table 9-67 Relationship between the feature code of the SL16 and the type of optical interface...................9-140
Table 9-68 Parameters specified for the optical interfaces of the SL16...........................................................9-141
Table 9-69 Parameters specified for the optical interfaces that comply with the standard wavelengths specified in
ITU-T G.692......................................................................................................................................................9-142
Table 9-70 Versions of the SL16......................................................................................................................9-144
Table 9-71 Functions and features of the SL16A.............................................................................................9-145
Table 9-72 Optical interfaces of the SL16A.....................................................................................................9-150
Table 9-73 Relationship between the feature code of the SL16A and the type of optical interface................9-150
Table 9-74 Parameters specified for the optical interfaces of the SL16A........................................................9-151
Table 9-75 Functions and features of the SLD16.............................................................................................9-154
Tables
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Table 9-76 Optical interfaces of the SLD16.....................................................................................................9-159
Table 9-77 Relationship between the feature code of the SLD16 and the type of optical interface................9-159
Table 9-78 Parameters specified for the optical interfaces of the SLD16........................................................9-160
Table 9-79 Versions of the SLQ16...................................................................................................................9-162
Table 9-80 Functions and features of the SLQ16.............................................................................................9-163
Table 9-81 Optical interfaces of the SLQ16.....................................................................................................9-170
Table 9-82 Relationship between the feature code of the SLQ16 and the type of optical interface................9-170
Table 9-83 Parameters specified for the optical interfaces of the SLQ16........................................................9-171
Table 9-84 Functions and features of the SLO16.............................................................................................9-174
Table 9-85 Optical interfaces of the SLO16.....................................................................................................9-179
Table 9-86 Relationship between the feature code of the SLO16 and the type of optical interface................9-179
Table 9-87 Parameters specified for the optical interfaces of the SLO16........................................................9-180
Table 9-88 Functions and features of the SF16................................................................................................9-183
Table 9-89 Optical interfaces of the SF16........................................................................................................9-188
Table 9-90 Relationship between the feature code of the SF16 and the type of optical interface...................9-188
Table 9-91 Parameters specified for the optical interfaces of the SF16...........................................................9-189
Table 9-92 Parameters specified for the optical interfaces that comply with the standard wavelengths specified in
ITU-T G.692......................................................................................................................................................9-190
Table 9-93 Versions of the SL64......................................................................................................................9-192
Table 9-94 Functions and features of the SL64................................................................................................9-193
Table 9-95 Optical interfaces of the SL64........................................................................................................9-198
Table 9-96 Relationship between the feature code of the SL64 and the type of optical interface...................9-198
Table 9-97 Parameters specified for the optical interfaces of the SL64...........................................................9-200
Table 9-98 Parameters specified for the optical interfaces that comply with the standard wavelengths specified in
ITU-T G.692......................................................................................................................................................9-201
Table 9-99 Functions and features of the SLD64.............................................................................................9-203
Table 9-100 Optical interfaces of the SLD64...................................................................................................9-208
Table 9-101 Relationship between the feature code of the SLD64 and the type of optical interface..............9-208
Table 9-102 Parameters specified for the optical interfaces of the SLD64......................................................9-209
Table 9-103 Functions and features of the SF64..............................................................................................9-212
Table 9-104 Optical interfaces of the SF64......................................................................................................9-217
Table 9-105 Relationship between the feature code of the SF64 and the type of optical interface.................9-217
Table 9-106 Specifications of optical interfaces of the SF64...........................................................................9-218
Table 9-107 Parameters specified for the optical interfaces that comply with the standard wavelengths specified
in ITU-T G.692.................................................................................................................................................9-219
Table 9-108 Functions and features of the SF64A...........................................................................................9-221
Table 9-109 Optical interfaces of the SF64A...................................................................................................9-226
Table 9-110 Specifications of optical interfaces of the SF64A........................................................................9-226
Table 9-111 Parameters specified for the optical interfaces that comply with the standard wavelengths specified
in ITU-T G.692.................................................................................................................................................9-227
Table 9-112 Functions and features of the SLQ41...........................................................................................9-230
Table 9-113 Optical interfaces of the SLQ41...................................................................................................9-235
Table 9-114 Relationship between the feature code of the SLQ41 and the type of optical interface..............9-235
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Table 9-115 Parameters specified for the optical interfaces of the SLQ41 when the STM-1 optical module is used
...........................................................................................................................................................................9-236
Table 9-116 Parameters specified for the optical interfaces of the SLQ41 when the STM-4 optical module is used
...........................................................................................................................................................................9-237
Table 9-117 Interfaces of the EU04.................................................................................................................9-241
Table 9-118 Slots valid for the SEP and the corresponding slots for the EU04...............................................9-241
Table 9-119 Parameters specified for the electrical interfaces of the EU04....................................................9-242
Table 9-120 Interfaces of the EU08.................................................................................................................9-245
Table 9-121 Slots valid for the SLH1 and the corresponding slots for the EU08............................................9-245
Table 9-122 Slots valid for the SEP and the corresponding slots for the EU08...............................................9-246
Table 9-123 Parameters specified for the electrical interfaces of the EU08....................................................9-246
Table 9-124 Versions of the OU08...................................................................................................................9-247
Table 9-125 Interfaces of the N1OU08............................................................................................................9-250
Table 9-126 Interfaces of the N2OU08............................................................................................................9-251
Table 9-127 Slots valid for the SLH1 and the corresponding slots for the OU08...........................................9-251
Table 9-128 Slots valid for the SEP1 and the corresponding slots for the OU08............................................9-252
Table 9-129 Parameters specified for the optical interfaces of the OU08........................................................9-252
Table 10-1 Versions of the PQ1.........................................................................................................................10-4
Table 10-2 Functions and features of the PQ1...................................................................................................10-5
Table 10-3 Slots valid for the PQ1 and the corresponding slots for the D75S, D12S, and D12B in the main subrack
.............................................................................................................................................................................10-9
Table 10-4 Relationship between the feature code of the PQ1 and the type of interface impedance..............10-10
Table 10-5 Slot configuration for the 1:8 TPS protection of the PQ1..............................................................10-11
Table 10-6 Functions and features of the PQM................................................................................................10-15
Table 10-7 Slots valid for the PQM and the corresponding slots for the D12S and D12B in the main subrack
...........................................................................................................................................................................10-19
Table 10-8 Slot configuration for the 1:8 TPS protection of the PQM............................................................10-21
Table 10-9 Versions of the PL3........................................................................................................................10-23
Table 10-10 Functions and features of the PL3................................................................................................10-24
Table 10-11 Slots valid for the PL3 and the corresponding slots for the C34S in the main subrack...............10-29
Table 10-12 Slot configuration for the 1:3 TPS protection of the PL3............................................................10-30
Table 10-13 Slots for the PL3, C34S, and TSB8/TSB4...................................................................................10-31
Table 10-14 Versions of the PL3A...................................................................................................................10-33
Table 10-15 Functions and features of the PL3A.............................................................................................10-34
Table 10-16 Parameters specified for the electrical interfaces of the PL3A....................................................10-40
Table 10-17 Versions of the PD3.....................................................................................................................10-41
Table 10-18 Functions and features of the PD3...............................................................................................10-42
Table 10-19 Slots valid for the PD3 and the corresponding slots for the D34S in the main subrack..............10-47
Table 10-20 Slot configuration for the 1:3 TPS protection of the PD3............................................................10-48
Table 10-21 Slots for the PD3, D34S, and TSB8.............................................................................................10-49
Table 10-22 Functions and features of the PQ3...............................................................................................10-52
Table 10-23 Slots valid for the PQ3 and the corresponding slots for the D34S...............................................10-56
Table 10-24 Slot configuration for the 1:3 TPS protection of the PQ3............................................................10-57
Tables
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Table 10-25 Slots for the PQ3, D34S, and TSB8.............................................................................................10-58
Table 10-26 Functions and features of the DX1...............................................................................................10-61
Table 10-27 Slots valid for the DX1 and the corresponding slots for the DM12.............................................10-65
Table 10-28 Relationship between the feature code of the DX1 and the type of interface impedance............10-66
Table 10-29 Slots for the DX1 and DM12.......................................................................................................10-67
Table 10-30 Functions and features of the DXA..............................................................................................10-70
Table 10-31 Versions of the SPQ4...................................................................................................................10-74
Table 10-32 Functions and features of the SPQ4.............................................................................................10-75
Table 10-33 Slots valid for the SPQ4 and the corresponding slots for the MU04...........................................10-82
Table 10-34 Slots for the SPQ4, MU04, and TSB8/TSB4...............................................................................10-84
Table 10-35 Interfaces of the D12B.................................................................................................................10-88
Table 10-36 Pin assignments of the DB44 interface........................................................................................10-88
Table 10-37 Slots valid for the PQ1/PQM and the corresponding slots for the D12B....................................10-89
Table 10-38 Parameters specified for the electrical interfaces of the D12B....................................................10-89
Table 10-39 Interfaces of the D12S..................................................................................................................10-93
Table 10-40 Pin assignments of the DB44 interface........................................................................................10-93
Table 10-41 Slots valid for the PQ1/PQM and the corresponding slots for the D12S.....................................10-94
Table 10-42 Parameters specified for the electrical interfaces of the D12S.....................................................10-94
Table 10-43 Interfaces of the D75S..................................................................................................................10-98
Table 10-44 Pin assignments of the DB44 interface........................................................................................10-98
Table 10-45 Slots valid for the PQ1 and the corresponding slots for the D75S...............................................10-99
Table 10-46 Parameters specified for the electrical interfaces of the D75S.....................................................10-99
Table 10-47 Interfaces of the D34S................................................................................................................10-103
Table 10-48 Parameters specified for the electrical interfaces of the D34S...................................................10-103
Table 10-49 Interfaces of the C34S................................................................................................................10-106
Table 10-50 Slots valid for the PL3 and the corresponding slots for the C34S.............................................10-107
Table 10-51 Parameters specified for the electrical interfaces of the C34S...................................................10-107
Table 10-52 Interfaces of the MU04..............................................................................................................10-110
Table 10-53 Slots valid for the SPQ4 and the corresponding slots for the MU04.........................................10-111
Table 10-54 Parameters specified for the electrical interfaces of the MU04.................................................10-111
Table 10-55 Interfaces of the DM12..............................................................................................................10-114
Table 10-56 Pin assignments of the DB44 interface......................................................................................10-115
Table 10-57 Pin assignments of the DB28 interface......................................................................................10-116
Table 10-58 Slots valid for the DX1 and the corresponding slots for the DM12...........................................10-116
Table 10-59 Parameters specified for the electrical interfaces of the DM12.................................................10-117
Table 10-60 Slots valid for the TSB4 and the corresponding slots for the SPQ4 and MU04........................10-120
Table 10-61 Slots valid for the TSB4 and the corresponding slots for the SEP1 and EU04.........................10-121
Table 10-62 Slots valid for the TSB4 and the corresponding slots for the PL3 and C34S............................10-121
Table 10-63 Slots valid for the TSB8 and the corresponding slots for the SPQ4 and MU04........................10-125
Table 10-64 Slots valid for the TSB8 and the corresponding slots for the PL3 and C34S............................10-125
Table 10-65 Slots valid for the TSB8 and the corresponding slots for the PD3 and D34S...........................10-125
Table 10-66 Slots valid for the TSB8 and the corresponding slots for the PQ3 and D34S...........................10-126
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Table 10-67 Slots valid for the TSB8 and the corresponding slots for the SEP1 and EU04.........................10-126
Table 10-68 Slots valid for the TSB8 and the corresponding slots for the SEP1 and EU08.........................10-127
Table 10-69 Slots valid for the TSB8 and the corresponding slots for the SLH1 and EU08.........................10-127
Table 10-70 Slots valid for the TSB8 and the corresponding slots for the EFS0 and ETS8..........................10-127
Table 11-1 Functions and features of the EFT8.................................................................................................11-4
Table 11-2 Interfaces of the EFT8....................................................................................................................11-10
Table 11-3 Pins of the RJ-45 connector ..........................................................................................................11-10
Table 11-4 Throughput specifications of the EFT8..........................................................................................11-13
Table 11-5 Packet loss ratio in the case of overloading of the EFT8...............................................................11-14
Table 11-6 Latency specifications of the EFT8................................................................................................11-14
Table 11-7 Back-to-back specifications of the EFT8.......................................................................................11-15
Table 11-8 Functions and features of the EFT8A............................................................................................11-17
Table 11-9 Interfaces of the EFT8A.................................................................................................................11-23
Table 11-10 Pins of the RJ-45 connector.........................................................................................................11-23
Table 11-11 Throughput specifications of the EFT8A.....................................................................................11-26
Table 11-12 Packet loss ratio in the case of overloading of the EFT8A..........................................................11-27
Table 11-13 Latency specifications of the EFT8A...........................................................................................11-27
Table 11-14 Back-to-back specifications of the EFT8A..................................................................................11-28
Table 11-15 Versions of the EGT2...................................................................................................................11-29
Table 11-16 Functions and features of the EGT2.............................................................................................11-30
Table 11-17 Optical interfaces of the N1EGT2/N2EGT2................................................................................11-37
Table 11-18 Electrical interfaces of the N2EGT2............................................................................................11-37
Table 11-19 Pin assignments of the RJ-45 interface of the N2EGT2..............................................................11-37
Table 11-20 Relationship between the feature code of the EGT2 and the type of interface............................11-38
Table 11-21 Parameters specified for the optical interfaces of the EGT2........................................................11-39
Table 11-22 Throughput specifications of the N1EGT2..................................................................................11-41
Table 11-23 Packet loss ratio in the case of overloading of the N1EGT2.......................................................11-42
Table 11-24 Latency specifications of the N1EGT2........................................................................................11-42
Table 11-25 Back-to-back specifications of the N1EGT2...............................................................................11-43
Table 11-26 Throughput specifications of the N2EGT2..................................................................................11-44
Table 11-27 Packet loss ratio in the case of overloading of the N2EGT2.......................................................11-45
Table 11-28 Latency specifications of the N2EGT2........................................................................................11-46
Table 11-29 Back-to-back specifications of the N2EGT2...............................................................................11-47
Table 11-30 Versions of the EFS0...................................................................................................................11-48
Table 11-31 Functions and features of the EFS0.............................................................................................11-50
Table 11-32 Slots valid for the EFS0 and the corresponding slots for the ETF8 and EFF8............................11-58
Table 11-33 Slots for the EFS0, ETS8, and TSB8...........................................................................................11-60
Table 11-34 Throughput specifications of the N4EFS0...................................................................................11-61
Table 11-35 Packet loss ratio in the case of overloading of the N4EFS0........................................................11-62
Table 11-36 Latency specifications of the N4EFS0.........................................................................................11-63
Table 11-37 Back-to-back specifications of the N4EFS0................................................................................11-64
Table 11-38 Throughput specifications of the N5EFS0...................................................................................11-65
Tables
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Table 11-39 Packet loss ratio in the case of overloading of the N5EFS0........................................................11-66
Table 11-40 Latency specifications of the N5EFS0.........................................................................................11-67
Table 11-41 Back-to-back specifications of the N5EFS0................................................................................11-68
Table 11-42 Functions and features of the EFS0A...........................................................................................11-70
Table 11-43 Slots valid for the EFS0A and the corresponding slots for the ETF8 and EFF8.........................11-77
Table 11-44 Slots for the EFS0A, ETS8, and TSB8........................................................................................11-79
Table 11-45 Throughput specifications of the EFS0A.....................................................................................11-81
Table 11-46 Packet loss ratio in the case of overloading of the EFS0A..........................................................11-82
Table 11-47 Latency specifications of the EFS0A...........................................................................................11-83
Table 11-48 Back-to-back specifications of the EFS0A..................................................................................11-83
Table 11-49 Versions of the EFS4...................................................................................................................11-85
Table 11-50 Functions and features of the EFS4.............................................................................................11-86
Table 11-51 Interfaces of the EFS4..................................................................................................................11-93
Table 11-52 Pins of the RJ-45 connector.........................................................................................................11-93
Table 11-53 Throughput specifications of the N2EFS4...................................................................................11-96
Table 11-54 Packet loss ratio in the case of overloading of the N2EFS4........................................................11-96
Table 11-55 Latency specifications of the N2EFS4.........................................................................................11-97
Table 11-56 Back-to-back specifications of the N2EFS4................................................................................11-98
Table 11-57 Throughput specifications of the N3EFS4...................................................................................11-99
Table 11-58 Packet loss ratio in the case of overloading of the N3EFS4......................................................11-100
Table 11-59 Latency specifications of the N3EFS4.......................................................................................11-101
Table 11-60 Back-to-back specifications of the N3EFS4..............................................................................11-102
Table 11-61 Versions of the EGS2.................................................................................................................11-103
Table 11-62 Functions and features of the EGS2...........................................................................................11-105
Table 11-63 Optical interfaces of the N2EGS2/N3EGS2..............................................................................11-112
Table 11-64 Electrical interfaces of the N3EGS2..........................................................................................11-112
Table 11-65 Pin assignments of the RJ-45 interface of the N3EGS2............................................................11-112
Table 11-66 Relationship between the feature code of the EGS2 and the type of interface..........................11-113
Table 11-67 Parameters specified for the optical interfaces of the EGS2......................................................11-114
Table 11-68 Parameters specified for the electrical interfaces of the EGS2..................................................11-115
Table 11-69 Throughput specifications of the N2EGS2................................................................................11-116
Table 11-70 Packet loss ratio in the case of overloading of the N2EGS2......................................................11-117
Table 11-71 Latency specifications of the N2EGS2......................................................................................11-118
Table 11-72 Back-to-back specifications of the N2EGS2..............................................................................11-119
Table 11-73 Throughput specifications of the N3EGS2................................................................................11-120
Table 11-74 Packet loss ratio in the case of overloading of the N3EGS2......................................................11-121
Table 11-75 Latency specifications of the N3EGS2......................................................................................11-122
Table 11-76 Back-to-back specifications of the N3EGS2..............................................................................11-123
Table 11-77 Functions and features of the EMS2..........................................................................................11-125
Table 11-78 Optical interfaces of the EMS2..................................................................................................11-133
Table 11-79 Electrical interfaces of the EMS2...............................................................................................11-133
Table 11-80 Pin assignments of the RJ-45 interface of the EMS2.................................................................11-133
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Table 11-81 Slots valid for the EMS2 and the corresponding slots for the ETF8 and EFF8.........................11-134
Table 11-82 Relationship between the feature code of the EMS2 and the type of interface.........................11-135
Table 11-83 Parameters specified for the optical interfaces of the EMS2.....................................................11-135
Table 11-84 Throughput specifications of the EMS2 (three VC-3s is bound on the FE port).......................11-137
Table 11-85 Throughput specifications of the EMS2 (48 VC-12s are bound on the GE port)......................11-138
Table 11-86 Packet loss ratio in the case of overloading of the EMS2 (three VC-3s is bound on the FE port)
.........................................................................................................................................................................11-139
Table 11-87 Packet loss ratio in the case of overloading of the EMS2 (48 VC-12s are bound on the GE port)
.........................................................................................................................................................................11-139
Table 11-88 Latency specifications of the EMS2 (three VC-3s is bound on the FE port).............................11-140
Table 11-89 Latency specifications of the EMS2 (48 VC-12s are bound on the GE port)............................11-141
Table 11-90 Back-to-back specifications of the EMS2 (three VC-3s is bound on the FE port)....................11-142
Table 11-91 Back-to-back specifications of the EMS2 (48 VC-12s are bound on the GE port)...................11-143
Table 11-92 Functions and features of the EMS4..........................................................................................11-146
Table 11-93 Optical interfaces of the EMS4..................................................................................................11-154
Table 11-94 Electrical interfaces of the EMS4...............................................................................................11-154
Table 11-95 Pin assignments of the RJ-45 interface of the EMS4.................................................................11-154
Table 11-96 Slots valid for the EMS4 and the corresponding slots for the ETF8 and EFF8.........................11-155
Table 11-97 Relationship between the feature code of the EMS4 and the type of interface.........................11-156
Table 11-98 Parameters specified for the optical interfaces of the EMS4.....................................................11-161
Table 11-99 Throughput specifications of the EMS4 (one VC-4 is bound on the FE port)..........................11-163
Table 11-100 Throughput specifications of the EMS4 (24 VC-3s are bound on the GE port)......................11-163
Table 11-101 Packet loss ratio in the case of overloading of the EMS4 (one VC-4 is bound on the FE port)11-164
Table 11-102 Packet loss ratio in the case of overloading of the EMS4 (24 VC-3s are bound on the GE port)
.........................................................................................................................................................................11-165
Table 11-103 Latency specifications of the EMS4 (one VC-4 is bound on the FE port)...............................11-166
Table 11-104 Latency specifications of the EMS4 (24 VC-3s are bound on the GE port)............................11-167
Table 11-105 Back-to-back specifications of the EMS4 (one VC-4 is bound on the FE port)......................11-168
Table 11-106 Back-to-back specifications of the EMS4 (24 VC-3s are bound on the GE port)...................11-168
Table 11-107 Versions of the EGS4...............................................................................................................11-170
Table 11-108 Functions and features of the EGS4.........................................................................................11-171
Table 11-109 Optical interfaces of the N1EGS4/N3EGS4/N4EGS4.............................................................11-179
Table 11-110 Electrical interfaces of the N1EGS4/N4EGS4.........................................................................11-179
Table 11-111 Pin assignments of the RJ-45 interface of the N1EGS4/N4EGS4...........................................11-179
Table 11-112 Relationship between the feature code of the EGS4 and the type of interface........................11-180
Table 11-113 Parameters specified for the optical interfaces of the EGS4....................................................11-185
Table 11-114 Parameters specified for the electrical interfaces of the EGS4................................................11-185
Table 11-115 Throughput specifications of the N1EGS4..............................................................................11-187
Table 11-116 Packet loss ratio in the case of overloading of the N1EGS4....................................................11-188
Table 11-117 Latency specifications of the N1EGS4....................................................................................11-189
Table 11-118 Back-to-back specifications of the N1EGS4............................................................................11-190
Table 11-119 Throughput specifications of the N4EGS4..............................................................................11-191
Table 11-120 Packet loss ratio in the case of overloading of the N4EGS4....................................................11-192
Tables
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Table 11-121 Latency specifications of the N4EGS4....................................................................................11-193
Table 11-122 Back-to-back specifications of the N4EGS4............................................................................11-194
Table 11-123 Functions and features of the EAS2 board...............................................................................11-196
Table 11-124 Interfaces of the EAS2.............................................................................................................11-201
Table 11-125 Parameters specified for the optical interfaces of the EAS2....................................................11-202
Table 11-126 Throughput specifications of the EAS2...................................................................................11-203
Table 11-127 Packet loss ratio in the case of overloading of the EAS2.........................................................11-204
Table 11-128 Latency specifications of the EAS2.........................................................................................11-204
Table 11-129 Interfaces of the EFF8..............................................................................................................11-208
Table 11-130 Slots valid for the EFT8/EFS0/EMR0/EFP0 and the corresponding slots for the EFF8.........11-208
Table 11-131 Slots valid for the EMS4 and the corresponding slots for the EFF8........................................11-208
Table 11-132 Parameters specified for the optical interfaces of the EFF8.....................................................11-209
Table 11-133 Interfaces of the EFF8A...........................................................................................................11-213
Table 11-134 Slots valid for the N5EFS0 and the corresponding slots for the EFF8A.................................11-213
Table 11-135 Parameters specified for the optical interfaces of the EFF8A..................................................11-213
Table 11-136 Interfaces of the ETF8..............................................................................................................11-217
Table 11-137 Pin assignments of the RJ-45 connector of the ETF8..............................................................11-218
Table 11-138 Slots valid for the EFT8/EFS0/EMR0/EFP0 and the corresponding slots for the ETF8.........11-218
Table 11-139 Slots valid for the EMS4 and the corresponding slots for the ETF8.......................................11-219
Table 11-140 Parameters specified for the optical interfaces of the ETF8....................................................11-219
Table 11-141 Interfaces of the ETF8A...........................................................................................................11-222
Table 11-142 Pin assignments of the RJ-45 connector of the ETF8A...........................................................11-223
Table 11-143 Slots valid for the N5EFS0 and the corresponding slots for the ETF8A.................................11-223
Table 11-144 Parameters specified for the optical interfaces of the ETF8A.................................................11-224
Table 11-145 Interfaces of the ETS8..............................................................................................................11-227
Table 11-146 Pin assignments of the RJ-45 connector of the ETS8..............................................................11-227
Table 11-147 Slots valid for the EFS0 and the corresponding slots for the ETS8.........................................11-227
Table 11-148 Slots valid for the EFS0A and the corresponding slots for the ETS8......................................11-228
Table 11-149 Parameters specified for the optical interfaces of the ETS8....................................................11-228
Table 12-1 Functions and features of the ADL4................................................................................................12-4
Table 12-2 Optical interface of the ADL4 .........................................................................................................12-9
Table 12-3 Relationship between the feature code of the ADL4 and the type of optical interface....................12-9
Table 12-4 Parameters specified for the optical interfaces of the ADL4.........................................................12-10
Table 12-5 Functions and features of the ADQ1..............................................................................................12-13
Table 12-6 Optical interfaces of the ADQ1......................................................................................................12-18
Table 12-7 Relationship between the feature code of the ADQ1 and the type of optical interface.................12-18
Table 12-8 Parameters specified for the optical interfaces of the ADQ1.........................................................12-19
Table 12-9 Functions and features of the IDL4................................................................................................12-22
Table 12-10 Optical interface of the IDL4.......................................................................................................12-27
Table 12-11 Relationship between the feature code of the IDL4 and the type of optical interface.................12-27
Table 12-12 Parameters specified for the optical interfaces of the IDL4.........................................................12-28
Table 12-13 Functions and features of the IDQ1.............................................................................................12-31
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Table 12-14 Optical interfaces of the IDQ1.....................................................................................................12-36
Table 12-15 Relationship between the feature code of the IDQ1 and the type of optical interface.................12-36
Table 12-16 Parameters specified for the optical interfaces of the IDQ1........................................................12-37
Table 13-1 Functions and features of the EGR2................................................................................................13-3
Table 13-2 Optical interfaces of the EGR2 .....................................................................................................13-11
Table 13-3 Relationship between the feature code of the EGR2 and the type of optical interface..................13-11
Table 13-4 Parameters specified for the optical interfaces of the EGR2.........................................................13-12
Table 13-5 Throughput specifications of the EGR2.........................................................................................13-14
Table 13-6 Packet loss ratio in the case of overloading of the EGR2..............................................................13-15
Table 13-7 Latency specifications of the EGR2...............................................................................................13-16
Table 13-8 Back-to-back specifications of the EGR2......................................................................................13-16
Table 13-9 Functions and features of the EMR0..............................................................................................13-19
Table 13-10 Interfaces of the EMR0................................................................................................................13-27
Table 13-11 Slots valid for the EMR0 and the corresponding slots for the ETF8 and EFF8..........................13-28
Table 13-12 Relationship between the feature code of the EMR0 and the type of optical interface...............13-28
Table 13-13 Parameters specified for the optical interfaces of the EMR0.......................................................13-29
Table 13-14 Throughput specifications of the EMR0 (eight VC-4s are bound on the FE port)......................13-31
Table 13-15 Throughput specifications of the EMR0 (eight VC-4s are bound on the GE port).....................13-31
Table 13-16 Packet loss ratio in the case of overloading of the EMR0 (eight VC-4s are bound on the FE port)
...........................................................................................................................................................................13-32
Table 13-17 Packet loss ratio in the case of overloading of the EMR0 (eight VC-4s are bound on the GE port)
...........................................................................................................................................................................13-33
Table 13-18 Latency specifications of the EMR0 (eight VC-4s are bound on the FE port)............................13-34
Table 13-19 Latency specifications of the EMR0 (eight VC-4s are bound on the GE port)...........................13-34
Table 13-20 Back-to-back specifications of the EMR0 (eight VC-4s are bound on the FE port)...................13-35
Table 13-21 Back-to-back specifications of the EMR0 (eight VC-4s are bound on the GE port)...................13-36
Table 14-1 Functions and features of the MST4................................................................................................14-3
Table 14-2 Service types service rates supported by the MST4.........................................................................14-4
Table 14-3 Optical interfaces of the MST4........................................................................................................14-8
Table 14-4 Relationship between the feature code of the MST4, the type of supported services, type of optical
interface, and transmission distance....................................................................................................................14-9
Table 14-5 Parameters specified for the optical interfaces of the MST4.........................................................14-10
Table 15-1 Functions and features of the IFSD1................................................................................................15-3
Table 15-2 Interfaces of the IFSD1....................................................................................................................15-8
Table 15-3 Radio work modes..........................................................................................................................15-10
Table 15-4 IF performance...............................................................................................................................15-11
Table 15-5 Baseband signal processing performance of the modem...............................................................15-12
Table 15-6 Functions and features of the RPWR.............................................................................................15-14
Table 15-7 Interfaces of the RPWR.................................................................................................................15-18
Table 16-1 Functions and features of the CMR2...............................................................................................16-3
Table 16-2 Optical interfaces of the CMR2.......................................................................................................16-6
Table 16-3 Feature code of the CMR2...............................................................................................................16-6
Table 16-4 Parameters specified for the optical interfaces of the CMR2...........................................................16-7
Tables
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Table 16-5 Functions and features of the CMR4...............................................................................................16-9
Table 16-6 Optical interfaces of the CMR4.....................................................................................................16-12
Table 16-7 Feature code of the CMR4.............................................................................................................16-12
Table 16-8 Parameters specified for the optical interfaces of the CMR4.........................................................16-13
Table 16-9 Functions and features of the MR2................................................................................................16-16
Table 16-10 Optical interfaces of the MR2......................................................................................................16-19
Table 16-11 Feature code of the MR2..............................................................................................................16-19
Table 16-12 Parameters specified for the optical interfaces of the MR2.........................................................16-20
Table 16-13 Functions and features of the MR2A...........................................................................................16-22
Table 16-14 Optical interfaces of the MR2A...................................................................................................16-25
Table 16-15 Parameters specified for the optical interfaces of the MR2A......................................................16-26
Table 16-16 Functions and features of the MR2C...........................................................................................16-28
Table 16-17 Optical interfaces of the MR2C...................................................................................................16-31
Table 16-18 Parameters specified for the optical interfaces of the MR2C.......................................................16-32
Table 16-19 Functions and features of the MR4..............................................................................................16-34
Table 16-20 Optical interfaces of the MR4......................................................................................................16-37
Table 16-21 Feature code of the MR4..............................................................................................................16-38
Table 16-22 Parameters specified for the optical interfaces of the MR4.........................................................16-38
Table 16-23 Functions and features of the LWX.............................................................................................16-41
Table 16-24 Optical interfaces of the LWX.....................................................................................................16-45
Table 16-25 Relationship between the feature code of the LWX and the signal receive/transmit scheme.....16-45
Table 16-26 Parameters specified for the client-side optical interfaces of the LWX.......................................16-46
Table 16-27 Parameters specified for the WDM-side optical interfaces of the LWX.....................................16-47
Table 16-28 Functions and features of the FIB................................................................................................16-50
Table 16-29 Optical interfaces of the FIB .......................................................................................................16-51
Table 16-30 Parameters specified for the optical interfaces of the FIB...........................................................16-52
Table 17-1 Functions and features of the AUX..................................................................................................17-3
Table 17-2 External time input interfaces..........................................................................................................17-4
Table 17-3 External time input interfaces..........................................................................................................17-4
Table 17-4 Interfaces of the AUX......................................................................................................................17-8
Table 17-5 Pins of the CLK1 and CLK2 interfaces...........................................................................................17-9
Table 17-6 Pins of the ETH, COM, EXT, and F1 interfaces.............................................................................17-9
Table 17-7 Pins of the F&f interface................................................................................................................17-10
Table 17-8 Pins of the PHONE, V1, and V2 interfaces...................................................................................17-10
Table 17-9 Pins of the LAMP1 and LAMP2 interfaces...................................................................................17-10
Table 17-10 Pins of the ALM01 and ALM02 interfaces..................................................................................17-11
Table 17-11 Pins of the OAM interface...........................................................................................................17-11
Table 17-12 Pins of the S1, S2, S3, and S4 interfaces of the AUX..................................................................17-12
Table 17-13 Pins of the ALMI1 interface........................................................................................................17-12
Table 17-14 Pins of the ALMI2 interface........................................................................................................17-13
Table 17-15 Pins of the ALMI3 interface........................................................................................................17-13
Table 17-16 Pins of the ALMI4 interface........................................................................................................17-14
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Table 17-17 Functions and features of the FAN..............................................................................................17-16
Table 18-1 Functions and features of the BA2...................................................................................................18-3
Table 18-2 Optical interface of the one-interface BA2......................................................................................18-8
Table 18-3 Optical interfaces of the two-interface BA2....................................................................................18-8
Table 18-4 Relationship between the feature code of the BA2 and the output optical power...........................18-9
Table 18-5 Parameters specified for the optical interfaces of the BA2..............................................................18-9
Table 18-6 Versions of the BPA.......................................................................................................................18-11
Table 18-7 Functions and features of the BPA.................................................................................................18-12
Table 18-8 Optical interfaces of the BPA........................................................................................................18-15
Table 18-9 Relationship between the feature code of the BPA and the output optical power.........................18-16
Table 18-10 Parameters specified for the optical interfaces of the BPA..........................................................18-16
Table 18-11 Versions of the COA....................................................................................................................18-18
Table 18-12 Functions and features of the 61COA/N1COA...........................................................................18-19
Table 18-13 Functions and features of the 62COA..........................................................................................18-21
Table 18-14 Pin assignments of the RS-232 serial port...................................................................................18-25
Table 18-15 Pin assignments of the MONITOR interfaces.............................................................................18-26
Table 18-16 Pin assignments of the RJ-45 connector of the 62COA...............................................................18-26
Table 18-17 Relationship between the feature code of the 61COA and the output optical power..................18-28
Table 18-18 Parameters specified for the optical interfaces of the COA.........................................................18-28
Table 18-19 Functions and features of the RPC01...........................................................................................18-31
Table 18-20 Interfaces of the RPC01...............................................................................................................18-34
Table 18-21 Feature code of the RPC01..........................................................................................................18-35
Table 18-22 Serial numbers of the optical interfaces on the front panel of the RPC01 on the NMS..............18-36
Table 18-23 Parameters specified for the optical interfaces of the RPC01......................................................18-36
Table 18-24 Functions and features of the RPC02...........................................................................................18-38
Table 18-25 Interfaces of the RPC02...............................................................................................................18-41
Table 18-26 Feature code of the RPC02..........................................................................................................18-42
Table 18-27 Serial numbers of the optical interfaces on the front panel of the RPC02 on the NMS..............18-42
Table 18-28 Parameters specified for the optical interfaces of the RPC02......................................................18-43
Table 18-29 Functions and features of the OBU1............................................................................................18-45
Table 18-30 Optical interfaces of the OBU1....................................................................................................18-48
Table 18-31 Feature code of the OBU1............................................................................................................18-48
Table 18-32 Parameters specified for the optical interfaces of the OBU1.......................................................18-49
Table 18-33 Versions of the DCU....................................................................................................................18-51
Table 18-34 Functions and features of the DCU..............................................................................................18-52
Table 18-35 Optical interface of the one-interface DCU.................................................................................18-56
Table 18-36 Optical interfaces of the two-interface DCU................................................................................18-56
Table 18-37 Relationship between the feature code of the DCU and the compensated dispersion.................18-57
Table 18-38 Parameters specified for the optical interfaces of the DCU.........................................................18-58
Table 19-1 Mapping policies of UPM on the OptiX OSN 3500........................................................................19-3
Table 19-2 Functions and features of the EPS75-4815AF.................................................................................19-4
Table 19-3 Interfaces of the EPS75-4815AF.....................................................................................................19-7
Tables
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Table 19-4 Power parameters of the UPM.........................................................................................................19-8
Table 19-5 Functions and features of the PIU..................................................................................................19-10
Table 19-6 Interfaces of the PIU......................................................................................................................19-13
Table 19-7 Functions and features of the PIUA...............................................................................................19-15
Table 19-8 Interfaces of the PIUA...................................................................................................................19-17
Table 19-9 Functions and features of the PIUB board.....................................................................................19-19
Table 19-10 Description of the interfaces on the PIUB board.........................................................................19-22
Table 19-11 Pin description of the PWS interfaces on the PIUB board...........................................................19-22
Table 20-1 Mapping table of the BOM numbers and the types of the SFP/eSFP optical modules ..................20-3
Table 20-2 Mapping table of the BOM numbers and the types of the XFP optical modules............................20-8
Table 20-3 Mapping table of the BOM numbers and the types of the 1.25 Gbit/s CWDM eSFP optical modules
.............................................................................................................................................................................20-9
Table 20-4 Mapping table of the BOM numbers and the types of the 10 Gbit/s DWDM XFP optical modules
...........................................................................................................................................................................20-10
Table 21-1 Categories of the fiber jumpers that the OptiX OSN equipment uses.............................................21-2
Table 21-2 Types of fiber connectors.................................................................................................................21-3
Table 21-3 Technical specifications of the power cable of the cabinet for the N1PDU....................................21-8
Table 21-4 Technical specifications of the power cable of the cabinet for the TN51PDU................................21-8
Table 21-5 Pin assignments of the general and enhanced subrack (1100 W) subrack power cable................21-11
Table 21-6 Technical specifications of the power cable for thegeneral and enhanced subrack (1100 W) subrack
...........................................................................................................................................................................21-11
Table 21-7 Technical specifications of the power cable for the large power subrack.....................................21-11
Table 21-8 Pin assignments of the COA power cable......................................................................................21-12
Table 21-9 Pin assignments of the cabinet indicator cable...............................................................................21-14
Table 21-10 Pin assignments of the indicator cascading cable between subracks or the alarm cascading cable
between the OptiX OSN equipment..................................................................................................................21-15
Table 21-11 Pin assignments of the alarm cascading cable between the OptiX OSN equipment and the other Huawei
transmission equipment.....................................................................................................................................21-17
Table 21-12 Pin assignments of the alarm input/output cable..........................................................................21-19
Table 21-13 Pin assignments of the OAM serial port cable.............................................................................21-21
Table 21-14 Pin assignments of the serial 14/F1/F&f serial port cable.........................................................21-22
Table 21-15 Pin assignments of the RS-232/RS-422 serial port cable.............................................................21-24
Table 21-16 Pin assignments of the ordinary telephone line............................................................................21-25
Table 21-17 Pin assignments of the COA cascading cable..............................................................................21-26
Table 21-18 Pin assignments of the straight through cable..............................................................................21-27
Table 21-19 Pin assignments of the crossover cable........................................................................................21-28
Table 21-20 Pin assignments of the 75-ohm 8xE1 cable.................................................................................21-30
Table 21-21 Specifications of the 75-ohm E1 cable with the external braid shield layer................................21-31
Table 21-22 Specifications of the 75-ohm E1 cable without the external braid shield layer...........................21-32
Table 21-23 Pin assignments of the 120-ohm 8xE1 cable...............................................................................21-33
Table 21-24 Pin assignments of the DB28 connector of the DM12.................................................................21-36
Table 21-25 Pin assignments of the V.35 DCE cable......................................................................................21-38
Table 21-26 Pin assignments of the V.35 DTE cable.......................................................................................21-40
Table 21-27 Pin assignments of the V.24 DCE cable......................................................................................21-41
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Table 21-28 Technical specifications of the V.24 DCE cable..........................................................................21-42
Table 21-29 Pin assignments of the V.24 DTE cable.......................................................................................21-43
Table 21-30 Technical specifications of the V.24 DTE cable..........................................................................21-44
Table 21-31 Pin assignments of the X.21 DCE cable......................................................................................21-44
Table 21-32 Technical specifications of the X.21 DCE cable..........................................................................21-45
Table 21-33 Pin assignments of the X.21 DTE cable.......................................................................................21-46
Table 21-34 Technical specifications of the X.12 DTE cable..........................................................................21-47
Table 21-35 Pin assignments of the RS-449 DCE cable..................................................................................21-47
Table 21-36 Technical specifications of the RS-449 DCE cable.....................................................................21-48
Table 21-37 Pin assignments of the RS-449 DTE cable..................................................................................21-49
Table 21-38 Technical specifications of the RS-449 DTE cable.....................................................................21-50
Table 21-39 Pin assignments of the RS-530 DCE cable..................................................................................21-51
Table 21-40 Technical specifications of the RS-530 DCE cable.....................................................................21-52
Table 21-41 Pin assignments of the RS-530 DTE cable..................................................................................21-53
Table 21-42 Technical specifications of the RS-530 DTE cable.....................................................................21-54
Table 21-43 Pin assignments of the 120-ohm clock cable...............................................................................21-55
Table 21-44 Pin assignments of the two-channel 75-ohm-to-120-ohm clock transit cable.............................21-57
Table 23-1 Labels on the equipment..................................................................................................................23-2
Table 23-2 Huawei specifications for the engineering labels.............................................................................23-7
Table 24-1 Information on whether a board of a specific version is supported by the OptiX OSN products
.............................................................................................................................................................................24-2
Table 24-2 Common parameters specified for the optical interfaces of the SDH boards..................................24-9
Table 24-3 Common parameters specified for optical interfaces of SDH boards (FEC boards).....................24-14
Table 24-4 Common parameters specified for the optical interfaces of the packet boards..............................24-15
Table 24-5 Common parameters specified for the optical interfaces of the data boards.................................24-17
Table 24-6 Basic functions of SDH boards......................................................................................................24-19
Table 24-7 Basic functions of PDH boards......................................................................................................24-22
Table 24-8 Basic functions of data boards.......................................................................................................24-23
Table 24-9 Basic functions of packet boards....................................................................................................24-25
Table 24-10 Loopback capability of the SDH boards......................................................................................24-29
Table 24-11 Information on whether each SDH board of the OptiX OSN equipment supports the insertion of the
AU_AIS when the board is looped back...........................................................................................................24-31
Table 24-12 Loopback capability of the PDH boards......................................................................................24-33
Table 24-13 Loopback capability of the data boards of the OptiX OSN equipment.......................................24-34
Table 24-14 Loopback capability of the ATM/IMA boards of the OptiX OSN equipment............................24-35
Table 24-15 Loopback capability of the packet boards of the OptiX OSN equipment....................................24-36
Table 24-16 Loopback capability of the dual-plane boards of the OptiX OSN equipment.............................24-37
Table 24-17 Protection schemes that the SDH boards of the OptiX OSN equipment support........................24-37
Table 24-18 Protection schemes that the PDH boards of the OptiX OSN equipment support........................24-39
Table 24-19 Protection schemes that the data boards of the OptiX OSN equipment support..........................24-40
Table 24-20 Protection schemes that the microwave boards of the OptiX OSN equipment support..............24-42
Table 24-21 Protection schemes that the packet boards of the OptiX OSN equipment support......................24-43
Table 24-22 Protection schemes that the dual-plane boards of the OptiX OSN equipment support...............24-43
Tables
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Table 24-23 Power consumption and weight of each board............................................................................24-44
Table 25-1 Relationship between the service type and the parameter settings of the C2 byte...........................25-5
Table 25-2 Relationship between the service type and the parameter settings of the V5 byte..........................25-5
Table 25-3 Relation between the service type and the value of the V5 byte......................................................25-7
Table 25-4 Relation between the service type and the value of the C2 byte....................................................25-11
Table 25-5 Relation between the service type and the value of the C2 byte....................................................25-11
Table 25-6 Relation between the service type and the value of the V5 byte....................................................25-12
Table 25-7 Parameters that need to be set for the cross-connect and timing units...........................................25-21
OptiX OSN 3500 Intelligent Optical Transmission System
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About This Document
Purpose
This document describes the structure, composition, boards, and cables of the OptiX OSN
equipment.
The readers can have a comprehensive understanding of the hardware of the OptiX OSN
equipment through this document.
Related Versions
The following table lists the product versions related to this document.
Product Name Version
OptiX OSN 3500 V200R011

Intended Audience
This document is intended for:
l Network design and planning engineers
l Hardware installers
Organization
This document is organized as follows.
Chapter Description
1 Equipment Structure Introduces the structure of the equipment.
2 Cabinet Describes the dimensions, appearances,
technical specifications, and configurations of
the cabinets that can house the equipment.
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Chapter Description
3 Subrack Describes the structure of the subrack.
4 Board List and Classification Describes the appearance and classification of
the boards.
5 Cross-Connect Boards and System
Control Boards
Describes the functions, working principles,
front panels, jumpers, interfaces, and technical
specifications of the cross-connect boards and
SCC boards.
6 Packet Boards Describes the versions, functions, working
principles, front panels, interfaces, valid slots,
and technical specifications of the packet
transmission boards.
7 Dual-Plane Bridging Boards Describes the functions, working principle,
front panel, jumpers, interfaces, and technical
specifications of the dual-plane bridging
board.
8 CES Boards Describes the versions, functions, working
principles, front panels, interfaces, valid slots,
and technical specifications of the CES boards.
9 SDH Boards Describes the versions, functions, working
principles, front panels, interfaces, valid slots,
and technical specifications of the SDH
boards.
10 PDH Boards Describes the versions, functions, working
principles, front panels, interfaces, valid slots,
and technical specifications of the PDH
boards.
11 EoS Boards Describes the versions, functions, working
principles, front panels, interfaces, valid slots,
and technical specifications of the EOS boards.
12 ATM Boards Describes the versions, functions, working
principles, front panels, interfaces, valid slots,
and technical specifications of the ATM
boards.
13 RPR Boards Describes the versions, functions, working
principles, front panels, interfaces, valid slots,
and technical specifications of the RPR boards.
14 SAN Boards Describes the versions, functions, working
principles, front panels, interfaces, valid slots,
and technical specifications of the SAN
boards.
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Chapter Description
15 Microwave Boards Describes the versions, functions, working
principles, front panels, interfaces, valid slots,
and technical specifications of the microwave
boards.
16 WDM Boards Describes the versions, functions, working
principles, front panels, interfaces, valid slots,
and technical specifications of the WDM
boards.
17 Auxiliary Boards Describes the versions, functions, working
principles, front panels, interfaces, valid slots,
and technical specifications of the auxiliary
boards.
18 Optical Amplifier Boards and
Dispersion Compensation Boards
Describes the versions, functions, working
principles, front panels, interfaces, valid slots,
and technical specifications of the optical
amplifier boards and dispersion compensation
boards.
19 Power Boards Describes the versions, functions, working
principles, front panels, interfaces, valid slots,
and technical specifications of the power
boards.
20 Pluggable Optical Module Describes the BOM number and types of
optical modules supported by the boards.
21 Cables Describes the structure, appearance, pin
assignments, and technical specifications of
the external cables and internal cables that the
equipment uses.
22 Indicators Describes the indicators on the equipment and
the indicators on the boards of the equipment.
23 Labels Describes the safety labels, optical module
labels, and engineering labels on the
equipment.
24 Board Information Quick Reference Describes the version compatibility, interface
specifications, loopback capability, and
supported protection schemes of boards.
25 Parameter Settings Describes the parameters that can be set by
using the T2000.
A Glossary Lists the terms that are used in this document.
B Acronyms and Abbreviations Lists the acronyms and abbreviations that are
used in this document.

OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description About This Document
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3
Conventions
Symbol Conventions
The symbols that may be found in this document are defined as follows.
Symbol Description
DANGER
Indicates a hazard with a high level of risk, which if not
avoided, will result in death or serious injury.
WARNING
Indicates a hazard with a medium or low level of risk, which
if not avoided, could result in minor or moderate injury.
CAUTION
Indicates a potentially hazardous situation, which if not
avoided, could result in equipment damage, data loss,
performance degradation, or unexpected results.
TIP
Indicates a tip that may help you solve a problem or save
time.
NOTE
Provides additional information to emphasize or supplement
important points of the main text.

General Conventions
The general conventions that may be found in this document are defined as follows.
Convention Description
Times New Roman Normal paragraphs are in Times New Roman.
Boldface Names of files, directories, folders, and users are in
boldface. For example, log in as user root.
Italic Book titles are in italics.
Courier New Examples of information displayed on the screen are in
Courier New.

Command Conventions
The command conventions that may be found in this document are defined as follows.
Convention Description
Boldface The keywords of a command line are in boldface.
Italic Command arguments are in italics.
About This Document
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
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Convention Description
[ ] Items (keywords or arguments) in brackets [ ] are optional.
{ x | y | ... } Optional items are grouped in braces and separated by
vertical bars. One item is selected.
[ x | y | ... ] Optional items are grouped in brackets and separated by
vertical bars. One item is selected or no item is selected.
{ x | y | ... }
*
Optional items are grouped in braces and separated by
vertical bars. A minimum of one item or a maximum of all
items can be selected.
[ x | y | ... ]
*
Optional items are grouped in brackets and separated by
vertical bars. Several items or no item can be selected.

GUI Conventions
The GUI conventions that may be found in this document are defined as follows.
Convention Description
Boldface Buttons, menus, parameters, tabs, window, and dialog titles
are in boldface. For example, click OK.
> Multi-level menus are in boldface and separated by the ">"
signs. For example, choose File > Create > Folder.

Keyboard Operations
The keyboard operations that may be found in this document are defined as follows.
Format Description
Key Press the key. For example, press Enter and press Tab.
Key 1+Key 2 Press the keys concurrently. For example, pressing Ctrl+Alt
+A means the three keys should be pressed concurrently.
Key 1, Key 2 Press the keys in turn. For example, pressing Alt, A means
the two keys should be pressed in turn.

Mouse Operations
The mouse operations that may be found in this document are defined as follows.
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Action Description
Click Select and release the primary mouse button without moving
the pointer.
Double-click Press the primary mouse button twice continuously and
quickly without moving the pointer.
Drag Press and hold the primary mouse button and move the
pointer to a certain position.

Update History
Updates between document issues are cumulative. Therefore, the latest document issue contains
all updates made in previous issues.
Updates in Issue 01 (2010-01-15) Based on Product Version V200R011
This document of the V200R011 version is of the first release.
About This Document
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
6 Huawei Proprietary and Confidential
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1 Equipment Structure
The OptiX OSN 3500 equipment consists of the cabinet, cabinet doors, DC power distribution
unit (PDU), subracks, orderwire phone fixing frame, boards, and cables. The OptiX OSN 3500
subrack can be installed in a 300 mm or 600 mm ETSI cabinet.
Figure 1-1 shows the appearance of the OptiX OSN 3500 that is installed in the 300 mm ETSI
cabinet.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 1 Equipment Structure
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Figure 1-1 Appearance of the OptiX OSN 3500 that is installed in the 300 mm ETSI cabinet
7
7
W
H
D
1
2
3
4
5
6
8
7
1. DC PDU 2. Side panel 3. Cable distribution plate 4. Orderwire phone fixing frame
5. Subrack 6. Cabinet 7. Fiber management tray 8. Front door

Figure 1-2 shows the appearance of the general OptiX OSN 3500 subrack and enhanced OptiX
OSN 3500 subrack (1100 W).
1 Equipment Structure
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Figure 1-2 Appearance of the general OptiX OSN 3500 subrack and enhanced OptiX OSN 3500
subrack (1100 w)
1
2
3
4
1. Interface board area 2. Fan area 3. Processing board area 4. Cable routing area

Figure 1-3 shows the appearance of the enhanced OptiX OSN 3500 subrack (2300 W).
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 1 Equipment Structure
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Figure 1-3 Appearance of the enhanced OptiX OSN 3500 subrack (2300 W)
1
2
3
4
1. Interface board area 2. Fan area 3. Processing board area 4. Cable routing area

1 Equipment Structure
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2 Cabinet
About This Chapter
The OptiX OSN subracks are installed in the cabinets.
2.1 Types of Cabinets
The OptiX OSN 3500 subrack can be installed in the 300 mm or 600 mm ETSI cabinet.
2.2 Configuration of the Cabinet
An ETSI cabinet has indicators and a DC PDU at the top.
2.3 Technical Specifications
The technical specifications of the cabinet include the dimensions, weight, and number of
permitted subracks.
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2.1 Types of Cabinets
The OptiX OSN 3500 subrack can be installed in the 300 mm or 600 mm ETSI cabinet.
NOTE
The cabinets described in this topic are provided by Huawei.
The 300 mm ETSI cabinet is available in two types, namely, T63 cabinet and N63E cabinet.
Figure 2-1 shows the appearances of the T63 cabinet and N63E cabinet.
2 Cabinet
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Figure 2-1 Appearances of the T63 cabinet and N63E cabinet
T63 Cabinet N63E Cabinet

Comparison Between the Specifications of the T63 Cabinet and the Specifications
of the N63E Cabinet
Table 2-1 provides the comparison between the specifications of the T63 cabinet and the
specifications of the N63E cabinet.
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Table 2-1 Comparison between the specifications of the T63 cabinet and the specifications of
the N63E cabinet
Cabinet Dimensions (mm) Weight (kg)
300 mm ETSI cabinet (T63) 600 (W) x 300 (D) x 2000 (H) 55
600 (W) x 300 (D) x 2200 (H) 60
600 (W) x 300 (D) x 2600 (H) 70
300 mm ETSI cabinet (N63E) 600 (W) x 300 (D) x 2000 (H) 42
600 (W) x 300 (D) x 2200 (H) 45

T63 Cabinet
The specifications of the T63 cabinet comply with the ETSI standard. The T63 cabinet is 600
mm wide and 300 mm deep.
There are two grounding bolts on the frame at the top of the T63 cabinet. Figure 2-2 shows the
locations of the cable holes at the top of the T63 cabinet. Figure 2-3 shows the locations of the
cable holes at the bottom of the T63 cabinet.
Figure 2-2 Locations of the cable holes at the top of the T63 cabinet
110mm 110mm
1
5
m
m
Cabling hole
Cabniet grounding terminal Power cable hole
2
9
5
m
m
1
6
0
m
m
2
0
0
m
m
600mm
106mm 106mm 200mm

2 Cabinet
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Figure 2-3 Locations of the cable holes at the bottom of the T63 cabinet
2
9
5
m
m
1
6
0
m
m
2
0
0
m
m
110mm
1
5
m
m
600mm
106mm 106mm 200mm
Power cable hole
Cabling hole
Cabniet installtion hole

N63E Cabinet
The specifications of the N63E cabinet comply with the ETSI standard. The N63E cabinet is
600 mm wide and 300 mm deep.
There are two grounding bolts on the frame at the top of the N63E cabinet. Figure 2-4 shows
the locations of the cable holes at the top of the N63E cabinet. Figure 2-5 shows the locations
of the cable holes at the bottom of the N63E cabinet.
Figure 2-4 Locations of the cable holes at the top of the N63E cabinet
600mm
251mm
62mm
300mm
81mm
143mm 155mm
188mm
66mm
Power cable hole
Cable hole
Fiber hole Fiber hole
Grounding bolt
Cable hole Cable hole Cable hole

OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 2 Cabinet
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Figure 2-5 Locations of the cable holes at the bottom of the N63E cabinet
360mm
184mm
Fiber hole
Cable hole
Cable hole
Fiber hole

CAUTION
The difference between the cable routing in the case of the T63 cabinet and the cable routing in
the case of the N63E cabinet is with regard to the cable routing at the top and bottom cable holes.
The cable routing in the T63 cabinet is the same as the cable routing in the N63E cabinet.
The T63 cabinet is approximately 16 mm deeper than the N63E cabinet. When you install the
mounting ears of the components, select proper mounting holes according to the type of cabinet
on site.
2.2 Configuration of the Cabinet
An ETSI cabinet has indicators and a DC PDU at the top.
Figure 2-6 shows the positions of the indicators and the DC PDU.
2 Cabinet
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Figure 2-6 ETSI cabinet
1
2
PowerCritical MajorMinor
Power distribution unit
W
H
D
1. Indicators 2. DC PDU

2.2.1 Indicators
The ETSI cabinet has one power indicator and three alarm severity indicators.
2.2.2 DC Power Distribution Unit
The DC power distribution unit (PDU) is located on the top of a cabinet and is used to supply
power to the equipment.
2.2.3 Other Configurations
External case-shaped devices can be installed in a cabinet as required.
2.2.1 Indicators
The ETSI cabinet has one power indicator and three alarm severity indicators.
Table 2-2 provides the meanings of the status of the indicators.
Table 2-2 Meanings of the status of the indicators
Indicator Status Meaning
Power indicator - Power (green) On Power is supplied to the
equipment.
Off Power is not supplied to
the equipment.
Critical alarm indicator - Critical (red) On A critical alarm occurs
on the equipment.
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Indicator Status Meaning
Off No critical alarm
occurs on the
equipment.
Major alarm indicator - Major (orange) On A major alarm occurs
on the equipment.
Off No major alarm occurs
on the equipment.
Minor alarm indicator - Minor (yellow) On A minor alarm occurs
on the equipment.
Off No minor alarm occurs
on the equipment.

CAUTION
The status of the indicators is controlled by the AUX on the subrack. The indicators work only
after the cables of the indicators are correctly connected and the subrack is powered on.
2.2.2 DC Power Distribution Unit
The DC power distribution unit (PDU) is located on the top of a cabinet and is used to supply
power to the equipment.
DC Power Distribution Unit N1PDU
Figure 2-7 shows the front panel of the general cabinet DC PDU, N1PDU.
Figure 2-7 Front panel of the N1PDU
NEG2(-)
INPUT
RTN2(+) RTN1(+) NEG1(-)
2 3 4 5
ON
OFF
20A 32A 32A 20A
ON
OFF
1 2 3 4
1 6
1 2 3 4
20A 32A 32A 20A
OUTPUT OUTPUT A
B
7 8
1. Terminal block (A) 2. Power grounding cable RTN1(+)
2 Cabinet
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3. Power grounding cable RTN2(+) 4. Power cable NEG1(-)
5. Power cable NEG2(-) 6. Terminal block (B)
7. PGND 8. Power switch

In the case of the OptiX OSN 3500, the output terminal block on side A supplies power to the
power interface board on side A of the subrack, and the output terminal block on side B supplies
power to the power interface board on side B of the subrack. Table 2-3 shows the connections
of the output terminal blocks on side A and side B.
Table 2-3 Connections of the output terminal blocks on side A and side B
Terminal
Block on
Side A
Corresponding Subrack
and Power Interface
Board
Terminal
Block on
Side B
Corresponding Subrack
and Power Interface
Board
1 Power interface board on
side A of the first subrack
1 Power interface board on
side B of the first subrack
2 Power interface board on
side A of the second subrack
2 Power interface board on
side B of the second subrack
3 Power interface board on
side A of the third subrack
3 Power interface board on
side B of the third subrack
4 Power interface board on
side A of the fourth subrack
4 Power interface board on
side B of the fourth subrack

NOTE
In the case of an enhanced subrack, the two power inputs work in load-sharing mode (each input carries
16 A). In the telecommunications room, however, the PDU needs to provide power supply of 34 A to an
entire subrack. In the case of a general subrack, the two power inputs work in load-sharing mode (each
input carries 10 A). In the telecommunications room, however, the PDU needs to provide power supply of
20 A to an entire subrack. In this case, power failure will not occur if either of the power inputs fails.
CAUTION
In the case of the OptiX OSN 3500, the first and second terminal blocks are used. The third and
fourth terminal blocks supplies power to other equipment such as case-shaped optical amplifiers.
The number of the subracks increases from the bottom up.
DC Power Distribution Unit TN51PDU
The PDU, TN51PDU, is installed at the top of the cabinet, and is divided into two parts, namely,
part A and part B that back up each other. Part A and part B respectively access four -48 V power
supplies. Among them:
l Connections of main power supply: Party A is connected to RTN(+) and NEG(-).
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 2 Cabinet
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
2-9
l Connections of standby power supply: Party B is connected to RTN(+) and NEG(-).
The TN51PDU provides eight power output interfaces, supplying power to the subracks inside
the cabinet. Figure 2-8 shows the front panel of the TN51PDU.
Figure 2-8 Front panel of the TN51PDU

l Power output area: On both sides of the DC PDU, there are respectively four output terminal
blocks that are used to connect to the power cables of subracks.
l Power input area: The TN51PDU supports corresponding power input capability based on
the power supply capacity of the telecommunications room.
When the telecommunications room provides four power inputs not less than 64 A, part
A and part B can respectively be connected to four -48 V DC power cables and four
power grounding cables, that is, eight -48 V DC power cables and eight power grounding
cables in total.
When the telecommunications room provides two power inputs not less than 120 A,
part A and part B can respectively be connected to two -48 V DC power cables and two
power grounding cables, that is, four-48 V DC power cables and four power grounding
cables in total.
l Power switch area: On both sides of the DC PDU, there are respectively four power output
switches that correspond to the output terminal blocks. The power output switches control
power supply to the corresponding subracks.
2.2.3 Other Configurations
External case-shaped devices can be installed in a cabinet as required.
l Uninterruptible power module (UPM)
l Roman pump amplifiers RPC01 and RPC02
l Orderwire phone
l Dispersion compensation module (DCM)
l Case-shaped optical amplifier (COA)
l Fiber management tray, which is used to manage the excess fibers inside the cabinet.
2.3 Technical Specifications
The technical specifications of the cabinet include the dimensions, weight, and number of
permitted subracks.
2 Cabinet
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
2-10 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Table 2-4 lists the technical specifications of the ETSI cabinet.
Table 2-4 Technical specifications of the ETSI cabinet
Dimensions (mm) Weight (kg) Number of Permitted
Subracks
600 (W) x 300 (D) x 2000 (H) (T63) 58 1
600 (W) x 300 (D) x 2000 (H) (N63E) 41 1
600 (W) x 600 (D) x 2000 (H) (N66T) 71 1
600 (W) x 600 (D) x 2000 (H) (T66) 80 1
600 (W) x 300 (D) x 2200 (H) (T63) 63 2
600 (W) x 300 (D) x 2200 (H) (N63E) 45 2
600 (W) x 600 (D) x 2200 (H) (N66T) 76 2
600 (W) x 600 (D) x 2200 (H) (T66) 85 2
600 (W) x 300 (D) x 2600 (H) (T63) 73 2
600 (W) x 600 (D) x 2600 (H) (T66) 101 2

NOTE
Both the N63E cabinet and N66T cabinet are available in two heights, namely, 2000 mm and 2200 mm. If
the cabinet that is 2600 mm high is required, add an enclosure frame that is 400 mm high on a cabinet that
is 2200 mm high.
The DC power distribution unit (PDU) is located on the top of a cabinet and is used to provide
power to the equipment. Table 2-5 lists the technical specifications of the PDU.
Table 2-5 Technical specifications of the PDU
Board Single-Cabinet
Input Voltage
(V)
Single-Cabinet
Output Voltage
(V)
Output
Current (A)
Maximum
Number of
Allowed
Subracks
N1PDU -48 (DC) -38.4 to -57.6 l 4x20 A
l 4x32 A
2
-60 (DC) -48 to -72
TN51PDU
02
-48 (DC) -38.4 to -57.6 l 4x60 A
l 4x30 A
2
-60 (DC) -48 to -72
NOTE
Two power inputs need to be provided, and they work in 1+1 mode. Theoretically, the two power inputs
work in load-sharing mode. In the telecommunications room, however, it is required that the PDU needs
to provide power supply for an entire subrack. In this case, power failure does not occur if either of the
power inputs fails.

OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 2 Cabinet
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
2-11
3 Subrack
About This Chapter
This topic describes the structure, capacity, slot layout, and technical specifications of the
subrack.
3.1 Structure
The OptiX OSN 3500 subrack has a two-layer structure. The subrack consists of the processing
board area, interface board area, fan area, and cable routing area.
3.2 Slot Allocation
The OptiX OSN 3500 subrack consists of the upper layer and the lower layer. The upper layer,
where 19 slots are available, is the slot area for interface boards. The lower layer, where 18 slots
are available, is the slot area for processing boards.
3.3 Slot Access Capacity On The Packet Mode
When the cross-connect board is N1PSXCS or N2PSXCSA, the access capacity of each slot on
the OptiX OSN 3500 is different.
3.4 Slot Access Capacity On The TDM Mode
When the cross-connect board is N1PSXCS or N2PSXCSA, the OptiX OSN 3500 supports the
slots blew.
3.5 Ventilation Mode
The subrack of the equipment has many minute air vents and houses fans. The air enters from
the front and exits from the back, and the air flows from the bottom to the top. In this manner,
the equipment has good performance in heat dissipation.
3.6 Cable Management
This topic describes the function of the cable distribution plate and fiber spool box and the overall
scheme for cable routing.
3.7 Mapping Policies of Power Consumption
The increasing features supported by the equipment causes higher power consumption. To
ensure the normal operation of the equipment, the internal power supply system provides
different mapping policies of power consumption according to different power consumption
requirements.
3.8 Technical Specifications
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 3 Subrack
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
3-1
The technical specifications of the subrack include the dimensions, weight, and maximum power
consumption.
3 Subrack
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
3-2 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
3.1 Structure
The OptiX OSN 3500 subrack has a two-layer structure. The subrack consists of the processing
board area, interface board area, fan area, and cable routing area.
Figure 3-1 shows the structure of the OptiX OSN 3500 subrack.
Figure 3-1 Structure of the OptiX OSN 3500 subrack
1
2
3
4
W
H
D
5
1. Interface board area 2. Fan area
3. Processing board area 4. Cable routing area
5. Mounting ear -

The functions of the areas are as follows:
l Interface board area: This area houses the interface boards of the OptiX OSN 3500.
l Fan area: This area houses three fan modules, which dissipate heat generated by the
equipment.
l Processing board area: These areas house the processing boards of the OptiX OSN 3500.
l Cable routing area: This area houses the fiber jumpers in the subrack.
NOTE
The interface board is also called the access board or transit board. The interface board provides physical
interfaces for optical signals and electrical signals, and transmits the optical signals or electrical signals to
the corresponding processing board.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 3 Subrack
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
3-3
3.2 Slot Allocation
The OptiX OSN 3500 subrack consists of the upper layer and the lower layer. The upper layer,
where 19 slots are available, is the slot area for interface boards. The lower layer, where 18 slots
are available, is the slot area for processing boards.
Figure 3-2 shows the slot layout of the OptiX OSN 3500 subrack.
Figure 3-2 Slot layout of the OptiX OSN 3500 subrack
Fiber Routing
S
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FAN
SLOT 40
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Figure 3-3 shows the dual-slot layout of the OptiX OSN 3500 subrack.
3 Subrack
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
3-4 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Figure 3-3 Dual-slot layout of the OptiX OSN 3500 subrack
Fiber Routing
S
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P
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SLOT 38
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SLOT 39
FAN
SLOT 40
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5

Slot Area for Interface Boards
Slots for the interface boards: slots 19-26 and 29-36
Slot Area for Processing Boards
Slots for the processing boards: slots 1-8 and 11-17
Other Slots
l Slots for the cross-connect and timing boards: slots 9-10
l Slots for the SCC boards: slots 17-18 (slot 17 can also house a processing board)
l Slots for the PIU boards: slots 27-28
l Slot for the auxiliary interface board: slot 37
l Slots for the fan boards: slots 38-40
Mapping Relation Between Slots for Interface Boards and Slots for Processing
Boards
Table 3-1 lists the mapping relation between slots for the interface boards and slots for the
processing boards.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 3 Subrack
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
3-5
Table 3-1 Mapping relation between slots for the interface boards and slots for the processing
boards
Slots for
Processi
ng
Boards
Dual-Slots
for
Processing
Boards
Slots for
Correspondin
g Interface
Boards
Slots for
Processing
Boards
Dual-Slots
for
Processing
Boards
Slots for
Correspondi
ng Interface
Boards
Slot 2 - Slots 19 and 20 Slot 13 Slot 13 Slot 29 and 30
Slot 3 Slot 3 Slots 21 and 22 Slot 14 - Slot 31 and 32
Slot 4 - Slots 23 and 24 Slot 15 Slot 15 Slot 33 and 34
Slot 5 Slot 5 Slots 25 and 26 Slot 16 - Slot 35 and 36

Paired Slots
If the overhead bytes pass through the backplane bus between two slots, the two slots are paired
slots. When an NE is configured with an orderwire phone, realizes the service protection in DPS
mode, or is configured with the ring MSP at the STM-16/STM-64 level, the two boards that
form a ring must be inserted into the paired slots. Table 3-2 lists the paired slots.
Table 3-2 Paired slots
Cross-Connect Capacity Paired Slots
200 Gbit/s (Slot 2, Slot 17)
(Slot 3, Slot 16)
(Slot 4, Slot 15)
(Slot 5, Slot 14)
(Slot 6, Slot 13)
(Slot 7, Slot 12)
(Slot 8, Slot 11)

3.3 Slot Access Capacity On The Packet Mode
When the cross-connect board is N1PSXCS or N2PSXCSA, the access capacity of each slot on
the OptiX OSN 3500 is different.
When the N1PSXCS board is used to support packet services, one service processing board
occupies two slots. In this case, the neighboring two slots function as one slot, as shown in
Figure 3-4.
3 Subrack
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
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Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Figure 3-4 Slot access capacity when the N1PSXCS board is used
1
0
G
b
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t
/
s
Cable routing
FAN FAN FAN
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Figure 3-5 and Figure 3-6 show the slot access capacity when the N2PSXCSA board is used
to support packet services.
Figure 3-5 Slot access capacity when the N2PSXCSA board is used (single slots)
Cable routing
FAN FAN FAN
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OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 3 Subrack
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
3-7
Figure 3-6 Slot access capacity when the N2PSXCSA board is used (double slots)
1
0
G
b
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t
/
s
Cable routing
FAN FAN FAN
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3.4 Slot Access Capacity On The TDM Mode
When the cross-connect board is N1PSXCS or N2PSXCSA, the OptiX OSN 3500 supports the
slots blew.
When the cross-connect board is N1PSXCS, as shown in Figure 3-7. When the cross-connect
board is N2PSXCSA, as shown in Figure 3-8.
Figure 3-7 Access capacity of each slot when the N1PSXCS board is used
1
0
G
b
i
t
/
s
2
0
G
b
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t
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s
Cable routing
FAN
1
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FAN FAN
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o
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3 Subrack
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
3-8 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Figure 3-8 Access capacity of slots when the N2PSXCSA is used
Cable routing
FAN FAN FAN
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3.5 Ventilation Mode
The subrack of the equipment has many minute air vents and houses fans. The air enters from
the front and exits from the back, and the air flows from the bottom to the top. In this manner,
the equipment has good performance in heat dissipation.
NOTE
Make smooth ventilation of the air pipe of the cabinet. Do not block the air inlets and outlets of the subrack.
Do not place any sundries in the upper part of the subrack to ensure that air can flow through the subrack.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 3 Subrack
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Figure 3-9 Ventilation mode of the OptiX OSN 3500
AIR IN
AIR OUT
AIR OUT
AIR OUT

3.6 Cable Management
This topic describes the function of the cable distribution plate and fiber spool box and the overall
scheme for cable routing.
Cable Distribution Plate
One subrack needs to be installed with one cable distribution plate on its top. Figure 3-10 shows
the appearance of the cable distribution plate. The function of the cable distribution plate is to
fix the equipment cable to avoid the difficulty that the board may not be easily reseated or that
the air vents of the equipment are blocked and thus the heat dissipation of the equipment is poor.
3 Subrack
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Figure 3-10 Appearance of the cable distribution plate

Fiber Spool Box
The fiber spool box is used to coil the redundant optical fibers inside the cabinet. Figure 3-11
shows the appearance of the fiber spool box.
Figure 3-11 Appearance of the fiber spool box
Cable-through
hole
Fiber spool
box

For the installation position of the fiber spool box and cable distribution plate in the cabinet,
see 1 Equipment Structure.
Overall Scheme for Fiber Jumper Routing
l The fiber jumpers of the equipment are routed through the front vertical columns at the two
sides of the cabinet.
l The fiber jumpers of the equipment are led out through the fiber hole of the cabinet.
l The fiber jumpers between the cabinet and the ODF are protected with a protection pipe.
The two ends of the protective pipe should be extended 10 cm into the cabinet and the ODF.
l The fiber jumpers are secured smoothly and interconnected reliably in the ODF. The
redundant fiber jumpers are coiled tidily.
l When the internal fiber jumpers are routed, the redundant fibers are coiled tidily in the fiber
spool box.
l The routing and connection of the fiber jumpers should be consistent with the design. The
optical attenuators are added according to the requirements of the engineering design.
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l The bend radius of the fiber jumper must be greater than its minimum curvature radius.
Specifically, the minimum curvature radius for the 2 mm fiber jumper is 40 mm, and that
for the 3 mm fiber jumper is 60 mm.
Overall Scheme for Cable Routing
l The external power cables and grounding cables are arranged separately from the signal
cables, with a space more than 3 cm.
l The power cables of the subrack are bundled under the cable distribution plate. The power
cables of the subrack are routed separately towards the back of the two sides of the cabinet,
and are routed along the back of the side doors to reach the power box.
l The power cables of the IF board connect the IF power board to the IF board and are routed
through the cable-routing channel. If the IF power cable is redundant in the cable-routing
channel, bundle the redundant part of the power cable on the vertical column or at the cable-
routing area on the side of the cabinet.
l The method of routing the IF cables is the same as the method of routing the signal cables.
l In the case of upward cabling, the signal cables of the upper subrack are led out from the
cable-through holes in the top middle of the cabinet, and the signal cables of the lower
subrack are led out from the cable-through holes on the two sides of the top of the cabinet.
l In the case of downward cabling, the signal cables of the upper and lower subracks are led
out from the cable-through holes on the two sides of the bottom of the cabinet.
3.7 Mapping Policies of Power Consumption
The increasing features supported by the equipment causes higher power consumption. To
ensure the normal operation of the equipment, the internal power supply system provides
different mapping policies of power consumption according to different power consumption
requirements.
The internal power supply system consists of PDU and PIU. Table 3-3 shows different mapping
policies of power consumption.
Table 3-3 Mapping policies of power consumption on the OptiX OSN 3500
Type of
Subrack
Label of Subrack Mapping
PDU
Mapping
PIU
Maximu
m Power
Consum
ption
Fuse
Capacity
Standard
OptiX
OSN 3500
subrack
- N1PDU N1PIU,
N1PIUA
720 W 20 A
Enhanced
OptiX
OSN 3500
subrack
(1100 W)
N1PDU N1PIUA 1100 W 32 A
3 Subrack
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Issue 01 (2010-01-15)
Type of
Subrack
Label of Subrack Mapping
PDU
Mapping
PIU
Maximu
m Power
Consum
ption
Fuse
Capacity
Enhanced
OptiX
OSN 3500
subrack
(2300 W)
TN51PDU N1PIUB 2300 W 60 A

CAUTION
When the enhanced subrack (2300 W) is configured with N1PDU, the maximum power
consumption of the equipment is 1100 W. Therefore, it is recommended that the enhanced
subrack (2300 W) be configured with 51PDU.
3.8 Technical Specifications
The technical specifications of the subrack include the dimensions, weight, and maximum power
consumption.
Table 3-4 lists the dimensions and weight of the OptiX OSN 3500 subrack.
Table 3-4 Dimensions and weight of the OptiX OSN 3500 subrack
Dimensions (mm) Weight (kg)
497 (W) x 295 (D) x 722 (H) 23 (net weight of the subrack that is not
installed with boards and fans)

Table 3-5 lists the maximum power consumption of the OptiX OSN 3500 subrack.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 3 Subrack
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3-13
Table 3-5 Maximum power consumption of the OptiX OSN 3500 subrack
Subrack
Type
Maximum Configuration Typical Configuration
Maximum
Power
Consumption
Fuse
Capacity
Typical
Power
Consumpti
on
Typical Configuration
General
OptiX OSN
3500 subrack
720 W 20 A 496 W l Two N1SLD64
(S-64.2b, LC) boards
l Two N2SLQ4 (S-4.1,
LC) boards
l Two N1SLQ16 (L-16.2,
LC) boards
l Two N1SLH1 (S-1.1,
LC) boards
l Four N1OU08 boards
l Two N2EGT2 boards
l Two N1PSXCS boards
l One N4GSCC board
l One N1AUX board
l Two N1PIU boards
Enhanced
OptiX OSN
3500 subrack
1100 W 32 A 626 W l Two N1SL64 (S-64.2b,
LC) boards
l Two N2SLQ4 (S-4.1,
LC) boards
l One N1SLT1 (S-1.1,
LC) board
l Two N1PEG8 boards
l Two N1PEX2 boards
l Two N1PETF8 boards
l Two N2PSXCSA boards
l One N1AUX board
l Two N1PIUA boards
Enhanced
OptiX OSN
3500 subrack
2300 W
a
60 A 920 W l Five N1PEG8 boards
l Two N1PEX2 boards
l Two N2PEX1 boards
l Three N1PETF8 boards
l Two N2PSXCSA boards
l One N1AUX board
l Two N1PIUB boards
a: indicated the default maximum power consumption of the equipment is 1100 W.
3 Subrack
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Hardware Description
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OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 3 Subrack
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3-15
4 Board List and Classification
About This Chapter
This topic describes the appearances, dimensions, bar codes, and classification of the boards
used on the OptiX OSN systems.
4.1 Appearances and Dimensions of the Boards
Different boards have different appearances and dimensions.
4.2 Bar Codes of the Boards
The bar code on the front panel of a board indicates the version, name, and feature code of the
board.
4.3 Classification of the Boards
By function, the boards can be classified into SDH boards, PDH processing boards, packet
boards, dual-mode bridging boards, CES boards, data boards, WDM boards, and auxiliary
boards.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 4 Board List and Classification
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4-1
4.1 Appearances and Dimensions of the Boards
Different boards have different appearances and dimensions.
Table 4-1 provides information about the appearances and dimensions of the boards used on
the OptiX OSN 3500.
Table 4-1 Appearances and dimensions of the boards used on the OptiX OSN 3500
Parameter Appearance and Dimensions
Board
appearance


Board
classificatio
n
Optical interface board
(for example, SL16)
Service processing
board (for example,
PQ1)
Service interface board
(for example, D75S)
Height
(mm)
262.05 262.05 262.05
Depth (mm) 220 220 110
Width (mm) 25.4 25.4 22
Board
appearance


Board
classificatio
n
System auxiliary
interface board (AUX)
Power interface board
(PIU)
4 Board List and Classification
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Parameter Appearance and Dimensions
Height
(mm)
262.05 262.05 262.05
Depth (mm) 220 110 110
Width (mm) 40 44 44
Note: The figure in the right cell shows the three dimensions.
"H" and "W" indicate the height and width of the front panel
respectively and "D" indicates the depth of the printed circuit
board (PCB).
W
H
D

CAUTION
Wear an antistatic wrist strap when holding a board. To prevent the static discharge from
damaging the board, ensure that the antistatic wrist strap is grounded properly.
DANGER
Do not look directly at the optical interface board or optical interface. The laser beams inside
the fiber can damage your eyes.
CAUTION
l A level optical module cannot be directly connected to an optical attenuator. If an optical
attenuator is required, use the attenuator on the optical distribution frame (ODF) side.
l If an optical attenuator is required, insert the attenuator in the IN interface instead of the OUT
interface.
l Add an attenuator when performing a loopback to prevent the optical module from being
damaged.
4.2 Bar Codes of the Boards
The bar code on the front panel of a board indicates the version, name, and feature code of the
board.
Two types of bar codes are used for the boards of the OptiX OSN 3500, which are as follows:
l 16-digit manufacturing code + board version + board name + board feature code
l 20-digit manufacturing code + board version + board name + board feature code
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 4 Board List and Classification
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4-3
The bar code is affixed to the front panel of a board. Figure 4-1 shows the bar code with a 16-
digit manufacturing code.
Figure 4-1 Bar code of a board
0364401055000015 -SSN3SL16A01

Last six digits of the BOM code
Internal code

Board version
Board name
Bar code
Board feature code
5
5

NOTE
For details on the feature code of a board, see the topic that describes the feature code of the board.
4.3 Classification of the Boards
By function, the boards can be classified into SDH boards, PDH processing boards, packet
boards, dual-mode bridging boards, CES boards, data boards, WDM boards, and auxiliary
boards.
SDH Boards
NOTE
For details on the board version replacement relation between boards, refer to the table of board version
replacement relations in the Parts Replacement.
The OptiX OSN 3500 supports the SDH boards that operate at the STM-64, STM-16, STM-4,
and STM-1 rates.
Table 4-2 lists the SDH boards that the OptiX OSN 3500 supports.
4 Board List and Classification
OptiX OSN 3500 Intelligent Optical Transmission System
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Table 4-2 SDH boards that the OptiX OSN 3500 supports
Board Description Board Description
N1SL64,
N2SL64
1xSTM-64 optical interface
board
N1SLD4,
N2SLD4
2xSTM-4 optical interface
board
N1SF64,
N1SF64A
1xSTM-64 optical interface
board (with the forward
error correction (FEC)
function)
N1SLD4A 2xSTM-4 optical interface
board
N1SLD64 2xSTM-64 optical interface
board
N1SLT1 12xSTM-1 optical interface
board
N1SL16,
N2SL16,
N3SL16
1xSTM-16 optical interface
board
N1SLQ1,
N2SLQ1
4xSTM-1 optical interface
board
N1SL16A,
N2SL16A,
N3SL16A
1xSTM-16 optical interface
board
N1SLQ1A 4xSTM-1 optical interface
board
N1SLD16 2xSTM-16 optical interface
board
N1SL1, N2SL1 1xSTM-1 optical interface
board
N1SLQ16,
N2SLQ16
4xSTM-16 optical interface
board
N1SL1A 1xSTM-1 optical interface
board
N1SF16 1xSTM-16 optical interface
board (with the out-band
FEC function)
N1SLH1 16xSTM-1 signal
processing board
N1SLO16 8xSTM-16 optical interface
board
N1SEP1 2xSTM-1 line processing
board when the interfaces
are available on the front
panel
8xSTM-1 line processing
board when the interfaces
are available on the
corresponding interface
board
N1SL4,
N2SL4,
N1SL4A
1xSTM-4 optical interface
board
N2SLO1,
N3SLO1
8xSTM-1 optical interface
board
N1SLQ4,
N2SLQ4,
N1SLQ4A
4xSTM-4 optical interface
board
N3SLQ41 4xSTM-4/STM-1 optical
interface board

PDH Boards
The OptiX OSN 3500 supports the PDH boards that operate at different rates and have different
impedances.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 4 Board List and Classification
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4-5
Table 4-3 lists the PDH boards that the OptiX OSN 3500 supports.
Table 4-3 PDH boards that the OptiX OSN 3500 supports
Board Description Board Description
N1PQ1,
N2PQ1
63xE1 service processing board N2PQ3 12xE3/T3 service processing
board
N1PQM 63xE1/T1 service processing
board
N1DX1 DDN service accessing and
converging board
N1PL3,
N2PL3
3xE3/T3 service processing
board
N1DXA DDN service converging and
processing board
N1PL3A,
N2PL3A
3xE3/T3 service processing
board (The interfaces are
available on the front panel.)
N1SPQ4,
N2SPQ4
4xE4/STM-1 electrical
processing board
N1PD3,
N2PD3
6xE3/T3 service processing
board
- -

Packet Boards
The OptiX OSN 3500 supports the processing boards and electrical interface boards that operate
at various rates and provide the packet feature.
Table 4-4 lists the packet boards that the OptiX OSN 3500 supports.
Table 4-4 Packet boards that the OptiX OSN 3500 supports
Board Description Board Description
N1PEG16 16xGE processing board N1PEX1 1x10GE processing board
N1PETF8 8xFE electrical interface
board
- -
N1PEG8 8xGE Ethernet switch
processing board
N1PEX2 2x10 GE Ethernet switch
processing board
N2PEX1 1x10GE processing board N1PEFF8 8-port Megabit Ethernet
optical interface board

Dual-Mode Bridging Boards
The OptiX OSN 3500 supports multiple dual-mode bridging boards.
Table 4-5 lists the name and description of the dual-mode bridging boards supported by the
OptiX OSN 3500.
4 Board List and Classification
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Table 4-5 Dual-mode bridging boards supported by the OptiX OSN 3500
Board Description Board Description
N1EDQ41 4-port 622M/155M SDH
optical interface Ethernet
double mode multiple function
processing board
- -

CES Boards
The OptiX OSN 3500 supports multiple CES boards.
Table 4-6 lists the name and description of the CES boards supported by the OptiX OSN 3500.
Table 4-6 CES boards supported by the OptiX OSN 3500
Board Description Board Description
N1CQ1 4-port channelized STM-1
optical interface board
N1MD75 Multi-protocol 32 channels E1
interface board (75 ohm)
N1MD12 Multi-protocol 32 channels E1
interface board (120 ohm)
- -

Data Boards
The OptiX OSN 3500 supports the data boards that provide the transparent transmission
function, switching function, or RPR function.
Table 4-7 lists the data boards that the OptiX OSN 3500 supports.
Table 4-7 Data boards that the OptiX OSN 3500 supports
Board Description Board Description
N1EFT8 8xFE or 16xFE transparent
transmission board
N1EMS2 2xGE and 16xFE transparent
transmission and converging
board
N1EFT8A 8xFE transparent
transmission board
N2EGR2 2xGE ring processing board
N1EGS4,
N3EGS4,
N4EGS4
4xGE switching and
processing board
N2EMR0 12xFE and 1xGE ring
processing board
N1EGT2,
N2EGT2
2xGE transparent
transmission board
N1ADL4 1xSTM-4 ATM service
processing board
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 4 Board List and Classification
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Board Description Board Description
N1EFS0,
N2EFS0,
N4EFS0,
N5EFS0
8xFE switching and
processing board
N1ADQ1 4xSTM-1 ATM service
processing board
N1EFS0A 16xFE switching and
processing board
N1IDL4 1xSTM-4 ATM service
processing board
N1EFS4,
N2EFS4,
N3EFS4
4xFE switching and
processing board
N1IDQ1 4xSTM-1 ATM service
processing board
N2EGS2,
N3EGS2
2xGE switching and
processing board
N1MST4 4-port multi-service
transparent transmission
board
N1EMS4 4xGE and 16xFE transparent
transmission and converging
board
N1EAS2 2-port 10xGE Layer 2
switching and processing
board

Interface Boards and Switching and Bridging Boards
The OptiX OSN 3500 supports optical interface boards, electrical interface boards, and switching
and bridging boards.
Table 4-8 lists the interface boards and switching and bridging boards that the OptiX OSN 3500
supports.
Table 4-8 Interface boards and switching and bridging boards that the OptiX OSN 3500 supports
Board Description Board Description
N1EU08 8xSTM-1 electrical interface
board
N1D12S 32xE1/T1 switching access
board (120 ohms)
N1OU08 8xSTM-1 optical interface
board (LC)
N1D12B 32xE1/T1 access board (120
ohms)
N2OU08 8xSTM-1 optical interface
board (SC)
N1EFF8,
N1EFF8A
8x100M Ethernet optical
interface board
N1D75S 32xE1 switching access board
(75 ohms)
N1ETF8,
N1ETF8A
8x100M Ethernet twisted
pair interface board
N1MU04 4xE4/STM-1 electrical
interface board
N1ETS8 8x10/100M Ethernet twisted
pair interface switching
board
N1D34S 6xE3/T3 switching access board N1DM12 DDN service interface board
4 Board List and Classification
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Board Description Board Description
N1C34S 3xE3/T3 switching access board N1TSB4 4-channel electrical
interface protection
switching board
N1EU04 4xSTM-1 electrical interface
board
N1TSB8 8-channel electrical
interface protection
switching board

Cross-Connect Boards and System Control Boards
The OptiX OSN 3500 supports multiple system control boards and cross-connect boards that
have different cross-connect capacities.
Table 4-9 lists the cross-connect boards and system control boards that the OptiX OSN 3500
supports.
Table 4-9 Cross-connect boards and system control boards that the OptiX OSN 3500 supports
Board Description
N1PSXCS Cross-connect and timing board (supporting the packet feature)
N4GSCC,
N6GSCC
Intelligent system control and communication board
N2PSXCSA Super cross-connect and timing board

Auxiliary Boards
The OptiX OSN 3500 supports auxiliary boards such as the system auxiliary interface board and
fan board.
Table 4-10 lists the auxiliary boards that the OptiX OSN 3500 supports.
Table 4-10 Auxiliary boards that the OptiX OSN 3500 supports
Board Description
N1AUX System auxiliary interface board
N1FAN Fan board

WDM Boards
The OptiX OSN 3500 supports WDM boards such as the optical add/drop multiplexing board
and optical amplifier board.
Table 4-11 lists the WDM boards that the OptiX OSN 3500 supports.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 4 Board List and Classification
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Copyright Huawei Technologies Co., Ltd.
4-9
Table 4-11 WDM boards that the OptiX OSN 3500 supports
Board Description Board Description
TN11CMR2 2-channel optical add/
drop multiplexing board
N1MR2C 2-channel optical add/drop
multiplexing board
TN11CMR4 4-channel optical add/
drop multiplexing board
N1LWX Arbitrary bit rate
wavelength conversion
board
TN11MR2 2-channel optical add/
drop multiplexing board
TN11OBU1 Optical booster amplifier
board
TN11MR4 4-channel optical add/
drop multiplexing board
N1FIB Filter isolating board
N1MR2A 2-channel optical add/
drop multiplexing board
- -

Microwave Boards
The OptiX OSN 3500 supports microwave boards such as the microwave IF board and
microwave power board.
Table 4-12 lists the microwave boards that the OptiX OSN 3500 supports.
Table 4-12 Microwave boards that the OptiX OSN 3500 supports
Board Description
N1IFSD1 Dual-port IF board
N1RPWR 6-channel ODU power board

Optical Amplifier Boards and Dispersion Compensation Boards
The OptiX OSN 3500 supports multiple optical amplifier boards and dispersion compensation
boards.
Table 4-13 lists the optical amplifier boards and dispersion compensation boards that the OptiX
OSN 3500 supports.
Table 4-13 Optical amplifier boards and dispersion compensation boards that the OptiX OSN
3500 supports
Board Description Board Description
N1BPA and
N2BPA
Optical booster and
pre-amplifier board
N1COA, 61COA, and
62COA
Case-shaped optical
amplifier
4 Board List and Classification
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
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Issue 01 (2010-01-15)
Board Description Board Description
N1BA2 Optical booster
amplifier board
N1DCU, N2DCU Dispersion
compensation board
N1RPC01 Forward Raman
driving board
(external)
N1RPC02 Backward Raman
driving board
(external)

Power Boards
The OptiX OSN 3500 supports power boards such as the UPM and power interface board.
Table 4-14 lists the power boards that the OptiX OSN 3500 supports.
Table 4-14 Power boards that the OptiX OSN 3500 supports
Board Description
UPM Uninterruptible power module
N1PIU Power interface board
N1PIUA Power interface board (This board can be used in the enhanced
subrack that consumes 1100 W high power.)
N1PIUB Power interface board (This board can be used in the enhanced
subrack that consumes 2300 W high power.)

OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 4 Board List and Classification
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4-11
5 Cross-Connect Boards and System Control
Boards
About This Chapter
This topic describes the system control boards and the cross-connect boards that have different
capacities.
5.1 PSXCS(A)
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PSXCS(A) (cross-connect and timing board). This topic also
describes how to configure and commission the PSXCS(A).
5.2 GSCC
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the GSCC (intelligent system communication and control board).
This topic also describes how to configure and commission the GSCC.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 5 Cross-Connect Boards and System Control Boards
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Copyright Huawei Technologies Co., Ltd.
5-1
5.1 PSXCS(A)
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PSXCS(A) (cross-connect and timing board). This topic also
describes how to configure and commission the PSXCS(A).
5.1.1 Version Description
PSXCS(A) is available in two functional versions, namely, N1PSXCS and N2PSXCSA.
5.1.2 Application
The PSXCS(A) is a super cross-connect and synchronous timing board. The PSXCS(A) provides
service grooming and clock input/output functions in the OptiX OSN 3500 system.
5.1.3 Functions and Features
The PSXCS(A) board grooms services and inputs/outputs clock signals.
5.1.4 Working Principle and Signal Flow
The PSXCS(A) consists of the higher order cross-connect matrix, lower order cross-connect
matrix, packet cross-connect matrix, communication and control module, clock unit, and power
module.
5.1.5 Front Panel
The front panel of the PSXCS(A) has indicators and a bar code.
5.1.6 Jumpers and DIP Switches
The PSXCS(A) does not have any jumpers or DIP switches that are used for board settings.
5.1.7 Valid Slots
The PSXCS(A) can be installed in slots 9 and 10 in the subrack.
5.1.8 Feature Code
The PSXCS(A) does not have the feature code.
5.1.9 Parameter Settings
You can set parameters for the PSXCS(A) by using the T2000.
5.1.10 Technical Specifications
The technical specifications of the PSXCS(A) include the cross-connect capacity, clock access
capability, mechanical specifications, and power consumption.
5.1.1 Version Description
PSXCS(A) is available in two functional versions, namely, N1PSXCS and N2PSXCSA.
Table 5-1 provides version description of PSXCS(A).
Table 5-1 Versions of the PSXCS board
Item Description
Functional versions PSXCS(A) is available in two functional versions, namely,
N1PSXCS and N2PSXCSA.
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Item Description
Differences l N1PSXCS provides 80 Gbit/s packet data cross-connect
capacity and 60 Gbit/s packet access capacity.
l N2PSXCSA provides 160 Gbit/s packet data cross-connect
capacity and 100 Gbit/s packet access capacity.
Substitution N2PSXCSA can substitute for N1PSXCS and N1SXCSA.

5.1.2 Application
The PSXCS(A) is a super cross-connect and synchronous timing board. The PSXCS(A) provides
service grooming and clock input/output functions in the OptiX OSN 3500 system.
The PSXCS(A) provides the timing information to the other boards in the system and grooms
the services between SDH line boards, packet boards, or tributary boards.
Figure 5-1 shows the position of the PSXCS(A) in the system.
Figure 5-1 Position of the PSXCS(A) in the system
SDH/PDH
service
Packet data
Higher order/
Lower order
cross-connect
unit
Auxillary
unit
Auxillary
interface
XCS
PIU
-48 V/-60 V
Packet data
processing
unit
Packet data
Clock
unit

5.1.3 Functions and Features
The PSXCS(A) board grooms services and inputs/outputs clock signals.
Cross-Connect Unit
Table 5-2 provides the functions and features of the cross-connect unit of the PSXCS(A) board.
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Table 5-2 Functions and features of the cross-connect unit of the PSXCS(A)
Functions and
Features
Description
Basic functions l The N1PSXCS board implements 200 Gbit/s higher order cross-
connection at the VC-4 level, 20 Gbit/s lower order cross-
connection at the VC-12 or VC-3 level, 80 Gbit/s packet data
cross-connect capacity and 60 Gbit/s packet access capacity.
l The N2PSXCSA board implements 200 Gbit/s higher order cross-
connection at the VC-4 level, 20 Gbit/s lower order cross-
connection at the VC-12 or VC-3 level, 160 Gbit/s packet data
cross-connect capacity and 100 Gbit/s packet access capacity.
Service processing l Supports the flexible service grooming and supports the cross-
connect, multicast, and broadcast services.
l Communicates with other boards.
l Supports the tact switch and performs the protection switching
without service interruption.
l Supports the SNCP protection at the levels of VC-4-4c, VC-4-8c,
VC-4-16c, VC-4-64c, VC-4, VC-12, VC-3, and AU-3.
l Supports VC-4, VC-12, VC-3, and AU-3 services.
l Supports VC-4-4c, VC-4-8c, VC-4-16c, and VC-4-64c
concatenation services.
l Supports a maximum of 40 linear MSP groups.
l Supports a maximum of 12 ring MSP groups.
l Supports a maximum of 1184 SNCP pairs.
l Supports a maximum of 592 SNCMP pairs.
l Supports a maximum of 512 SNCTP pairs.
Protection Scheme Supports 1+1 hot standby. The default protection mode is the non-
revertive switching mode.
Maintenance
features
Supports the PRBS function.
Others Supports querying and reporting the working temperature of the
cross-connect and timing board and the entire equipment.

Clock Unit
Table 5-3 provides the functions and features of the clock unit of the PSXCS(A) board.
Table 5-3 Functions and features of the clock unit of the PSXCS(A) board
Functions and
Features
Description
Basic functions Provides the standard system synchronization clock.
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Functions and
Features
Description
Other functions l Supports the processing of the S1 byte to perform clock protection
switching.
l Supports the extraction, insertion, and processing of the SSM and
clock ID.
l Supports the synchronous Ethernet clock.
l Supports the IEEE 1588v2 clock.
Input and output l Inputs two-channel 2048 kHz or 2048 kbit/s timing signals, and
selects the external timing source.
l Outputs two-channel 2048 kHz or 2048 kbit/s timing signals.

5.1.4 Working Principle and Signal Flow
The PSXCS(A) consists of the higher order cross-connect matrix, lower order cross-connect
matrix, packet cross-connect matrix, communication and control module, clock unit, and power
module.
Figure 5-2 shows the functional block diagram of the PSXCS(A).
Figure 5-2 Functional block diagram of the PSXCS(A)
Communication
and control unit
Higher order cross-
connect matrix
Clock unit
Lower order cross-
connect matrix
Backplane
The board and system
SCC unit
+3.3 V -48 V/-60 V
Power
module
Fuse
-48 V/-60 V
Service unit/SCC unit/
AUX
Packet cross-
connect matrix

Higher Order Cross-Connect Matrix
Realizes higher order cross-connection at the VC-4 level.
Lower Order Cross-Connect Matrix
Realizes lower order cross-connection at the VC-3 or VC-12 level.
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Packet Cross-Connect Matrix
Cross-connects the packet data.
Communication and Control Module
Communicates with the SCC unit and other boards, ensures communication with the other boards
when the GSCC is not in position, and generates the other control signals for the PSXCS and
system.
Clock Unit
The clock unit performs the following functions:
l Traces external clock sources, line clock sources, or tributary clock sources, and provides
the PSXCS and the system with a synchronization clock source.
l Through system timing, provides the nodes in the data stream of the system with the clock
signals that have proper frequency and phase. In this way, the components at each node
can meet the requirements regarding data setup and data holding during data receiving.
l Provides the system with the frame indication signal that is used to indicate the position of
the frame header in the data.
l Supports the synchronous Ethernet clock.
l Supports the IEEE 1588 V2 clock.
Power Module
The power module converts the accessed DC voltage into the DC voltages that the modules of
the PSXCS require.
5.1.5 Front Panel
The front panel of the PSXCS(A) has indicators and a bar code.
Diagram of the Front Panel
Figure 5-3 shows the appearance of the front panel of the PSXCS(A).
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Figure 5-3 Front panel of the PSXCS(A)
N2PSXCSA N1PSXCS
PSXCS
PSXCS
ACT
PROG
STAT
SRV
SYNC
PSXCSA
PSXCSA
ACT
PROG
STAT
SRV
SYNC

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) three colors (red, green, and yellow)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Synchronization clock status indicator (SYNC) two colors (red and green)
For the meanings of the status of the indicators, see 22.2 Alarm Indicators on the Boards.
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Interfaces
The front panel of the PSXCS(A) has no interface. The AUX provides the PSXCS(A) with the
external clock interface that can be set in 2048 kHz mode or 2048 kbit/s mode. The AUX provides
two BITS clock interfaces with 120-ohm or 75-ohm impedance. For details, see the topic that
describes the interfaces of the AUX.
5.1.6 Jumpers and DIP Switches
The PSXCS(A) does not have any jumpers or DIP switches that are used for board settings.
5.1.7 Valid Slots
The PSXCS(A) can be installed in slots 9 and 10 in the subrack.
5.1.8 Feature Code
The PSXCS(A) does not have the feature code.
5.1.9 Parameter Settings
You can set parameters for the PSXCS(A) by using the T2000.
You can set the following principal parameters for the PSXCS(A) by using the T2000:
l Clock synchronization status
l Clock source priority
l Phase-locked source output by external clock
l Clock source switching
l Clock subnet configuration
For more parameters and the description of the parameters, see 25.8 Cross-Connect and Timing
Units.
5.1.10 Technical Specifications
The technical specifications of the PSXCS(A) include the cross-connect capacity, clock access
capability, mechanical specifications, and power consumption.
Cross-Connect Capacity
The cross-connect capacity of the N1PSXCS is as follows:
l Higher order cross-connect capacity: 200 Gbit/s
l Lower order cross-connect capacity: 20 Gbit/s
l Packet switching capability: 80 Gbit/s
l Access capacity:
TDM mode: 155 Gbit/s
Packet mode: 60 Gbit/s
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The cross-connect capacity of the N2PSXCSA is as follows:
l Higher order cross-connect capacity: 200 Gbit/s
l Lower order cross-connect capacity: 20 Gbit/s
l Packet switching capability: 160 Gbit/s
l Access capacity:
TDM mode: 155 Gbit/s
Packet mode: 100 Gbit/s
Clock Access Capability
The clock access capability of the PSXCS(A) is as follows:
l External input clock: two channels of 2048 kbit/s or 2048 kHz external clock signals
l External output clock: two channels of 2048 kbit/s or 2048 kHz external clock signals
Mechanical Specifications
The mechanical specifications of the N1PSXCS are as follows:
l Dimensions (mm): 40 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 2.1
The mechanical specifications of the N2PSXCSA are as follows:
l Dimensions (mm): 40 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 2.0
Power Consumption
The maximum power consumption of the N1PSXCS at room temperature (25C) is 90 W.
The maximum power consumption of the N2PSXCSA at room temperature (25C) is 80 W.
5.2 GSCC
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the GSCC (intelligent system communication and control board).
This topic also describes how to configure and commission the GSCC.
5.2.1 Version Description
The GSCC is available in several functional versions. The functions provided by the functional
versions are different.
5.2.2 Application
The GSCC is the intelligent system control board. The GSCC works with the T2000 to manage
the boards on the equipment and realize the communication between different pieces of
equipment.
5.2.3 Functions and Features
The GSCC supports the system control, orderwire, communication, and system power supply
monitoring.
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5.2.4 Working Principle and Signal Flow
The GSCC consists of the communication and control module, OHP module, and power module.
5.2.5 Front Panel
The front panel of the GSCC has indicators and a bar code.
5.2.6 Jumpers and DIP Switches
The GSCC has jumpers, which are used to set the input voltage and running state of the
equipment.
5.2.7 Valid Slots
The GSCC must be installed in a valid slot in the subrack. Otherwise, the GSCC cannot work
normally.
5.2.8 Feature Code
The GSCC does not have the feature code.
5.2.9 Parameter Settings
You can set parameters for the GSCC by using the T2000.
5.2.10 Technical Specifications
The technical specifications of the GSCC include the mechanical specifications and power
consumption.
5.2.1 Version Description
The GSCC is available in several functional versions. The functions provided by the functional
versions are different.
Table 5-4 describes the versions of the GSCC.
Table 5-4 Versions of the GSCC
Item Description
Functional
versions
The GSCC is available in the following functional versions: N4 and N6.
Differences None
Substitution The GSCC boards of different versions cannot directly substitute for each
other. If the N6GSCC needs to replace the N4GSCC, the NE software
needs to be upgraded accordingly.

5.2.2 Application
The GSCC is the intelligent system control board. The GSCC works with the T2000 to manage
the boards on the equipment and realize the communication between different pieces of
equipment.
Figure 5-4 shows the position of the GSCC in the system.
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Figure 5-4 Position of the GSCC in the system
Auxiliary interface
SCC unit
Auxiliary unit
PIU
Other boards
-48 V/-60 V

5.2.3 Functions and Features
The GSCC supports the system control, orderwire, communication, and system power supply
monitoring.
Table 5-5 provides the functions and features of the GSCC.
Table 5-5 Functions and features of the GSCC
Function and
Feature
GSCC
Basic functions Performs the service configuration function and service grooming
function, monitors the service performance, and collects information
about the performance events and alarms.
Interfaces l Provides the 10M/100M Ethernet port, which is used for
communicating with the NMS. The Ethernet port is accessed through
the AUX.
l Provides the F&f interface, which is accessed through the AUX and is
used to manage the COA.
l Provides one 64 kbit/s synchronous data port F1, which is accessed
through the AUX.
l Provides the RS232 OAM interface, which is used for connecting a PC
or workstation, and supports the remote maintenance by using a
modem that uses the RS232 DCE interface. The OAM interface is
accessed through the AUX.
DCC
communication
Processes 160 DCCs (D1D3). In this manner, the link is provided for
transmitting the NM information.
Supports the 1.5 Mbit/s DCN.
Overhead
processing
Processes the E1, E2, F1, and serial14 bytes.
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Clock function l Provides the RTC.
l Supports the high-precision clock synchronization feature, and
complies with the IEEE 1588 V2 protocol. The N4GSCC accesses the
time information through interfaces S1S4 of the AUX. The S1 and
S3 interfaces access the first channel of time information, and the S2
and S4 interfaces access the second channel of time information.
l Supports the synchronous Ethernet feature.
Alarms and
maintenance
features
l Supports service performance monitoring and collects information
about the performance events and alarms.
l Provides 16 alarm inputs and four alarm outputs through the AUX.
l Controls the four cabinet indicators through the AUX.
l Supports intelligent fan speed control and manages the fan alarms.
l Supports the function of detecting whether a packet data board is in
position.
Power supply
management
l Supports the monitoring of the 48 V or 60 V power supply.
l Supports the in-service check function for the PIU board and supports
the failure check function for the lightning protection module of the
PIU.
Protection
schemes
Supports the 1+1 Hot Backup for the SCC Unit. When the active board
is faulty, services are switched to the standby board automatically.
Packet function The N4GSCC and N6GSCC support the packet function.

5.2.4 Working Principle and Signal Flow
The GSCC consists of the communication and control module, OHP module, and power module.
Figure 5-5 shows the functional block diagram of the GSCC.
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Figure 5-5 Functional block diagram of the GSCC
Communication
and control
module
Reset
-48 V/-60 V Power
module
Boot
ROM
RAM
NVRAM
Flash
PIU test
Power monitor
Control of subrack
indicators
OHP OH
manager
S1-S4
F1
V2
V1
Phone
AUX unit
Inter-board
communication
PIU unit
Other
units
OHP module
ALM CUT
PIU
interface
AUX power monitor
and reset control
Other
units
ETH
OAM
F&f
COM
Input/Output alarm 16-input/4-output
alarm control
ETH port
COM interface
AUX interface
OAM interface
F&f interface

Communication and Control Module
The communication and control module controls and manages the boards, realizes the
communication between NEs, manages the network, and performs other functions.
l The system control module communicates with the boards in the subrack, manages the
boards, monitors the performance events and alarms of the boards, collects the status
information about the other functional modules, and performs the corresponding
management operations.
l The communication and control module provides the function that NEs communicate with
each other through DCCs. The communication module transfers the OAM information to
other NEs through DCCs, reports the alarms and performance data of the equipment to the
network management terminal, and responds to the commands issued by the network
management terminal.
l The communication and control module configures and operates the NE.
NOTE
The service protection is realized by the cross-connect and timing board. When services are switched, the
switching event is reported to the GSCC, which then reports the switching event to the NMS.
When the communication and control module fails, the following situations occur:
l Communication failure
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The communication and control module cannot manage the boards in the subrack, monitor
the performance events and alarms of the boards, collect the status information about the
other functional modules, or perform the corresponding management operations.
l DCC failure
The communication and control module cannot transfer the OAM information to other NEs
through the local NE, report the alarms and performance data of the equipment to the
network management terminal, or respond to the commands issued by the network
management terminal.
OHP Module
l Receives overhead signals from the line slot.
l Processes such bytes as E1, E2, F1 and serial14serial
l Sends overhead signals to the line board.
l Provides the following external interfaces:
One orderwire interface
Two SDH NNI audio interfaces
Interface F1
Broadcast data ports serial14serial
Figure 5-6 shows the orderwire bytes in the SDH frame.
Figure 5-6 Position of these orderwire bytes in the SDH frame
A1 A1 A1 A2 A2 A2 J0
B1 E1 F1
D1 D2 D3 Serial 1 Serial2
AU_PTR
B2 B2 B2 K1 K2
D4 Serial 4 D5 D6
D7 D8 D9
D10 D11 D12 Serial3
S1 M1 E2

Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
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5.2.5 Front Panel
The front panel of the GSCC has indicators and a bar code.
Diagram of the Front Panel
Figure 5-7 shows the appearance of the N4GSCC/N6GSCC.
Figure 5-7 Front panel of the N4GSCC/N6GSCC
GSCC
GSCC
ACT
PROG
STAT
SRV
ALM CUT
RESET
PWRB
PWRC
PWRA
ALMC

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
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l Service alarm indicator (SRV) three colors (red, green, and yellow)
l 48 V power supply indicator of channel A (PWRA) two colors (red and green)
l 48 V power supply indicator of channel B (PWRB) two colors (red and green)
l +3.3 V backup power supply indicator of the system (PWRC) two colors (red and green)
l Alarm mute indicator (ALMC) one color (yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the GSCC has no interface. The AUX provides interfaces for the GSCC. For
details, see AUX.
The front panel of the N4GSCC/N6GSCC has one warm reset switch and one alarm cut switch.
Table 5-6 describes the types and usage of the switches
Table 5-6 Types and usage of the switches of the GSCC
Switch Type of
Switch
Usage
RESET Warm reset
switch
Press the switch to perform a warm reset for the SCC unit.
ALM CUT Alarm cut
switch
Press the switch to mute the alarm. Press the switch for five
seconds to mute the alarm permanently. Press the switch
again for five seconds to resume the alarm sound.

5.2.6 Jumpers and DIP Switches
The GSCC has jumpers, which are used to set the input voltage and running state of the
equipment.
CAUTION
The jumpers are used for test and maintenance. Do not change the setting of jumpers at random.
Otherwise, the board may become faulty.
N4GSCC
Figure 5-8 shows the layout of the J2101, J7100, J3201, and J3202 jumpers on the N4GSCC.
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Figure 5-8 Position of the jumpers of the N4GSCC
Power
module
CPU
J3202
J7100
J2101
1
2
3
J3201

Table 5-7 lists the jumpers of the N4GSCC.
Table 5-7 Jumpers of the N4GSCC
Jumper Function Description
J2101 To enable the
battery
12: If jumper bits (positions) 1 and 2 are capped, the
database and clock are cleared.
23: If jumper bits (positions) 2 and 3 are capped, the
battery is enabled.
J7100 To set the running
state of the board
Jumper J7100 is a group of two-pin jumpers located in
five rows. The jumper in the lowest row is reserved and
need not be set. In the case of the jumpers in the top
four rows, the value of a jumper bit is defined as
follows:
If a jumper bit is not capped, the value is 0.
If a jumper bit is capped, the value is 1.
The jumper bit values are queued from bottom to top
and from the higher bit to the lower bit, and thus form
a four-bit binary number. For details, refer to Table
5-8.
J3202 and
J3201
To set the input
voltage of the
equipment
When the jumpers are not capped, the equipment is
supplied with the 60 V power.
When the jumpers are capped, the equipment is
supplied with the 48 V power.

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CAUTION
Set J3202 and J3201 correctly based on the power voltage provided in the telecommunications
room. If J3202 and J3201 are set incorrectly, the POWER_ABNORMAL alarm is generated.
Table 5-8 Jumper J7100
Value Description
0b0000 Indicates the running state when the watchdog is started. It is the default
state.
0b0001 Changes to the self-test state of the SDRAM Burst.
0b0011 Indicates the commissioning state.
0b0100 Indicates the running state when the watchdog is stopped.
0b0101 The software is in the BIOS state. The SCC does not work even though
the NE software exists. The IP address of the parameter area, however,
is not changed, which is for querying.
0b0110 The software enters the exhibition mode.
0b1001 Indicates the running state when the watchdog is started.
0b1011 Erases the database.
0b1100 Erases the NE software, including the patches.
0b1101 Erases the database and NE software, including the patches.
0b1110 Erases the database, NE software, and NE.ini file.
0b1111 Erases the extended BIOS and system parameter area in the file system
and flash memory.

N6GSCC
Figure 5-9 shows the layout of the J18, J11, J30, and J31 jumpers on the N6GSCC.
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Figure 5-9 Position of the jumpers of the N6GSCC
Power
module
J11
J18
J30
J31
CPU
1 2 3
1 2 3
1 2 3

Table 5-9 lists the jumpers of the N6GSCC.
Table 5-9 Jumpers of the N6GSCC
Jumper Function Description
J18 To enable the
battery
12: If jumper bits (positions) 1 and 2 are capped, the
database and clock are cleared.
23: If jumper bits (positions) 2 and 3 are capped, the
battery is enabled.
J11 To set the running
state of the board
Jumper J11 is a group of two-pin jumpers located in
five rows. The jumper in the leftest row is reserved and
need not be set. In the case of the jumpers in the right
four rows, the value of a jumper bit is defined as
follows:
If a jumper bit is not capped, the value is 0.
If a jumper bit is capped, the value is 1.
The jumper bit values are queued from right to left and
from the higher bit to the lower bit, and thus form a
four-bit binary number. For details, refer to Table
5-10.
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Jumper Function Description
J30 and J31 To set the input
voltage of the
equipment
12 or jumpers are not capped: If jumper bits
(positions) 1 and 2 are capped or jumpers are not
capped, the equipment is supplied with the 60 V
power.
23: If jumper bits (positions) 2 and 3 are capped, the
equipment is supplied with the 48 V power.

CAUTION
Set J30 and J31 correctly based on the power voltage provided in the telecommunications room.
If J30 and J31 are set incorrectly, the POWER_ABNORMAL alarm is generated.
Table 5-10 Jumper J11
Value Description
0b0000 Indicates the running state when the watchdog is started. It is the default
state.
0b0001 Changes to the self-test state of the SDRAM Burst.
0b0011 Indicates the commissioning state.
0b0100 Indicates the running state when the watchdog is stopped.
0b0101 The software is in the BIOS state. The SCC does not work even though
the NE software exists. The IP address of the parameter area, however,
is not changed, which is for querying.
0b0110 The software enters the exhibition mode.
0b1001 Indicates the running state when the watchdog is started.
0b1011 Erases the database.
0b1100 Erases the NE software, including the patches.
0b1101 Erases the database and NE software, including the patches.
0b1110 Erases the database, NE software, and NE.ini file.
0b1111 Erases the extended BIOS and system parameter area in the file system
and flash memory.

5.2.7 Valid Slots
The GSCC must be installed in a valid slot in the subrack. Otherwise, the GSCC cannot work
normally.
5 Cross-Connect Boards and System Control Boards
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The GSCC can be installed in slots 17 and 18 in the subrack.
5.2.8 Feature Code
The GSCC does not have the feature code.
5.2.9 Parameter Settings
You can set parameters for the GSCC by using the T2000.
You can set the following parameters for the GSCC by using the T2000:
l NE ID
l NE name, date, and time
l F&f debugging serial port
l OAM NM port
l Broadcast data port
l F1 data port
5.2.10 Technical Specifications
The technical specifications of the GSCC include the mechanical specifications and power
consumption.
Mechanical Specifications
The mechanical specifications of the GSCC are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight of the N4GSCC (kg): 1.0
l Weight of the N6GSCC (kg): 0.7
Power Consumption
The maximum power consumption of the N4GSCC at room temperature (25C) is 19 W.
The maximum power consumption of the N6GSCC at room temperature (25C) is 38 W.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 5 Cross-Connect Boards and System Control Boards
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5-21
6 Packet Boards
About This Chapter
The packet boards include the PEX1, PEX2, PEG16, PEG8, PEFF8, and PETF8. The packet
boards realize the packet switching function on the packet plane.
6.1 PEX1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PEX1 (1x10GE Ethernet processing board). This topic also
describes how to configure and commission the PEX1.
6.2 PEX2
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PEX2 (2-port 10 Gigabit Ethernet switching processing board).
This topic also describes how to configure and commission the PEX2.
6.3 PEG8
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PEG8 (8-Port Gigabit Ethernet switching processing board). This
topic also describes how to configure and commission the PEG8
6.4 PEG16
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PEG16 (16xGE Ethernet processing board). This topic also
describes how to configure and commission the PEG16.
6.5 PETF8
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PETF8 (8xFE electrical interface board). This topic also describes
how to configure and commission the PETF8.
6.6 PEFF8
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PEFF8 (8-port fast Ethernet optical interface processing board).
This topic also describes how to configure and commission the PEFF8.
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6-1
6.1 PEX1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PEX1 (1x10GE Ethernet processing board). This topic also
describes how to configure and commission the PEX1.
6.1.1 Version Description
The PEX1 is available in N1 and N2.
6.1.2 Application
The PEX1 is mainly used in the packet data transmission field to access data packets, manage
bandwidths, and realize switching of data packets.
6.1.3 Functions and Features
The PEX1 processes and forwards 1x10 Gbit/s Ethernet services and supports QoS functions
such as traffic management, congestion control, and queue scheduling for data packets.
6.1.4 Working Principle and Signal Flow
The PEX1 consists of the network processing module, transmission management module,
switching network buffering module, CPU management module, logic control module,
temperature and voltage detecting module, clock module, and power module.
6.1.5 Front Panel
The front panel of the PEX1 has indicators, an interface, a bar code, and a laser safety class label.
6.1.6 Jumpers and DIP Switches
The PEX1 does not have any jumpers or DIP switches that are used for board settings.
6.1.7 Valid Slots
The PEX1 must be installed in a valid slot in the subrack. Otherwise, the PEX1 fails to work
normally.
6.1.8 Feature Code
The PEX1 does not have the feature code.
6.1.9 Parameter Settings
You can set parameters for the PEX1 by using the T2000.
6.1.10 Technical Specifications
The technical specifications of the PEX1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
6.1.1 Version Description
The PEX1 is available in N1 and N2.
Table 6-1 describes the versions of the PEX1.
Table 6-1 Versions of the PEX1
Item Description
Functional versions The PEX1 is available in two functional versions, namely, N1
and N2.
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Item Description
Differences l The N1PEX1 occupies two slots, but the N1PEX1 occupies
only one slot.
l The N1PEX1 does not support the following functions or
features: MPLS PW APS, MPLS PW OAM, DHCP relay,
MC-LAG, VRRP, BFD, L3VPN, MS-PW, DNI APS, and
response to the ping command.
Substitution None

6.1.2 Application
The PEX1 is mainly used in the packet data transmission field to access data packets, manage
bandwidths, and realize switching of data packets.
Figure 6-1 shows the typical networking and application of the PEX1. The PEX1 works with
the cross-connect board that provides the packet switching function to meet the requirement of
packet features. With this board, the TDM plane can be overlapped with the packet plane on the
OptiX OSN equipment to transmit data on the two planes. Thus, the equipment realizes the
smooth evolution from the MSTP network to the PTN network.
Figure 6-1 Networking and application of the PEX1
PSN
Traffic flow
Cross-connect board on the
TDM and packet planes
NMS
PSN: Packet switched network
OptiX OSN 1500
OptiX OSN 1500
OptiX OSN 3500/
7500
OptiX OSN 3500/
7500
OptiX OSN 3500/
7500
OptiX OSN 3500/
7500
OptiX OSN 1500
OptiX OSN 1500
GE ring
10GE ring
PSN
GE ring
PSN
FE interface board/
processing board
GE processing board
GE aggregation board
10GE processing board

6.1.3 Functions and Features
The PEX1 processes and forwards 1x10 Gbit/s Ethernet services and supports QoS functions
such as traffic management, congestion control, and queue scheduling for data packets.
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6-3
Table 6-2 provides the functions and features of the PEX1.
Table 6-2 Functions and features of the PEX1
Function and
Feature
Description
Basic functions Provides one 10GE optical interface and can access and process 1x10
GE services independently. The optical interface supports the colored
optical interface.
Functions when
being used with the
access board
Does not support the access board, and one 10GE interface is available
on the front panel of the board.
Specifications of the
interface
(N1PEX1) Supports 10GBase-SR, 10GBase-SW, 10GBase-LR,
10GBase-LW, 10GBase-ER, 10GBase-EW, 10GBase-ZR, and
10GBase-ZW Ethernet optical interfaces.
(N2PEX1) Supports the 10GBase-SR, 10GBase-LR, 10GBase-ER,
and 10GBase-ZR Ethernet optical interfaces.
The optical interface uses the LC connector and supports the
transmission distances of 0.3 km, 2 km, 10 km, 40 km, and 80 km.
Characteristics of the
interface
l Supports the full-duplex mode for the port.
l Supports the setting of the MTU for the Ethernet port.
l Supports the setting of the following parameters for the port: flow
control, number of received packets, number of transmitted
packets, loopback mode, state, and query of the type of optical
interface.
l Supports the configuration of the LAN mode or WAN mode for
the port on the N1PEX1. The default mode of the port is the LAN
mode.The N2PEX1 supports only the LAN mode.
l Supports the measurement based on the RMON function.
l Supports the setting and query of the optical power threshold.
Processing
capability
Processes 10 Gbit/s services in full-duplex mode.
Loopback function N1PEX1:
l Supports inloops at the PHY layer of the Ethernet port.
l Supports inloops at the MAC layer of the Ethernet ports.
N2PEX1: Supports inloops and outloops at the MAC layer of the
Ethernet port.
Format of service
frames
l Supports the encapsulation in IEEE 802.3 format, Ethernet II
format, or IEEE 802.1q/p format.
l Supports the Jumbo frame with a length not more than 9600 bytes.
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Function and
Feature
Description
Type of Ethernet
services
l Supports point-to-point E-Line services.
l Supports multipoint-to-multipoint E-LAN services.
l Supports multipoint-to-point E-Aggr services.
HQoS Provides the HQoS function, including the scheduling function at
multiple levels for the flow queue and port queue and the bandwidth
restricting function, and provides the corresponding statistical
information.
LAG The number of inter-board LAG groups must not exceed 128. Each
LAG group supports a maximum of 16 LAG members.
Protection schemes l Supports the MPLS tunnel APS.
l Supports the LAG protection.
The N2PEX1 also supports the following protection schemes:
l MPLS PW APS
l MC-LAG
l DNI APS
Clock function l Supports one channel of the synchronous Ethernet clock and the
extraction of the clock from the physical layer of the port. The
quality of the clock meets the requirement of the clock source.
l Supports one channel of the IEEE 1588 V2 clock.
Maintenance
features
l Detects the fault at the physical layer of the board, the alarm
reporting that the connection at the network port is lost, the alarm
reporting that the interface fails, and the alarm reporting that the
bit errors at the interface cross the threshold.
l Supports the hot-pluggable optical module and query of the
information about the optical module.
l Supports the alarm detection function and reports various alarms
and performance events, which facilitates the management and
maintenance of the equipment.
ETH-OAM Supports the ETH-OAM function, which complies with IEEE
802.1ag, IEEE 802.3ah, and ITU-T Y.1731.
MPLS OAM Supports MPLS tunnel OAM and PW OAM, with MPLS OAM in
compliance with ITU-T Y.1711.
NOTE
N1PEX1 supports only the MPLS tunnel OAM function.
MSTP Supports the MSTP function, which is compatible with the functions
of STP and RSTP.
LPT for packet
services
Supports P2P LPT and P2MP LPT for packet services.
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Function and
Feature
Description
IGMP snooping The integrated equipment supports a maximum of 4k multicast
groups. One multicast group supports a maximum of 24k members.
Number of supported
E-Line services
l When working with the N4GSCC: 4k
l When working with the N6GSCC: 6k
Number of supported
E-LAN services
1k
Number of supported
E-Aggr services
4, each of which supports 127 leaf ports
Number of MPLS
tunnels
Number of unidirectional/bidirectional MPLS tunnels (with the
tunnels shared):
N1PEX1: 4k
N2PEX1:
l When working with the N4GSCC: 4k
l When working with the N6GSCC: 16k
Number of
bidirectional static
PWs
16k
Number of QinQ
links
1k
Number of static
MAC addresses in E-
LAN services
2k
Number of VLANs 4094
Number of VLAN
sub-interfaces
l When working with the N4GSCC: 256
l When working with the N6GSCC: 2k
Number of MPLS
tunnel APS
protection groups
l When working with the N4GSCC: 1k
l When working with the N6GSCC: 4k
Number of MPLS
PW APS protection
groups
Supports a maximum of 1k MPLS PW APS protection groups, and a
PW protection group can bind a maximum of 512 members (only on
the N2PEX1).
NOTE
MPLS PW APS and MPLS tunnel APS share the protection resources.
Number of MPLS
tunnels that support
OAM
2k
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Function and
Feature
Description
Number of MPLS
PWs that support
OAM
2k (only on the N2PEX1)
NOTE
MPLS PW OAM and MPLS tunnel OAM share the resources.
Number of DNI APS
protection groups
1k (only on the N2PEX1)
Number of MC-LAG
protection groups
64 (only on the N2PEX1)
Number of FIBs 4k (only on the N2PEX1)
Number of VRF
instances
64 (only on the N2PEX1)
Number of static IP
routes
8k (only on the N2PEX1)
Number of DHCP
relays
Supports a maximum of 16 hops of DHCP relay (only on the
N2PEX1).
Response to ping Supports response to the IP ping command (only on the N2PEX1).
Number of VRRP
groups
256 (only on the N2PEX1)
Number of BFD
sessions
512 (only on the N2PEX1)
MS-PW function l Supports static switching of MS-PWs.
l Supports continuity check for MS-PWs.

6.1.4 Working Principle and Signal Flow
The PEX1 consists of the network processing module, transmission management module,
switching network buffering module, CPU management module, logic control module,
temperature and voltage detecting module, clock module, and power module.
Figure 6-2 shows the functional block diagram of the PEX1.
OptiX OSN 3500 Intelligent Optical Transmission System
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Figure 6-2 Functional block diagram of the PEX1
Service
signal
Clock
module
Service
signal

CPU
management
module
Data backup bus
Inter-board communication bus
PSXCSA
Two system clock signals
GSCC
Backplane
Synchronous Ethernet clock
Network
processing module
Working clock
Modules of the board
1x10GE signals
Logic control
module
Power
module
- 48V/ - 60V
IEEE 1588 V2 packet
PSXCSA
PSXCSA
PSXCSA
GSCC
- 48V/ - 60V
IEEE 1588 V2 packet
Synchronous Ethernet clock
Service
signal
Modules of the
board
Packet f orwarding
module
Data processing
module
Upstream
transmission module
Downstream
transmission module
Transmission
management module
Upstream
scheduling module
Downstream
scheduling module
Switching network
buf f ering module
Parallel management bus Parallel management bus
Parallel management
bus
Parallel management bus
Temperature and
voltage detecting
signals
Temperature
and voltage
detecting signals

Receive Direction
The network processing module accesses the 10xGE optical signals, decodes the signals, and
converts the serial signals into parallel signals. Then, the network processing module performs
route searching or address matching for the data packets, and transmits the corresponding packets
to the transmission management module. The transmission management module buffers and
grooms the packets, slices the packets into cells that the switching network requires, and sends
the cells to the switching network buffering module. The switching network buffering module
buffers the cells and sends the cells to the cross-connect unit.
Transmit Direction
The switching network buffering module processes the cells sent by the cross-connect unit and
sends the cells to the transmission management module. The transmission management module
rearranges the cells to form packets, performs buffering and QoS management for the packets,
and sends the packets to the network processing module. The network processing module
converts the parallel signals into serial signals and sends the signals to the 10xGE optical
interface.
Network Processing Module
The network processing module performs route searching, address matching, and other functions
for data packets. The network processing module of the PEX1 can process the 10 Gbit/s data
packets in full-duplex mode.
Transmission Management Module
The transmission management module slices packets into cells, and performs QoS management
and large volume buffering for the cells.
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l QoS management: The transmission management module provides the scheduling function
at five levels including the flow queue and port queue, the bandwidth restricting function,
and the corresponding statistical information.
l Large volume buffering: The transmission management module supports the traffic of 10
Gbit/s.
Switching Network Buffering Module
The switching network buffering module performs cell buffering, queue management,
scheduling, and other functions. This module and the cross-connect unit form a three-level
switching network to switch cells.
CPU Management Module
The CPU management module provides the parallel management bus, Ethernet bus, and other
buses to manage the modules of the PEX1. The CPU management module also monitors alarms
and performance events and reports the alarms and performance events to the SCC unit.
Logic Control Module
The logic control module controls the logic of the PEX1. The PEX1 occupies two slots. Each
board part that occupies one slot has the control part. The control logic of the PEX1 is realized
on the board part that occupies the slot with a smaller slot number between the two slots that
house the PEX1.
Temperature and Voltage Detecting Module
The temperature and voltage detecting module monitors the temperature and voltage.
Clock Module
The clock module performs the following functions:
l Provides the clock signal for each module of the PEX1.
l Supports the IEEE 1588 V2 clock.
l Supports the synchronous Ethernet clock.
Power Module
The power module converts the accessed DC voltage into the DC voltages that the modules of
the PEX1 require.
6.1.5 Front Panel
The front panel of the PEX1 has indicators, an interface, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 6-3 shows the appearance of the front panel of the N1PEX1.
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Figure 6-3 Front panel of the N1PEX1
PEX1
PEX1
ACT
PROG
STAT
CLASS 1
LASER
PRODUCT
LINK
ACT
SRV
O
U
T
1
I
N
1

Figure 6-4 shows the appearance of the N2PEX1.
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Figure 6-4 Front panel of the N2PEX1
PEX1
PEX1
CLASS 1
LASER
PRODUCT
ACT
PROG
STAT
SRV
OUT1
IN1
ACT
LINK

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Connection status indicator (LINK) one color (green)
l Data receiving and transmission indicator (ACT) one color (orange)
For the meanings of the status of the indicators, see 22.2 Alarm Indicators on the Boards.
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Interfaces
The front panel of the PEX1 has one optical interface. Table 6-3 describes the type and usage
of the optical interface of the PEX1.
Table 6-3 Optical interface of the PEX1
Interface Type of Interface Usage
IN1 LC (pluggable) Receives 10GE signals.
OUT1 LC (pluggable) Transmits 10GE signals.

6.1.6 Jumpers and DIP Switches
The PEX1 does not have any jumpers or DIP switches that are used for board settings.
6.1.7 Valid Slots
The PEX1 must be installed in a valid slot in the subrack. Otherwise, the PEX1 fails to work
normally.
The N1PEX1 occupies two slots, and it can be installed in slots 18, and 1116. The PEX1 slot
displayed on the T2000 is the slot that has a smaller slot number between the two slots that house
the PEX1. For example, if the PEX1 is installed in slots 1 and 2, the PEX1 slot displayed on the
T2000 is slot 1. The mapping relationships between the valid slots for the PEX1 and the allocated
bandwidths are as follows:
l Slot 1: 5 Gbit/s
l Slot 3: 7.5 Gbit/s
l Slot 5, 7, 11, or 13: 10 Gbit/s
l Slot 15: 7.5 Gbit/s
Table 6-4 lists the slots valid for the PEX1 and the corresponding logical slots of the N1PEX1
on the T2000.
Table 6-4 Slots valid for the N1PEX1 and the corresponding logical slots of the N1PEX1 on
the T2000
Slot Valid for the PEX1 Corresponding Logical Slot
Slots 1 and 2 Slot 1
Slots 3 and 4 Slot 3
Slots 5 and 6 Slot 5
Slots 7 and 8 Slot 7
Slots 11 and 12 Slot 11
Slots 13 and 14 Slot 13
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Slot Valid for the PEX1 Corresponding Logical Slot
Slots 15 and 16 Slot 15

The N2PEX1 occupies one slot, and it can be installed in slots 18, and 1116. The mapping
relationships between the valid slots for the N2PEX1 and the allocated bandwidths are as
follows:
l Slots 13, and 16: 2.5 Gbit/s
l Slot 46, and 13 15: 5 Gbit/s
l Slot 7, 8,, 11, and 12: 10 Gbit/s
6.1.8 Feature Code
The PEX1 does not have the feature code.
6.1.9 Parameter Settings
You can set parameters for the PEX1 by using the T2000.
Displayed Slots
The N1PEX1 occupies two slots in the subrack. The logical slot of the N1PEX1 displayed on
the T2000 is the slot that has a smaller slot number between the two slots that house the PEX1.
For the logical slots of the N1PEX1 displayed on the T2000, refer to Table 6-4.
NOTE
The N2PEX1 occupies one slot in the subrack. The logical slot of the N2PEX1 displayed on the NMS corresponds
to the installation slot.
Board Parameters
You can set the following principal parameter for the PEX1 by using the T2000:
l Ethernet interface
For more parameters and the description of the parameters, see 25.1 Packet Boards.
6.1.10 Technical Specifications
The technical specifications of the PEX1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 6-5 lists the parameters specified for the optical interfaces of the N1PEX1.
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Table 6-5 Parameters specified for the optical interfaces of the N1PEX1
Parameter Value
Type of
interface
10GBASE-
SR (LAN)
10GBASE-
SW (WAN)
10GBASE-
LR (LAN)
10GBASE-
LW (WAN)
10GBASE-
LR (LAN)
10GBASE-
LW (WAN)
10GBASE-
ER (LAN)
10GBASE-
EW (WAN)
10GBASE-
ZR (LAN)
10GBASE-
ZW (WAN)
Transmissio
n distance
(km)
0.3 2 10 40 80
Type of fiber Multi-mode
LC
Single-mode
LC
Single-mode
LC
Single-
mode LC
Single-
mode LC
Launched
optical power
range (dBm)
-1.3 to -7.3 -6 to -1 -6 to -1 -1 to 2 0 to 4
Operating
wavelength
range (nm)
840 to 860 1260 to 1330 1260 to 1330 1530 to
1565
1530 to
1565
Minimum
overload
(dBm)
-1 -1 0.5 -1 -7
Receiver
sensitivity
(dBm)
-7.5 -11 -11 -15 -24
Minimum
extinction
ratio (dB)
3 6 6 8.2 9

Table 6-6 lists the parameters specified for the optical interfaces of the N2PEX1.
Table 6-6 Parameters specified for the optical interfaces of the N2PEX1
Parameter Value
Type of
interface
10GBASE-
SR (LAN)
10GBASE-
SW (WAN)
10GBASE-
LR (LAN)
10GBASE-
LW (WAN)
10GBASE-
LR (LAN)
10GBASE-
LW (WAN)
10GBASE-
ER (LAN)
10GBASE-
EW (WAN)
10GBASE-
ZR (LAN)
10GBASE-
ZW (WAN)
Transmissio
n distance
(km)
0.3 2 10 40 80
Type of fiber Multi-mode
LC
Single-mode
LC
Single-mode
LC
Single-
mode LC
Single-
mode LC
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Parameter Value
Launched
optical power
range (dBm)
-1.3 to -7.3 -6 to -1 -6 to -1 -1 to 2 0 to 4
Operating
wavelength
range (nm)
840 to 860 1260 to 1330 1260 to 1330 1530 to
1565
1530 to
1565
Minimum
overload
(dBm)
-1 -1 0.5 -1 -7
Receiver
sensitivity
(dBm)
-7.5 -11 -11 -15 -24
Minimum
extinction
ratio (dB)
3 6 6 8.2 9

Table 6-7 lists the parameters specified for the 10GE colored optical interfaces of the PEX1.
Table 6-7 Parameters specified for the 10GE colored optical interfaces of the PEX1
Parameter Value
Nominal bit rate 9953280 kbit/s 10312500 kbit/s
Launched optical power
range (dBm)
-1 to 2 -1 to 2
Receiver sensitivity
(dBm)
-12 -12
Minimum overload
(dBm)
3 3
Maximum allowed
dispersion (ps/nm)
800 800
Minimum extinction
ratio (dB)
8.2 8.2

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
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Mechanical Specifications
The mechanical specifications of the N1PEX1 are as follows:
l Dimensions (mm): 50.8 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 2.4
The mechanical specifications of the N2PEX1 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.4
Power Consumption
The maximum power consumption of the N1PEX1 at room temperature (25C) is 107 W.
The maximum power consumption of the N2PEX1 at room temperature (25C) is 75 W.
6.2 PEX2
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PEX2 (2-port 10 Gigabit Ethernet switching processing board).
This topic also describes how to configure and commission the PEX2.
6.2.1 Version Description
The PEX2 is available in one functional version, namely, N1.
6.2.2 Application
The PEX2 is mainly used in the packet data transmission field to access data packets, manage
bandwidths, and implement switching of data packets.
6.2.3 Functions and Features
The PEX2 processes and forwards 2x10 Gbit/s Ethernet services and supports QoS functions
such as traffic management, congestion control, and queue scheduling for data packets.
6.2.4 Working Principle and Signal Flow
The PEX2 consists of the network processing module, transmission management module,
switching network buffering module, CPU management module, logic control module,
temperature and voltage detecting module, clock module, and power module.
6.2.5 Front Panel
The front panel of the PEX2 has indicators, interfaces, a bar code, and a laser safety class label.
6.2.6 Jumpers and DIP Switches
The PEX2 does not have any jumpers or DIP switches that are used for board settings.
6.2.7 Valid Slots
The PEX2 must be installed in a valid slot in the subrack. Otherwise, the PEX2 fails to work
normally.
6.2.8 Feature Code
The PEX2 does not have the feature code.
6.2.9 Parameter Settings
You can set the parameters for the PEX2 by using the T2000.
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6.2.10 Technical Specifications
The technical specifications of the PEX2 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
6.2.1 Version Description
The PEX2 is available in one functional version, namely, N1.
6.2.2 Application
The PEX2 is mainly used in the packet data transmission field to access data packets, manage
bandwidths, and implement switching of data packets.
Figure 6-5 shows the typical networking and application of the PEX2. The PEX2 works with
the cross-connect board that provides the packet switching function to meet the requirement of
packet features. With this board, the TDM can be overlapped with the packet plane on the OptiX
OSN equipment so that the data can be transmitted on two planes. In this manner, an MSTP
network can smoothly evolve to a PTN network.
Figure 6-5 Networking and application of the PEX2
PSN
Traffic flow
Cross-connect board on the
TDM and packet planes
NMS
PSN: Packet switched network
OptiX OSN 1500
OptiX OSN 1500
OptiX OSN 3500/
7500
OptiX OSN 3500/
7500
OptiX OSN 3500/
7500
OptiX OSN 3500/
7500
OptiX OSN 1500
OptiX OSN 1500
GE ring
10GE ring
PSN
GE ring
PSN
FE interface board/
processing board
GE processing board
GE aggregation board
10GE processing board

6.2.3 Functions and Features
The PEX2 processes and forwards 2x10 Gbit/s Ethernet services and supports QoS functions
such as traffic management, congestion control, and queue scheduling for data packets.
Table 6-8 provides the functions and features of the PEX2.
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Table 6-8 Functions and features of the PEX2
Function and
Feature
PEX2
Basic functions Provides two 10GE optical interfaces and can access and process 2x10
GE services. The optical interface supports the colored optical
interface.
Functions when
being used with the
access board
Does not support the access board, and two 10GE interfaces are
available on the front panel of the board.
Specifications of the
interface
Supports the 10GBASE-SR, 10GBASE-LR, 10GBASE-ER, and
10GBASE-ZR Ethernet optical interfaces. The optical interface uses
the LC connector and supports the transmission distances of 0.3 km,
2 km, 10 km, 40 km, and 80 km.
Characteristics of the
interface
l Supports the full-duplex mode for the port.
l Supports the setting of the MTU for the Ethernet port.
l Supports the setting of the following parameters for the port: flow
control, number of received packets, number of transmitted
packets, loopback mode, state, and query of the type of optical
interface.
l Supports the RMON performance measurement function.
l Supports the setting and query of the optical power threshold.
Processing
capability
Processes 20 Gbit/s services in full-duplex mode.
Loopback function Supports inloops at the MAC layer of the Ethernet ports.
Format of service
frames
l Supports the encapsulation in IEEE 802.3 format, Ethernet II
format, or IEEE 802.1q/p format.
l Supports the Jumbo frame with a length not more than 9600 bytes.
Type of Ethernet
services
l Supports point-to-point E-Line services.
l Supports multipoint-to-multipoint E-LAN services.
l Supports multipoint-to-point E-Aggr services.
HQoS Provides the HQoS function, including the scheduling function at
multiple levels for the flow queue and port queue and the bandwidth
restricting function, and provides the corresponding statistical
information.
LAG Supports a maximum of 128 intra-board or inter-board LAGs. Each
LAG supports a maximum of 16 members.
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Function and
Feature
PEX2
Protection schemes l Supports MPLS tunnel APS.
l Supports LAG protection.
l Supports MPLS PW APS.
l Supports MC-LAG protection.
l Supports DNI APS.
Clock function l Supports two channels of synchronous Ethernet clocks and the
extraction of the clock from the physical layer of the port. The
quality of the clock meets the requirement of the clock source.
l Supports two channels of IEEE 1588 V2 clocks.
Maintenance
features
l Detects the fault at the physical layer of the board, the alarm
reporting that the connection at the network port is lost, the alarm
reporting that the interface fails, and the alarm reporting that the
bit errors at the interface cross the threshold.
l Supports the hot-pluggable optical module and query of the
information about the optical module.
l Supports the alarm detection function and reports various alarms
and performance events, which facilitates management and
maintenance of the equipment.
ETH-OAM function Supports the ETH-OAM function, which complies with IEEE
802.1ag, IEEE 802.3ah, and ITU-T Y.1731.
MPLS OAM Supports the MPLS tunnel OAM and PW OAM functions, with
MPLS OAM in compliance with ITU-T Y.1711.
MSTP Supports MSTP, which is compatible with the functions of STP and
RSTP.
LPT for packet
services
Supports P2P LPT and P2MP LPT for packet services.
IGMP snooping
function
Supports a maximum of 4k multicast groups. One multicast group
supports a maximum of 24k members.
Number of supported
E-Line services
l When working with the N4GSCC: 4k
l When working with the N6GSCC: 8k
Number of supported
E-LAN services
1k
Number of supported
E-Aggr services
4, each of which supports 127 leaf ports
Number of MPLS
tunnels
Number of unidirectional/bidirectional MPLS tunnels (with tunnels
shared):
l When working with the N4GSCC: 4k
l When working with the N6GSCC: 16k
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Function and
Feature
PEX2
Number of
bidirectional static
PWs
16k
Number of QinQ
links
1k
Number of static
MAC addresses in E-
LAN services
2k
Number of VLANs 4094
Number of VLAN
sub-interfaces
l When working with the N4GSCC: 256
l When working with the N6GSCC: 2k
Number of MPLS
tunnel APS
protection groups
l When working with the N4GSCC: 1k
l When working with the N6GSCC: 4k
Number of MPLS
PW APS protection
groups
Supports a maximum of 1k MPLS PW APS protection groups, and a
PW protection group can bind a maximum of 512 members.
NOTE
MPLS PW APS and MPLS tunnel APS share the protection resources.
Number of MPLS
tunnels that support
OAM
2k
Number of MPLS
PWs that support
OAM
2k
NOTE
MPLS PW OAM and MPLS tunnel OAM share the resources.
Number of DNI APS
protection groups
1k
Number of MC-LAG
protection groups
64
Number of FIBs 4k
Number of VRF
instances
64
Number of static IP
routes
8k
Number of DHCP
relays
A maximum of 16 hops of DHCP relays.
Response to ping Supports response to the IP ping command.
Number of VRRP
groups
256
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Function and
Feature
PEX2
Number of BFD
sessions
512
MS-PW function l Supports static switching of MS-PWs.
l Supports continuity check for MS-PWs.

6.2.4 Working Principle and Signal Flow
The PEX2 consists of the network processing module, transmission management module,
switching network buffering module, CPU management module, logic control module,
temperature and voltage detecting module, clock module, and power module.
Figure 6-6 shows the functional block diagram of the PEX2.
Figure 6-6 Functional block diagram of the PEX2
Service
signal

CPU
management
module
PSXCSA
GSCC
Backplane
Working clock
Modules of the board
2x10GE
signals
Logic control
module
Power
module
- 48V/ - 60V
PSXCSA
PSXCSA
PSXCSA
GSCC
- 48V/ - 60V
Upstream
transmission module
Downstream
transmission module
Transmission
management module
Upstream
scheduling module
Downstream
scheduling module
Switching network
buf f ering module
Network
processing module
Packet f orwarding
module
Data processing
module
Service
signal
Service
signal
Two system clock signals
Clock
module
IEEE 1588 V2 packet
Synchronous Ethernet
clock
IEEE 1588 V2 packet
Synchronous Ethernet clock
Parallel
management bus
Parallel management bus Parallel management bus
Data backup bus
Inter-board communication bus
Parallel management bus
Temperature
and voltage
detecting signals
Temperature and
voltage detecting
signals
Modules of the
board

Receive Direction
The network processing module accesses 2x10GE optical signals, decodes the signals, and
converts the serial signals into parallel signals. Then, the network processing module performs
route searching or address matching for the data packets, and transmits the corresponding packets
to the transmission management module. The transmission management module buffers and
schedules the packets, slices the packets into cells that the switching network requires, and sends
the cells to the switching network buffering module. The switching network buffering module
buffers the cells and sends the cells to the cross-connect unit.
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Transmit Direction
The switching network buffering module processes the cells sent by the cross-connect unit and
sends the cells to the transmission management module. The transmission management module
rearranges the cells to form packets, performs buffering and QoS management for the packets,
and sends the packets to the network processing module. The network processing module
converts the parallel signals into serial signals and sends the signals to the 10xGE optical
interface.
Network Processing Module
The network processing module performs route searching, address matching, and other functions
for data packets. The network processing module of the PEX2 can process the 20 Gbit/s data
packets in full-duplex mode.
Transmission Management Module
The transmission management module slices packets into cells, and performs QoS management
and large volume buffering for the cells.
l QoS management: The transmission management module provides the scheduling function
at five levels for the flow queue and port queue, and the bandwidth restricting function,
and provides the corresponding statistics information.
l Large volume buffering: The transmission management module supports traffic of 20 Gbit/
s.
Switching Network Buffering Module
The switching network buffering module performs cell buffering, queue management,
scheduling, and other functions. This module and the cross-connect unit form a three-level
switching network to switch cells.
CPU Management Module
The CPU management module provides the parallel management bus, Ethernet bus, and other
buses to manage the modules of the board. The CPU management module also monitors alarms
and performance events and reports the alarms and performance events to the SCC unit.
Logic Control Module
The logic control module controls the logic of the PEX2. It performs the following functions:
l Decodes the address signals of the peripheral modules, allocates the registers, and controls
the logic.
l Reports and controls the board status, for example, the shutdown or startup of the laser.
l Controls the logic of the CPU module and decodes the address signals of the CPU module.
l Configures services, queries the performance, and controls alarms.
l Implements some clock functions.
Temperature and Voltage Detecting Module
The temperature and voltage detecting module monitors the temperature and voltage.
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Clock Module
The clock module performs the following functions:
l Provides clock signals for each module of the PEX2.
l Supports the IEEE 1588 V2 clock.
l Supports the synchronous Ethernet clock.
Power Module
The power module converts the accessed DC voltage into the DC voltages that the modules of
the PEX2 require.
6.2.5 Front Panel
The front panel of the PEX2 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 6-7 shows the appearance of the front panel of the PEX2.
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Figure 6-7 Front panel of the PEX2
PEX2
PEX2
CLASS 1
LASER
PRODUCT
ACT
PROG
STAT
SRV
OUT1
IN1
OUT2
IN2
ACT1
LINK2
LINK1
ACT2

Indicators
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Connection status indicator (LINK) one color (green)
l Data receiving and transmission indicator (ACT) one color (orange)
For the meanings of the status of the indicators, see 22.2 Alarm Indicators on the Boards.
Interfaces
The front panel of the PEX2 has two optical interfaces. Table 6-9 describes the type and usage
of the optical interfaces of the PEX2.
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Table 6-9 Optical interfaces of the PEX2
Interface Type of Interface Usage
IN1-IN2 LC (pluggable) Receives 10GE signals.
OUT1-
OUT2
LC (pluggable) Transmits 10GE signals.

6.2.6 Jumpers and DIP Switches
The PEX2 does not have any jumpers or DIP switches that are used for board settings.
6.2.7 Valid Slots
The PEX2 must be installed in a valid slot in the subrack. Otherwise, the PEX2 fails to work
normally.
The following part lists the valid slots of the PEX2 and the corresponding bandwidths:
l Slots 1-3, and 16 (2.5 Gbit/s)
l Slots 4-6 and 13-15 (5 Gbit/s)
l Slots 7 and 12 (10 Gbit/s)
l Slots 8 and 11 (20 Gbit/s)
6.2.8 Feature Code
The PEX2 does not have the feature code.
6.2.9 Parameter Settings
You can set the parameters for the PEX2 by using the T2000.
You can set the following parameters for the PEX2 by using the T2000:
l Ethernet interface
For information about more parameters and the description of each parameter, see 25.1 Packet
Boards.
6.2.10 Technical Specifications
The technical specifications of the PEX2 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 6-10 lists the parameters specified for the optical interfaces of the PEX2.
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Table 6-10 Parameters specified for the optical interfaces of the PEX2
Parameter Value
Type of
interface
10GBASE-
SR (LAN)
10GBASE-
LR (LAN)
10GBASE-
LR (LAN)
10GBASE-
ER (LAN)
10GBASE-
ZR (LAN)
Transmissio
n distance
(km)
0.3 2 10 40 80
Type of fiber Multi-mode
LC
Single-mode
LC
Single-mode
LC
Single-
mode LC
Single-
mode LC
Launched
optical power
range (dBm)
-1.3 to -7.3 -6 to -1 -6 to -1 -1 to 2 0 to 4
Operating
wavelength
range (nm)
840 to 860 1260 to 1330 1260 to 1330 1530 to
1565
1530 to
1565
Minimum
overload
(dBm)
-1 -1 0.5 -1 -7
Receiver
sensitivity
(dBm)
-7.5 -11 -11 -15 -24
Minimum
extinction
ratio (dB)
3 6 6 8.2 9

Table 6-11 lists the parameters specified for the 10GE colored optical interfaces of the PEX2.
Table 6-11 Parameters specified for the 10GE colored optical interfaces of the PEX2
Parameter Value
Nominal bit rate 9953280 kbit/s 10312500 kbit/s
Launched optical power
range (dBm)
-1 to 2 -1 to 2
Receiver sensitivity
(dBm)
-12 -12
Minimum overload
(dBm)
3 3
Maximum allowed
dispersion (ps/nm)
800 800
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Parameter Value
Minimum extinction
ratio (dB)
8.2 8.2

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the PEX2 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.4
Power Consumption
The maximum power consumption of the PEX2 at room temperature (25C) is 78 W.
6.3 PEG8
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PEG8 (8-Port Gigabit Ethernet switching processing board). This
topic also describes how to configure and commission the PEG8
6.3.1 Version Description
The PEG8 is available in one functional version, namely, N1.
6.3.2 Application
The PEG8 is mainly used in the packet data transmission field to access data packets, manage
bandwidths, and realize switching of data packets.
6.3.3 Functions and Features
The PEG8 processes and forwards 8xGE services and supports QoS functions such as traffic
management, congestion control, and queue scheduling for data packets.
6.3.4 Working Principle and Signal Flow
The PEG8 consists of the network processing module, transmission management module,
switching network buffering module, CPU management module, clock module, and power
module.
6.3.5 Front Panel
The front panel of the PEG8 has indicators, interfaces, a bar code, and a laser safety class label.
6.3.6 Jumpers and DIP Switches
The PEG8 does not have any jumpers or DIP switches that are used for board settings.
6.3.7 Valid Slots
The PEG8 must be installed in a valid slot in the subrack. Otherwise, the PEG8 fails to work
normally.
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6.3.8 Feature Code
The PEG8 does not have the feature code.
6.3.9 Parameter Settings
You can set the parameters for the PEG8 by using the T2000.
6.3.10 Technical Specifications
The technical specifications of the PEG8 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
6.3.1 Version Description
The PEG8 is available in one functional version, namely, N1.
6.3.2 Application
The PEG8 is mainly used in the packet data transmission field to access data packets, manage
bandwidths, and realize switching of data packets.
Figure 6-8 shows the typical networking and application of the PEG8. The PEG8 works with
the cross-connect board that provides the packet switching function to meet the requirement of
packet features. With this board, the TDM can be overlapped with the packet plane on the OptiX
OSN equipment so that the data can be transmitted on two planes. In this manner, an MSTP
network can smoothly evolve to a PTN network.
6.5.2 Application describes the typical networking and application when the PEG8 works with
the PETF8.
6.6.2 Application describes the typical networking and application when the PEG8 works with
the PEFF8.
Figure 6-8 Networking and application of the PEG8
PSN
Traffic flow
Cross-connect board on the
TDM and packet planes
NMS
PSN: Packet switched network
OptiX OSN 1500
OptiX OSN 1500
OptiX OSN 3500/
7500
OptiX OSN 3500/
7500
OptiX OSN 3500/
7500
OptiX OSN 3500/
7500
OptiX OSN 1500
OptiX OSN 1500
GE ring
10GE ring
PSN
GE ring
PSN
FE interface board/
processing board
GE processing board
GE aggregation board
10GE processing board
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6.3.3 Functions and Features
The PEG8 processes and forwards 8xGE services and supports QoS functions such as traffic
management, congestion control, and queue scheduling for data packets.
Table 6-12 provides the functions and features of the PEG8.
Table 6-12 Functions and features of the PEG8
Function and
Feature
PEG8
Basic functions l Provides eight GE interfaces and can access and process 8xGE
signals. The GE interface supports the colored optical interface.
l Works with the interface board PETF8 or PEFF8. One PEG8 board
can access the FE service of a maximum of two interface boards.
Specifications of the
interface
Supports the 1000BASE-SX, 1000BASE-LX, 1000BASE-VX, and
1000BASE-ZX optical interfaces. The optical interface uses the LC
connector and supports the transmission distances of 500 m, 10 km,
40 km, and 80 km.
Characteristics of the
interface
l Supports the configuration of the full-duplex mode or auto-
negotiation mode for the port.
l Supports the setting of the MTU for the Ethernet port.
l Supports the setting of the following parameters for the port: flow
control function, number of received packets, number of
transmitted packets, loopback mode, state, and query of the type
of optical interface.
l Supports the RMON performance measurement function.
l Supports the setting and query of the optical power threshold.
Processing
capability
Processes 5 Gbit/s services in full-duplex mode.
Loopback function Supports inloops at the MAC layer of the Ethernet ports.
Format of service
frames
l Provides the Layer 2 forwarding function and supports the
encapsulation in IEEE 802.3 format, Ethernet II format, or IEEE
802.1q/p format.
l Supports the Jumbo frame with a length not more than 9600 bytes.
Type of Ethernet
services
l Supports point-to-point E-Line services.
l Supports multipoint-to-multipoint E-LAN services.
l Supports multipoint-to-point E-Aggr services.
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Function and
Feature
PEG8
HQoS Provides the HQoS function and supports the flow control function
that complies with IEEE 802.3x. The PEG8 provides the scheduling
function at multiple levels for the flow queue and port queue and the
bandwidth restricting function, and provides the corresponding
statistics information.
LAG Supports a maximum of 128 intra-board or inter-board LAGs. Each
LAG supports a maximum of 16 members.
Protection schemes l Supports MPLS tunnel APS.
l Supports LAG protection.
l Supports MPLS PW APS.
l Supports MC-LAG protection.
l Supports DNI APS.
Clock function l Provides eight GE optical interfaces that support the synchronous
Ethernet clock feature.
l Supports eight channels of IEEE 1588 V2 clock signals.
Maintenance
features
l Detects the fault at the physical layer of the board, the alarm
reporting that the connection at the network port is lost, the alarm
reporting that the interface fails, and the alarm reporting that the
bit errors at the interface cross the threshold.
l Supports the hot-pluggable optical module and query of the
information about the optical module.
l Supports the alarm detection function and reports various alarms
and performance events, which facilitates management and
maintenance of the equipment.
ETH-OAM function Supports the ETH-OAM function, which complies with IEEE
802.1ag, IEEE 802.3ah, and ITU-T Y.1731.
MPLS OAM Supports the MPLS tunnel OAM and PW OAM functions, with
MPLS OAM in compliance with ITU-T Y.1711.
MSTP Supports MSTP, which is compatible with the functions of STP and
RSTP.
LPT for packet
services
Supports P2P LPT and P2MP LPT for packet services.
IGMP snooping
function
The integrated equipment supports a maximum of 4k multicast
groups. One multicast group supports a maximum of 24k members.
Number of supported
E-Line services
l When working with the N4GSCC: 4k
l When working with the N6GSCC: 8k
Number of supported
E-LAN services
1k
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Function and
Feature
PEG8
Number of supported
E-Aggr services
4, each of which supports 127 leaf ports
Number of MPLS
tunnels
Number of unidirectional/bidirectional MPLS tunnels (with tunnels
shared):
l When working with the N4GSCC: 4k
l When working with the N6GSCC: 16k
Number of
bidirectional static
PWs
16k
Number of QinQ
links
1k
Number of static
MAC addresses in E-
LAN services
2k
Number of VLANs 4094
Number of VLAN
sub-interfaces
l When working with the N4GSCC: 256
l When working with the N6GSCC: 2k
Number of MPLS
tunnel APS
protection groups
l When working with the N4GSCC: 1k
l When working with the N6GSCC: 4k
Number of MPLS
PW APS protection
groups
Supports a maximum of 1k MPLS PW APS protection groups, and a
PW protection group can bind a maximum of 512 members.
NOTE
MPLS PW APS and MPLS tunnel APS share the protection resources.
Number of MPLS
tunnels that support
OAM
2k
Number of MPLS
PWs that support
OAM
2k
NOTE
MPLS PW OAM and MPLS tunnel OAM share the resources.
Number of DNI APS
protection groups
1k
Number of MC-LAG
protection groups
64
Number of FIBs 4k
Number of VRF
instances
64
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Function and
Feature
PEG8
Number of static IP
routes
8k
Number of DHCP
relays
A maximum of 16 hops of DHCP relays.
Response to ping Supports response to the IP ping command.
Number of VRRP
groups
256
Number of BFD
sessions
512
MS-PW function l Supports static switching of MS-PWs.
l Supports continuity check for MS-PWs.

6.3.4 Working Principle and Signal Flow
The PEG8 consists of the network processing module, transmission management module,
switching network buffering module, CPU management module, clock module, and power
module.
Figure 6-9 shows the functional block diagram of the PEG8.
Figure 6-9 Functional block diagram of the PEG8
8xGE signals
GE signals
Interf ace board
PSXCSA
Clock module

CPU management
module
Ethernet communication bus
GSCC
Other boards
Backplane
Working clock
Power
module
- 48V/ - 60 V
Synchronous Ethernet
clock
System clock
Interf ace board
PSXCSA
Interf ace board
Service
signal
Service
signal
- 48V/ - 60 V
PSXCSA
PSXCSA
Data processing
module
Packet f orwarding
module
Network
processing module
IEEE 1588 V2 packet
Interf ace board
Service
signal
Upstream
transmission module
Downstream
transmission module
Transmission
management module
Upstream
scheduling module
Downstream
scheduling module
Switching network
buf f ering module
Parallel
management bus
Parallel management bus Parallel management bus
Inter-board communication bus
Modules of the board
Interf ace board/Eight GE signals
Interf ace board/Eight GE signals
Modules of the board
IEEE 1588 V2 packet
Two system clock
signals
Synchronous Ethernet
clock
IEEE 1588 V2 packet

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Receive Direction
The network processing module accesses the signals sent from the GE interface on the front
panel or the interface board, decodes the signals, and converts the serial signals into parallel
signals. Then, the network processing module performs route searching or address matching for
the data packets, and sends the corresponding packets to the transmission management module.
The transmission management module buffers and schedules the packets, slices the packets into
cells that the switching network requires, and sends the cells to the switching network buffering
module. The switching network buffering module buffers the cells and sends the cells to the
cross-connect unit.
Transmit Direction
The switching network buffering module processes the cells sent by the cross-connect unit and
sends the cells to the transmission management module. The transmission management module
rearranges the cells to form packets, performs buffering and QoS management for the packets,
and sends the packets to the network processing module. The network processing module
converts the parallel signals into serial signals, and sends the signals to the GE interface on the
front panel of the board or the corresponding interface board through the backplane.
Network Processing Module
The network processing module performs route searching, address matching, and other functions
for data packets. The network processing module of the PEG8 can process 5 Gbit/s data packets
in full-duplex mode.
Transmission Management Module
The transmission management module slices packets into cells, and performs QoS management
and large volume buffering for the cells.
l QoS management: The transmission management module provides the scheduling function
at five levels for the flow queue and port queue, and the bandwidth restricting function,
and provides the corresponding statistics information.
l Large volume buffering: The transmission management module supports traffic of 5 Gbit/
s.
Switching Network Buffering Module
The switching network buffering module performs cell buffering, queue management,
scheduling, and other functions. This module and the cross-connect unit form a three-level
switching network to switch cells.
CPU Management Module
The CPU management module provides the parallel management bus, Ethernet bus, and other
buses to manage the modules of the PEG8 and the interface board to which the PEG8
corresponds. The CPU management module also monitors alarms and performance events and
reports the alarms and performance events to the SCC unit.
Clock Module
The clock module performs the following functions:
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l Provides the clock signal for each module of the board.
l Supports the transparent transmission of the IEEE 1588 V2 packets from the interface board
or the 8xGE signals to the PSXCSA.
l Selects a clock source from the two system clocks sent from the PSXCSA and sends the
selected clock to the interface board and the modules of the PEG8.
l Selects a clock source from the synchronous Ethernet clock signals accessed by the interface
board or the 8xGE signals and sends the selected clock to the PSXCSA.
Power Module
The power module converts the accessed DC voltage into the DC voltages that the modules of
the board require.
6.3.5 Front Panel
The front panel of the PEG8 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 6-10 shows the appearance of the front panel of the PEG8.
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Figure 6-10 Front panel of the PEG8
PEG8
PEG8
CLASS 1
LASER
PRODUCT
ACT
PROG
STAT
SRV
T
X
1
R
X
1
T
X
2
R
X
2
T
X
3
R
X
3
T
X
4
R
X
4
T
X
5
R
X
5
T
X
6
R
X
6
T
X
7
R
X
7
T
X
8
R
X
8

Indicators
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22.2 Alarm Indicators on the Boards.
Interfaces
The front panel of the PEG8 has eight optical interfaces. Table 6-13 describes the type and usage
of the optical interface of the PEG8.
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Table 6-13 Optical interfaces of the PEG8
Interface Type of Interface Usage
RX1-RX8 LC (pluggable) Receives GE signals.
TX1-TX8 LC (pluggable) Transmits GE signals.

6.3.6 Jumpers and DIP Switches
The PEG8 does not have any jumpers or DIP switches that are used for board settings.
6.3.7 Valid Slots
The PEG8 must be installed in a valid slot in the subrack. Otherwise, the PEG8 fails to work
normally.
The PEG8 can be installed in slots 16, and 1316 in the subrack.
l When the PEG8 is installed in slots 1-3, and 16, the bandwidth is 2.5 Gbit/s.
l When the PEG8 is installed in slots 4-6 and 13-15, the bandwidth is 5 Gbit/s.
When the PEG8 works with the interface board PETF8 or PEFF8, one PEG8 can work with a
maximum of two PETF8 or PEFF8 boards. In this case, all the optical interfaces on the PEG8
can be used. Table 6-14 lists the slots valid for the PEG8 and the corresponding slots for the
interface boards.
Table 6-14 Slots valid for the PEG8 and the corresponding slots for the PETF8/PEFF8
Slot Valid for the PEG8 Corresponding Slot for the PETF8/PEFF8
Slot 1 -
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 6 -
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

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6.3.8 Feature Code
The PEG8 does not have the feature code.
6.3.9 Parameter Settings
You can set the parameters for the PEG8 by using the T2000.
You can set the following parameters for the PEG8 by using the T2000:
l Ethernet interface
For information about more parameters and the description of each parameter, see 25.1 Packet
Boards.
6.3.10 Technical Specifications
The technical specifications of the PEG8 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 6-15 lists the parameters specified for the optical interfaces of the PEG8.
Table 6-15 Parameters specified for the optical interfaces of the PEG8
Parameter Value
Type of
interface
1000BASE-SX 1000BASE-LX 1000BASE-
VX
1000BASE-ZX
Transmission
distance (km)
0.5 10 40 80
Type of fiber Multi-mode LC Single-mode LC Single-mode
LC
Single-mode LC
Launched
optical power
range (dBm)
-9.5 to 0 -11 to -3 -5 to 0 -2 to 5
Operating
wavelength
range (nm)
770 to 860 1270 to 1355 1270 to 1355 1500 to 1580
Minimum
overload
(dBm)
0 -3 -3 -3
Receiver
sensitivity
(dBm)
-17 -19 -22 -22
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Parameter Value
Minimum
extinction ratio
(dB)
9 9 9 9

Table 6-16 lists the parameters specified for the GE colored optical interfaces of the PEG8.
Table 6-16 Parameters specified for the GE colored optical interfaces of the PEG8
Parameter Value
Nominal bit rate 1250000 kbit/s
Launched optical power range
(dBm)
0 to 5
Receiver sensitivity (dBm) -19
Minimum overload (dBm) -3
Maximum allowed dispersion
(ps/nm)
800
Minimum extinction ratio (dB) 9

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the PEG8 are as follows:
l Dimensions (mm): 50.8 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.2
Power Consumption
The maximum power consumption of the PEG8 at room temperature (25C) is 80 W.
6.4 PEG16
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PEG16 (16xGE Ethernet processing board). This topic also
describes how to configure and commission the PEG16.
6.4.1 Version Description
The PEG16 is available in one functional version, namely, N1.
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6.4.2 Application
The PEG16 is mainly used in the packet data transmission field to access data packets, manage
bandwidths, and realize switching and aggregation of data packets.
6.4.3 Functions and Features
The PEG16 processes and forwards 16xGE services, and supports the QoS functions such as
traffic measurement, congestion control, and queue scheduling for data packets.
6.4.4 Working Principle and Signal Flow
The PEG16 consists of the network processing module, transmission management module,
switching network buffering module, CPU management module, clock module, and power
module.
6.4.5 Front Panel
The front panel of the PEG16 has indicators, interfaces, a bar code, and a laser safety class label.
6.4.6 Jumpers and DIP Switches
The PEG16 does not have any jumpers or DIP switches that are used for board settings.
6.4.7 Valid Slots
The PEG16 occupies two slots and can be installed in any two adjacent slots among slots 16
and 1316. The PEG16 slot displayed on the T2000 is the slot that has a smaller slot number
between the two slots that house the PEG16. For example, if the PEG16 is installed in slots 1
and 2, the PEG16 slot displayed on the T2000 is slot 1.
6.4.8 Feature Code
The PEG16 does not have the feature code.
6.4.9 Parameter Settings
You can set parameters for the PEG16 by using the T2000.
6.4.10 Technical Specifications
The technical specifications of the PEG16 include the Ethernet performance specifications, laser
safety class, parameters specified for optical interfaces, mechanical specifications, and power
consumption.
6.4.1 Version Description
The PEG16 is available in one functional version, namely, N1.
6.4.2 Application
The PEG16 is mainly used in the packet data transmission field to access data packets, manage
bandwidths, and realize switching and aggregation of data packets.
Figure 6-11 shows the typical networking and application when the PEG16 works with the other
boards on the network. The PEG16 works with the cross-connect board that provides the packet
switching function to meet the requirement of packet features. With this board, the TDM plane
can be overlapped with the packet plane on the OptiX OSN equipment to transmit data on the
two planes. Thus, the equipment realizes the smooth evolution from the MSTP network to the
PTN network.
For the typical networking and application when the PEG16 works with the PETF8/PEFF8, see
6.5.2 Application and 6.6.2 Application.
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Figure 6-11 Networking and application of the PEG16
PSN
Traffic flow
Cross-connect board on the
TDM and packet planes
NMS
PSN: Packet switched network
OptiX OSN 1500
OptiX OSN 1500
OptiX OSN 3500/
7500
OptiX OSN 3500/
7500
OptiX OSN 3500/
7500
OptiX OSN 3500/
7500
OptiX OSN 1500
OptiX OSN 1500
GE ring
10GE ring
PSN
GE ring
PSN
FE interface board/
processing board
GE processing board
GE aggregation board
10GE processing board

6.4.3 Functions and Features
The PEG16 processes and forwards 16xGE services, and supports the QoS functions such as
traffic measurement, congestion control, and queue scheduling for data packets.
Table 6-17 provides the functions and features of the PEG16.
Table 6-17 Functions and features of the PEG16
Function and
Feature
PEG16
Basic functions l Provides 16 GE interfaces and can access and process 16xGE
signals. The GE interface can be the colored optical interface.
l Works with the interface board PETF8/PEFF8. One PEG16 board
can access the FE services of a maximum of two interface boards.
Specifications of the
interface
Supports the 1000BASE-SX, 1000BASE-LX, 1000BASE-VX, and
1000BASE-ZX optical interfaces. The optical interface uses the LC
connector and supports the transmission distances of 500 m, 10 km,
40 km, and 80 km.
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Function and
Feature
PEG16
Characteristics of the
interface
l Supports the configuration of the full-duplex mode or auto-
negotiation mode for the port.
l Supports the setting of the MTU for the Ethernet port.
l Supports the setting of the following parameters for the port: flow
control function, number of received packets, number of
transmitted packets, loopback mode, state, and query of the type
of optical interface.
l Supports the RMON performance measurement function.
l Supports the setting and query of the optical power threshold.
Processing
capability
Processes 10 Gbit/s services in full-duplex mode.
Loopback function l Supports inloops at the PHY layer of the Ethernet port.
l Supports inloops at the MAC layer of the Ethernet port.
Format of service
frames
l Provides the Layer 2 forwarding function and supports the
encapsulation in IEEE 802.3 format, Ethernet II format, or IEEE
802.1q/p format.
l Supports the Jumbo frame with a length not more than 9600 bytes.
Type of Ethernet
services
l Supports point-to-point E-Line services.
l Supports multipoint-to-multipoint E-LAN services.
l Supports multipoint-to-point E-Aggr services.
HQoS function Provides the hierarchical QoS function and supports the flow control
function that complies with IEEE 802.3x. The board provides the
scheduling function at multiple levels including the flow queue and
port queue, the bandwidth restricting function, and the corresponding
statistical information.
LAG The sum of the number of intra-board LAG groups and the number
of inter-board LAG groups must not exceed 128. Each LAG group
supports a maximum of 16 LAG members.
Protection schemes l Supports the MPLS tunnel APS.
l Supports the LAG protection.
Clock function l Provides two GE optical interfaces (that is, the first two optical
interfaces) that support the synchronous Ethernet clock feature.
l The first two optical interfaces support IEEE 1588 V2 clock
signals.
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Function and
Feature
PEG16
Maintenance
features
l Detects the fault at the physical layer of the board, the alarm
indicating that the connection at the network port is lost, the alarm
indicating that the interface fails, and the alarm indicating that the
bit errors at the interface cross the threshold.
l Supports the hot-swappable optical module and query of the
information about the optical module.
l Supports the alarm detection function and reports various alarms
and performance events, which facilitates the management and
maintenance of the equipment.
ETH-OAM function Supports the ETH-OAM function, which complies with IEEE
802.1ag, IEEE 802.3ah, and ITU-T Y.1731.
MPLS OAM
function
Supports the MPLS OAM function, which complies with ITU-T Y.
1711.
MSTP Supports the MSTP protocol, which is compatible with the STP
function and RSTP function.
LPT for packet
services
Supports P2P LPT and P2MP LPT for packet services.
IGMP snooping
function
The integrated equipment supports 4k multicast groups. One
multicast group supports a maximum of 24k members.
Number of supported
E-Line services
l When working with the N4GSCC: 4k
l When working with the N6GSCC: 8k
Number of supported
E-LAN services
1k
Number of supported
E-Aggr services
4, each of which supports 127 leaf ports
Number of MPLS
tunnels
Number of unidirectional/bidirectional MPLS tunnels (with the
tunnels shared):
4k
Number of
bidirectional static
PWs
16k
Number of QinQ
links
1k
Number of static
MAC addresses in E-
LAN services
2k
Number of VLANs 4094
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Function and
Feature
PEG16
Number of MPLS
tunnel APS
protection groups
l When working with the N4GSCC: 1k
l When working with the N6GSCC: 4k
Number of MPLS
tunnels that support
OAM
2k
MS-PW function l Supports static switching of MS-PWs.
l Supports continuity check for MS-PWs.

6.4.4 Working Principle and Signal Flow
The PEG16 consists of the network processing module, transmission management module,
switching network buffering module, CPU management module, clock module, and power
module.
Figure 6-12 shows the functional block diagram of the PEG16.
Figure 6-12 Functional block diagram of the PEG16
16xGE signals
GE signals
Interf ace board
PSXCSA
Clock module

CPU management
module
Ethernet communication bus
GSCC
Other boards
Backplane
Working clock
Power
module
- 48V/ - 60 V
Synchronous Ethernet
clock
System clock
Interf ace board
PSXCSA
Interf ace board
Service
signal
Service
signal
- 48V/ - 60 V
PSXCSA
PSXCSA
Data processing
module
Packet f orwarding
module
Network
processing module
IEEE 1588 V2 packet
Interf ace board
Service
signal
Upstream
transmission module
Downstream
transmission module
Transmission
management module
Upstream
scheduling module
Downstream
scheduling module
Switching network
buf f ering module
Parallel
management bus
Parallel management bus Parallel management bus
Inter-board communication bus
Modules of the board
Interf ace board/First two GE signals
Interf ace board/First two GE signals
Modules of the board
IEEE 1588 V2 packet
Two system clock
signals
Synchronous Ethernet
clock
IEEE 1588 V2 packet

Receive Direction
The network processing module accesses the signals sent from the GE interface on the front
panel or the interface board, decodes the signals, and converts the serial signals into parallel
signals. Then, the network processing module performs route searching or address matching for
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the data packets, and sends the corresponding packets to the transmission management module.
The transmission management module buffers and grooms the packets, slices the packets into
cells that the switching network requires, and sends the cells to the switching network buffering
module. The switching network buffering module buffers the cells and sends the cells to the
cross-connect unit.
Transmit Direction
The switching network buffering module processes the cells sent by the cross-connect unit and
sends the cells to the transmission management module. The transmission management module
rearranges the cells to form packets, performs buffering and QoS management for the packets,
and sends the packets to the network processing module. The network processing module
converts the parallel signals into serial signals, and sends the signals to the GE interface on the
front panel of the PEG16 or the corresponding interface board through the backplane.
Network Processing Module
The network processing module performs route searching, address matching, and other functions
for data packets. The network processing module of the PEG16 can process the 10 Gbit/s data
packets in full-duplex mode.
Transmission Management Module
The transmission management module slices packets into cells, and performs QoS management
and large volume buffering for the cells.
l QoS management: The transmission management module provides the scheduling function
at five levels including the flow queue and port queue, the bandwidth restricting function,
and the corresponding statistical information.
l Large volume buffering: The transmission management module supports the traffic of 10
Gbit/s.
Switching Network Buffering Module
The switching network buffering module performs cell buffering, queue management,
scheduling, and other functions. This module and the cross-connect unit form a three-level
switching network to switch cells.
CPU Management Module
The CPU management module provides the parallel management bus, Ethernet bus, and other
buses to manage the modules of the PEG16 and the interface board to which the PEG16
corresponds. The CPU management module also monitors alarms and performance events and
reports the alarms and performance events to the SCC unit.
Clock Module
The clock module performs the following functions:
l Provides the clock signal for each module of the PEG16.
l Supports the transparent transmission of the IEEE 1588 V2 packets from the interface board
or the first two channels of GE signals to the PSXCS.
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l Selects a clock source from the two system clocks sent from the PSXCS and sends the
selected clock to the interface board and the modules of the PEG16.
l Selects a clock source from the synchronous Ethernet clock signals accessed by the interface
board or the first two channels of GE signals and sends the selected clock to the PSXCS.
Power Module
The power module converts the accessed DC voltage into the DC voltages that the modules of
the PEG16 require.
6.4.5 Front Panel
The front panel of the PEG16 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 6-13 shows the appearance of the front panel of the PEG16.
Figure 6-13 Front panel of the PEG16
PEG16
PEG16
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
O
U
T
9
I
N
9
O
U
T
2
I
N
2
O
U
T
1
0
I
N
1
0
O
U
T
3
I
N
3
O
U
T
1
1
I
N
1
1
O
U
T
4
I
N
4
O
U
T
1
2
I
N
1
2
O
U
T
5
I
N
5
O
U
T
1
3
I
N
1
3
O
U
T
6
I
N
6
O
U
T
1
4
I
N
1
4
O
U
T
7
I
N
7
O
U
T
1
5
I
N
1
5
O
U
T
8
I
N
8
O
U
T
1
6
I
N
1
6
ACT
PROG
STAT
SRV
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Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22.2 Alarm Indicators on the Boards.
Interfaces
The front panel of the PEG16 has sixteen GE optical interface. Table 6-18 describes the types
and usage of the optical interfaces of the PEG16.
Table 6-18 Optical interfaces of the PEG16
Interface Type of Interface Usage
IN1IN16 LC (pluggable) Receives GE signals.
OUT1
OUT16
LC (pluggable) Transmits GE signals.

6.4.6 Jumpers and DIP Switches
The PEG16 does not have any jumpers or DIP switches that are used for board settings.
6.4.7 Valid Slots
The PEG16 occupies two slots and can be installed in any two adjacent slots among slots 16
and 1316. The PEG16 slot displayed on the T2000 is the slot that has a smaller slot number
between the two slots that house the PEG16. For example, if the PEG16 is installed in slots 1
and 2, the PEG16 slot displayed on the T2000 is slot 1.
When the PEG16 works with the interface board PETF8/PEFF8, one PEG16 board can work
with a maximum of two PETF8/PEFF8 boards. In this case, all the optical interfaces on the
PEG16 can be used. Table 6-19 lists the slots valid for the PEG16 and the corresponding slots
for the PETF8/PEFF8.
Table 6-19 Slots valid for the PEG16 and the corresponding slots for the PETF8/PEFF8
Slot Valid for the
PEG16
Corresponding Logical Slot Corresponding Slot for the
PETF8/PEFF8
Slots 1 and 2 Slot 1 -
Slots 3 and 4 Slot 3 Slots 21 and 22
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Slot Valid for the
PEG16
Corresponding Logical Slot Corresponding Slot for the
PETF8/PEFF8
Slots 5 and 6 Slot 5 Slots 25 and 26
Slots 13 and 14 Slot 13 Slots 29 and 30
Slots 15 and 16 Slot 15 Slots 33 and 34

6.4.8 Feature Code
The PEG16 does not have the feature code.
6.4.9 Parameter Settings
You can set parameters for the PEG16 by using the T2000.
Displayed Slots
The PEG16 occupies two slots in the subrack. The logical slot of the PEG16 displayed on the
T2000 is the slot that has a smaller slot number between the two slots that house the PEG16.
For the logical slots of the PEG16 displayed on the T2000, refer to Table 6-19.
Board Parameters
You can set the following principal parameter for the PEG16 by using the T2000:
l Ethernet interface
For more parameters and the description of the parameters, see 25.1 Packet Boards.
6.4.10 Technical Specifications
The technical specifications of the PEG16 include the Ethernet performance specifications, laser
safety class, parameters specified for optical interfaces, mechanical specifications, and power
consumption.
Parameters Specified for Optical Interfaces
Table 6-20 lists the parameters specified for the optical interfaces of the PEG16.
Table 6-20 Parameters specified for the optical interfaces of the PEG16
Parameter Value
Type of
interface
1000BASE-SX 1000BASE-LX 1000BASE-
VX
1000BASE-ZX
Transmission
distance (km)
0.5 10 40 80
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Parameter Value
Type of fiber Multi-mode LC Single-mode LC Single-mode
LC
Single-mode LC
Launched
optical power
range (dBm)
-9.5 to 0 -11 to -3 -5 to 0 -2 to 5
Operating
wavelength
range (nm)
770 to 860 1270 to 1355 1270 to 1355 1500 to 1580
Minimum
overload
(dBm)
0 -3 -3 -3
Receiver
sensitivity
(dBm)
-17 -19 -22 -22
Minimum
extinction ratio
(dB)
9 9 9 9

Table 6-21 lists the parameters specified for the GE colored optical interfaces of the PEG16.
Table 6-21 Parameters specified for the GE colored optical interfaces of the PEG16
Parameter Value
Nominal bit rate 1250000 kbit/s
Launched optical power range
(dBm)
0 to 5
Receiver sensitivity (dBm) -19
Minimum overload (dBm) -3
Maximum allowed dispersion
(ps/nm)
800
Minimum extinction ratio (dB) 9

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the PEG16 are as follows:
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l Dimensions (mm): 50.8 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 2.3
Power Consumption
The maximum power consumption of the PEG16 at room temperature (25C) is 137 W.
6.5 PETF8
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PETF8 (8xFE electrical interface board). This topic also describes
how to configure and commission the PETF8.
6.5.1 Version Description
The PETF8 is available in one functional version, namely, N1.
6.5.2 Application
The PETF8 is mainly used in the packet data transmission field to access data packets, manage
bandwidths, and realize switching of data packets.
6.5.3 Functions and Features
The PETF8 accesses 8xFE electrical signals and works with the PEG8/PEG16 to process
services.
6.5.4 Working Principle and Signal Flow
The PETF8 consists of the access and converging module, control and driving module, voltage
detecting module, clock module, and power module.
6.5.5 Front Panel
The front panel of the PETF8 has indicators, interfaces, a bar code, and a laser safety class label.
6.5.6 Jumpers and DIP Switches
The PETF8 does not have any jumpers or DIP switches that are used for board settings.
6.5.7 Valid Slots
The PETF8 must be installed in a valid slot on the subrack. Otherwise, the PETF8 fails to work
normally.
6.5.8 Feature Code
The PETF8 does not have the feature code.
6.5.9 Parameter Settings
You can set the parameters for the PETF8 by using the T2000.
6.5.10 Technical Specifications
The technical specifications of the PETF8 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
6.5.1 Version Description
The PETF8 is available in one functional version, namely, N1.
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6.5.2 Application
The PETF8 is mainly used in the packet data transmission field to access data packets, manage
bandwidths, and realize switching of data packets.
Figure 6-14 shows the typical networking and application of the PETF8. The PETF8 works with
the cross-connect board that provides the packet switching function to meet the requirement of
packet features. With this board, the TDM plane can be overlapped with the packet plane on the
OptiX OSN equipment to transmit data on the two planes. Thus, the equipment realizes the
smooth evolution from the MSTP network to the PTN network.
Figure 6-14 Networking and application of the PETF8
NE1
NE2 NE4
NE3
PSN
Traffic flow
PEG8/PEG16
PETF8
Cross-connect board on
the TDM and packet planes
User A2
User B2
User B1
User A1
T2000
PSN: Packet switched network

6.5.3 Functions and Features
The PETF8 accesses 8xFE electrical signals and works with the PEG8/PEG16 to process
services.
Table 6-22 provides the functions and features of the PETF8. When the PETF8 works with the
PEG8, 6.3.3 Functions and Features describes the functions and features of the PETF8; when
the PETF8 works with the PEG8, 6.4.3 Functions and Features describes the functions and
features of the PETF8.
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Table 6-22 Functions and features of the PETF8
Function and
Feature
PETF8
Basic functions Provides eight FE electrical interfaces, which are used to receive and
transmit 8xFE electrical signals.
Specifications of the
interface
Uses the RJ-45 connector and meets the specifications of the
100BASE-TX physical layer provided in IEEE 802.3.
Characteristics of the
interface
l Supports the configuration of the full-duplex mode or auto-
negotiation mode for the FE electrical port (in auto-negotiation
mode, only the 100 Mbit/s full-duplex working mode is supported).
l Supports the RMON performance measurement function.
l Supports the setting of the MTU for the Ethernet port.
Loopback function l Supports inloops at the PHY layer of the Ethernet port.
l Supports outloops at the MAC layer of the Ethernet port.
Format of service
frames
l Supports the encapsulation in IEEE 802.3 format, Ethernet II
format, or IEEE 802.1q/p format.
l Supports the Jumbo frame with a length not more than 9600 bytes.
Type of Ethernet
services
l Supports point-to-point E-Line services.
l Supports multipoint-to-multipoint E-LAN services.
l Supports multipoint-to-point E-Aggr services.
HQoS function Provides the hierarchical QoS function. The board provides the
scheduling function at multiple levels including the flow queue and
port queue, the bandwidth restricting function, and the corresponding
statistical information.
LAG The sum of the number of intra-board LAG groups and the number
of inter-board LAG groups must not exceed 16. Each LAG group
supports a maximum of 128 LAG members.
Clock function l Supports eight channels of synchronous Ethernet clocks.
l Supports eight channels of IEEE 1588 V2 clocks.
Protection schemes l Supports the MPLS Tunnel APS.
l Supports the LAG protection.
l Supports the MPLS PW APS.
l Supports the MC-LAG protection.
l Supports the DNI APS protection.
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Function and
Feature
PETF8
Maintenance
features
l Detects the fault at the physical layer of the board, the alarm
indicating that the connection at the network port is lost, the alarm
indicating that the interface fails, and the alarm indicating that the
bit errors at the interface cross the threshold.
l Supports the hot-swappable function.
l Supports the alarm detection function and reports various alarms
and performance events, which facilitates the management and
maintenance of the equipment.
l Supports the function of monitoring the voltage.

6.5.4 Working Principle and Signal Flow
The PETF8 consists of the access and converging module, control and driving module, voltage
detecting module, clock module, and power module.
Figure 6-15 shows the functional block diagram of the PETF8.
Figure 6-15 Functional block diagram of the PETF8
Access and
converging
module
GE
Management bus
GE service
Clock
module
Power
module
One system clock
Backplane
Working
clock signal
Modules of
the board
PEG16/PEG8
IEEE
1588 V2
signal
IEEE
1588 V2
signal
Fuse
Fuse
Modules of
the board
PEG16/PEG8
PEG16/PEG8
PEG16/PEG8
PEG16/PEG8
PEG16/PEG8
8xFE electrical
signals
Synchronous
clock
Working clock
signal
Control and
driving module
Voltage detecting
module
Voltage detecting
signal
Synchronous Ethernet clock
IEEE 1588 V2 packet
+3.3 V backup power

Upstream Direction
The services in the upstream direction are accessed by the FE ports. The service packets are
added with different VLAN tags according to the ingress ports. Then, the services are transmitted
to the GE port on the backplane side. As a result, the FE services are converged into the GE
services. After the PEG16 receives the packets, the PEG8/PEG16 identifies the ports to which
the services correspond according to the VLAN tags and strips the VLAN tags.
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Downstream Direction
The services in the downstream direction are added with VLAN tags on the PEG8/PEG16
according to the destination ports. Then, the services are accessed by the GE port on the
backplane side. The VLAN tags indicate the destination ports of the service packets. The service
packets are sent to the destination ports after the VLAN tags are stripped.
Access and Converging Module
The access and converging module performs the following functions:
l Accesses 8xFE electrical signals.
l Converges 8xFE services into 1xGE services on the backplane side.
l Extracts the IEEE 1588 V2 clock information.
Control and Driving Module
The control and driving module performs the following functions:
l Detects the system status through the management control bus.
Checks whether the board is properly inserted.
Detects the voltage of the PETF8.
l Realizes the hot-swappable function of the PETF8.
Voltage Detecting Module
The voltage detecting module monitors the voltage.
Clock Module
The clock module performs the following functions:
l Provides the working clock signal for each module of the PETF8.
l Supports the synchronous Ethernet clock.
l Supports the IEEE 1588 V2 clock.
Power Module
The power module converts the accessed DC voltage into the DC voltages that the modules of
the PETF8 require.
6.5.5 Front Panel
The front panel of the PETF8 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 6-16 shows the appearance of the front panel of the PETF8.
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Figure 6-16 Front panel of the PETF8
PETF8
PETF8
ACT
SRV
STAT
F
E
1
F
E
2
F
E
3
F
E
4
F
E
5
F
E
6
F
E
7
F
E
8

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Service alarm indicator (SRV) two colors (red and green)
l Connection status indicator (LINK) one color (green and located on the RJ-45 connector)
l Data receiving and transmission indicator (ACT) one color (orange and located on the
RJ-45 connector)
l
For the meanings of the status of the indicators, see 22.2 Alarm Indicators on the Boards.
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Interfaces
The front panel of the PETF8 has eight FE electrical interfaces. Table 6-23 describes the types
and usage of the electrical interfaces of the PETF8.
Table 6-23 Electrical interfaces of the PETF8
Interface Type of Interface Usage
FE1FE8 RJ-45 Transmits and receives FE signals.

6.5.6 Jumpers and DIP Switches
The PETF8 does not have any jumpers or DIP switches that are used for board settings.
6.5.7 Valid Slots
The PETF8 must be installed in a valid slot on the subrack. Otherwise, the PETF8 fails to work
normally.
The PETF8 can be installed in slots 1926, and 2936 in the subrack.
The PETF8 works as the interface board for the PEG8 and PEG16. For the slots valid for the
PEG8 and PEG16 and the corresponding slots for the PETF8, refer to Table 6-14 andTable
6-19.
6.5.8 Feature Code
The PETF8 does not have the feature code.
6.5.9 Parameter Settings
You can set the parameters for the PETF8 by using the T2000.
You can set the following parameters for the PETF8 by using the T2000:
l Ethernet interface
For more parameters the description of the parameters, see 25.1 Packet Boards.
6.5.10 Technical Specifications
The technical specifications of the PETF8 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
Table 6-24 lists the parameters specified for the electrical interfaces of the PETF8.
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Table 6-24 Parameters specified for the electrical interfaces of the PETF8
Parameter Value
Nominal bit rate 100 Mbit/s
Line code pattern MLT-3 encoding signal (100M)
Specifications of the
interface
Complies with IEEE 802.3u.

Mechanical Specifications
The mechanical specifications of the PETF8 are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
The maximum power consumption of the PETF8 at room temperature (25C) is 8 W.
6.6 PEFF8
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PEFF8 (8-port fast Ethernet optical interface processing board).
This topic also describes how to configure and commission the PEFF8.
6.6.1 Version Description
The PEFF8 is available in one functional version, namely, N1.
6.6.2 Application
The PEFF8 is mainly used in the packet data transmission field to access data packets, manage
bandwidths, and implement switching of data packets.
6.6.3 Functions and Features
The PEFF8 accesses 8xFE optical signals and works with the PEG8/PEG16 to process services.
6.6.4 Working Principle and Signal Flow
The PEFF8 consists of the access and converging module, control and driving module,
temperature and voltage detecting module, clock module, and power module.
6.6.5 Front Panel
The front panel of the PEFF8 has indicators, interfaces, a bar code, and a laser safety class label.
6.6.6 Valid Slots
The PEFF8 must be installed in a valid slot on the subrack. Otherwise, the PEFF8 fails to work
normally.
6.6.7 Feature Code
The PEFF8 does not have the feature code.
6.6.8 Parameter Settings
You can set the parameters for the PEFF8 by using the T2000.
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6.6.9 Technical Specifications
The technical specifications of the PEFF8 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
6.6.1 Version Description
The PEFF8 is available in one functional version, namely, N1.
6.6.2 Application
The PEFF8 is mainly used in the packet data transmission field to access data packets, manage
bandwidths, and implement switching of data packets.
Figure 6-17 shows the typical networking and application of the PEFF8. The PEFF8 works with
the cross-connect board that provides the packet switching function to meet the requirement of
packet features. With this board, the TDM can be overlapped with the packet plane on the OptiX
OSN equipment so that the data can be transmitted on two planes. In this manner, an MSTP
network can smoothly evolve to a PTN network.
Figure 6-17 Networking and application of the PEFF8
NE1
NE2 NE4
NE3
PSN
Service flow
PEG8
PEFF8
TDM/Packet dual-plane
cross-connect board
User A2
User B2
User B1
User A1
T2000
PSN: Packet switched network

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NOTE
The PEFF8 can work with the service processing board PEG8 or PEG16.
6.6.3 Functions and Features
The PEFF8 accesses 8xFE optical signals and works with the PEG8/PEG16 to process services.
Table 6-25 lists the functions and features of the PEFF8. When working with the PEG8, the
PEFF8 supports the functions and features as described in 6.3.3 Functions and Features.When
working with the PEG16, the PEFF8 supports the functions and features as described in 6.4.3
Functions and Features.
Table 6-25 Functions and features of the PEFF8
Function and
Feature
PEFF8
Basic functions Provides eight FE optical interfaces, which are used to receive and
transmit 8xFE optical signals.
Specifications of the
interface
Supports the 100Base-FX Ethernet optical interfaces. The optical
interface uses the LC connector and supports the transmission
distances of 2 km, 15 km, 40 km, and 80 km.
Characteristics of the
interface
l Supports two working modes of Ethernet interfaces, namely, full
duplex and auto-negotiation. The Ethernet interface can be
automatically negotiated into the 100M full duplex working mode
only.
l Supports the setting of the MTU for the Ethernet port.
l Supports the setting of the following parameters for the port:
number of received packets, number of transmitted packets,
loopback mode, state, and query of the type of optical interface.
l Supports the measurement based on the RMON function.
l Supports the setting and query of the optical power threshold.
Loopback function l Supports inloops at the PHY layer of the Ethernet port.
l Supports outloops at the MAC layer of the Ethernet port.
Format of service
frames
l Supports the encapsulation in IEEE 802.3 format, Ethernet II
format, or IEEE 802.1q/p format.
l Supports the jumbo frame with a length not more than 9600 bytes.
Type of Ethernet
services
l Supports point-to-point E-Line services.
l Supports multipoint-to-multipoint E-LAN services.
l Supports multipoint-to-point E-Aggr services.
HQoS Provides the HQoS function, including the scheduling function at
multiple levels for the flow queue and port queue and the bandwidth
restricting function, and provides the corresponding statistical
information.
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Function and
Feature
PEFF8
LAG The number of intra-board/inter-board LAG groups must not exceed
128. Each LAG group supports a maximum of 16 LAG members.
Protection Scheme l Supports MPLS Tunnel APS
l Supports LAG protection.
l Supports MPLS PW APS.
l Supports MC-LAG protection.
l Supports DNI APS.
Clock function l Supports eight channels of synchronous Ethernet clocks and the
extraction of the clock from the physical layer of the port. The
quality of the clock meets the requirement of the clock source.
l Supports eight channels of IEEE 1588 V2 clocks.
Maintenance
features
l Detects the fault at the physical layer of the board, the alarm
reporting that the connection at the network port is lost, the alarm
reporting that the interface fails, and the alarm reporting that the
bit errors at the interface crosses the threshold.
l Supports the hot-pluggable optical module and query of the
information about the optical module.
l Supports the alarm detection function and reports various alarms
and performance events, which facilitates the management and
maintenance of the equipment.

6.6.4 Working Principle and Signal Flow
The PEFF8 consists of the access and converging module, control and driving module,
temperature and voltage detecting module, clock module, and power module.
Figure 6-18 shows the functional block diagram of the PEFF8.
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Figure 6-18 Functional block diagram of the PEFF8
Access and
converging
module
8xFE optical
signals
GE
Control and
driving module
Management bus
GE service
Clock
module
Power
module
One channel of system clock
Synchronous Ethernet clock
IEEE 1588 V2 packet
Backplane
Working clock signal
Each module
of board
PEG8
Working clock
signal
Synchronous
clock
IEEE1588v2 signal
IEEE
1588v2
signal
Fuse
Fuse
Each module of board
+3.3 V backup power
Voltage
detecting module
Voltage detecting signal
PEG8
PEG8
PEG8
PEG8
PEG8

NOTE
The PEFF8 can work with the service processing board PEG8 or PEG16.
Upstream direction
The services in the upstream direction are accessed by the FE ports. The service packets are
added with different VLAN tags based on the ingress ports. Then, the services are transmitted
to the GE port on the backplane side. As a result, the FE services are converged into the GE
services. After receiving the packets, the PEG8/PEG16 identifies the ports to which the services
correspond based on the VLAN tags and strips the VLAN tags.
Downstream direction
The services in the downstream direction are added with VLAN tags on the PEG8/PEG16 based
on the destination ports. Then, the services are accessed by the GE port on the backplane side.
The destination ports of the service packets are determined based on the VLAN tags. After the
destination ports of the service packets are determined, the VLAN tags are striped and the
services are sent to the destination ports.
Access and Converging Module
The access and converging module performs the following functions:
l Accesses 8xFE optical signals.
l Converges 8xFE services into 1xGE services on the backplane side.
l Extracts IEEE 1588 V2 clock information.
Control and Driving Module
The control and driving module performs the following functions:
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l Detects the system status through the management control bus.
Checks whether the board is properly inserted.
Tests the voltage status.
l Implements the hot-pluggable function of the PEFF8.
Voltage Test Module
The voltage test module mainly provides the voltage monitoring function.
Clock Module
The clock module performs the following functions:
l Provides the working clock signal for each module of the PEFF8.
l Supports the synchronous Ethernet clock.
l Supports the IEEE 1588 V2 clock.
Power Module
The power module converts the accessed DC voltage into the DC voltages that the modules of
the board require.
6.6.5 Front Panel
The front panel of the PEFF8 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 6-19 shows the appearance of the front panel of the PEFF8.
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Figure 6-19 Front panel of the PEFF8
PEFF8
PEFF8
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4
O
U
T
5
I
N
5
O
U
T
6
I
N
6
O
U
T
7
I
N
7
O
U
T
8
I
N
8
CLASS 1
LASER
PRODUCT
L/A 1
ACT
STAT
SRV
L/A 2
L/A 3
L/A 4
L/A 5
L/A 6
L/A 7
L/A 8

Indicators
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Service alarm indicator (SRV) two colors (red and green)
l Connection status indicator (L/A1-L/A8) two colors (yellow and green)
For the meanings of the status of the indicators, see 22.2 Alarm Indicators on the Boards.
Interfaces
The front panel of the PEFF8 has eight FE optical interfaces. Table 6-26 describes the interfaces
of the PEFF8.
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Table 6-26 Interfaces of the PEFF8
Interface Type of Interface Usage
IN1-IN8 LC (pluggable) Receives FE signals.
OUT1-
OUT8
LC (pluggable) Transmits FE signals.

6.6.6 Valid Slots
The PEFF8 must be installed in a valid slot on the subrack. Otherwise, the PEFF8 fails to work
normally.
The PEFF8 can be installed in slots 1926, and 2936 in the subrack.
The PEFF8 works as the interface board of the PEG8/PEG16. For the slots valid for the PEG8/
PEG16, see Table 6-19 and Table 6-14.
6.6.7 Feature Code
The PEFF8 does not have the feature code.
6.6.8 Parameter Settings
You can set the parameters for the PEFF8 by using the T2000.
You can set the following parameters for the PEFF8 by using the T2000.
l Ethernet interface
For information about more parameters and the description of each parameter, see 25.1 Packet
Boards.
6.6.9 Technical Specifications
The technical specifications of the PEFF8 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Specifications Specified for Optical Interfaces
Table 6-27 provides the specifications of the optical interfaces on the PEFF8.
Table 6-27 Specifications of the electrical interfaces
Item Value
Type of
interface
100BASE-FX 100BASE-
FX
100BASE-FX 100BASE-FX
Transmission
distance (km)
80 40 15 2
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Item Value
Type of fiber Single-mode
LC
Single-mode
LC
Single-mode LC Multi-mode LC
Launched
optical power
range (dBm)
-5 to 0 -5 to 0 -15 to -8 -19 to -14
Operating
wavelength
range (nm)
1263 to 1360 1480 to 1580 1261 to 1360 1270 to 1380
Minimum
overload
(dBm)
-10 -10 -7 -14
Receiver
sensitivity
(dBm)
-34 -34 -28 -30
Minimum
extinction ratio
(dB)
10 10 10 10

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the PEFF8 are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight: 0.5 kg
Power Consumption
The maximum power consumption of the PEFF8 at room temperature (25C) is 14 W.
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7 Dual-Plane Bridging Boards
About This Chapter
OptiX The OptiX OSN equipment supports the dual-plane bridging board EDQ41, which bridges
Ethernet services between the TDM plane and packet plane.
7.1 EDQ41
This topic describes the version, application, functions, working principle, front panel, valid
slots, and technical specifications of the EDQ41 (4-port 622/155 Mbit/s SDH optical interface
Ethernet double plane multiple function processing board).
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7-1
7.1 EDQ41
This topic describes the version, application, functions, working principle, front panel, valid
slots, and technical specifications of the EDQ41 (4-port 622/155 Mbit/s SDH optical interface
Ethernet double plane multiple function processing board).
7.1.1 Version Description
The EDQ41 is available in one functional version, namely, N1.
7.1.2 Application
The EDQ41 is mainly used for interoperation between the SDH network and the packet network.
The board converges the TDM signals and Ethernet packets from the SDH access network and
deconverges the TDM signals to the SDH ring and the Ethernet packets to the packet ring. In
this manner, the board achieves the interoperation between the TDM plane and the packet plane,
facilitating the smooth evolution of the network.
7.1.3 Functions and Features
The EDQ41 processes 4x155 Mbit/s or 4x622 Mbit/s SDH services and 2.5 Gbit/s EoS services
at the same time.
7.1.4 Working Principle and Signal Flow
The EDQ41 consists of network processing module, mapping module, clock module, logic
control module, O/E converting module, SDH overhead processing module, and power module.
7.1.5 Front Panel
The front panel of the EDQ41 has indicators, interfaces, a bar code, and a laser safety class label.
7.1.6 Jumpers and DIP Switches
The EDQ41 does not have any jumpers or DIP switches for board settings.
7.1.7 Valid Slots
The EDQ41 must be installed in a valid slot in the subrack. Otherwise, the EDQ41 fails to work
normally.
7.1.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the EDQ41.
The feature code of the EDQ41 indicates the type of optical interface.
7.1.9 Parameter Settings
You can set the parameters for the EDQ41 by using the T2000.
7.1.10 Technical Specifications
The technical specifications of the EDQ41 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
7.1.1 Version Description
The EDQ41 is available in one functional version, namely, N1.
7.1.2 Application
The EDQ41 is mainly used for interoperation between the SDH network and the packet network.
The board converges the TDM signals and Ethernet packets from the SDH access network and
deconverges the TDM signals to the SDH ring and the Ethernet packets to the packet ring. In
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this manner, the board achieves the interoperation between the TDM plane and the packet plane,
facilitating the smooth evolution of the network.
Figure 7-1 shows the typical networking and application of the EDQ41. The four signal flows
in this figure indicate four typical applications.
l Application 1: The EDQ41 accesses services from the STM-1/STM-4 EoS ring to the PSN
GE/10GE ring.
l Application 2: The EDQ41 accesses the services from line boards to the PSN GE/10GE
ring.
l Application 3: The EDQ41 accesses the services from the GE/10GE packet network to the
STM-1/STM-4 EoS ring through line boards.
l Application 4: The EDQ41 accesses the services from line boards to the PSN GE/10GE
ring or to the STM-1/STM-4 EoS ring.
Figure 7-1 Networking and application of the EDQ41
10GE Ring
STM-16/STM-64 Ring
STM-1/STM-4 Ring
E1
FE
FE
BSC
RNC
GE Ring
Packet
core
TDM
Core
Packet
board
EDQ41
Borad
GE/10GE
Ring
STM-1/
STM-4 Ring
STM-N
Packet
core
TDM
Core
Packet
board
SDH
Board
EDQ41
Borad
GE/10GE
Ring
STM-N
TDM
Core
SDH
Board
EDQ41
Borad
GE/10GE
Ring
GE/10GE
Ring
Packet
core
TDM
Core
Packet
board
SDH
Board
EDQ41
Borad
Signal flow 1:
Signal flow 2:
Signal flow 3: Signal flow 4:
Packet
core
Packet
board
STM-1/
STM-4 Ring
STM-N
TDM plane networking Packet plane networking

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7.1.3 Functions and Features
The EDQ41 processes 4x155 Mbit/s or 4x622 Mbit/s SDH services and 2.5 Gbit/s EoS services
at the same time.
Table 7-1, Table 7-2, and Table 7-3 provide the functions and features of the EDQ41.
Table 7-1 Functions and features of the EDQ41
Function and
Feature
Description
Basic functions Transmits and receives 4xSTM-1/STM-4 optical signals.
Specifications of the
interface
l The STM-1 or STM-4 optical module can be used.
l When the STM-1 optical module is used, the standard S-1.1, L-1.1,
and L-1.2 optical interfaces are supported. The optical interfaces
comply with ITU-T G.957.
l When the STM-4 optical module is used, the standard S-4.1, L-4.1,
L-4.2, and Ve-4.2 optical interfaces are supported. The optical
interfaces of the S-4.1, L-4.1, and L-4.2 types comply with ITU-T
G.957. The optical interface of the Ve-4.2 type complies with the
standards defined by Huawei.
Specifications of
optical modules
l Supports the detection and query of the information about optical
modules.
l Supports the usage and detection of SFP pluggable optical
modules, facilitating the maintenance of optical modules.
l Provides the ALS function. The optical interface supports the
function of setting the on/off state of a laser.
Service processing Supports VC-12/VC-3/VC-4 services when the STM-1 or STM-4
optical module is used.
Overhead processing l Processes the section overheads of STM-4/STM-1 signals.
l Processes path overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports the ECC communication.
Loopback function l Supports inloops and outloops at optical interfaces.
l Supports inloops and outloops at the VC-4 level.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
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Function and
Feature
Description
Protection scheme l Supports two-fiber ring MSP.
l Supports four-fiber ring MSP.
l Supports linear MSP.
l Supports SNCP.
l Supports SNCMP.
l Supports SNCTP.
l Supports fiber-shared virtual trail protection.
l Supports optical-path-shared MSP. Each optical interface can
process four sets of K bytes. One EDQ41 can support a maximum
of four MSP rings.
Maintenance
features
l Supports the warm reset and cold reset. A warm reset does not
affect services.
l Supports the alarm detection function and reports various alarms
and performance events, which facilitates the management and
maintenance of the equipment.

Table 7-2 Data features of the EDQ41
Function and
Feature
Description
Basic functions Bridges a maximum of 2.5 Gbit/s EoS services to the packet plane.
Format of service
frames
l Provides the Layer 2 forwarding function and supports the
encapsulation in IEEE 802.3 format, Ethernet II format, or IEEE
802.1q/p format.
l Supports the jumbo frame with a length not more than 9600 bytes.
Maximum uplink
bandwidth
2.5 Gbit/s
Type of Ethernet
services
l Supports point-to-point E-Line services.
l Supports multipoint-to-multipoint E-LAN services.
l Supports multipoint-to-point E-Aggr services.
LCAS Dynamically increases or decreases the bandwidth and protects the
bandwidth in compliance with ITU-T G.7042.
HQoS Provides complete QoS policies, supports the classification of VLAN
packets and MPLS packets and the scheduling of queues with four
priorities.
LAG Supports a maximum of 128 inter-board and intra-board LAGs. Each
LAG supports a maximum of 16 members.
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Function and
Feature
Description
Protection scheme Supports the manual setting of LAG protection.
Test frames Receives and transmits GFP and MAC test frames.
Maintenance
features
l Supports the performance statistics and report of VCTRUNKs.
l Supports the query and report of alarms.
ETH-OAM Supports the ETH-OAM function. The ETH-OAM function complies
with IEEE 802.1ag.
MSTP Supports MSTP, STP, and RSTP.
IGMP Snooping Supports a maximum of 4k multicast groups, with 24k members
supported by each multicast group.
Number of supported
E-Line services
l When working with the N4GSCC: 4k
l When working with the N6GSCC: 6k
Number of supported
E-LAN services
1k
Number of supported
E-Aggr services
4

Table 7-3 EoS data features of the EDQ41
Function and
Feature
EDQ41
Encapsulation
format
Supports the GFP-F and LAPS protocols.
Number of
VCTRUNKs
Binds a maximum of 63 VCTRUNKs, equivalent to 504 VC-12s, 48
VC-3s, or 16 VC-4s.
Configuration features:
l VC-12 paths can be bound to the 5th to 8th and the 13th to 16th
VC-4s.
l VC-3 and VC-4 signals can be bound to any of the 1st to 16th
VC-4s.
l VCTRUNK1 to VCTRUNK63 can be bound to any of the 1st to
16th VC-4s.
l A VC-4 cannot be bound with VC-3 and VC-12 paths at the same
time.
Test frames Supports the transmitting and receiving of GFP test frames.

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7.1.4 Working Principle and Signal Flow
The EDQ41 consists of network processing module, mapping module, clock module, logic
control module, O/E converting module, SDH overhead processing module, and power module.
Figure 7-2 shows the functional block diagram of the EDQ41.
Figure 7-2 Functional block diagram of the EDQ41
Mapping
module
Reference clock and
frame header unit
Communication unit
Logic control
module
SCC
+3.3 V
Power
module
Fuse
-48V/-60V
SDH cross-
connect unit
Power
module
SCC
Backplane
Packet cross-
connect unit
SDH
overhead
processing
module
Clock
module
4xSTM-1/
STM-4
-48V/-60V
SDH cross-
connect unit
Network
processing
module
O
/
E
c
o
n
v
e
r
t
i
n
g
m
o
d
u
l
e

Services on the SDH Plane
l In the transmit direction: The O/E converting module converts the received STM-1/STM-4
optical signals into electrical signals and sends the electrical signals to the SDH overhead
processing module. Then, the SDH overhead processing module extracts and processes the
overheads, converts the signals into a format that applies to the backplane bus, and then
sends the signals to the SDH cross-connect unit.
l In the receive direction: The SDH overhead processing module inserts overhead bytes into
the electrical signals from the SDH cross-connect unit, and sends the electrical signals to
the E/O converting module. The E/O converting module converts the STM-1/STM-4
electrical signals into optical signals, and then sends the optical signal to fibers for
transmission.
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Services Transmitted from the SDH Plane to the Packet Plane
The mapping module demaps the signals from the SDH cross-connect module and compensates
the delay of virtual concatenation. The mapping module decapsulates the packets through
alignment and sends the data to the network processing module. The network processing module
processes the data according to service types and configuration requirements, and then sends
Ethernet services to the packet cross-connect unit.
Services Transmitted from the Packet Plane to the SDH Plane
The network processing module processes the Ethernet services from the packet cross-connect
unit, and then sends the services to the mapping module. The mapping module encapsulates the
Ethernet services in LAPS or GFP format and concatenates the services. Then, the mapping unit
converts the Ethernet services into STM-16 signals and sends the signals to the SDH cross-
connect unit.
Network Processing Module
The network processing module performs the functions at the MAC layer, including code
conversion, Ethernet packet framing, CRC check, and Ethernet performance statistics. In
addition, the network processing module classifies the services according to service types and
configuration requirements. Then, the module encapsulates or decapsulates frames. The module
supports the Ethernet/VLAN encapsulation formats.
The module supports the following functions:
l Traffic detection and traffic classification
l Unicast, multicast, and broadcast of flows
l Priorities of data
l Weighted fair queuing (WFQ) scheduling
l Three service classes
Mapping Module
The mapping module performs encapsulation and mapping functions.
l In the upstream direction, the mapping module encapsulates Ethernet signals in LAPS,
GFP-F, or HDLC format and then performs concatenation. The module supports LCAS.
Then, the mapping module converts Ethernet signals into SDH signals.
l In the downstream direction, the mapping module demaps SDH signals and compensates
the delay of virtual concatenation. The mapping module decapsulates packets accordingly
through the alignment operation. The decapsulated data is finally transmitted to the network
processing module.
Logic Control Module
The logic control module is connected to external circuits through the bus. The logic control
module performs the following functions:
l Manages and configures the other modules on the local board.
l Implements inter-board communication through the internal Ethernet interface.
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O/E Converting Module
l In the receive direction, the O/E converting unit converts the received optical signals into
electrical signals.
l In the transmit direction, the O/E converting unit converts the received electrical signals
into SDH optical signals and transmits the optical signals to optical fibers.
l This module also detects the R_LOS alarm and provides the ALS function.
SDH Overhead Processing Module
The SDH overhead processing module includes the RST, MST, MSA, and HPT sub-modules.
This module provides the inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module terminates the RSOH. That is, the RST
sub-module detects the frame alignment bytes (A1 and A2), descrambles all the bytes
except the first row of the RSOH, restores and checks the J0 byte, and checks the B1
byte.
In the transmit direction, the RST sub-module generates the RSOH. That is, the RST
sub-module writes bytes such as A1, A2, and J0, calculates and writes the B1 byte, and
scrambles all the bytes except the first row of the RSOH.
l MST sub-module
In the receive direction, the MST sub-module terminates the MSOH. That is, the MST
sub-module generates the MS_AIS or MS_RDI alarm after detecting the K2 byte. In
addition, the sub-module generates the B2_SD or B2_EXC alarm after checking the B2
byte and sends the MS_REI alarm to the opposite end.
In the transmit direction, the MST sub-module generates the MSOH. That is, the MST
sub-module writes bytes such as E2, D4-D12, K1, K2, S1, and M1, and calculates and
writes the B2 byte.
l MSA sub-module
In the receive direction, the MSA sub-module de-interleaves AUGs, divides an AUG
into N AU-4s, detects the AU_LOP and AU_AIS alarms, and performs pointer
justifications.
In the transmit direction, the MSA sub-module adds the AU-PTR to a VC-4 to generate
an AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
l HPT sub-module
In the receive direction, the HPT sub-module terminates the POH. That is, the HPT sub-
module sends the HP_REI alarm to the opposite end after detecting byte B3. In addition,
the sub-module generates the HP_TIM and HP_SLM alarms, and sends the HP_RDI
alarm to the opposite end after detecting bytes J1 and C2 (the sub-module also generates
the HP_UNEQ alarm if it detects the VC-4 path unequipped).
In the transmit direction, the HPT sub-module generates the POH. That is, the HPT sub-
module writes bytes such as J1 and C2, and calculates and writes the B3 byte.
Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip.
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Power Module
The power module converts the accessed DC voltage into the DC voltages that the modules of
the board require.
7.1.5 Front Panel
The front panel of the EDQ41 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 7-3 shows the front panel of the EDQ41.
Figure 7-3 Front panel of the EDQ41
EDQ41
EDQ41
CLASS 1
LASER
PRODUCT
ACT
PROG
STAT
SRV
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4

Indicators
l Board hardware status indicator (STAT) two colors (red and green)
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l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the indicators, see 22.2 Alarm Indicators on the Boards.
Interfaces
The front panel of the EDQ41 has four optical interfaces. Table 7-4 lists the types and usage of
the optical interfaces of the EDQ41.
Table 7-4 Interfaces of the EDQ41
Interface Type of Interface Usage
IN1-IN4 LC (pluggable) Receives the STM-1/STM-4 optical signals.
OUT1-
OUT4
LC (pluggable) Transmits the STM-1/STM-4 optical signals.

7.1.6 Jumpers and DIP Switches
The EDQ41 does not have any jumpers or DIP switches for board settings.
7.1.7 Valid Slots
The EDQ41 must be installed in a valid slot in the subrack. Otherwise, the EDQ41 fails to work
normally.
EDQ41 can be housed in any of slots 4-8 and slots 11-14. The bandwidth of SDH services in all
slots is 2.5 Gbit/s, and the bandwidth of packet services in all slots is 2.5 Gbit/s.
7.1.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the EDQ41.
The feature code of the EDQ41 indicates the type of optical interface.
Table 7-5 provides the relationship between the feature code of the EDQ41 and types of optical
interfaces.
Table 7-5 Relationship between the feature code of the EDQ41 and types of optical interfaces
Board Feature Code Type of Optical Interface




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7.1.9 Parameter Settings
You can set the parameters for the EDQ41 by using the T2000.
You can set the following parameters for the EDQ41 by using the T2000:
SDH Parameters
l J0
l J1
l J2
l C2
For the description of parameters, see 25 Parameter Settings.
Ethernet Parameters
You can set the following parameters for the EDQ41 by using the T2000:
l VCTRUNK interfaces
For information about more parameters and the description of each parameter, see 25.1 Packet
Boards.
7.1.10 Technical Specifications
The technical specifications of the EDQ41 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Specifications of Optical Interfaces
The EDQ41 supports the STM-1/STM-4 optical modules.
Table 7-6 provides the specifications of STM-1 optical interfaces on the EDQ41.
Table 7-6 Specifications of the optical interfaces on the EDQ41
Item Value
Nominal bit
rate
155520 kbit/s
Line code NRZ
Type of
optical
interface
S-1.1 L-1.1 L-1.2 Ve-1.2
Type of Fiber Single-mode LC Single-mode LC Single-mode LC Single-mode LC
Transmission
distance (km)
2 to 15 20 to 40 60 to 80 80 to 100
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Item Value
Operating
wavelength
range (nm)
1261 to 1360 1263 to 1360 1480 to 1580 1480 to 1580
Launched
optical power
range (dBm)
-15 to -8 -5 to 0 -5 to 0 -3 to 0
Receiver
sensitivity
(dBm)
-28 -34 -34 -34
Minimum
overload
(dBm)
-8 -10 -10 -10
Minimum
extinction
ratio (dB)
8.2 10 10 10

Table 7-7 provides the specifications specified for STM-4 optical interfaces on the EDQ41.
Table 7-7 Specifications of STM-4 optical interfaces on the EDQ41
Item Value
Nominal bit rate 622080 kbit/s
Line code NRZ
Type of optical
interface
S-4.1 L-4.1 L-4.2 Ve-4.2
Transmission
distance (km)
2 to 15 20 to 40 50 to 80 80 to 100
Operating wavelength
range (nm)
1274 to 1356 1280 to 1335 1480 to 1580 1480 to 1580
Type of fiber Single-mode
LC
Single-mode
LC
Single-mode
LC
Single-mode
LC
Launched optical
power range (dBm)
-15 to -8 -3 to -2 -3 to -2 -3 to -2
Receiver sensitivity
(dBm)
-28 -28 -28 -34
Minimum Overload
(dBm)
-8 -8 -8 -13
Minimum extinction
ratio (dB)
8.2 10 10 10.5
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Mechanical Specifications
The mechanical specifications of the EDQ41 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight: 1.2 kg
Power Consumption
The maximum power consumption of the EDQ41 at room temperature (25C) is 75 W.
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8 CES Boards
About This Chapter
CES boards include CES service processing boards.
8.1 CQ1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the CQ1 (4-channel channelized STM-1 CES optical interface board).
8.2 MD12
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the MD12 (multi-protocol 32-channels E1 interface processing
board). This topic also describes how to configure and commission the MD12.
8.3 MD75
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the MD75 (multi-protocol 32-channels E1 interface processing
board). This topic also describes how to configure and commission the MD75.
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8-1
8.1 CQ1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the CQ1 (4-channel channelized STM-1 CES optical interface board).
8.1.1 Version Description
The CQ1 is available in one functional version, namely, N1.
8.1.2 Application
The CQ1 directly accesses channelized STM-1 services from the TDM plane, transmits the
channelized STM-1 services on the packet ring, and directly separates the channelized STM-1
services from other services on the Base Station Controller (BSC) side. In this manner, the
smooth evolution from the TDM plane to the packet plane is implemented.
8.1.3 Functions and Features
The CQ1 accesses four-port channelized STM-1 services, and works with the PEG8 to process
service signals. The CQ1 supports the CES protocol.
8.1.4 Working Principle and Signal Flow
The CQ1 consists of the line processing module, CES service processing module, management
module, clock module, and power module.
8.1.5 Front Panel
The front panel of the CQ1 has indicators, interfaces, a bar code, and a laser safety class label.
8.1.6 Jumpers and DIP Switches
The CQ1 does not have any jumpers or DIP switches that are used for board settings.
8.1.7 Valid Slots
The CQ1 must be installed in a valid slot on the subrack. Otherwise, the CQ1 fails to work
normally.
8.1.8 Feature Code
The CQ1 does not have any feature code.
8.1.9 Parameter Settings
You can set the parameters for the CQ1 by using the T2000.
8.1.10 Technical Specifications
The technical specifications of the CQ1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
8.1.1 Version Description
The CQ1 is available in one functional version, namely, N1.
8.1.2 Application
The CQ1 directly accesses channelized STM-1 services from the TDM plane, transmits the
channelized STM-1 services on the packet ring, and directly separates the channelized STM-1
services from other services on the Base Station Controller (BSC) side. In this manner, the
smooth evolution from the TDM plane to the packet plane is implemented.
Figure 8-1 shows the application of the CQ1. The CQ1 works with the PEG8 to transmit
channelized STM-1 services on the packet ring.
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Figure 8-1 Networking and application of the CQ1
Service flow
TDM/Packet dual-plane
cross-connect board
NMS
RNC BSC
GE STM-1
BTS
NodeB
NodeB
BTS
STM-1/
STM-4
Ring
STM-1/
STM-4
Ring
10GE Ring
STM-1
Ring
GE Ring
Packet ring
TDM ring
FE
E1
FE
E1
CQ1
PEG8 P
E
G
8
P
E
G
8
CQ1
PEG8
P
E
G
8
P
E
G
8
8.1.3 Functions and Features
The CQ1 accesses four-port channelized STM-1 services, and works with the PEG8 to process
service signals. The CQ1 supports the CES protocol.
Table 8-1 provides the functions and features of the CQ1.
Table 8-1 Functions and features of the CQ1
Function and
Feature
CQ1
Basic functions Transmits and receives four-port channelized STM-1 optical signals.
Functions of the
interface
ALS Supported
Loopback types of the port Inloop
Outloop
Auto disabling of port loopback Supported
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Function and
Feature
CQ1
CES Supported CES services 252
Supported emulation mode CESoPSN
SAToP
Supports the timeslot compression function. In the case of the CES
service in CESoPSN mode, the CQ1 compresses idle timeslots to
improve the bandwidth utilization on the NNI side.
Supported clock mode Adaptive clock mode, retiming
clock mode, and loopback clock
mode.
The jitter buffer time of CES services can be set to a value in the range
of 0.125 ms to 16 ms with a step of 0.125 ms.
The encapsulation buffer time of CES services can be set to a value in
the range of 0.125 ms to 5 ms with a step of 0.125 ms.
Bit error test
function
Supports the function of testing bit errors, and reports alarms in the case
of bit errors within a certain period.
LMSP Supports the LMSP 1+1 protection.
SSM protocol Supported
PRBS Supported

8.1.4 Working Principle and Signal Flow
The CQ1 consists of the line processing module, CES service processing module, management
module, clock module, and power module.
Figure 8-2 shows the functional block diagram of the CQ1.
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Figure 8-2 Functional block diagram of the CQ1
Line
processing
module
CES service
processing
module
Service signal
Service
signal
PEG8
Management
module
Management bus
Management bus
PEG8
Clock
module
Power
module +3.3 V backup
power supply
Management bus
4-port channelized
STM-1 signals
.
.
.
3.3 V
1.2 V
Backplane
Line clock
System clock
.
.
.
PEG8
Line clock
PEG8

Receive Direction
In the receive direction, the line processing module accesses four-channel channelized STM-1
services through the interfaces on the front panel of the CQ1 board. The line processing module
demultiplexes STM-1 signals into VC-12 signals, and demaps the VC-12 signals into E1 signals.
Then, the line processing module processes the overhead bytes, pointers, and alarm signals, and
sends the E1 signals to the CES service processing module. Then, the CES service processing
module rearranges the E1 frames, processes the rearranged signals based on the service type,
and performs PWE3 encapsulation and PW scheduling. Finally, the CES service processing
module sends the processed signals to the PEG8 through the interface on the backplane.
Transmit Direction
In the transmit direction, the CES service processing module receives service signals from the
PEG8, identifies the service type, and performs PWE3 decapsulation and queue scheduling.
Then, the CES service processing module sends the processed signals to the line processing
module. The line processing module maps the E1 service signals into VC-12 signals, and
multiplexes the VC-12 signals into STM-1 signals. Then, the line processing module processes
the overhead bytes, pointers, and alarm signals, and sends out the STM-1 signals through the
interface on the front panel of the CQ1.
Line Processing Module
The line processing module performs the following functions.
l In the receive direction, the line processing module accesses four-port channelized STM-1
services, demultiplexes STM-1 signals into VC-12 signals, and demaps the VC-12 signals
into E1 signals. Then, the line processing module processes the overhead bytes, pointers,
and alarm signals.
l In the transmit direction, the line processing module receives E1 signals from the PEG8,
maps the E1 service signals into VC-12 signals, and multiplexes the VC-12 signals into
STM-1 signals. Then, the line processing module processes the overhead bytes, pointers,
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and alarm signals, and sends out the STM-1 signals through the interface on the front panel
of the CQ1.
l In the case of a service fault, the line processing module implements the LMSP, and
performs service switching.
l The line processing module extracts and restores line clock signals.
CES Service processing module
The CES service processing module performs the following functions.
l In the receive direction, the CES service processing module receives signals from the line
processing module, rearranges the E1 frames, and processes the signals (for example,
compresses timeslots for the CES service). Then, the CES service processing module
performs PWE3 encapsulation and PW scheduling, and sends the processed signals to the
PEG8 through the interface on the backplane.
l In the transmit direction, the CES service processing module receives signals from the
PEG8, performs interface conversion, and performs PWE3 decapsulation and service
scheduling. Then, the CES service processing module processes the signals, and sends the
processed signals to the line processing module.
Management Module
The management module manages and controls the modules on the CQ1.
Clock Module
The clock module provides clock information for the modules on the CQ1.
Power Module
The power module converts the accessed DC voltage into the DC voltages that the modules of
the board require.
8.1.5 Front Panel
The front panel of the CQ1 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 8-3 shows the appearance of the front panel of the CQ1.
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Figure 8-3 Front panel of the CQ1
CQ1
CQ1
STAT
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4
ACT
SRV

Indicators
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22.2 Alarm Indicators on the Boards.
Interfaces
The front panel of the CQ1 has four optical interfaces. Table 8-2 describes the type ands usage
of the optical interfaces of the CQ1.
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Table 8-2 Interfaces of the CQ1
Optical
Interface
Type of Interface Usage
IN1-IN4 LC Channelized STM-1 signal input interface
OUT1-
OUT4
LC Channelized STM-1 signal output interface

8.1.6 Jumpers and DIP Switches
The CQ1 does not have any jumpers or DIP switches that are used for board settings.
8.1.7 Valid Slots
The CQ1 must be installed in a valid slot on the subrack. Otherwise, the CQ1 fails to work
normally.
The CQ1 can be installed in any slot of slots 19-26 and slots 29-36.
The CQ1 needs to be used with the PEG8. Table 8-3 lists the slots valid for the PEG8 and the
corresponding slots for the CQ1.
Table 8-3 Slots valid for the PEG8 and the corresponding slots for the CQ1
Slot for the PEG8 Slot for the CQ1
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

8.1.8 Feature Code
The CQ1 does not have any feature code.
8.1.9 Parameter Settings
You can set the parameters for the CQ1 by using the T2000.
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You can set the following parameters for the CQ1 by using the T2000.
l J0
l J1
l J2
l C2
l V5
l SDH interface
l Channel configuration
l ALS
l Recovery value of the idle timeslots
For more parameters and the description of the parameters, see 25.3 CES Boards.
8.1.10 Technical Specifications
The technical specifications of the CQ1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Specifications of Optical Interfaces
Table 8-4 provides the specifications of the optical interfaces on the CQ1.
Table 8-4 Specifications of the optical interfaces on the CQ1
Item Value
Nominal bit
rate
155520 kbit/s
Line code NRZ
Type of
optical
interface
S-1.1 L-1.1 L-1.2
Type of Fiber Single-mode LC Single-mode LC Single-mode LC
Transmission
distance (km)
2 to 15 20 to 40 60 to 80
Operating
wavelength
range (nm)
1261 to 1360 1263 to 1360 1480 to 1580
Launched
optical power
range (dBm)
-15 to -8 -5 to 0 -5 to 0
Receiver
sensitivity
(dBm)
-28 -34 -34
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Item Value
Minimum
overload
(dBm)
-8 -10 -10
Minimum
extinction
ratio (dB)
8.2 10 10

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the N1CQ1 are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight: 0.6 kg
Power Consumption
The maximum power consumption of the N1CQ1 at the room temperature (25C) is 16 W.
8.2 MD12
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the MD12 (multi-protocol 32-channels E1 interface processing
board). This topic also describes how to configure and commission the MD12.
NOTE
The interface on the MD12 is a 120-ohm E1 interface.
8.2.1 Version Description
The MD12 is available in one functional version, namely, N1.
8.2.2 Application
The MD12 directly accesses E1 services from the TDM plane, transmits the E1 services on the
packet ring, and directly separates the E1 services from other services on the BSC side. In this
manner, the smooth evolution from the TDM plane to the packet plane is implemented.
8.2.3 Functions and Features
The MD12 accesses 32xE1 signals and works with the PEG8 to process CES E1 services.
8.2.4 Working Principle and Signal Flow
The MD12 consists of the tributary processing module, CES service processing module,
management module, clock module, and power supply module.
8.2.5 Front Panel
The front panel of the MD12 has interfaces and a bar code.
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8.2.6 Jumpers and DIP Switches
The MD12 does not have any jumpers or DIP switches that are used for board settings.
8.2.7 Valid Slots
The MD12 must be installed in a valid slot in the subrack. Otherwise, the MD12 fails to work
normally.
8.2.8 Feature Code
The MD12 does not have any feature code.
8.2.9 Parameter Settings
You can set the parameters for the MD12 by using the T2000.
8.2.10 Technical Specifications
The technical specifications of the MD12 include the parameters specified for interfaces,
mechanical specifications, and power consumption.
8.2.1 Version Description
The MD12 is available in one functional version, namely, N1.
8.2.2 Application
The MD12 directly accesses E1 services from the TDM plane, transmits the E1 services on the
packet ring, and directly separates the E1 services from other services on the BSC side. In this
manner, the smooth evolution from the TDM plane to the packet plane is implemented.
Figure 8-4 shows the application of the MD12. The MD12 works with the PEG8 to transmit E1
services on the packet ring.
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Figure 8-4 Networking and application of the MD12
Service flow
TDM/Packet dual-plane
cross-connect board
NMS
RNC BSC
GE STM-1
BTS
NodeB
NodeB
BTS
STM-1/
STM-4
Ring
STM-1/
STM-4
Ring
10GE Ring
GE Ring
GE Ring
Packet ring
TDM ring
FE
E1
FE
E1
MD12
PEG8 P
E
G
8
P
E
G
8
CQ1
PEG8
P
E
G
8
P
E
G
8
8.2.3 Functions and Features
The MD12 accesses 32xE1 signals and works with the PEG8 to process CES E1 services.
Table 8-5 provides the functions and features of the MD12.
Table 8-5 Functions and features of the MD12
Function and
Feature
MD12
Basic functions Transmits and receives 32xE1 signals, and works with the PEG8 to
process CES E1 services.
Bit error test
function
Supports the function of testing bit errors, and reports alarms in the case
of bit errors within a certain period.
Number of CES
services
32
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Function and
Feature
MD12
Emulation mode CESoPSN, SAToP
Timeslot
compression
function
In the case of the CES services in CESoPSN mode, the MD12 compresses
idle timeslots to improve the bandwidth utilization on the NNI side.
Clock mode Adaptive clock mode, retiming clock mode, and loopback clock mode.
Line code of E1
link
HDB3 code
Frame format of
E1 link
Unframed format, standard frame format, or E1 CRC-4 multiframe
format (default value)
Loopback mode Inloop, outloop, or non-loopback (default value)
Jitter buffer time
of CES services
The jitter buffer time of CES services can be set to a value in the range
of 0.125 ms to 16 ms with a step of 0.125 ms.
Encapsulation
buffer time of
CES packets
The encapsulation buffer time of CES services can be set to a value in
the range of 0.125 ms to 5 ms with a step of 0.125 ms.

8.2.4 Working Principle and Signal Flow
The MD12 consists of the tributary processing module, CES service processing module,
management module, clock module, and power supply module.
Figure 8-5 shows the functional block diagram of the MD12.
Figure 8-5 Functional block diagram of the MD12
Tributary
processing
module
CES service
processing
module
Service
signal
PEG8
Management
module
Management bus
Management bus
PEG8
Clock
module
Power
module
PEG8
Management bus
32xE1
signals
.
.
.
3.3 V
1.2 V
Backplane
Line clock
.
.
.
Service signal
System clock
PEG8
+3.3 V backup
power supply
Line clock
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Receive Direction
The tributary processing module accesses E1 signals, and performs the functions of impedance
matching, signal equalization, level conversion, clock recovery, de-jitter, and decoding. After
the tributary processing module processes the E1 signals, the signals are sent to the CES service
processing module for framing, PWE3 encapsulation and mapping, and PW scheduling. Then,
the signals are sent to the PEG8 through the backplane interface module.
Transmit Direction
The cross-connect unit receives packets from the backplane interface module, and sends the
packets to the CES service processing module. The CES service processing module decapsulates
the packets, buffers the data in queues, schedules the queues based on service types, and then
processes and converts the data. The converted data is sent to the tributary processing module.
The tributary processing module performs the functions of coding, dejitter, pulse shaping, and
line drive, and then sends the services to E1 interfaces.
Tributary Processing Module
The tributary processing module consists of 32 independent receive channels and transmit
channels.
l The receive channels implement the functions of impedance matching, signal equalization,
level conversion, clock recovery, de-jitter, and decoding.
l The transmit channels implement the functions of coding, dejitter, pulse shaping, and line
drive.
Service Processing Module
The CES service processing module performs framing, CES emulation, and PWE3
encapsulation for 32 channels of E1 services.
l In the receive direction, the CES service processing module obtains the PW information
of each E1 service, performs PWE3 encapsulation and PW scheduling, and then sends the
signals to the PEG8 through the backplane interface.
l In the transmit direction, the CES service processing module receives the services from the
PEG8, identifies different service types, and performs PWE3 decapsulation and service
scheduling.
Management Module
The management module manages and controls the modules on the MD12.
Clock Module
Provides the clock signal for each module of the MD12.
Power Module
The power module converts the accessed DC voltage into the DC voltages that the modules of
the board require.
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8.2.5 Front Panel
The front panel of the MD12 has interfaces and a bar code.
Diagram of the Front Panel
Figure 8-6 shows the appearance of the front panel of the MD12.
Figure 8-6 Front panel of the MD12
MD12
MD12

Interfaces
The front panel of the MD12 has four DB44 interfaces. Table 8-6 describes the types and usage
of the interfaces of the MD12.
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Table 8-6 Interfaces of the MD12
Interface Type of Interface Usage
1-8 DB44 Receives E1 signals from the 1st channel to the 8th
channel.
9-16 DB44 Receives E1 signals from the 9th channel to the 16th
channel.
17-24 DB44 Receives E1 signals from the 17th channel to the 24th
channel.
25-32 DB44 Receives E1 signals from the 25th channel to the 32th
channel.

Table 8-7 lists the pins of the DB44 interface.
Table 8-7 Pin description of the DB44 interfaces on the MD12
Front View Pin Usage Pin Usage
44
1
15
16
30
31
38 R1 to receive the
first channel of
signals
34 R5 to receive the
fifth channel of
signals
23 19
37 R2 to receive the
second channel
of signals
33 R6 to receive the
sixth channel of
signals
22 18
36 R3 to receive the
third channel of
signals
32 R7 to receive the
seventh channel of
signals
21 17
35 R4 to receive the
fourth channel of
signals
31 R8 to receive the
eighth channel of
signals
20 16
15 T1 to transmit
the first channel
of signals
11 T5 to transmit the
fifth channel of
signals
30 26
14 T2 to transmit
the second
channel of
signals
10 T6 to transmit the
sixth channel of
signals
29 25
13 T3 to transmit
the third channel
of signals
9 T7 to transmit the
seventh channel of
signals
28 24
12 T4 to transmit
the fourth
8 T8 to transmit the
eighth channel of
signals
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Front View Pin Usage Pin Usage
27 channel of
signals
7

8.2.6 Jumpers and DIP Switches
The MD12 does not have any jumpers or DIP switches that are used for board settings.
8.2.7 Valid Slots
The MD12 must be installed in a valid slot in the subrack. Otherwise, the MD12 fails to work
normally.
The MD12 can be installed in any slot of slots 19-26 and slots 29-36.
The MD12 needs to be used with the PEG8. Table 8-8 lists the slots valid for the PEG8 and the
corresponding slots for the MD12.
Table 8-8 Slots valid for the PEG8 and the corresponding slots for the MD12
Slot for the PEG8 Slot for the MD12
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

8.2.8 Feature Code
The MD12 does not have any feature code.
8.2.9 Parameter Settings
You can set the parameters for the MD12 by using the T2000.
You can set the E1 interfaces parameters for the MD12 by using the T2000.
For the description of the E1 interfaces parameter, see 25.3 CES Boards.
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8.2.10 Technical Specifications
The technical specifications of the MD12 include the parameters specified for interfaces,
mechanical specifications, and power consumption.
Specifications of Electrical Interfaces
Table 8-9 Specifications of the electrical interfaces of the MD12
Item Value
Type of electrical interface 2048 kbit/s
Code pattern HDB3 code
Signal bit rate at the output
port
Compliant with ITU-T G.703
Permitted frequency
deviation at the input port
Allowed attenuation at the
input port
Input jitter tolerance

Mechanical Specifications
The mechanical specifications of the MD12 are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight: 0.5 kg
Power Consumption
The maximum power consumption of the MD12 at the room temperature (25C) is 14 W.
8.3 MD75
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the MD75 (multi-protocol 32-channels E1 interface processing
board). This topic also describes how to configure and commission the MD75.
NOTE
The interface on the MD12 is a 120-ohm E1 interface.
8.3.1 Version Description
The MD75 is available in one functional version, namely, N1.
8.3.2 Application
The MD75 directly accesses E1 services from the TDM plane, transmits the E1 services on the
packet ring, and directly separates the E1 services from other services on the BSC side. In this
manner, the smooth evolution from the TDM plane to the packet plane is implemented.
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8.3.3 Functions and Features
The MD75 accesses 32xE1 signals and works with the PEG8 to process CES E1 services.
8.3.4 Working Principle and Signal Flow
The MD75 consists of the tributary processing module, CES service processing module,
management module, clock module, and power supply module.
8.3.5 Front Panel
The front panel of the MD75 has interfaces and a bar code.
8.3.6 Jumpers and DIP Switches
The MD75 does not have any jumpers or DIP switches that are used for board settings.
8.3.7 Valid Slots
The MD75 must be installed in a valid slot in the subrack. Otherwise, the MD75 fails to work
normally.
8.3.8 Feature Code
The MD75 does not have any feature code.
8.3.9 Parameter Settings
You can set the parameters for the MD75 by using the T2000.
8.3.10 Technical Specifications
The technical specifications of the MD12 include the parameters specified for interfaces,
mechanical specifications, and power consumption.
8.3.1 Version Description
The MD75 is available in one functional version, namely, N1.
8.3.2 Application
The MD75 directly accesses E1 services from the TDM plane, transmits the E1 services on the
packet ring, and directly separates the E1 services from other services on the BSC side. In this
manner, the smooth evolution from the TDM plane to the packet plane is implemented.
Figure 8-7 shows the application of the MD75. The MD75 works with the PEG8 to transmit E1
services on the packet ring.
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Figure 8-7 Networking and application of the MD75
Signal flow
TDM-packet dual-
plane cross-
connect board
NMS
RNC
BSC
GE STM-1
BTS
NodeB
NodeB
BTS
STM-1/
STM-4
Ring
STM-1/
STM-4
Ring
10GE Ring
GE Ring
GE Ring
Packet ring
TDM ring
FE
E1
FE
E1
MD75
PEG8 P
E
G
8
P
E
G
8
CQ1
PEG8
P
E
G
8
P
E
G
8
8.3.3 Functions and Features
The MD75 accesses 32xE1 signals and works with the PEG8 to process CES E1 services.
Table 8-10 provides the functions and features of the MD75.
Table 8-10 Functions and features of the MD75
Function and
Feature
MD75
Basic functions Transmits and receives 32xE1 signals, and works with the PEG8 to
process CES E1 services.
Bit error test
function
Supports the function of testing bit errors, and reports alarms in the case
of bit errors within a certain period.
Number of CES
services
32
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Function and
Feature
MD75
Emulation mode CESoPSN, SAToP
Timeslot
compression
function
In the case of the CES services in CESoPSN mode, the MD75 compresses
idle timeslots to improve the bandwidth utilization on the NNI side.
Clock mode Adaptive clock mode, retiming clock mode, and loopback clock mode.
Line code of E1
link
HDB3 code
Frame format of
E1 link
Unframed format, standard frame format, or E1 CRC-4 multiframe
format (default value)
Loopback mode Inloop, outloop, or non-loopback (default value)
Jitter buffer time
of CES services
The jitter buffer time of CES services can be set to a value in the range
of 0.125 ms to 16 ms with a step of 0.125 ms.
Encapsulation
buffer time of
CES packets
The encapsulation buffer time of CES services can be set to a value in
the range of 0.125 ms to 5 ms with a step of 0.125 ms.

8.3.4 Working Principle and Signal Flow
The MD75 consists of the tributary processing module, CES service processing module,
management module, clock module, and power supply module.
Figure 8-8 shows the functional block diagram of the MD75.
Figure 8-8 Functional block diagram of the MD75
Tributary
processing
module
CES service
processing
module
Service
signal
PEG8
Management
module
Management bus
Management bus
PEG8
Clock
module
Power
module
PEG8
Management bus
32xE1
signals
.
.
.
3.3 V
1.2 V
Backplane
Line clock
.
.
.
Service signal
System clock
PEG8
+3.3 V backup
power supply
Line clock
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Receive Direction
The tributary processing module accesses E1 signals, and performs the functions of impedance
matching, signal equalization, level conversion, clock recovery, de-jitter, and decoding. After
the tributary processing module processes the E1 signals, the signals are sent to the CES service
processing module for framing, PWE3 encapsulation and mapping, and PW scheduling. Then,
the signals are sent to the PEG8 through the backplane interface module.
Transmit Direction
The cross-connect unit receives packets from the backplane interface module, and sends the
packets to the CES service processing module. The CES service processing module decapsulates
the packets, buffers the data in queues, schedules the queues based on service types, and then
processes and converts the data. The converted data is sent to the tributary processing module.
The tributary processing module performs the functions of coding, dejitter, pulse shaping, and
line drive, and then sends the services to E1 interfaces.
Tributary Processing Module
The tributary processing module consists of 32 independent receive channels and transmit
channels.
l The receive channels implement the functions of impedance matching, signal equalization,
level conversion, clock recovery, de-jitter, and decoding.
l The transmit channels implement the functions of coding, dejitter, pulse shaping, and line
drive.
Service Processing Module
The CES service processing module performs framing, CES emulation, and PWE3
encapsulation for 32 channels of E1 services.
l In the receive direction, the CES service processing module obtains the PW information
of each E1 service, performs PWE3 encapsulation and PW scheduling, and then sends the
signals to the PEG8 through the backplane interface.
l In the transmit direction, the CES service processing module receives the services from the
PEG8, identifies different service types, and performs PWE3 decapsulation and service
scheduling.
Management Module
The management module manages and controls the modules on the MD75.
Clock Module
Provides the clock signal for each module of the MD75.
Power Module
The power module converts the accessed DC voltage into the DC voltages that the modules of
the board require.
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8.3.5 Front Panel
The front panel of the MD75 has interfaces and a bar code.
Diagram of the Front Panel
Figure 8-9 shows the appearance of the front panel of the MD75.
Figure 8-9 Front panel of the MD75
MD75
MD75

Interfaces
The front panel of the MD75 has four DB44 interfaces. Table 8-11 describes the types and usage
of the interfaces of the MD75.
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Table 8-11 Interfaces of the MD75
Interface Type of Interface Usage
1-8 DB44 Receives E1 signals from the 1st channel to the 8th
channel.
9-16 DB44 Receives E1 signals from the 9th channel to the 16th
channel.
17-24 DB44 Receives E1 signals from the 17th channel to the 24th
channel.
25-32 DB44 Receives E1 signals from the 25th channel to the 32th
channel.

Table 8-12 lists the pins of the DB44 interface.
Table 8-12 Pin description of the DB44 interfaces on the MD75
Front View Pin Usage Pin Usage
44
1
15
16
30
31
38 R1 to receive the
first channel of
signals
34 R5 to receive the
fifth channel of
signals
23 19
37 R2 to receive the
second channel
of signals
33 R6 to receive the
sixth channel of
signals
22 18
36 R3 to receive the
third channel of
signals
32 R7 to receive the
seventh channel of
signals
21 17
35 R4 to receive the
fourth channel of
signals
31 R8 to receive the
eighth channel of
signals
20 16
15 T1 to transmit
the first channel
of signals
11 T5 to transmit the
fifth channel of
signals
30 26
14 T2 to transmit
the second
channel of
signals
10 T6 to transmit the
sixth channel of
signals
29 25
13 T3 to transmit
the third channel
of signals
9 T7 to transmit the
seventh channel of
signals
28 24
12 T4 to transmit
the fourth
8 T8 to transmit the
eighth channel of
signals
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Front View Pin Usage Pin Usage
27 channel of
signals
7

8.3.6 Jumpers and DIP Switches
The MD75 does not have any jumpers or DIP switches that are used for board settings.
8.3.7 Valid Slots
The MD75 must be installed in a valid slot in the subrack. Otherwise, the MD75 fails to work
normally.
The MD75 can be installed in any slot of slots 19-26 and slots 29-36.
The MD75 needs to be used with the PEG8. Table 8-13 lists the slots valid for the PEG8 and
the corresponding slots for the MD75.
Table 8-13 Slots valid for the PEG8 and the corresponding slots for the MD75
Slot for the PEG8 Slot for the MD75
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

8.3.8 Feature Code
The MD75 does not have any feature code.
8.3.9 Parameter Settings
You can set the parameters for the MD75 by using the T2000.
You can set the E1 interfaces parameters for the MD75 by using the T2000.
For the description of the E1 interfaces parameter, see 25.3 CES Boards.
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8.3.10 Technical Specifications
The technical specifications of the MD12 include the parameters specified for interfaces,
mechanical specifications, and power consumption.
Specifications of Electrical Interfaces
Table 8-14 Specifications of the electrical interfaces of the MD75
Item Value
Type of
electrical
interface
2048 kbit/s
Code pattern HDB3 code
Signal bit rate at
the output port
Compliant with ITU-T G.703
Permitted
frequency
deviation at the
input port
Allowed
attenuation at
the input port
Input jitter
tolerance

Mechanical Specifications
The mechanical specifications of the MD75 are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight: 0.5 kg
Power Consumption
The maximum power consumption of the MD75 at room temperature (25C) is 14 W.
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9 SDH Boards
About This Chapter
This topic describes the SDH boards that operate at the STM-64, STM-16, STM-4, and STM-1
rates.
9.1 SL1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SL1 (1xSTM-1 optical interface board). This topic also describes
how to configure and commission the SL1.
9.2 SL1A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL1A (1xSTM-1 optical interface board).
9.3 SLQ1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ1 (4xSTM-1 optical interface board).
9.4 SLQ1A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ1A (4xSTM-1 optical interface board).
9.5 SLO1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLO1 (8xSTM-1 optical interface board).
9.6 SLT1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLT1 (12xSTM-1 optical interface board).
9.7 SLH1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SLH1 (16xSTM-1 signal processing board). This topic also
describes how to configure and commission the SLH1.
9.8 SEP1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SEP1 (2xSTM-1 line processing board). This topic also describes
how to configure and commission the SEP1.
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9.9 SL4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL4 (1xSTM-4 optical interface board).
9.10 SL4A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL4A (1xSTM-4 optical interface board).
9.11 SLD4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLD4 (2xSTM-4 optical interface board).
9.12 SLD4A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLD4A (2xSTM-4 optical interface board).
9.13 SLQ4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ4 (4xSTM-4 optical interface board).
9.14 SLQ4A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ4A (4xSTM-4 optical interface board).
9.15 SL16
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL16 (1xSTM-16 optical interface board).
9.16 SL16A
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SL16A (1xSTM-16 optical interface board). This topic also
describes how to configure and commission the SL16A.
9.17 SLD16
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SLD16 (2xSTM-16 optical interface board). This topic also
describes how to configure and commission the SLD16.
9.18 SLQ16
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SLQ16 (4xSTM-16 optical interface board). This topic also
describes how to configure and commission the SLQ16.
9.19 SLO16
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SLO16 (8xSTM-16 optical interface board). This topic also
describes how to configure and commission the SLO16.
9.20 SF16
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SF16 (1xSTM-16 optical interface board with the out-band FEC
function).
9.21 SL64
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SL64 (1xSTM-64 optical interface board). This topic also
describes how to configure and commission the SL64.
9.22 SLD64
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This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SLD64 (2xSTM-64 optical interface board). This topic also
describes how to configure and commission the SLD64.
9.23 SF64
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SF64 (1xSTM-64 optical interface board with the FEC function).
This topic also describes how to configure and commission the SF64.
9.24 SF64A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SF64A (1xSTM-64 optical interface board with the FEC function).
9.25 SLQ41
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SLQ41 (4xSTM-4/STM-1 optical interface board). This topic also
describes how to configure and commission the SLQ41.
9.26 EU04
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EU04 (4xSTM-1 electrical interface board).
9.27 EU08
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EU08 (8xSTM-1 electrical interface board).
9.28 OU08
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the OU08 (8xSTM-1 optical interface board).
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9.1 SL1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SL1 (1xSTM-1 optical interface board). This topic also describes
how to configure and commission the SL1.
9.1.1 Version Description
The SL1 is available in several functional versions. The functions provided by the functional
versions are different.
9.1.2 Application
The SL1 is a line board. The SL1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SL1 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SL1 converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
9.1.3 Functions and Features
The SL1 transmits and receives STM-1 optical signals, performs O/E conversion for the STM-1
optical signals, extracts and inserts overhead bytes, and generates alarm signals on the line.
9.1.4 Working Principle and Signal Flow
The SL1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, and power module.
9.1.5 Front Panel
The front panel of the SL1 has indicators, interfaces, and a bar code.
9.1.6 Jumpers and DIP Switches
The SL1 does not have any jumpers or DIP switches that are used for board settings.
9.1.7 Valid Slots
The SL1 must be installed in a valid slot in the subrack. Otherwise, the SL1 cannot work
normally.
9.1.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL1 indicates the type of optical interface.
9.1.9 Parameter Settings
You can set parameters for the SL1 by using the T2000.
9.1.10 Technical Specifications
The technical specifications of the SL1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.1.1 Version Description
The SL1 is available in several functional versions. The functions provided by the functional
versions are different.
The SL1 is available in the following functional versions: N1 and N2. The difference between
the functional versions is with regard to whether they support the tandem connection monitoring
(TCM) function and AU-3 services.
The N1SL1 is no longer manufactured.
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Table 9-1 describes the versions of the SL1.
Table 9-1 Versions of the SL1
Item Description
Functional versions The SL1 is available in the following functional versions: N1 and N2.
Differences l The N2SL1 supports the TCM function and AU-3 services, but the
TCM function and AU-3 services cannot be available at the same
time.
l The N1SL1 does not support the TCM function or AU-3 services.
Substitution Through the board version replacement function, the N1SL1A can
substitute for the N1SL1.

NOTE
When you configure the multiplex section protection (MSP) or sub-network connection protection (SNCP),
you cannot configure the N1SL1 as the protection board if the working board is the N2SL1 on which the
TCM function is enabled or AU-3 services are configured. Otherwise, the services are interrupted when a
switching operation is performed.
9.1.2 Application
The SL1 is a line board. The SL1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SL1 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SL1 converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
Figure 9-1 shows the application of the SL1. The SL1 boards can form a ring network or a chain
network in the system.
NOTE
The SL1 does not support the two-fiber bidirectional ring MSP.
Figure 9-1 Networking and application of the SL1
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board
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9.1.3 Functions and Features
The SL1 transmits and receives STM-1 optical signals, performs O/E conversion for the STM-1
optical signals, extracts and inserts overhead bytes, and generates alarm signals on the line.
Table 9-2 provides the functions and features of the SL1.
Table 9-2 Functions and features of the SL1
Function and
Feature
SL1
Basic functions Transmits and receives 1xSTM-1 optical signals.
Specifications of
the optical
interface
l Supports different types of standard optical interfaces, namely, the I-1,
S-1.1, L-1.1, L-1.2, and Ve-1.2.
l The characteristics of the optical interfaces of the I-1, S-1.1, L-1.1, and
L-1.2 types comply with ITU-T G.957.
l The characteristics of the optical interface of the Ve-1.2 type comply
with the standards defined by Huawei.
Specifications of
the optical
module
l Supports the detection and query of the information about the optical
module.
l Supports the usage and detection of the small form-factor pluggable
(SFP) optical module, which facilitates the maintenance of the optical
module.
l Provides the automatic laser shutdown (ALS) function. The optical
interface supports the setting of the on/off state of a laser.
Service
processing
l Supports the VC-12 services, VC-3 services, and VC-4 services.
l The N2SL1 supports the AU-3 services.
Overhead
processing
l Processes the section overheads of the STM-1 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one channel of ECC communication.
Alarms and
performance
events
Provides various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection
schemes
l Supports the two-fiber ring MSP.
l Supports the four-fiber ring MSP.
l Supports the linear MSP.
l Supports the SNCP.
l Supports the sub-network connection multi-protection (SNCMP).
l Supports the sub-network connection tunnel protection (SNCTP).
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Function and
Feature
SL1
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l The N1SL1 supports inloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l The N2SL1 supports the TCM function.
l Supports the press-to-collect function in fault data collection.

9.1.4 Working Principle and Signal Flow
The SL1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, and power module.
Figure 9-2 shows the functional block diagram of the SL1.
Figure 9-2 Functional block diagram of the SL1
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
LOS
Laser shutdown
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
155 MHz
Reference clock
K1 and K2
insertion/extraction
MSA
IIC
CDR
.

.

.

.
.

.

.

.
CDR
-48 V/-60 V
155 Mbit/s
O/E
E/O
SPI
O/E
SPI
Frame header
Cross-connect
unit
K1 and K2
155
Mbit/s
155 Mbit/s
155 Mbit/s
155 Mbit/s
E/O
Power
module
SCC unit
O/E converting
module
155
Mbit/s
Backplane
155 MHz
PLL
HPT MST RST
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination CDR: clock data restoration -

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O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l Detects the R_LOS alarm and provides the function of shutting down the laser.
CDR Module
This module restores the clock signal.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module terminates the regenerator section
overhead (RSOH). That is, the RST sub-module detects the frame alignment bytes (A1
and A2), descrambles all the bytes except the first line of the RSOH, restores and checks
the regenerator section trace byte (J0), and checks the B1 byte.
In the transmit direction, the RST sub-module generates the RSOH. That is, the RST
sub-module writes bytes such as A1, A2, and J0, calculates and writes the B1 byte, and
scrambles all the bytes except the first line of the RSOH.
l MST sub-module
In the receive direction, the MST sub-module terminates the multiplex section overhead
(MSOH). That is, the MST sub-module generates the multiplex section-alarm indication
signal (MS_AIS) alarm and detects the multiplex section-remote defect indication
(MS_RDI) alarm after detecting the K2 byte, and detects the multiplex section-remote
error indication (MS_REI) alarm and generates the B2-excessive errors (B2_EXC)
alarm after checking the B2 byte.
In the transmit direction, the MST sub-module generates the MSOH. That is, the MST
sub-module writes bytes such as E2, D4-D12, K1, K2, S1, and M1, and calculates and
writes the B2 byte.
l MSA sub-module
In the receive direction, the MSA sub-module de-interleaves the administration unit
group (AUG), divides an AUG into N AU-4s, detects the administration unit-loss of
pointer (AU_LOP) alarm and the administration unit-alarm indication signal (AU_AIS)
alarm, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
l HPT sub-module
In the receive direction, the HPT sub-module terminates the path overhead (POH). That
is, the HPT sub-module detects the higher order path-remote error indication (HP_REI)
alarm after checking the B3 byte, generates the higher order path-trace identifier
mismatch (HP_TIM) alarm and the higher order path-signal label mismatch (HP_SLM)
alarm and detects the higher order path-remote defect indication (HP_RDI) alarm after
detecting the J1 and C2 bytes, and generates the higher order path-unequipped
(HP_UNEQ) alarm after detecting the C2 byte.
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In the transmit direction, the HPT sub-module generates the POH. That is, the HPT sub-
module writes bytes such as J1 and C2, and calculates and writes the B3 byte.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not in position.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
9.1.5 Front Panel
The front panel of the SL1 has indicators, interfaces, and a bar code.
Diagram of the Front Panel
Figure 9-3 shows the appearance of the front panel of the SL1.
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Figure 9-3 Front panel of the SL1
SL1
SL1
ACT
PROG
SRV
STAT
O
U
T
1
I
N
1
CLASS 1
LASER
PRODUCT

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SL1 has one optical interface. Table 9-3 describes the types and usage of
the optical interfaces of the SL1.
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Table 9-3 Optical interfaces of the SL1
Interface Type of Interface Usage
IN LC Receives optical signals.
OUT LC Transmits optical signals.

9.1.6 Jumpers and DIP Switches
The SL1 does not have any jumpers or DIP switches that are used for board settings.
9.1.7 Valid Slots
The SL1 must be installed in a valid slot in the subrack. Otherwise, the SL1 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SL1 vary with the cross-connect capacity of the subrack. The slots valid
for the board are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SL1 can be installed in slots 18 and
1117.
9.1.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL1 indicates the type of optical interface.
Table 9-4 provides the relationship between the feature code of the SL1 and the type of optical
interface.
Table 9-4 Relationship between the feature code of the SL1 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SL110 and
SSN2SL110
10 S-1.1
SSN1SL111 and
SSN2SL111
11 L-1.1
SSN1SL112 and
SSN2SL112
12 L-1.2
SSN1SL113 and
SSN2SL113
13 Ve-1.2
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Board Feature Code Type of Optical Interface
SSN1SL114 and
SSN2SL114
14 I-1

9.1.9 Parameter Settings
You can set parameters for the SL1 by using the T2000.
You can set the following parameters for the SL1 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.1.10 Technical Specifications
The technical specifications of the SL1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-5 lists the parameters specified for the optical interfaces of the SL1.
Table 9-5 Parameters specified for the optical interfaces of the SL1
Parameter Value
Nominal bit rate 155520 kbit/s
Line code
pattern
Non-return to zero (NRZ)
Application
code
I-1 S-1.1 L-1.1 L-1.2 Ve-1.2
Transmission
distance (km)
0 to 2 2 to 15 20 to 40 60 to 80 80 to 100
Type of fiber Single-mode LC Single-mode LC Single-mode
LC
Single-mode LC Single-mode LC
Operating
wavelength
range (nm)
1260 to 1360 1261 to 1360 1263 to 1360 1480 to 1580 1480 to 1580
Launched
optical power
range (dBm)
-15 to -8 -15 to -8 -5 to 0 -5 to 0 -3 to 0
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Parameter Value
Receiver
sensitivity
(dBm)
-23 -28 -34 -34 -34
Minimum
overload (dBm)
-8 -8 -10 -10 -10
Minimum
extinction ratio
(dB)
8.2 8.2 10 10 10

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the N1SL1 and N2SL1 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight of the N1SL1 (kg): 0.6
l Weight of the N2SL1 (kg): 1.0
Power Consumption
The maximum power consumption of the N1SL1 at room temperature (25C) is 17 W.
The maximum power consumption of the N2SL1 at room temperature (25C) is 14 W.
9.2 SL1A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL1A (1xSTM-1 optical interface board).
9.2.1 Version Description
The SL1A is available in one functional version, namely, N1.
9.2.2 Application
The SL1A is a line board. The SL1A can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SL1A converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SL1A converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
9.2.3 Functions and Features
The SL1A transmits and receives STM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
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9.2.4 Working Principle and Signal Flow
The SL1A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, power module, and other modules.
9.2.5 Front Panel
The front panel of the SL1A has indicators, interfaces, a bar code, and a laser safety class label.
9.2.6 Valid Slots
The slots valid for the SL1A vary with the cross-connect capacity of the subrack.
9.2.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL1A indicates the type of optical interface.
9.2.8 Parameter Settings
You can set the parameters for the SL1A by using the T2000.
9.2.9 Technical Specifications
The technical specifications of the SL1A include the parameters specified for optical interfaces,
laster safety class, mechanical specifications, and power consumption.
9.2.1 Version Description
The SL1A is available in one functional version, namely, N1.
9.2.2 Application
The SL1A is a line board. The SL1A can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SL1A converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SL1A converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
Figure 9-4 shows the application of the SL1A. The SL1A boards can form a ring network or a
chain network in the system.
Figure 9-4 Networking and application of the SL1A
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

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9.2.3 Functions and Features
The SL1A transmits and receives STM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 9-6 provides the functions and features of the SL1A.
Table 9-6 Functions and features of the SL1A
Function and
Feature
SL1A
Basic functions Transmits and receives 1xSTM-1 optical signals.
Specifications of
the optical
interface
l Supports different types of standard optical interfaces, namely, the I-1,
S-1.1, L-1.1, L-1.2, and Ve-1.2.
l The characteristics of the optical interfaces of the I-1, S-1.1, L-1.1, and
L-1.2 types comply with ITU-T G.957.
l The characteristics of the optical interface of the Ve-1.2 type comply
with the standards defined by Huawei.
Specifications of
the optical
module
l Supports the detection and query of the information about the optical
module.
l Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
Service
processing
Supports the VC-12 services, VC-3 services, and VC-4 services.
Overhead
processing
l Processes the section overheads of the STM-1 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one channel of ECC communication.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection
schemes
Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP, SNCP,
SNCTP, and SNCMP.
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Function and
Feature
SL1A
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the press-to-collect function in fault data collection.

9.2.4 Working Principle and Signal Flow
The SL1A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, power module, and other modules.
Figure 9-5 shows the functional block diagram of the SL1A.
Figure 9-5 Functional block diagram of the SL1A
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
LOS
Laser shutdown
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
155 MHz
Reference clock
K1 and K2
insertion/extraction
MSA
IIC
CDR
.

.

.

.
.

.

.

.
CDR
-48 V/-60 V
155 Mbit/s
O/E
E/O
SPI
O/E
SPI
Frame header
Cross-connect
unit
K1 and K2
155
Mbit/s
155 Mbit/s
155 Mbit/s
155 Mbit/s
E/O
Power
module
SCC unit
O/E converting
module
155
Mbit/s
Backplane
155 MHz
PLL
HPT MST RST
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery

The functional modules of the STM-1 units are described as follows:
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O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function of shutting down the laser.
CDR Module
This module restores the data signal and the clock signal.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
l MST sub-module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.
In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.
l MSA sub-module
In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.
l HPT sub-module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
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l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
9.2.5 Front Panel
The front panel of the SL1A has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-6 shows the appearance of the front panel of the SL1A.
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Figure 9-6 Front panel of the SL1A
SL1A
SL1A
ACT
PROG
SRV
STAT
O
U
T
1
I
N
1
CLASS 1
LASER
PRODUCT

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SL1A has one optical interface. Table 9-7 describes the types and usage
of the optical interfaces of the SL1A.
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Table 9-7 Optical interfaces of the SL1A
Interface Type of
Interface
Usage
IN LC Receives optical signals.
OUT LC Transmits optical signals.

9.2.6 Valid Slots
The slots valid for the SL1A vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SL1A are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SL1A can be installed in slots 18 and
1117.
9.2.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL1A indicates the type of optical interface.
Table 9-8 provides the relationship between the feature code of the SL1A and the type of optical
interface.
Table 9-8 Relationship between the feature code of the SL1A and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SL1A10 10 S-1.1
SSN1SL1A11 11 L-1.1
SSN1SL1A12 12 L-1.2
SSN1SL1A13 13 Ve-1.2
SSN1SL1A14 14 I-1

9.2.8 Parameter Settings
You can set the parameters for the SL1A by using the T2000.
You can set the following parameters for the SL1A by using the T2000:
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l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.2.9 Technical Specifications
The technical specifications of the SL1A include the parameters specified for optical interfaces,
laster safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-9 lists the parameters specified for the optical interfaces of the SL1A.
Table 9-9 Parameters specified for the optical interfaces of the SL1A
Parameter Value
Nominal bit
rate
155520 kbit/s
Line code
pattern
NRZ
Application
code
I-1 S-1.1 L-1.1 L-1.2 Ve-1.2
Transmissio
n distance
(km)
0 to 2 2 to 15 20 to 40 60 to 80 80 to 100
Type of fiber Single-mode
LC
Single-mode
LC
Single-mode
LC
Single-mode
LC
Single-mode
LC
Operating
wavelength
range (nm)
1260 to 1360 1261 to 1360 1263 to 1360 1480 to 1580 1480 to 1580
Launched
optical
power range
(dBm)
-15 to -8 -15 to -8 -5 to 0 -5 to 0 -3 to 0
Receiver
sensitivity
(dBm)
-23 -28 -34 -34 -34
Minimum
overload
(dBm)
-8 -8 -10 -10 -10
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Parameter Value
Minimum
extinction
ratio (dB)
8.2 8.2 10 10 10

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SL1A are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.6
Power Consumption
The maximum power consumption of the SL1A at room temperature (25C) is 17 W.
9.3 SLQ1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ1 (4xSTM-1 optical interface board).
9.3.1 Version Description
The SLQ1 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SLQ1 is no longer manufactured.
9.3.2 Application
The SLQ1 is a line board. The SLQ1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SLQ1 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLQ1 converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
9.3.3 Functions and Features
The SLQ1 transmits and receives 4xSTM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
9.3.4 Working Principle and Signal Flow
The SLQ1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, power module, and other modules.
9.3.5 Front Panel
The front panel of the SLQ1 has indicators, interfaces, a bar code, and a laser safety class label.
9.3.6 Valid Slots
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The slots valid for the SLQ1 vary with the cross-connect capacity of the subrack.
9.3.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ1 indicates the type of optical interface.
9.3.8 Parameter Settings
You can set the parameters for the SLQ1 by using the T2000.
9.3.9 Technical Specifications
The technical specifications of the SLQ1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.3.1 Version Description
The SLQ1 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SLQ1 is no longer manufactured.
Table 9-10 describes the versions of the SLQ1.
Table 9-10 Versions of the SLQ1
Item Description
Functional
versions
The SLQ1 is available in two functional versions, namely, N1 and N2.
Differences l The N2SLQ1 supports the TCM function and AU-3 services, but the
TCM function and AU-3 services cannot be available at the same
time.
l The N1SLQ1 does not support the TCM function or AU-3 services.
Substitution Through the board version replacement function, the N3SLQ41 can
substitute for the N1SLQ1 and N2SLQ1 at the same line rate.

NOTE
When you configure the MSP or SNCP, you cannot configure the N1SLQ1 as the protection board if the
working board is the N2SLQ1 on which the TCM function is enabled or AU-3 services are configured.
Otherwise, the services are interrupted when a switching operation is performed.
9.3.2 Application
The SLQ1 is a line board. The SLQ1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SLQ1 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLQ1 converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
Figure 9-7 shows the application of the SLQ1. The SLQ1 boards can form a ring network or a
chain network in the system.
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Figure 9-7 Networking and application of the SLQ1
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.3.3 Functions and Features
The SLQ1 transmits and receives 4xSTM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 9-11 provides the functions and features of the SLQ1.
Table 9-11 Functions and features of the SLQ1
Function and
Feature
SLQ1
Basic functions Transmits and receives 4xSTM-1 optical signals.
Specifications of
the optical
interface
l Supports different types of standard optical interfaces, namely, the I-1,
S-1.1, L-1.1, L-1.2, Ie-1, and Ve-1.2.
l The characteristics of the optical interfaces of the I-1, S-1.1, L-1.1, and
L-1.2 types comply with ITU-T G.957.
l The characteristics of the optical interfaces of the Ie-1 and Ve-1.2 types
comply with the standards defined by Huawei.
Specifications of
the optical
module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
l Supports the usage and detection of the SFP optical module, which
facilitates the maintenance of the optical module.
Service
processing
l Supports the VC-12 services, VC-3 services, and VC-4 services.
l The N2SLQ1 supports the AU-3 services.
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Function and
Feature
SLQ1
Overhead
processing
l Processes the section overheads of the STM-1 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one to four channels of ECC communication.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection
schemes
Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP, SNCP,
SNCTP, and SNCMP.
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l The N1SLQ1 supports inloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l The N2SLQ1 supports the TCM function.
l Supports the press-to-collect function in fault data collection.

9.3.4 Working Principle and Signal Flow
The SLQ1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, power module, and other modules.
Figure 9-8 shows the functional block diagram of the SLQ1.
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Figure 9-8 Functional block diagram of the SLQ1
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
LOS
Laser shutdown
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
155 MHz
Reference clock
K1 and K2
insertion/extraction
MSA
IIC
CDR
.

.

.

.
.

.

.

.
CDR
-48 V/-60 V
155 Mbit/s
O/E
E/O
SPI
O/E
SPI
Frame header
Cross-connect
unit
K1 and K2
155
Mbit/s
155 Mbit/s
155 Mbit/s
155 Mbit/s
E/O
Power
module
SCC unit
O/E converting
module
155
Mbit/s
Backplane
155 MHz
PLL
HPT MST RST
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery

The functional modules of the STM-1 units are described as follows:
O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function of shutting down the laser.
CDR Module
This module restores the data signal and the clock signal.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
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l MST sub-module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.
In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.
l MSA sub-module
In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.
l HPT sub-module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
9.3.5 Front Panel
The front panel of the SLQ1 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-9 shows the appearance of the front panel of the SLQ1.
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Figure 9-9 Front panel of the SLQ1
SLQ1
SLQ1
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SLQ1 has four optical interfaces. Table 9-12 describes the types and usage
of the optical interfaces of the SLQ1.
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Table 9-12 Optical interfaces of the SLQ1
Interface Type of
Interface
Usage
IN1-IN4 LC Receives optical signals.
OUT1-OUT4 LC Transmits optical signals.

9.3.6 Valid Slots
The slots valid for the SLQ1 vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SLQ1 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SLQ1 can be installed in slots 18 and
1117 in the subrack.
9.3.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ1 indicates the type of optical interface.
Table 9-13 provides the relationship between the feature code of the SLQ1 and the type of optical
interface.
Table 9-13 Relationship between the feature code of the SLQ1 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SLQ110 and
SSN2SLQ110
10 S-1.1
SSN1SLQ111 and
SSN2SLQ111
11 L-1.1
SSN1SLQ112 and
SSN2SLQ112
12 L-1.2
SSN1SLQ113 and
SSN2SLQ113
13 Ve-1.2
SSN1SLQ114 and
SSN2SLQ114
14 I-1
SSN1SLQ115 15 Ie-1

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9.3.8 Parameter Settings
You can set the parameters for the SLQ1 by using the T2000.
You can set the following parameters for the SLQ1 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.3.9 Technical Specifications
The technical specifications of the SLQ1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-14 lists the parameters specified for the optical interfaces of the SLQ1.
Table 9-14 Parameters specified for the optical interfaces of the SLQ1
Parameter Value
Nominal bit rate 155520 kbit/s
Line code
pattern
NRZ
Application
code
I-1 S-1.1 L-1.1 L-1.2 Ve-1.2 Ie-1
Transmission
distance (km)
0 to 2 2 to 15 20 to 40 60 to 80 80 to 100 0 to 2
Type of fiber Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-mode
LC
Multi-mode LC
Operating
wavelength
range (nm)
1260 to
1360
1261 to 1360 1263 to
1360
1480 to
1580
1480 to 1580 1270 to 1380
Launched
optical power
range (dBm)
-15 to -8 -15 to -8 -5 to 0 -5 to 0 -3 to 0 -19 to -14
Receiver
sensitivity
(dBm)
-23 -28 -34 -34 -34 -30
Minimum
overload (dBm)
-8 -8 -10 -10 -10 -14
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Parameter Value
Minimum
extinction ratio
(dB)
8.2 8.2 10 10 10 10

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the N1SLQ1 and N2SLQ1 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the N1SLQ1 at room temperature (25C) is 15 W.
The maximum power consumption of the N2SLQ1 at room temperature (25C) is 15 W.
9.4 SLQ1A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ1A (4xSTM-1 optical interface board).
9.4.1 Version Description
The SLQ1A is available in one functional version, namely, N1.
9.4.2 Application
The SLQ1A is a line board. The SLQ1A can be used on the OptiX OSN equipment series to
transmit and receive STM-1 optical signals. The SLQ1A converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SLQ1A converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
9.4.3 Functions and Features
The SLQ1A transmits and receives STM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
9.4.4 Working Principle and Signal Flow
The SLQ1A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
9.4.5 Front Panel
The front panel of the SLQ1A has indicators, interfaces, a bar code, and a laser safety class label.
9.4.6 Valid Slots
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The slots valid for the SLQ1A vary with the cross-connect capacity of the subrack.
9.4.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ1A indicates the type of optical interface.
9.4.8 Parameter Settings
You can set the parameters for the SLQ1A by using the T2000.
9.4.9 Technical Specifications
The technical specifications of the SLQ1A include the parameters specified for optical
interfaces, laser safety class, mechanical specifications, and power consumption.
9.4.1 Version Description
The SLQ1A is available in one functional version, namely, N1.
Through the board version replacement function, the N1SLQ1 can substitute for the N1SLQ1A.
9.4.2 Application
The SLQ1A is a line board. The SLQ1A can be used on the OptiX OSN equipment series to
transmit and receive STM-1 optical signals. The SLQ1A converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SLQ1A converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
Figure 9-10 shows the application of the SLQ1A. The SLQ1A boards can form a ring network
or a chain network in the system.
Figure 9-10 Networking and application of the SLQ1A
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.4.3 Functions and Features
The SLQ1A transmits and receives STM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
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Table 9-15 provides the functions and features of the SLQ1A.
Table 9-15 Functions and features of the SLQ1A
Function and
Feature
SLQ1A
Basic functions Transmits and receives 4xSTM-1 optical signals.
Specifications of
the optical
interface
l Supports different types of standard optical interfaces, namely, the I-1,
S-1.1, L-1.1, L-1.2, Ie-1, and Ve-1.2.
l The characteristics of the optical interfaces of the I-1, S-1.1, L-1.1, and
L-1.2 types comply with ITU-T G.957.
l The characteristics of the optical interfaces of the Ie-1 and Ve-1.2 types
comply with the standards defined by Huawei.
Specifications of
the optical
module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
l Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
Service
processing
Supports the VC-12 services, VC-3 services, and VC-4 services.
Overhead
processing
l Processes the section overheads of the STM-1 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one to four channels of ECC communication.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection
schemes
Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP, SNCP,
SNCTP, and SNCMP.
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the press-to-collect function in fault data collection.

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9.4.4 Working Principle and Signal Flow
The SLQ1A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 9-11 shows the functional block diagram of the SLQ1A.
Figure 9-11 Functional block diagram of the SLQ1A
Logic and
control
module
Cross-connect unit A
+3.3 V backup power
+3.3 V
SDH overhead processing module
DCC
SCC unit
LOS
Laser shutdown SCC unit
Communication
High-speed
bus
+3.3 V
-48 V/ -60 V
DC/DC
converter
Fuse
Fuse
DC/DC
converter
Cross-connect unit
Cross-connect unit B
155 MHz
PLL
Cross-connect unit
155 MHz Reference clock
K1 and K2 insertion/extraction
MS
A
HPT
MS
T
RST
IIC
CDR
.

.

.

.
.

.

.

.
CDR
-48 V/ -60 V
155 Mbit/s
O/E
E/O
S
P
I
O/E
E/O
S
P
I
Frame header
Cross-connect unit
K1 and K2
155
Mbit/s
155 Mbit/s
155 Mbit/s
155
Mbit/s
155 Mbit/s
155
Mbit/s
155
Mbit/s
155
Mbit/s
155
Mbit/s
High-speed
bus
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery

The functional modules of the STM-1 units are described as follows.
O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function of shutting down the laser.
CDR Module
This module restores the data signal and the clock signal.
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SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
l MST sub-module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.
In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.
l MSA sub-module
In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.
l HPT sub-module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two optical interface
boards when the GSCC is not online.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
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9.4.5 Front Panel
The front panel of the SLQ1A has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-12 shows the appearance of the front panel of the SLQ1A.
Figure 9-12 Front panel of the SLQ1A
SLQ1A
SLQ1A
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
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l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SLQ1A has four optical interfaces. Table 9-16 describes the types and
usage of the optical interfaces of the SLQ1A.
Table 9-16 Optical interfaces of the SLQ1A
Interface Type of
Interface
Usage
IN1IN4 LC Receives optical signals.
OUT1OUT4 LC Transmits optical signals.

9.4.6 Valid Slots
The slots valid for the SLQ1A vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SLQ1A are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SLQ1A can be installed in slots 18
and 1117 in the subrack.
9.4.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ1A indicates the type of optical interface.
Table 9-17 provides the relationship between the feature code of the SLQ1A and the type of
optical interface.
Table 9-17 Relationship between the feature code of the SLQ1A and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SLQ1A10 10 S-1.1
SSN1SLQ1A11 11 L-1.1
SSN1SLQ1A12 12 L-1.2
SSN1SLQ1A13 13 Ve-1.2
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Board Feature Code Type of Optical Interface
SSN1SLQ1A14 14 I-1
SSN1SLQ1A15 15 Ie-1

9.4.8 Parameter Settings
You can set the parameters for the SLQ1A by using the T2000.
You can set the following parameters for the SLQ1A by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.4.9 Technical Specifications
The technical specifications of the SLQ1A include the parameters specified for optical
interfaces, laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-18 lists the parameters specified for the optical interfaces of the SLQ1A.
Table 9-18 Parameters specified for the optical interfaces of the SLQ1A
Parameter Value
Nominal bit
rate
155520 kbit/s
Line code
pattern
NRZ
Application
code
I-1 S-1.1 L-1.1 L-1.2 Ve-1.2 Ie-1
Transmissio
n distance
(km)
0 to 2 2 to 15 20 to 40 60 to 80 80 to 100 0 to 2
Type of fiber Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-
mode LC
Multi-mode
LC
Operating
wavelength
range (nm)
1260 to
1360
1261 to
1360
1263 to
1360
1480 to
1580
1480 to
1580
1270 to
1380
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Parameter Value
Launched
optical
power range
(dBm)
-15 to -8 -15 to -8 -5 to 0 -5 to 0 -3 to 0 -19 to -14
Receiver
sensitivity
(dBm)
-23 -28 -34 -34 -34 -30
Minimum
overload
(dBm)
-8 -8 -10 -10 -10 -14
Minimum
extinction
ratio (dB)
8.2 8.2 10 10 10 10

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SLQ1A are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the SLQ1A at room temperature (25C) is 15 W.
9.5 SLO1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLO1 (8xSTM-1 optical interface board).
9.5.1 Version Description
The SLO1 is available in two functional versions, namely, N2 and N3. The difference between
the two versions is with regard to whether they support the TCM function or AU-3 services. The
N3SLO1 is discontinued.
9.5.2 Application
The SLO1 is a line board. The SLO1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SLO1 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLO1 converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
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9.5.3 Functions and Features
The SLO1 transmits and receives 8xSTM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
9.5.4 Working Principle and Signal Flow
The SLO1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, power module, and other modules.
9.5.5 Front Panel
The front panel of the SLO1 has indicators, interfaces, a bar code, and a laser safety class label.
9.5.6 Valid Slots
The slots valid for the SLO1 vary with the cross-connect capacity of the subrack.
9.5.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLO1 indicates the type of optical interface.
9.5.8 Parameter Settings
You can set the parameters for the SLO1 by using the T2000.
9.5.9 Technical Specifications
The technical specifications of the SLO1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.5.1 Version Description
The SLO1 is available in two functional versions, namely, N2 and N3. The difference between
the two versions is with regard to whether they support the TCM function or AU-3 services. The
N3SLO1 is discontinued.
Table 9-19 describes the versions of the SLO1.
Table 9-19 Versions of the SLO1
Item Description
Functional versions The SLO1 is available in two functional versions, namely, N2 and N3.
Differences l The N2SLO1 supports the TCM function and AU-3 services, but the
TCM function and AU-3 services cannot be available at the same
time.
l The N3SLO1 does not support the TCM function and AU-3 services.
Substitution When the N2SLO1 is not configured with the TCM function and AU-3
services, the N3SLO1 can substitute for the N2SLO1.

NOTE
When you configure the MSP or SNCP, you cannot configure the N3SLO1 as the protection board if the
working board is the N2SLO1 on which the TCM function or AU-3 services are configured. Otherwise,
the services are interrupted when a switching operation is performed.
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9.5.2 Application
The SLO1 is a line board. The SLO1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SLO1 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLO1 converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
Figure 9-13 shows the application of the SLO1. The SLO1 boards can form a ring network or
a chain network in the system.
Figure 9-13 Networking and application of the SLO1
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.5.3 Functions and Features
The SLO1 transmits and receives 8xSTM-1 optical signals, performs O/E conversion for the
STM-1 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 9-20 provides the functions and features of the SLO1.
Table 9-20 Functions and features of the SLO1 board
Function and
Feature
SLO1
Basic functions Receives and transmits 8xSTM-1 optical signals.
Specifications of
the optical interface
l Supports different types of standard optical interfaces, namely, the
I-1, S-1.1, L-1.1, L-1.2, and Ve-1.2.
l The characteristics of the optical interfaces of the I-1, S-1.1, L-1.1,
and L-1.2 types comply with ITU-T G.957.
l The characteristics of the optical interface of the Ve-1.2 type comply
with the standards defined by Huawei.
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Function and
Feature
SLO1
Specifications of
the optical module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
l Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
Service processing l Supports the VC-12 services, VC-3 services, and VC-4 services.
l The N2SLO1 supports the AU-3 services.
Overhead
processing
l Processes the section overheads of the STM-1 signals.
l Processes the path overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one to eight channels of ECC communication.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection schemes Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l The N3SLO1 supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting
services.
l The N2SLO1 supports the TCM function.
l The N3SLO1 supports the PRBS function.
l Supports the press-to-collect function in fault data collection.

9.5.4 Working Principle and Signal Flow
The SLO1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, power module, and other modules.
Figure 9-14 shows the functional block diagram of the SLO1.
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Figure 9-14 Functional block diagram of the SLO1
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
LOS
Laser shutdown
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
155 MHz
Reference clock
K1 and K2
insertion/extraction
MSA
IIC
CDR
.

.

.

.
.

.

.

.
CDR
-48 V/-60 V
155 Mbit/s
O/E
E/O
SPI
O/E
SPI
Frame header
Cross-connect
unit
K1 and K2
155
Mbit/s
155 Mbit/s
155 Mbit/s
155 Mbit/s
E/O
Power
module
SCC unit
O/E converting
module
155
Mbit/s
Backplane
155 MHz
PLL
HPT MST RST
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery

The functional modules of the STM-1 units are described as follows:
O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function of shutting down the laser.
CDR Module
This module restores the data signal and the clock signal.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
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l MST sub-module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.
In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.
l MSA sub-module
In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.
l HPT sub-module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
9.5.5 Front Panel
The front panel of the SLO1 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-15 shows the appearance of the front panel of the SLO1.
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Figure 9-15 Front panel of the SLO1
SLO1
SLO1
CLASS 1
LASER
PRODUCT
ACT
PROG
STAT
SRV
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4
O
U
T
5
I
N
5
O
U
T
6
I
N
6
O
U
T
7
I
N
7
O
U
T
8
I
N
8

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SLO1 has eight optical interfaces. Table 9-21 describes the types and
usage of the optical interfaces of the SLO1.
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Table 9-21 Optical interfaces of the SLO1
Interface Type of
Interface
Usage
IN1IN8 LC Receives optical signals.
OUT1OUT8 LC Transmits optical signals.

CAUTION
The optical interfaces of the SLO1 are level optical interfaces. Hence, use an optical attenuator
only on the ODF side.
9.5.6 Valid Slots
The slots valid for the SLO1 vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SLO1 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SLO1 can be installed in slots 18 and
1117. In this case, eight optical interfaces can be configured.
9.5.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLO1 indicates the type of optical interface.
Table 9-22 provides the relationship between the feature code of the SLO1 and the type of optical
interface.
Table 9-22 Relationship between the feature code of the SLO1 and the type of optical interface
Board Feature Code Type of Optical interface
SSN2SLO110 and
SSN3SLO110
10 S-1.1
SSN2SLO111 and
SSN3SLO111
11 L-1.1
SSN2SLO112 and
SSN3SLO112
12 L-1.2
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Board Feature Code Type of Optical interface
SSN2SLO113 and
SSN3SLO113
13 Ve-1.2
SSN2SLO114 and
SSN3SLO114
14 I-1

9.5.8 Parameter Settings
You can set the parameters for the SLO1 by using the T2000.
You can set the following parameters for the SLO1 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.5.9 Technical Specifications
The technical specifications of the SLO1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-23 lists the parameters specified for the optical interfaces of the SLO1.
Table 9-23 Parameters specified for the optical interfaces of the SLO1
Parameter Value
Nominal bit rate 155520 kbit/s
Line code pattern NRZ
Application code I-1.1 S-1.1 L-1.1 L-1.2 Ve-1.2
Transmission
distance (km)
0 to 2 2 to 15 20 to 40 60 to 80 80 to 100
Type of fiber Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-
mode LC
Operating
wavelength range
(nm)
1261 to
1360
1261 to
1360
1263 to
1360
1480 to
1580
1480 to
1580
Launched optical
power range (dBm)
-15 to -8 -15 to -8 -5 to 0 -5 to 0 -3 to 0
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Parameter Value
Receiver sensitivity
(dBm)
-23 -28 -34 -34 -34
Minimum overload
(dBm)
-8 -8 -10 -10 -10
Minimum extinction
ratio (dB)
8.2 8.2 10 10 10

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the N2SLO1 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.1
The mechanical specifications of the N3SLO1 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.2
Power Consumption
The maximum power consumption of the N2SLO1 at room temperature (25C) is 26 W.
The maximum power consumption of the N3SLO1 at room temperature (25C) is 20 W.
9.6 SLT1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLT1 (12xSTM-1 optical interface board).
9.6.1 Version Description
The SLT1 is available in one functional version, namely, N1.
9.6.2 Application
The SLT1 is a line board. The SLT1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SLT1 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLT1 converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
9.6.3 Functions and Features
The SLT1 transmits and receives STM-1 optical signals, performs O/E conversion for the STM-1
optical signals, extracts and inserts overhead bytes, and generates alarm signals on the line.
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9.6.4 Working Principle and Signal Flow
The SLT1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules. The external services
are accessed by the external interface boards EU08 and OU08. The EU08 is an electrical interface
board and the OU08 is an optical interface board.
9.6.5 Front Panel
The front panel of the SLT1 has indicators, interfaces, a bar code, and a laser safety class label.
9.6.6 Valid Slots
The slots valid for the SLT1 vary with the cross-connect capacity of the subrack.
9.6.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLT1 indicates the type of optical interface.
9.6.8 Parameter Settings
You can set the parameters for the SLT1 by using the T2000.
9.6.9 Technical Specifications
The technical specifications of the SLT1 include the parameters specified for optical interfaces,
dimensions, weight, and power consumption.
9.6.1 Version Description
The SLT1 is available in one functional version, namely, N1.
9.6.2 Application
The SLT1 is a line board. The SLT1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical signals. The SLT1 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLT1 converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
Figure 9-16 shows the application of the SLT1. The SLT1 boards can form a ring network or a
chain network in the system.
Figure 9-16 Networking and application of the SLT1
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board
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9.6.3 Functions and Features
The SLT1 transmits and receives STM-1 optical signals, performs O/E conversion for the STM-1
optical signals, extracts and inserts overhead bytes, and generates alarm signals on the line.
Table 9-24 provides the functions and features of the SLT1.
Table 9-24 Functions and features of the SLT1
Function and
Feature
SLT1
Basic functions Transmits and receives 12xSTM-1 optical signals.
Specifications of
the optical
interface
Supports S-1.1, L-1.1 and L-1.2 standard optical interfaces whose
characteristics comply with ITU-T G.957.
Specifications of
the optical
module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
l Supports the usage and detection of the SFP optical module, which
facilitates the maintenance of the optical module.
Service
processing
Supports the VC-12 services, VC-3 services, and VC-4 services.
Overhead
processing
l Processes the section overheads of the STM-1 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one to twelve channels of ECC communication. Port 1 to port
8 support the ECC communication by using bytes D1D12. Port 9 to
port 12 support the ECC communication by using bytes D1D3.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection
schemes
Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP, SNCP,
SNCTP, and SNCMP.
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Function and
Feature
SLT1
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the PRBS function.
l Supports the press-to-collect function in fault data collection.

9.6.4 Working Principle and Signal Flow
The SLT1 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules. The external services
are accessed by the external interface boards EU08 and OU08. The EU08 is an electrical interface
board and the OU08 is an optical interface board.
Figure 9-17 shows the functional block diagram of the SLT1.
Figure 9-17 Functional block diagram of the SLT1
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
LOS
Laser shutdown
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
155 MHz
Reference clock
K1 and K2
insertion/extraction
MSA
IIC
CDR
.

.

.

.
.

.

.

.
CDR
-48 V/-60 V
155 Mbit/s
O/E
E/O
SPI
O/E
SPI
Frame header
Cross-connect
unit
K1 and K2
155
Mbit/s
155 Mbit/s
155 Mbit/s
155 Mbit/s
E/O
Power
module
SCC unit
O/E converting
module
155
Mbit/s
Backplane
155 MHz
PLL
HPT MST RST
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery

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The functional modules of the STM-1 units are described as follows:
O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function of shutting down the laser.
CDR Module
This module restores the data signal and the clock signal.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
l MST sub-module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.
In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.
l MSA sub-module
In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.
l HPT sub-module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
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Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
9.6.5 Front Panel
The front panel of the SLT1 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-18 shows the appearance of the front panel of the SLT1.
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Figure 9-18 Front panel of the SLT1
SLT1
SLT1
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
ACT
PROG
STAT
SRV
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4
O
U
T
5
I
N
5
O
U
T
6
I
N
6
O
U
T
7
I
N
7
O
U
T
8
I
N
8
O
U
T
9
I
N
9
O
U
T
1
0
I
N
1
0
O
U
T
1
1
I
N
1
1
O
U
T
1
2
I
N
1
2

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SLT1 has 12 optical interfaces. Table 9-25 describes the types and usage
of the optical interfaces of the SLT1.
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Table 9-25 Optical interfaces of the SLT1
Interface Type of
Interface
Usage
IN1IN12 LC Receives optical signals.
OUT1OUT12 LC Transmits optical signals.

CAUTION
The optical interfaces of the SLT1 are level optical interfaces. Hence, use an optical attenuator
only on the ODF side.
9.6.6 Valid Slots
The slots valid for the SLT1 vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
l When the cross-connect capacity is 200 Gbit/s, the SLT1 can be installed in slots 18 and
1116. When the SLT1 is installed in slots 14, 15, and 16, one to eight optical interfaces
can be configured. When the SLT1 is installed in slots 58 and 1114, one to twelve optical
interfaces can be configured.
9.6.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLT1 indicates the type of optical interface.
Table 9-26 provides the relationship between the feature code of the SLT1 and the type of optical
interface.
Table 9-26 Relationship between the feature code of the SLT1 and the type of optical interface
Board Feature Code Type of Optical interface
SSN1SLT123 23 S-1.1
SSN1SLT124 24 L-1.1
SSN1SLT125 25 L-1.2

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9.6.8 Parameter Settings
You can set the parameters for the SLT1 by using the T2000.
You can set the following parameters for the SLT1 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.6.9 Technical Specifications
The technical specifications of the SLT1 include the parameters specified for optical interfaces,
dimensions, weight, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-27 lists the parameters specified for the optical interfaces of the SLT1.
Table 9-27 Parameters specified for the optical interfaces of the SLT1
Parameter Value
Nominal bit rate 155520 kbit/s
Line code pattern NRZ
Application code S-1.1 L-1.1 L-1.2
Transmission distance (km) 2 to 15 20 to 40 60 to 80
Type of fiber Single-mode LC Single-mode LC Single-mode LC
Operating wavelength range
(nm)
1261 to 1360 1263 to 1360 1480 to 1580
Launched optical power
range (dBm)
-15 to -8 -5 to 0 -5 to 0
Receiver sensitivity (dBm) -28 -34 -34
Minimum overload (dBm) -8 -10 -10
Minimum extinction ratio
(dB)
8.2 10 10

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
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Mechanical Specifications
The mechanical specifications of the SLT1 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.3
Power Consumption
The maximum power consumption of the SLT1 at room temperature (25C) is 22 W.
9.7 SLH1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SLH1 (16xSTM-1 signal processing board). This topic also
describes how to configure and commission the SLH1.
9.7.1 Version Description
The SLH1 is available in one functional version, namely, N1.
9.7.2 Application
The SLH1 is a line board. The SLH1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical/electrical signals. The SLH1 converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side, or directly sends
the received electrical signals to the cross-connect side. In addition, the SLH1 converts the
electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
9.7.3 Functions and Features
The SLH1 processes STM-1 optical and electrical signals.
9.7.4 Working Principle and Signal Flow
The SLH1 consists of the CDR module, SDH overhead processing module, logic and control
module, and power module. The external services are accessed by the external interface boards
EU08 and OU08. The EU08 is an electrical interface board and the OU08 is an optical interface
board.
9.7.5 Front Panel
The front panel of the SLH1 has indicators and a bar code.
9.7.6 Jumpers and DIP Switches
The SLH1 does not have any jumpers or DIP switches that are used for board settings.
9.7.7 Valid Slots
The SLH1 must be installed in a valid slot in the subrack. Otherwise, the SLH1 cannot work
normally.
9.7.8 Board Protection
The SLH1 supports the 1:N (N3) tributary protection switching (TPS) protection.
9.7.9 Parameter Settings
You can set the parameters for the SLH1 by using the T2000.
9.7.10 Technical Specifications
The technical specifications of the SLH1 include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.
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9.7.1 Version Description
The SLH1 is available in one functional version, namely, N1.
9.7.2 Application
The SLH1 is a line board. The SLH1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical/electrical signals. The SLH1 converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side, or directly sends
the received electrical signals to the cross-connect side. In addition, the SLH1 converts the
electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
Figure 9-19 shows the application of the SLH1. The SLH1 boards can form a ring network or
a chain network in the system.
Figure 9-19 Networking and application of the SLH1
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.7.3 Functions and Features
The SLH1 processes STM-1 optical and electrical signals.
Table 9-28 provides the functions and features of the SLH1.
Table 9-28 Functions and features of the SLH1
Function and
Feature
SLH1
Basic functions Processes 16xSTM-1 signals.
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Function and
Feature
SLH1
Specifications of
the optical
module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
l Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
Service
processing
Supports the VC-12 services, VC-3 services, and VC-4 services.
Overhead
processing
l Processes the section overheads of the STM-1 signals.
l Supports the transparent transmission and termination of the path
overheads. Supports the setting and query of the J0, J1, J2, and C2
bytes.
l Supports one to sixteen channels of ECC communication. Port 1 to
port 8 support the ECC communication by using bytes D1D12. Port
9 to port 16 support the ECC communication by using bytes D1D3.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection
schemes
l Supports the two-fiber ring MSP.
l Supports the four-fiber ring MSP.
l Supports the linear MSP.
l Supports the SNCP.
l Supports the SNCMP.
l Supports the SNCTP.
l Supports the TPS protection when used with the interface board and
the switching and bridging board.
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the press-to-collect function in fault data collection.

When the SLH1 works with different interface boards and electrical interface switching boards,
the access capabilities for the STM-1 signals are different. For details, refer to Table 9-29.
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Table 9-29 Access capabilities of the SLH1 when the SLH1 works with different interface
boards and electrical interface switching boards
Interface Board SLH1
None The SLH1 cannot access signals.
EU08 Accesses and processes 8-channel or 16-channel electrical signals.
OU08
a
Accesses and processes 8-channel or 16-channel optical signals.
EU08 + OU08
a
Accesses and processes 8-channel electrical signals and 8-channel
optical signals.
EU08 + TSB8 Accesses and processes 8-channel or 16-channel STM-1 electrical
signals, and realizes the 1:N (N3) TPS protection.
a: The N2OU08 does not support the usage and monitoring of the SFP optical module.

9.7.4 Working Principle and Signal Flow
The SLH1 consists of the CDR module, SDH overhead processing module, logic and control
module, and power module. The external services are accessed by the external interface boards
EU08 and OU08. The EU08 is an electrical interface board and the OU08 is an optical interface
board.
Figure 9-20 shows the functional block diagram of the SLH1 when the SLH1 works with the
EU08 by describing how to process 1xSTM-1 signals.
Figure 9-20 Functional block diagram of the SLH1 when the SLH1 works with the EU08
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
LOS
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
155 MHz
Reference clock
K1 and K2
insertion/extraction
MST
CDR
.

.

.

.
CDR
-48 V/-60 V
Frame header Cross-connect
unit
K1 and K2
155
Mbit/s
155 Mbit/s
155 Mbit/s
Power
module
SCC unit
155
Mbit/s
Backplane
155 Mbit/s
Encode/
Decode
Transformer
CMI
EU08
SPI
155 Mbit/s
155 MHz
PLL
MSA HPT RST
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination CDR: clock data restoration -

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Figure 9-21 shows the functional block diagram of the SLH1 when the SLH1 works with the
OU08 by describing how to process 1xSTM-1 signals.
Figure 9-21 Functional block diagram of the SLH1 when the SLH1 works with the OU08
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
LOS
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
155 MHz
Reference clock
K1 and K2
insertion/extraction
HPT
CDR
.

.

.

.
CDR
-48 V/-60 V
Frame header Cross-connect
unit
K1 and K2
155
Mbit/s
155 Mbit/s
155 Mbit/s
Power
module
SCC unit
155
Mbit/s
Backplane
155 Mbit/s
OU08
155 Mbit/s
Laser shutdown
SPI
O/E
E/O
155 MHz
PLL
MSA MST RST
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination CDR: clock data restoration -

CDR Module
This module restores the clock signal.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module terminates the RSOH. That is, the RST
sub-module detects the frame alignment bytes (A1 and A2), descrambles all the bytes
except the first line of the RSOH, restores and checks the J0 byte, and checks the B1
byte.
In the transmit direction, the RST sub-module generates the RSOH. That is, the RST
sub-module writes bytes such as A1, A2, and J0, calculates and writes the B1 byte, and
scrambles all the bytes except the first line of the RSOH.
l MST sub-module
In the receive direction, the MST sub-module terminates the MSOH. That is, the MST
sub-module generates the MS_AIS alarm and detects the MS_RDI alarm after detecting
the K2 byte, and detects the MS_REI alarm and generates the B2_EXC alarm after
checking the B2 byte.
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In the transmit direction, the MST sub-module generates the MSOH. That is, the MST
sub-module writes bytes such as E2, D4-D12, K1, K2, S1, and M1, and calculates and
writes the B2 byte.
l MSA sub-module
In the receive direction, the MSA sub-module de-interleaves the AUG, divides an AUG
into N AU-4s, detects the AU_LOP alarm and the AU_AIS alarm, and performs pointer
justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
l HPT sub-module
In the receive direction, the HPT sub-module terminates the POH. That is, the HPT sub-
module detects the HP_REI alarm after checking the B3 byte, generates the HP_TIM
alarm and the HP_SLM alarm and detects the HP_RDI alarm after detecting the J1 and
C2 bytes, and generates the HP_UNEQ alarm after detecting the C2 byte.
In the transmit direction, the HPT sub-module generates the POH. That is, the HPT sub-
module writes bytes such as J1 and C2, and calculates and writes the B3 byte.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not in position.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
9.7.5 Front Panel
The front panel of the SLH1 has indicators and a bar code.
Diagram of the Front Panel
The front panel of the SLH1 does not have an interface. Hence, the SLH1 must be used with the
EU08 or OU08. Figure 9-22 shows the appearance of the front panel of the SLH1.
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Figure 9-22 Front panel of the SLH1
SLH1
SLH1
ACT
PROG
STAT
SRV

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
9.7.6 Jumpers and DIP Switches
The SLH1 does not have any jumpers or DIP switches that are used for board settings.
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9.7.7 Valid Slots
The SLH1 must be installed in a valid slot in the subrack. Otherwise, the SLH1 cannot work
normally.
The slots valid for the SLH1 vary with the cross-connect capacity of the subrack. The SLH1
needs to work with the OU08/EU08 and TSB8. The slots valid for the SLH1 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SLH1 can be installed in slots 25 and
1316.
9.7.8 Board Protection
The SLH1 supports the 1:N (N3) tributary protection switching (TPS) protection.
Protection Principle
The TPS protection is equipment-level protection. When the working board fails, the accessed
signals are switched to the protection board. Hence, complex network-level protection
operations such as the MSP and SNCP are not triggered. In addition, the reliability of the
equipment is enhanced.
The SLH1 can work with the EU08 and TSB8 to realize the 1:N (N3) TPS protection for
8xSTM-1 or 16xSTM-1 electrical signals. Figure 9-23 shows the TPS protection provided by
the SLH1.
Figure 9-23 TPS protection provided by the SLH1
I
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Service signal
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l Normal state
When each working board functions normally, the traffic signal is directly transmitted to
the corresponding working board through position 1 of the control switch on the interface
board.
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l Switching state
When a working board detects a failure and requires the switching operation, the control
switch of the corresponding interface board switches from position 1 to position 2. At the
same time, the control switch of the protection switching board switches to the
corresponding position so that the protection board can protect the failed working board.
Hardware Configuration
Figure 9-24 shows the slot configuration for two 1:3 TPS protection groups for 16xSTM-1
signals of the SLH1.
Figure 9-24 Slot configuration for two 1:3 TPS protection groups of the SLH1
S
L
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9
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1

In Figure 9-24, the board in slot 2 protects the boards in slots 35. The board in slot 16 protects
the boards in slots 1315.
Table 9-30 lists the slots for the SLH1, EU08, and TSB8.
OptiX OSN 3500 Intelligent Optical Transmission System
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Table 9-30 Slots for the SLH1, EU08, and TSB8
Board Protection Group 1 Protection Group 2
SLH1 (protection
board)
Slot 2 Slot 16
TSB8 Slots 1920 Slots 3536
SLH1 (working
board)
Slots 35 Slots 1315
EU08 Slots 2126 Slots 2934

NOTE
When the equipment is configured for two 1:3 TPS protection groups for 8xSTM-1 signals of the SLH1,
the TSB8 and EU08 can be inserted only in the odd slots.
9.7.9 Parameter Settings
You can set the parameters for the SLH1 by using the T2000.
You can set the following parameters for the SLH1 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.7.10 Technical Specifications
The technical specifications of the SLH1 include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-31 lists the parameters specified for the optical interfaces of the SLH1.
Table 9-31 Technical specifications of the SLH1
Parameter Value
Nominal bit rate 155520 kbit/s
Line code pattern Coded mark inversion (CMI) and NRZ

Mechanical Specifications
The mechanical specifications of the SLH1 are as follows:
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l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the SLH1 at room temperature (25C) is 27 W.
9.8 SEP1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SEP1 (2xSTM-1 line processing board). This topic also describes
how to configure and commission the SEP1.
9.8.1 Version Description
The SEP1 is available in one functional version, namely, N1.
9.8.2 Application
The SEP1 is a line board. The SEP1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical/electrical signals. The SEP1 converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side, or directly sends
the received electrical signals to the cross-connect side. In addition, the SEP1 converts the
electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
9.8.3 Functions and Features
The SEP1 processes STM-1 signals. When the interfaces are available on the front panel of the
SEP1 (the logical board of the SEP1 is displayed as SEP1 on the T2000), the SEP1 processes
2xSTM-1 electrical signals. In this case, the SEP1 is a 2xSTM-1 signal processing board. When
the SEP1 is used with the interface board (the logical board of the SEP1 is displayed as SEP on
the T2000), the SEP1 processes 8xSTM-1 optical signals or 8xSTM-1 electrical signals. In this
case, the SEP1 is an 8xSTM-1 signal processing board. The physical boards of the two types of
logical boards (SEP1 and SEP) are the same and are the SEP1. When the logical boards need
not be differentiated, both the SEP1 and SEP are defined as SEP1.
9.8.4 Working Principle and Signal Flow
The SEP1 consists of the line interface module, CDR module, SDH overhead processing module,
logic and control module, and power module. The external services are accessed by the external
interface boards EU04, EU08, and OU08. The EU04 and EU08 are electrical interface boards
and the OU08 is an optical interface board.
9.8.5 Front Panel
The front panel of the SEP1 has indicators, interfaces, and a bar code.
9.8.6 Jumpers and DIP Switches
The SEP1 does not have any jumpers or DIP switches that are used for board settings.
9.8.7 Valid Slots
The SEP1 must be installed in a valid slot in the subrack. Otherwise, the SEP1 cannot work
normally.
9.8.8 Board Protection
The TPS protection is equipment-level protection. When the working board fails, the accessed
services are switched to the protection board. Hence, complex network-level protection
operations such as the MSP and SNCP are not triggered. In addition, the reliability of the
equipment is enhanced.
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9.8.9 Feature Code
The IFSD1 does not have a feature code.
9.8.10 Parameter Settings
You can set the parameters for the SEP1 by using the T2000.
9.8.11 Technical Specifications
The technical specifications of the SEP1 include the parameters specified for interfaces,
mechanical specifications, and power consumption.
9.8.1 Version Description
The SEP1 is available in one functional version, namely, N1.
9.8.2 Application
The SEP1 is a line board. The SEP1 can be used on the OptiX OSN equipment series to transmit
and receive STM-1 optical/electrical signals. The SEP1 converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side, or directly sends
the received electrical signals to the cross-connect side. In addition, the SEP1 converts the
electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
Figure 9-25 shows the application of the SEP1. The SEP1 boards can form a ring network or a
chain network in the system.
Figure 9-25 Networking and application of the SEP1
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.8.3 Functions and Features
The SEP1 processes STM-1 signals. When the interfaces are available on the front panel of the
SEP1 (the logical board of the SEP1 is displayed as SEP1 on the T2000), the SEP1 processes
2xSTM-1 electrical signals. In this case, the SEP1 is a 2xSTM-1 signal processing board. When
the SEP1 is used with the interface board (the logical board of the SEP1 is displayed as SEP on
the T2000), the SEP1 processes 8xSTM-1 optical signals or 8xSTM-1 electrical signals. In this
case, the SEP1 is an 8xSTM-1 signal processing board. The physical boards of the two types of
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logical boards (SEP1 and SEP) are the same and are the SEP1. When the logical boards need
not be differentiated, both the SEP1 and SEP are defined as SEP1.
Table 9-32 provides the functions and features of the SEP1.
Table 9-32 Functions and features of the SEP1
Function and
Feature
SEP1
Basic functions l Processes 2xSTM-1 signals when the interfaces are available on the
front panel.
l Processes 8xSTM-1 signals when the SEP1 works with an interface
board.
Specifications of
the optical
module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
l Supports the usage and monitoring of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
Service
processing
Supports the VC-12 services, VC-3 services, and VC-4 services.
Overhead
processing
l Processes the section overheads of the STM-1 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one or two channels of ECC communication.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection
schemes
l Supports the two-fiber ring MSP.
l Supports the four-fiber ring MSP.
l Supports the linear MSP.
l Supports the SNCP.
l Supports the SNCMP.
l Supports the SNCTP.
l Supports the TPS protection when used with the interface board and
the switching and bridging board.
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Function and
Feature
SEP1
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the press-to-collect function in fault data collection.

When the SEP1 works with different interface boards and electrical interface switching boards,
the access capabilities for the STM-1 signals are different. For details, refer to Table 9-33.
Table 9-33 Access capabilities of the SEP1 when the SEP1 works with different interface boards
and electrical interface switching boards
Interface Board SEP1
None Accesses and processes 2xSTM-1 electrical signals, but does not
support the TPS protection.
EU04 Accesses and processes 4xSTM-1 electrical signals. One SEP1 can be
configured with a maximum of two EUO4 interface boards at the same
time.
EU08 Accesses and processes 8xSTM-1 electrical signals.
OU08 Accesses and processes 8xSTM-1 optical signals.
EU08 + OU08 Cannot work with the EU08 and OU08 at the same time.
EU04+TSB4 Accesses and processes 4xSTM-1 electrical signals, and supports the
TPS protection.
EU08 + TSB8 Accesses and processes 8xSTM-1 electrical signals, and supports the
TPS protection.

CAUTION
When the SEP1 works with an interface board, the two interfaces on the front panel of the SEP1
are invalid. The SEP1 cannot work with the EU08 and OU08 at the same time.
NOTE
When the cross-connect capability of the cross-connect board is 40Gbit/s, the SEP cannot work with the
EU08 or OU08.
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9.8.4 Working Principle and Signal Flow
The SEP1 consists of the line interface module, CDR module, SDH overhead processing module,
logic and control module, and power module. The external services are accessed by the external
interface boards EU04, EU08, and OU08. The EU04 and EU08 are electrical interface boards
and the OU08 is an optical interface board.
Figure 9-26 shows the functional block diagram of the SEP1.
Figure 9-26 Functional block diagram of the SEP1
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
SDH overhead
processing module
DCC
SCC unit
LOS
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
155 MHz
Reference clock
K1 and K2
insertion/extraction
HPT MST RST
CDR
.

.

.

.
CDR
-48 V/-60 V
Frame header Cross-connect
unit
K1 and K2
155 Mbit/s
155 Mbit/s
Power
module
SCC unit
155
Mbit/s
Backplane
Port 1
Port 2
CMI NRZ
CMI Encode/
Decode
Transformer
SPI
Encode/
Decode
Transformer
155 Mbit/s
155 Mbit/s
155 Mbit/s
155 Mbit/s
NRZ
155
Mbit/s
155 MHz
PLL
MSA
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination CDR: clock data restoration -

Figure 9-27 shows the functional block diagram of the SEP when the SEP works with the EU08.
When the SEP works with the EU04, the function block diagram is the same except that the
number of signals accessed and processed by the SEP is different.
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Figure 9-27 Functional block diagram of the SEP when the SEP works with the EU08
Logic and
control module
+3.3 V backup power
LOS
Communication
+3.3 V -48 V/-60 V
Power
module
Fuse
Fuse
-48 V/-60 V
Frame header Cross-connect
unit
Power
module
SCC unit
CMI
Encode/
Decode
Transformer
CMI
Port 1
Port 8
EU08
SPI
Transformer
Encode/
Decode
CDR
CDR
155 Mbit/s
155 Mbit/s
155 Mbit/s
155 Mbit/s
155 Mbit/s
Cross-connect
unit A
SDH overhead
processing module
DCC
SCC unit
High-speed
bus
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
Reference clock
K1 and K2
insertion/extraction
MSA HPT MST RST
K1 and K2
Backplane
155 Mbit/s
155 Mbit/s
155 Mbit/s
155 MHz
PLL
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination CDR: clock data restoration -

Figure 9-28 shows the functional block diagram of the SEP when the SEP works with the OU08.
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Figure 9-28 Functional block diagram of the SEP when the SEP works with the OU08
Logic and
control module
+3.3 V backup power
Communication
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
-48 V/-60 V
Frame header
Cross-connect
unit
Power
module
SCC unit
Cross-connect
unit A
SDH overhead
processing module
DCC
SCC unit
High-speed
bus
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
155 MHz
PLL
Cross-connect
unit
Reference clock
K1 and K2
insertion/extraction
MSA HPT MST RST
K1 and K2
Backplane
155
Mbit/s
LOS
Laser shutdown
Port 1
Port 8
O/E
OU08
NRZ
NRZ
SP
I
155 Mbit/s
155
Mbit/s
155 Mbit/s
155
Mbit/s
155
Mbit/s
155
Mbit/s
155
Mbit/s
CDR
CDR
E/O
O/E
E/O
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination CDR: clock data restoration -

Line Interface Module and CDR Module
l In the receive direction, the received electrical signals (CMI codes) are isolated through
the converter and then transmitted to the decoding unit. The CDR module restores the clock
signals after decoding.
l In the transmit direction, the SDH signals, which are processed by the SDH overhead
processing module, are transmitted to the encoding unit. The converter isolates the 155
Mbit/s electrical signals (CMI codes) and sends the signals. The encoding and decoding
units monitor R_LOS alarms.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module terminates the RSOH. That is, the RST
sub-module detects the frame alignment bytes (A1 and A2), descrambles all the bytes
except the first line of the RSOH, restores and checks the J0 byte, and checks the B1
byte.
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In the transmit direction, the RST sub-module generates the RSOH. That is, the RST
sub-module writes bytes such as A1, A2, and J0, calculates and writes the B1 byte, and
scrambles all the bytes except the first line of the RSOH.
l MST sub-module
In the receive direction, the MST sub-module terminates the MSOH. That is, the MST
sub-module generates the MS_AIS alarm and detects the MS_RDI alarm after detecting
the K2 byte, and detects the MS_REI alarm and generates the B2_EXC alarm after
checking the B2 byte.
In the transmit direction, the MST sub-module generates the MSOH. That is, the MST
sub-module writes bytes such as E2, D4-D12, K1, K2, S1, and M1, and calculates and
writes the B2 byte.
l MSA sub-module
In the receive direction, the MSA sub-module de-interleaves the AUG, divides an AUG
into N AU-4s, detects the AU_LOP alarm and the AU_AIS alarm, and performs pointer
justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
l HPT sub-module
In the receive direction, the HPT sub-module terminates the POH. That is, the HPT sub-
module detects the HP_REI alarm after checking the B3 byte, generates the HP_TIM
alarm and the HP_SLM alarm and detects the HP_RDI alarm after detecting the J1 and
C2 bytes, and generates the HP_UNEQ alarm after detecting the C2 byte.
In the transmit direction, the HPT sub-module generates the POH. That is, the HPT sub-
module writes bytes such as J1 and C2, and calculates and writes the B3 byte.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and the standby cross-connect unit.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not in position.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
9.8.5 Front Panel
The front panel of the SEP1 has indicators, interfaces, and a bar code.
Diagram of the Front Panel
Figure 9-29 shows the appearance of the front panel of the SEP1.
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Figure 9-29 Front panel of the SEP1
SEP1
SEP1
ACT
PROG
STAT
SRV
A
O
U
T
A
I
N
B
O
U
T
B
I
N

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SEP1 has two pairs of electrical interfaces. Table 9-34 describes the types
and usage of the electrical interfaces of the SEP1.
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Table 9-34 Electrical interfaces of the SEP1
Interface Type of Interface Usage
AINBIN 75-ohm SMB Receives the STM-1 signals.
AOUTBOUT 75-ohm SMB Transmits the STM-1 signals.
Note: The SEP1 can be used with the interface board EU04, EU08, or OU08. In this case, the
SEP1 is defined as SEP. When the SEP1 is used with the interface board, the two interfaces
on the front panel are invalid.

9.8.6 Jumpers and DIP Switches
The SEP1 does not have any jumpers or DIP switches that are used for board settings.
9.8.7 Valid Slots
The SEP1 must be installed in a valid slot in the subrack. Otherwise, the SEP1 cannot work
normally.
NOTE
When the SEP1 is used with the interface board, the logical board of the SEP1 is displayed as SEP on the
T2000.
The slots valid for the SEP1 are as follows:
l When the SEP1 is connected to cables by using the interfaces on its front panel, the SEP1
can be installed in slots 16 and 1316 in the subrack.
l When the SEP1 is used with the interface board, the SEP1 can be installed in slots 25 and
1316 in the subrack.
9.8.8 Board Protection
The TPS protection is equipment-level protection. When the working board fails, the accessed
services are switched to the protection board. Hence, complex network-level protection
operations such as the MSP and SNCP are not triggered. In addition, the reliability of the
equipment is enhanced.
NOTE
When the SEP1 is used with the interface board, the logical board of the SEP1 is displayed as SEP on the
T2000.
Protection Principle
The SEP can work with the EU08 and TSB8 to provide two 1:N (N3) TPS protection groups
for 8xSTM-1 electrical signals.
The SEP can also work with the EU04 and TSB4 to provide two 1:N (N3) TPS protection
groups for 4xSTM-1 electrical signals.
When the SEP works with the EU08 and TSB8 to realize the TPS protection, the protection
principle and valid slots of the involved boards are the same as the protection principle and valid
slots of the involved boards when the SEP works with the EU04 and TSB4 to realize the TPS
protection. Figure 9-30 shows the TPS protection provided by the SEP.
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Figure 9-30 TPS protection provided by the SEP
I
n
t
e
r
f
a
c
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b
o
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1
Failed
C
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a
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b
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Switching
control bus
Service signal
N 1 1 2 1 2
P
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N
Service signal

l Normal state
When each working board functions normally, the traffic signal is directly transmitted to
the corresponding working board through position 1 of the control switch on the interface
board.
l Switching state
When a working board detects a failure and requires the switching operation, the control
switch of the corresponding interface board switches from position 1 to position 2. At the
same time, the control switch of the protection switching board switches to the
corresponding position so that the protection board can protect the failed working board.
Hardware Configuration
Figure 9-31 shows the slot configuration for the two 1:3 TPS protection groups of the SEP.
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Figure 9-31 Slot configuration for the two 1:3 TPS protection groups of the SEP
S
L
O
T
9
S
L
O
T
1
0
X
C
S
FAN
S
L
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2
S
L
O
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3
S
L
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4
S
L
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5
S
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6
S
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3
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FAN FAN
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Fiber routing area
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2
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2

In Figure 9-31, the board in slot 2 protects the boards in slots 35. The board in slot 16 protects
the boards in slots 1315.
Table 9-35 lists the slots for the SEP, EU08, and TSB8.
Table 9-35 Slots for the SEP, EU08, and TSB8
Board Protection Group 1 Protection Group 2
SEP (working board) Slot 2 Slot 16
TSB8 Slot 19 Slot 35
SEP (working board) Slots 35 Slots 1315
EU08 Slots 21, 23, and 25 Slots 29, 31, and 33

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9.8.9 Feature Code
The IFSD1 does not have a feature code.
9.8.10 Parameter Settings
You can set the parameters for the SEP1 by using the T2000.
You can set the following parameters for the SEP1 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.8.11 Technical Specifications
The technical specifications of the SEP1 include the parameters specified for interfaces,
mechanical specifications, and power consumption.
Parameters Specified for Interfaces
Table 9-36 lists the parameters specified for the interfaces of the SEP1.
Table 9-36 Parameters specified for the interfaces of the SEP1
Parameter Value
Nominal bit rate 155520 kbit/s
Line code pattern CMI and NRZ
Connector SMB

Mechanical Specifications
The mechanical specifications of the SEP1 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the SEP1 at room temperature (25C) is 17 W.
9.9 SL4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL4 (1xSTM-4 optical interface board).
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9.9.1 Version Description
The SL4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SL4 is no longer manufactured.
9.9.2 Application
The SL4 is a line board. The SL4 can be used on the OptiX OSN equipment series to transmit
and receive STM-4 optical signals. The SL4 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SL4 converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
9.9.3 Functions and Features
The SL4 transmits and receives 1xSTM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
9.9.4 Working Principle and Signal Flow
The SL4 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
9.9.5 Front Panel
The front panel of the SL4 has indicators, interfaces, a bar code, and a laser safety class label.
9.9.6 Valid Slots
The slots valid for the SL4 vary with the cross-connect capacity of the subrack.
9.9.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL4 indicates the type of optical interface.
9.9.8 Parameter Settings
You can set the parameters for the SL4 by using the T2000.
9.9.9 Technical Specifications
The technical specifications of the SL4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.9.1 Version Description
The SL4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SL4 is no longer manufactured.
Table 9-37 describes the versions of the SL4.
Table 9-37 Versions of the SL4
Item Description
Functional versions The SL4 is available in two functional versions, namely, N1 and N2.
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Item Description
Differences l The N2SL4 supports the TCM function and AU-3 services, but the
TCM function and AU-3 services cannot be available at the same
time.
l The N1SL4 does not support the TCM function or AU-3 services.
Substitution Through the board version replacement function, the N1SL4A can
substitute for the N1SL4.

NOTE
When you configure the MSP or SNCP, you cannot configure the N1SL4 as the protection board if the
working board is the N2SL4 on which the TCM function is enabled or AU-3 services are configured.
Otherwise, the services are interrupted when a switching operation is performed.
9.9.2 Application
The SL4 is a line board. The SL4 can be used on the OptiX OSN equipment series to transmit
and receive STM-4 optical signals. The SL4 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SL4 converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
Figure 9-32 shows the application of the SL4. The SL4 boards can form a ring network or a
chain network in the system.
Figure 9-32 Networking and application of the SL4
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.9.3 Functions and Features
The SL4 transmits and receives 1xSTM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
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Table 9-38 provides the functions and features of the SL4.
Table 9-38 Functions and features of the SL4
Function and
Feature
SL4
Basic functions Receives and transmits 1xSTM-4 optical signals, and processes
1xSTM-4 standard or concatenation services.
Specifications of
the optical
interface
l Supports different types of standard optical interfaces, namely, the
I-4, S-4.1, L-4.1, L-4.2, and Ve-4.2.
l The characteristics of the optical interfaces of the I-4, S-4.1, L-4.1,
and L-4.2 types comply with ITU-T G.957.
l The characteristics of the optical interface of the Ve-4.2 type comply
with the standards defined by Huawei.
Specifications of
the optical module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
l Supports the usage and monitoring of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
Service
processing
l Supports the VC-12 services, VC-3 services, VC-4 services, and
VC-4-4c concatenation services.
l The N2SL4 supports the AU-3 services.
Overhead
processing
l Processes the section overheads of the STM-4 signals.
l Supports the transparent transmission and termination of the path
overheads. Supports the setting and query of the J0, J1, J2, and C2
bytes.
l Supports one channel of ECC communication.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection
schemes
l Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.
l Supports the fiber-shared MSP and SNCP and processes two sets of
K bytes. One SL4 supports a maximum of two MSP protection rings.
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Function and
Feature
SL4
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l The N1SL4 supports inloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l The N2SL4 supports the TCM function.
l Supports the press-to-collect function in fault data collection.

9.9.4 Working Principle and Signal Flow
The SL4 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 9-33 shows the functional block diagram of the .SL4
Figure 9-33 Functional block diagram of the SL4
Logic and
control
module
Cross-connect unit A
+3.3 V backup power
+3.3 V
SDH overhead processing module
DCC
SCC unit
LOS
Laser shutdown SCC unit
Communication
High-speed bus
+3.3 V
-48 V/ -60 V
DC/DC
converter
Fuse
Fuse
DC/DC
converter
Cross-connect unit
Cross-connect unit B
High-speed
bus
155 MHz
PLL
Cross-connect unit
155 MHz Reference clock
K1 and K2 insertion/extraction
MSA HPT MST RST
IIC
CDR
.

.

.

.
.

.

.

.
CDR
-48 V/ -60 V
O/E
E/O
S
P
I
O/E
E/O
622 Mbit/s
S
P
I
Frame header
Cross-connect unit
K1 and K2
622 Mbit/s
622 Mbit/s
622 Mbit/s
622
Mbit/s
622
Mbit/s
622 Mbit/s
622 Mbit/s
622
Mbit/s
622
Mbit/s
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery

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The functional modules of the STM-4 units are described as follows:
O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function of shutting down the laser.
CDR Module
This module restores the data signal and the clock signal.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
l MST sub-module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.
In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.
l MSA sub-module
In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.
l HPT sub-module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
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Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
9.9.5 Front Panel
The front panel of the SL4 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-34 shows the appearance of the front panel of the SL4.
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Figure 9-34 Front panel of the SL4
SL4
SL4
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SL4 has one optical interface. Table 9-39 describes the types and usage
of the optical interfaces of the SL4.
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Table 9-39 Optical interfaces of the SL4
Interface Type of
Interface
Usage
IN LC Receives optical signals.
OUT LC Transmits optical signals.

The SL4 can use the swappable optical modules to facilitate maintenance.
9.9.6 Valid Slots
The slots valid for the SL4 vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SL4 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SL4 can be installed in slots 18 and
1117.
9.9.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL4 indicates the type of optical interface.
Table 9-40 provides the relationship between the feature code of the SL4 and the type of optical
interface.
Table 9-40 Relationship between the feature code of the SL4 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SL410 and
SSN2SL410
10 S-4.1
SSN1SL411 and
SSN2SL411
11 L-4.1
SSN1SL412 and
SSN2SL412
12 L-4.2
SSN1SL413 and
SSN2SL413
13 Ve-4.2
SSN1SL414 and
SSN2SL414
14 I-4

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9.9.8 Parameter Settings
You can set the parameters for the SL4 by using the T2000.
You can set the following parameters for the SL4 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.9.9 Technical Specifications
The technical specifications of the SL4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-41 lists the parameters specified for the optical interfaces of the SL4.
Table 9-41 Parameters specified for the optical interfaces of the SL4
Parameter Value
Nominal bit rate 622080 kbit/s
Line code pattern NRZ
Application code I-4 S-4.1 L-4.1 L-4.2 Ve-4.2
Transmission
distance (km)
0 to 2 2 to 15 20 to 40 50 to 80 80 to 100
Type of fiber Single-mode
LC
Single-mode
LC
Single-
mode LC
Single-
mode LC
Single-
mode LC
Operating
wavelength range
(nm)
1261 to 1360 1274 to 1356 1280 to
1335
1480 to
1580
1480 to
1580
Launched optical
power range
(dBm)
-15 to -8 -15 to -8 -3 to +2 -3 to +2 -3 to +2
Receiver
sensitivity (dBm)
-23 -28 -28 -28 -34
Minimum
overload (dBm)
-8 -8 -8 -8 -13
Minimum
extinction ratio
(dB)
8.2 8.2 10 10 10.5

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Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the N1SL4 and N2SL4 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight of the N1SL4 (kg): 0.6
l Weight of the N2SL4 (kg): 1.0
Power Consumption
The maximum power consumption of the N1SL4 at room temperature (25C) is 17 W.
The maximum power consumption of the N2SL4 at room temperature (25C) is 15 W.
9.10 SL4A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL4A (1xSTM-4 optical interface board).
9.10.1 Version Description
The SL4A is available in one functional version, namely, N1.
9.10.2 Application
The SL4A is a line board. The SL4A can be used on the OptiX OSN equipment series to transmit
and receive STM-4 optical signals. The SL4A converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SL4A converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
9.10.3 Functions and Features
The SL4A transmits and receives 1xSTM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
9.10.4 Working Principle and Signal Flow
The SL4A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
9.10.5 Front Panel
The front panel of the SL4A has indicators, interfaces, a bar code, and a laser safety class label.
9.10.6 Valid Slots
The slots valid for the SL4A vary with the cross-connect capacity of the subrack.
9.10.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL4A indicates the type of optical interface.
9.10.8 Parameter Settings
You can set the parameters for the SL4A by using the T2000.
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9.10.9 Technical Specifications
The technical specifications of the SL4A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.10.1 Version Description
The SL4A is available in one functional version, namely, N1.
9.10.2 Application
The SL4A is a line board. The SL4A can be used on the OptiX OSN equipment series to transmit
and receive STM-4 optical signals. The SL4A converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SL4A converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
Figure 9-35 shows the application of the SL4A. The SL4A boards can form a ring network or
a chain network in the system.
Figure 9-35 Networking and application of the SL4A
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.10.3 Functions and Features
The SL4A transmits and receives 1xSTM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 9-42 provides the functions and features of the SL4A.
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Table 9-42 Functions and features of the SL4A
Function and
Feature
SL4A
Basic functions Receives and transmits 1xSTM-4 optical signals, and processes
1xSTM-4 standard or concatenation services.
Specifications of
the optical
interface
l Supports different types of standard optical interfaces, namely, the
I-4, S-4.1, L-4.1, L-4.2, and Ve-4.2.
l The characteristics of the optical interfaces of the I-4, S-4.1, L-4.1,
and L-4.2 types comply with ITU-T G.957.
l The characteristics of the optical interface of the Ve-4.2 type comply
with the standards defined by Huawei.
Specifications of
the optical module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
l Supports the usage and monitoring of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
Service
processing
Supports the VC-12 services, VC-3 services, VC-4 services, and
VC-4-4c concatenation services.
Overhead
processing
l Processes the section overheads of the STM-4 signals.
l Supports the transparent transmission and termination of the path
overheads. Supports the setting and query of the J0, J1, J2, and C2
bytes.
l Supports one channel of ECC communication.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection
schemes
l Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.
l Supports the fiber-shared MSP and SNCP and processes two sets of
K bytes. One SL4A supports a maximum of two MSP protection rings.
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the press-to-collect function in fault data collection.

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9.10.4 Working Principle and Signal Flow
The SL4A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 9-36 shows the functional block diagram of the SL4A.
Figure 9-36 Functional block diagram of the SL4A
Logic and
control
module
Cross-connect unit A
+3.3 V backup power
+3.3 V
SDH overhead processing module
DCC
SCC unit
LOS
Laser shutdown SCC unit
Communication
High-speed bus
+3.3 V
-48 V/ -60 V
DC/DC
converter
Fuse
Fuse
DC/DC
converter
Cross-connect unit
Cross-connect unit B
High-speed
bus
155 MHz
PLL
Cross-connect unit
155 MHz Reference clock
K1 and K2 insertion/extraction
MSA HPT MST RST
IIC
CDR
.

.

.

.
.

.

.

.
CDR
-48 V/ -60 V
O/E
E/O
S
P
I
O/E
E/O
622 Mbit/s
S
P
I
Frame header
Cross-connect unit
K1 and K2
622 Mbit/s
622 Mbit/s
622 Mbit/s
622
Mbit/s
622
Mbit/s
622 Mbit/s
622 Mbit/s
622
Mbit/s
622
Mbit/s
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery

The functional modules of the STM-4 units are described as follows:
O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function of shutting down the laser.
CDR Module
This module restores the data signal and the clock signal.
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SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
l MST sub-module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.
In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.
l MSA sub-module
In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.
l HPT sub-module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
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9.10.5 Front Panel
The front panel of the SL4A has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-37 shows the appearance of the front panel of the SL4A.
Figure 9-37 Front panel of the SL4A
SL4A
SL4A
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
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l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SL4A has one optical interface. Table 9-43 describes the types and usage
of the optical interfaces of the SL4A.
Table 9-43 Optical interfaces of the SL4A
Interface Type of
Interface
Usage
IN LC Receives optical signals.
OUT LC Transmits optical signals.

The SL4A can use the swappable optical modules to facilitate maintenance.
9.10.6 Valid Slots
The slots valid for the SL4A vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SL4A are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SL4A can be installed in slots 18 and
1117.
9.10.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL4A indicates the type of optical interface.
Table 9-44 provides the relationship between the feature code of the SL4A and the type of optical
interface.
Table 9-44 Relationship between the feature code of the SL4A and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SL4A10 10 S-4.1
SSN1SL4A11 11 L-4.1
SSN1SL4A12 12 L-4.2
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Board Feature Code Type of Optical Interface
SSN1SL4A13 13 Ve-4.2
SSN1SL4A14 14 I-4

9.10.8 Parameter Settings
You can set the parameters for the SL4A by using the T2000.
You can set the following parameters for the SL4A by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.10.9 Technical Specifications
The technical specifications of the SL4A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-45 lists the parameters specified for the optical interfaces of the SL4A.
Table 9-45 Parameters specified for the optical interfaces of the SL4A
Parameter Value
Nominal bit rate 622080 kbit/s
Line code pattern NRZ
Application code I-4 S-4.1 L-4.1 L-4.2 Ve-4.2
Transmission
distance (km)
0 to 2 2 to 15 20 to 40 50 to 80 80 to 100
Type of fiber Single-mode
LC
Single-mode
LC
Single-
mode LC
Single-
mode LC
Single-
mode LC
Operating
wavelength range
(nm)
1261 to 1360 1274 to 1356 1280 to
1335
1480 to
1580
1480 to
1580
Launched optical
power range
(dBm)
-15 to -8 -15 to -8 -3 to +2 -3 to +2 -3 to +2
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Parameter Value
Receiver
sensitivity (dBm)
-23 -28 -28 -28 -34
Minimum
overload (dBm)
-8 -8 -8 -8 -13
Minimum
extinction ratio
(dB)
8.2 8.2 10 10 10.5

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SL4A are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.6
Power Consumption
The maximum power consumption of the SL4A at room temperature (25C) is 17 W.
9.11 SLD4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLD4 (2xSTM-4 optical interface board).
9.11.1 Version Description
The SLD4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SLD4 is no longer manufactured.
9.11.2 Application
The SLD4 is a line board. The SLD4 can be used on the OptiX OSN equipment series to transmit
and receive STM-4 optical signals. The SLD4 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLD4 converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
9.11.3 Functions and Features
The SLD4 transmits and receives 2xSTM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
9.11.4 Working Principle and Signal Flow
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The SLD4 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
9.11.5 Front Panel
The front panel of the SLD4 has indicators, interfaces, a bar code, and a laser safety class label.
9.11.6 Valid Slots
The slots valid for the SLD4 vary with the cross-connect capacity of the subrack.
9.11.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLD4 indicates the type of optical interface.
9.11.8 Parameter Settings
You can set the parameters for the SLD4 by using the T2000.
9.11.9 Technical Specifications
The technical specifications of the SLD4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.11.1 Version Description
The SLD4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SLD4 is no longer manufactured.
Table 9-46 describes the versions of the SLD4.
Table 9-46 Versions of the SLD4
Item Description
Functional versions The SLD4 is available in two functional versions, namely, N1 and
N2.
Differences l The N2SLD4 supports the TCM function and AU-3 services, but
the TCM function and AU-3 services cannot be available at the
same time.
l The N1SLD4 does not support the TCM function or AU-3
services.
Substitution The versions cannot be substituted with each other.

NOTE
When you configure the MSP or SNCP, you cannot configure the N1SLD4 as the protection board if the
working board is the N2SLD4 on which the TCM function is enabled or AU-3 services are configured.
Otherwise, the services are interrupted when a switching operation is performed.
9.11.2 Application
The SLD4 is a line board. The SLD4 can be used on the OptiX OSN equipment series to transmit
and receive STM-4 optical signals. The SLD4 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLD4 converts
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the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
Figure 9-38 shows the application of the SLD4. The SLD4 boards can form a ring network or
a chain network in the system.
Figure 9-38 Networking and application of the SLD4
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.11.3 Functions and Features
The SLD4 transmits and receives 2xSTM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 9-47 provides the functions and features of the SLD4.
Table 9-47 Functions and features of the SLD4
Function and
Feature
SLD4
Basic functions Receives and transmits 2xSTM-4 optical signals, and processes
2xSTM-4 standard or concatenation services.
Specifications of
the optical
interface
l Supports different types of standard optical interfaces, namely, the
I-4, S-4.1, L-4.1, L-4.2, and Ve-4.2.
l The characteristics of the optical interfaces of the I-4, S-4.1, L-4.1,
and L-4.2 types comply with ITU-T G.957.
l The characteristics of the optical interface of the Ve-4.2 type comply
with the standards defined by Huawei.
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Function and
Feature
SLD4
Specifications of
the optical module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
l Supports the usage and monitoring of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
Service
processing
l Supports the VC-12 services, VC-3 services, VC-4 services, and
VC-4-4c concatenation services.
l The N2SLD4 supports the AU-3 services.
Overhead
processing
l Processes the section overheads of the STM-4 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one or two channels of ECC communication.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection
schemes
l Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.
l Supports the fiber-shared MSP and SNCP and processes four sets of
K bytes. A single optical interface supports two MSP protection rings,
and one SLD4 supports a maximum of four MSP protection rings.
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l The N1SLD4 supports inloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l The N2SLD4 supports the TCM function.
l Supports the press-to-collect function in fault data collection.

9.11.4 Working Principle and Signal Flow
The SLD4 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 9-39 shows the functional block diagram of the SLD4.
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Figure 9-39 Functional block diagram of the SLD4
Logic and
control
module
Cross-connect unit A
+3.3 V backup power
+3.3 V
SDH overhead processing module
DCC
SCC unit
LOS
Laser shutdown SCC unit
Communication
High-speed bus
+3.3 V
-48 V/ -60 V
DC/DC
converter
Fuse
Fuse
DC/DC
converter
Cross-connect unit
Cross-connect unit B
High-speed
bus
155 MHz
PLL
Cross-connect unit
155 MHz Reference clock
K1 and K2 insertion/extraction
MSA HPT MST RST
IIC
CDR
.

.

.

.
.

.

.

.
CDR
-48 V/ -60 V
O/E
E/O
S
P
I
O/E
E/O
622 Mbit/s
S
P
I
Frame header
Cross-connect unit
K1 and K2
622 Mbit/s
622 Mbit/s
622 Mbit/s
622
Mbit/s
622
Mbit/s
622 Mbit/s
622 Mbit/s
622
Mbit/s
622
Mbit/s
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery

The functional modules of the STM-4 units are described as follows:
O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function of shutting down the laser.
CDR Module
This module restores the data signal and the clock signal.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
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In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
l MST sub-module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.
In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.
l MSA sub-module
In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.
l HPT sub-module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
9.11.5 Front Panel
The front panel of the SLD4 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-40 shows the appearance of the front panel of the SLD4.
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Figure 9-40 Front panel of the SLD4
SLD4
SLD4
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
O
U
T
2
I
N
2

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SLD4 has two optical interfaces. Table 9-48 describes the types and usage
of the optical interfaces of the SLD4.
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Table 9-48 Optical interfaces of the SLD4
Interface Type of
Interface
Usage
IN1-IN2 LC Receives optical signals.
OUT1-OUT2 LC Transmits optical signals.

The SLD4 can use the swappable optical modules to facilitate maintenance.
9.11.6 Valid Slots
The slots valid for the SLD4 vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SLD4 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SLD4 can be installed in slots 18 and
1117.
9.11.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLD4 indicates the type of optical interface.
Table 9-49 provides the relationship between the feature code of the SLD4 and the type of optical
interface.
Table 9-49 Relationship between the feature code of the SLD4 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SLD410 and
SSN2SLD410
10 S-4.1
SSN1SLD411 and
SSN2SLD411
11 L-4.1
SSN1SLD412 and
SSN2SLD412
12 L-4.2
SSN1SLD413 and
SSN2SLD413
13 Ve-4.2
SSN1SLD414 and
SSN2SLD414
14 I-4

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9.11.8 Parameter Settings
You can set the parameters for the SLD4 by using the T2000.
You can set the following parameters for the SLD4 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.11.9 Technical Specifications
The technical specifications of the SLD4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-50 lists the parameters specified for the optical interfaces of the SLD4.
Table 9-50 Parameters specified for the optical interfaces of the SLD4
Parameter Value
Nominal bit rate 622080 kbit/s
Line code
pattern
NRZ
Application
code
I-4 S-4.1 L-4.1 L-4.2 Ve-4.2
Transmission
distance (km)
0 to 2 2 to 15 20 to 40 50 to 80 80 to 100
Type of fiber Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-mode
LC
Operating
wavelength
range (nm)
1261 to
1360
1274 to
1356
1280 to
1335
1480 to
1580
1480 to 1580
Launched
optical power
range (dBm)
-15 to -8 -15 to -8 -3 to +2 -3 to +2 -3 to +2
Receiver
sensitivity
(dBm)
-23 -28 -28 -28 -34
Minimum
overload (dBm)
-8 -8 -8 -8 -13
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Parameter Value
Minimum
extinction ratio
(dB)
8.2 8.2 10 10 10.5

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the N1SLD4 and N2SLD4 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight of the N1SLD4 (kg): 0.6
l Weight of the N2SLD4 (kg): 1.0
Power Consumption
The maximum power consumption of the N1SLD4 at room temperature (25C) is 17 W.
The maximum power consumption of the N2SLD4 at room temperature (25C) is 15 W.
9.12 SLD4A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLD4A (2xSTM-4 optical interface board).
9.12.1 Version Description
The SLD4A is available in one functional version, namely, N1.
9.12.2 Application
The SLD4A is a line board. The SLD4A can be used on the OptiX OSN equipment series to
transmit and receive STM-4 optical signals. The SLD4A converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SLD4A converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
9.12.3 Functions and Features
The SLD4A transmits and receives STM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
9.12.4 Working Principle and Signal Flow
The SLD4A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
9.12.5 Front Panel
The front panel of the SLD4A has indicators, interfaces, a bar code, and a laser safety class label.
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9.12.6 Valid Slots
The slots valid for the SLD4A vary with the cross-connect capacity of the subrack.
9.12.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLD4A indicates the type of optical interface.
9.12.8 Parameter Settings
You can set the parameters for the SLD4A by using the T2000.
9.12.9 Technical Specifications
The technical specifications of the SLD4A include the parameters specified for optical
interfaces, laser safety class, mechanical specifications, and power consumption.
9.12.1 Version Description
The SLD4A is available in one functional version, namely, N1.
Through the board version replacement function, the N1SLD4 can substitute for the N1SLD4A.
9.12.2 Application
The SLD4A is a line board. The SLD4A can be used on the OptiX OSN equipment series to
transmit and receive STM-4 optical signals. The SLD4A converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SLD4A converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
Figure 9-41 shows the application of the SLD4A. The SLD4A boards can form a ring network
or a chain network in the system.
Figure 9-41 Networking and application of the SLD4A
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

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9.12.3 Functions and Features
The SLD4A transmits and receives STM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 9-51 provides the functions and features of the SLD4A.
Table 9-51 Functions and features of the SLD4A
Function and
Feature
SLD4A
Basic functions Receives and transmits 2xSTM-4 optical signals, and processes
2xSTM-4 standard or concatenation services.
Specifications of
the optical
interface
l Supports different types of standard optical interfaces, namely, the
I-4, S-4.1, L-4.1, L-4.2, and Ve-4.2.
l The characteristics of the optical interfaces of the I-4, S-4.1, L-4.1,
and L-4.2 types comply with ITU-T G.957.
l The characteristics of the optical interface of the Ve-4.2 type comply
with the standards defined by Huawei.
Specifications of
the optical module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
l Supports the usage and monitoring of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
Service
processing
Supports the VC-12 services, VC-3 services, VC-4 services, and
VC-4-4c concatenation services.
Overhead
processing
l Processes the section overheads of the STM-4 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one or two channels of ECC communication.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection
schemes
l Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.
l Supports the fiber-shared MSP and SNCP and processes four sets of
K bytes. A single optical interface supports two MSP protection rings,
and one SLD4A supports a maximum of four MSP protection rings.
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Function and
Feature
SLD4A
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the press-to-collect function in fault data collection.

9.12.4 Working Principle and Signal Flow
The SLD4A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 9-42 shows the functional block diagram of the SLD4A.
Figure 9-42 Functional block diagram of the SLD4A
Logic and
control
module
Cross-connect unit A
+3.3 V backup power
+3.3 V
SDH overhead processing module
DCC
SCC unit
LOS
Laser shutdown SCC unit
Communication
High-speed bus
+3.3 V
-48 V/ -60 V
DC/DC
converter
Fuse
Fuse
DC/DC
converter
Cross-connect unit
Cross-connect unit B
High-speed
bus
155 MHz
PLL
Cross-connect unit
155 MHz Reference clock
K1 and K2 insertion/extraction
MSA HPT MST RST
IIC
CDR
.

.

.

.
.

.

.

.
CDR
-48 V/ -60 V
O/E
E/O
S
P
I
O/E
E/O
622 Mbit/s
S
P
I
Frame header
Cross-connect unit
K1 and K2
622 Mbit/s
622 Mbit/s
622 Mbit/s
622
Mbit/s
622
Mbit/s
622 Mbit/s
622 Mbit/s
622
Mbit/s
622
Mbit/s
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery

The functional modules of the STM-4 units are described as follows:
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O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function of shutting down the laser.
CDR Module
This module restores the data signal and the clock signal.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
l MST sub-module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.
In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.
l MSA sub-module
In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.
l HPT sub-module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
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l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
9.12.5 Front Panel
The front panel of the SLD4A has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-43 shows the appearance of the front panel of the SLD4A.
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Figure 9-43 Front panel of the SLD4A
SLD4A
SLD4A
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
O
U
T
2
I
N
2

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SLD4A has two optical interfaces. Table 9-52 describes the types and
usage of the optical interfaces of the SLD4A.
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Table 9-52 Optical interfaces of the SLD4A
Interface Type of
Interface
Usage
IN1IN2 LC Receives optical signals.
OUT1OUT2 LC Transmits optical signals.

The SLD4A can use the swappable optical modules to facilitate maintenance.
9.12.6 Valid Slots
The slots valid for the SLD4A vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SLD4A are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SLD4A can be installed in slots 18
and 1117.
9.12.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLD4A indicates the type of optical interface.
Table 9-53 provides the relationship between the feature code of the SLD4A and the type of
optical interface.
Table 9-53 Relationship between the feature code of the SLD4A and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SLD4A10 10 S-4.1
SSN1SLD4A11 11 L-4.1
SSN1SLD4A12 12 L-4.2
SSN1SLD4A13 13 Ve-4.2
SSN1SLD4A14 14 I-4

9.12.8 Parameter Settings
You can set the parameters for the SLD4A by using the T2000.
You can set the following parameters for the SLD4A by using the T2000:
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l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.12.9 Technical Specifications
The technical specifications of the SLD4A include the parameters specified for optical
interfaces, laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-54 lists the parameters specified for the optical interfaces of the SLD4A.
Table 9-54 Parameters specified for the optical interfaces of the SLD4A
Parameter Value
Nominal bit rate 622080 kbit/s
Line code
pattern
NRZ
Application
code
I-4 S-4.1 L-4.1 L-4.2 Ve-4.2
Transmission
distance (km)
0 to 2 2 to 15 20 to 40 50 to 80 80 to 100
Type of fiber Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-mode
LC
Operating
wavelength
range (nm)
1261 to
1360
1274 to
1356
1280 to
1335
1480 to
1580
1480 to 1580
Launched
optical power
range (dBm)
-15 to -8 -15 to -8 -3 to +2 -3 to +2 -3 to +2
Receiver
sensitivity
(dBm)
-23 -28 -28 -28 -34
Minimum
overload (dBm)
-8 -8 -8 -8 -13
Minimum
extinction ratio
(dB)
8.2 8.2 10 10 10.5

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Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SLD4A are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.6
Power Consumption
The maximum power consumption of the SLD4A at room temperature (25C) is 17 W.
9.13 SLQ4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ4 (4xSTM-4 optical interface board).
9.13.1 Version Description
The SLQ4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SLQ4 is no longer manufactured.
9.13.2 Application
The SLQ4 is a line board. The SLQ4 can be used on the OptiX OSN equipment series to transmit
and receive STM-4 optical signals. The SLQ4 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLQ4 converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
9.13.3 Functions and Features
The SLQ4 transmits and receives STM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
9.13.4 Working Principle and Signal Flow
The SLQ4 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
9.13.5 Front Panel
The front panel of the SLQ4 has indicators, interfaces, a bar code, and a laser safety class label.
9.13.6 Valid Slots
The SLQ4 can be installed in slots 18 and 1116 in the subrack.
9.13.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ4 indicates the type of optical interface.
9.13.8 Parameter Settings
You can set the parameters for the SLQ4 by using the T2000.
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9.13.9 Technical Specifications
The technical specifications of the SLQ4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.13.1 Version Description
The SLQ4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the TCM function and AU-3 services.
The N1SLQ4 is no longer manufactured.
Table 9-55 describes the versions of the SLQ4.
Table 9-55 Versions of the SLQ4
Item Description
Functional
versions
The SLQ4 is available in two functional versions, namely, N1 and N2.
Differences l The N2SLQ4 supports the TCM function and AU-3 services, but the
TCM function and AU-3 services cannot be available at the same
time.
l The N1SLQ4 does not support the TCM function or AU-3 services.
Substitution Through the board version replacement function, the N3SLQ41 can
substitute for the N1SLQ4 and N2SLQ4 at the same line rate.

NOTE
When you configure the MSP or SNCP, you cannot configure the N1SLQ4 as the protection board if the
working board is the N2SLQ4 on which the TCM function is enabled or AU-3 services are configured.
Otherwise, the services are interrupted when a switching operation is performed.
9.13.2 Application
The SLQ4 is a line board. The SLQ4 can be used on the OptiX OSN equipment series to transmit
and receive STM-4 optical signals. The SLQ4 converts the received optical signals into electrical
signals and sends the electrical signals to the cross-connect side. In addition, the SLQ4 converts
the electrical signals sent from the cross-connect side into optical signals and transmits the optical
signals.
Figure 9-44 shows the application of the SLQ4. The SLQ4 boards can form a ring network or
a chain network in the system.
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Figure 9-44 Networking and application of the SLQ4
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.13.3 Functions and Features
The SLQ4 transmits and receives STM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
Table 9-56 provides the functions and features of the SLQ4.
Table 9-56 Functions and features of the SLQ4
Function and
Feature
SLQ4
Basic functions Transmits and receives 4xSTM-4 optical signals.
Specifications of
the optical
interface
l Supports different types of standard optical interfaces, namely, the I-4,
S-4.1, L-4.1, L-4.2, and Ve-4.2.
l The characteristics of the optical interfaces of the I-4, S-4.1, L-4.1, and
L-4.2 types comply with ITU-T G.957.
l The characteristics of the optical interface of the Ve-4.2 type comply
with the standards defined by Huawei.
Specifications of
the optical
module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
l Supports the usage and monitoring of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
Service
processing
l Supports the VC-12 services, VC-3 services, VC-4 services, and
VC-4-4c concatenation services.
l The N2SLQ4 supports the AU-3 services.
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Function and
Feature
SLQ4
Overhead
processing
l Processes the section overheads of the STM-4 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one to four channels of ECC communication.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection
schemes
l Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.
l Supports the fiber-shared MSP and SNCP and processes eight sets of
K bytes. A single optical interface supports two MSP protection rings,
and one SLQ4 supports a maximum of eight MSP protection rings.
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l The N1SLQ4 supports inloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l The N2SLQ4 supports the TCM function.
l Supports the press-to-collect function in fault data collection.

9.13.4 Working Principle and Signal Flow
The SLQ4 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 9-45 shows the functional block diagram of the SLQ4.
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Figure 9-45 Functional block diagram of the SLQ4
Logic and
control
module
Cross-connect unit A
+3.3 V backup power
+3.3 V
SDH overhead processing module
DCC
SCC unit
LOS
Laser shutdown SCC unit
Communication
High-speed bus
+3.3 V
-48 V/ -60 V
DC/DC
converter
Fuse
Fuse
DC/DC
converter
Cross-connect unit
Cross-connect unit B
High-speed
bus
155 MHz
PLL
Cross-connect unit
155 MHz Reference clock
K1 and K2 insertion/extraction
MSA HPT MST RST
IIC
CDR
.

.

.

.
.

.

.

.
CDR
-48 V/ -60 V
O/E
E/O
S
P
I
O/E
E/O
622 Mbit/s
S
P
I
Frame header
Cross-connect unit
K1 and K2
622 Mbit/s
622 Mbit/s
622 Mbit/s
622
Mbit/s
622
Mbit/s
622 Mbit/s
622 Mbit/s
622
Mbit/s
622
Mbit/s
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery

The functional modules of the STM-4 units are described as follows:
O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function of shutting down the laser.
CDR Module
This module restores the data signal and the clock signal.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
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In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
l MST sub-module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.
In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.
l MSA sub-module
In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.
l HPT sub-module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
9.13.5 Front Panel
The front panel of the SLQ4 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-46 shows the appearance of the front panel of the SLQ4.
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Figure 9-46 Front panel of the SLQ4
SLQ4
SLQ4
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SLQ4 has four optical interfaces. Table 9-57 describes the types and usage
of the optical interfaces of the SLQ4.
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Table 9-57 Optical interfaces of the SLQ4
Interface Type of
Interface
Usage
IN1-IN4 LC Receives optical signals.
OUT1-OUT4 LC Transmits optical signals.

The SLQ4 can use the swappable optical modules to facilitate maintenance.
9.13.6 Valid Slots
The SLQ4 can be installed in slots 18 and 1116 in the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
l When the cross-connect capacity is 200 Gbit/s, the SLQ4 can be installed in slots 18 and
1116. When the SLQ4 is installed in slots 14, 15, and 16, two optical interfaces can be
configured. When the SLQ4 is installed in slots 58 and 1114, four optical interfaces can
be configured.
9.13.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ4 indicates the type of optical interface.
Table 9-58 provides the relationship between the feature code of the SLQ4 and the type of optical
interface.
Table 9-58 Relationship between the feature code of the SLQ4 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SLQ410 and
SSN2SLQ410
10 S-4.1
SSN1SLQ411 and
SSN2SLQ411
11 L-4.1
SSN1SLQ412 and
SSN2SLQ412
12 L-4.2
SSN1SLQ413 and
SSN2SLQ413
13 Ve-4.2
SSN1SLQ414 and
SSN2SLQ414
14 I-4

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9.13.8 Parameter Settings
You can set the parameters for the SLQ4 by using the T2000.
You can set the following parameters for the SLQ4 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.13.9 Technical Specifications
The technical specifications of the SLQ4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-59 lists the parameters specified for the optical interfaces of the SLQ4.
Table 9-59 Parameters specified for the optical interfaces of the SLQ4
Parameter Value
Nominal bit rate 622080 kbit/s
Line code
pattern
NRZ
Application
code
I-4 S-4.1 L-4.1 L-4.2 Ve-4.2
Transmission
distance (km)
0 to 2 2 to 15 20 to 40 50 to 80 80 to 100
Type of fiber Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-mode
LC
Operating
wavelength
range (nm)
1261 to
1360
1274 to
1356
1280 to
1335
1480 to
1580
1480 to 1580
Launched
optical power
range (dBm)
-15 to -8 -15 to -8 -3 to +2 -3 to +2 -3 to +2
Receiver
sensitivity
(dBm)
-23 -28 -28 -28 -34
Minimum
overload (dBm)
-8 -8 -8 -8 -13
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Parameter Value
Minimum
extinction ratio
(dB)
8.2 8.2 10 10 10.5

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SLQ4 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the N1SLQ4 at room temperature (25C) is 17 W.
The maximum power consumption of the N2SLQ4 at room temperature (25C) is 16 W.
9.14 SLQ4A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SLQ4A (4xSTM-4 optical interface board).
9.14.1 Version Description
The SLQ4A is available in one functional version, namely, N1.
9.14.2 Application
The SLQ4A is a line board. The SLQ4A can be used on the OptiX OSN equipment series to
transmit and receive STM-4 optical signals. The SLQ4A converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SLQ4A converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
9.14.3 Functions and Features
The SLQ4A transmits and receives STM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
9.14.4 Working Principle and Signal Flow
The SLQ4A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
9.14.5 Front Panel
The front panel of the SLQ4A has indicators, interfaces, a bar code, and a laser safety class label.
9.14.6 Valid Slots
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The SLQ4A can be installed in slots 18 and 1116 in the subrack.
9.14.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ4A indicates the type of optical interface.
9.14.8 Parameter Settings
You can set the parameters for the SLQ4A by using the T2000.
9.14.9 Technical Specifications
The technical specifications of the SLQ4A include the parameters specified for optical
interfaces, laser safety class, mechanical specifications, and power consumption.
9.14.1 Version Description
The SLQ4A is available in one functional version, namely, N1.
Through the board version replacement function, the N1SLQ4 can substitute for the N1SLQ4A.
9.14.2 Application
The SLQ4A is a line board. The SLQ4A can be used on the OptiX OSN equipment series to
transmit and receive STM-4 optical signals. The SLQ4A converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SLQ4A converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
Figure 9-47 shows the application of the SLQ4A. The SLQ4A boards can form a ring network
or a chain network in the system.
Figure 9-47 Networking and application of the SLQ4A
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.14.3 Functions and Features
The SLQ4A transmits and receives STM-4 optical signals, performs O/E conversion for the
STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm signals on the
line.
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Table 9-60 provides the functions and features of the SLQ4A.
Table 9-60 Functions and features of the SLQ4A
Function and
Feature
SLQ4A
Basic functions Transmits and receives 4xSTM-4 optical signals.
Specifications of
the optical
interface
l Supports different types of standard optical interfaces, namely, the I-4,
S-4.1, L-4.1, L-4.2, and Ve-4.2.
l The characteristics of the optical interfaces of the I-4, S-4.1, L-4.1, and
L-4.2 types comply with ITU-T G.957.
l The characteristics of the optical interface of the Ve-4.2 type comply
with the standards defined by Huawei.
Specifications of
the optical
module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
l Supports the usage and monitoring of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
Service
processing
Supports the VC-12 services, VC-3 services, VC-4 services, and VC-4-4c
concatenation services.
Overhead
processing
l Processes the section overheads of the STM-4 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one to four channels of ECC communication.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection
schemes
l Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.
l Supports the fiber-shared MSP and SNCP and processes eight sets of
K bytes. A single optical interface supports two MSP protection rings,
and one SLQ4A supports a maximum of eight MSP protection rings.
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Function and
Feature
SLQ4A
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the press-to-collect function in fault data collection.

9.14.4 Working Principle and Signal Flow
The SLQ4A consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, DC/DC converter, and other modules.
Figure 9-48 shows the functional block diagram of the SLQ4A.
Figure 9-48 Functional block diagram of the SLQ4A
Logic and
control
module
Cross-connect
unit A
+3.3 V backup
power
+3.3 V
SDH overhead processing module
DCC
SCC unit
LOS
Laser shutdown
SCC unit
Communication
High-speed
bus
+3.3
V
-48 V/ -60 V
DC/DC
converter
Fuse
Fuse
DC/DC
converter
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
155 MHz
PLL
Cross-connect
unit
155 MHz
Reference clock
K1 and K2 insertion/extraction
MSA HPT MST RST
IIC
CDR
.

.

.

.
.

.

.

.
CDR
-48 V/ -60 V
O/E
E/O
S
P
I
O/E
E/O
S
P
I
Frame header Cross-connect
unit
K1 and K2
622 Mbit/s
622 Mbit/s
622 Mbit/s
622 Mbit/s
622
Mbit/s
622
Mbit/s
622
Mbit/s
622 Mbit/s
622
Mbit/s
622 Mbit/s
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination IIC: inter-integrated circuit CDR: clock and data recovery

The functional modules of the STM-4 units are described as follows:
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O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function of shutting down the laser.
CDR Module
This module restores the data signal and the clock signal.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
l MST sub-module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.
In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.
l MSA sub-module
In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.
l HPT sub-module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
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l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
9.14.5 Front Panel
The front panel of the SLQ4A has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-49 shows the appearance of the front panel of the SLQ4A.
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Figure 9-49 Front panel of the SLQ4A
SLQ4A
SLQ4A
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SLQ4A has four optical interfaces. Table 9-61 describes the types and
usage of the optical interfaces of the SLQ4A.
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Table 9-61 Optical interfaces of the SLQ4A
Interface Type of
Interface
Usage
IN1IN4 LC Receives optical signals.
OUT1OUT4 LC Transmits optical signals.

The SLQ4A can use the swappable optical modules to facilitate maintenance.
9.14.6 Valid Slots
The SLQ4A can be installed in slots 18 and 1116 in the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
l When the cross-connect capacity is 200 Gbit/s, the SLQ4A can be installed in slots 18
and 1116. When the SLQ4A is installed in slots 14, 15, and 16, two optical interfaces
can be configured. When the SLQ4A is installed in slots 58 and 1114, four optical
interfaces can be configured.
9.14.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ4A indicates the type of optical interface.
Table 9-62 provides the relationship between the feature code of the SLQ4A and the type of
optical interface.
Table 9-62 Relationship between the feature code of the SLQ4A and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SLQ4A10 10 S-4.1
SSN1SLQ4A11 11 L-4.1
SSN1SLQ4A12 12 L-4.2
SSN1SLQ4A13 13 Ve-4.2
SSN1SLQ4A14 14 I-4

9.14.8 Parameter Settings
You can set the parameters for the SLQ4A by using the T2000.
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You can set the following parameters for the SLQ4A by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.14.9 Technical Specifications
The technical specifications of the SLQ4A include the parameters specified for optical
interfaces, laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-63 lists the parameters specified for the optical interfaces of the SLQ4A.
Table 9-63 Parameters specified for the optical interfaces of the SLQ4A
Parameter Value
Nominal bit rate 622080 kbit/s
Line code
pattern
NRZ
Application
code
I-4 S-4.1 L-4.1 L-4.2 Ve-4.2
Transmission
distance (km)
0 to 2 2 to 15 20 to 40 50 to 80 80 to 100
Type of fiber Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-mode
LC
Operating
wavelength
range (nm)
1261 to
1360
1274 to
1356
1280 to
1335
1480 to
1580
1480 to 1580
Launched
optical power
range (dBm)
-15 to -8 -15 to -8 -3 to +2 -3 to +2 -3 to +2
Receiver
sensitivity
(dBm)
-23 -28 -28 -28 -34
Minimum
overload (dBm)
-8 -8 -8 -8 -13
Minimum
extinction ratio
(dB)
8.2 8.2 10 10 10.5

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Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SLQ4A are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the SLQ4A at room temperature (25C) is 17 W.
9.15 SL16
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SL16 (1xSTM-16 optical interface board).
9.15.1 Version Description
The SL16 is available in three functional versions, namely, N1, N2, and N3. The difference
between the three versions is with regard to whether they support the TCM function and AU-3
services. The N1SL16 and N2SL16 are no longer manufactured.
9.15.2 Application
The SL16 is a line board. The SL16 can be used on the OptiX OSN equipment series to transmit
and receive STM-16 optical signals. The SL16 converts the received optical signals into
electrical signals and sends the electrical signals to the cross-connect side. In addition, the SL16
converts the electrical signals sent from the cross-connect side into optical signals and transmits
the optical signals.
9.15.3 Functions and Features
The SL16 receives and transmits 1xSTM-16 optical signals and processes overhead bytes.
9.15.4 Working Principle and Signal Flow
The SL16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, power module, and other modules.
9.15.5 Front Panel
The front panel of the SL16 has indicators, interfaces, a bar code, a laser safety class label, and
an APD alarm label.
9.15.6 Valid Slots
The slots valid for the SL16 vary with the cross-connect capacity of the subrack.
9.15.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL16 indicates the type of optical interface.
9.15.8 Parameter Settings
You can set the parameters for the SL16 by using the T2000.
9.15.9 Technical Specifications
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The technical specifications of the SL16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.15.1 Version Description
The SL16 is available in three functional versions, namely, N1, N2, and N3. The difference
between the three versions is with regard to whether they support the TCM function and AU-3
services. The N1SL16 and N2SL16 are no longer manufactured.
Table 9-64 describes the versions of the SL16.
Table 9-64 Versions of the SL16
Item Description
Functional
versions
The SL16 is available in three functional versions, namely, N1, N2, and
N3.
Differences l The N1SL16 does not support the TCM function or AU-3 services.
l The N2SL16 supports the TCM function and AU-3 services, but the
TCM function and AU-3 services cannot be available at the same
time.
l The N3SL16 supports the TCM function but does not support AU-3
services.
Substitution The N1SL16 and N2SL16 cannot be substituted with each other.
The N3SL16 supports the board version replacement function.
l The N3SL16 can substitute for the N1SL16.
l When the AU-3 services are not required, the N3SL16 can substitute
for the N2SL16.
After the N3SL16 substitutes for the N1SL16 or N2SL16, the
configuration and service status of the N3SL16 are the same as the
configuration and service status of the N1SL16 or N2SL16.

NOTE
In the case of the board of different versions, adhere to the following principles when configuring the MSP
or SNCP:
l You cannot configure the N1SL16 as the protection board if the working board is the N2SL16 or
N3SL16 on which the TCM function is enabled. Otherwise, the services are interrupted when a
switching operation is performed.
l You cannot configure the N1SL16 or N3SL16 as the protection board if the working board is the
N2SL16 on which the AU-3 services are configured. Otherwise, the services are interrupted when a
switching operation is performed.
9.15.2 Application
The SL16 is a line board. The SL16 can be used on the OptiX OSN equipment series to transmit
and receive STM-16 optical signals. The SL16 converts the received optical signals into
electrical signals and sends the electrical signals to the cross-connect side. In addition, the SL16
converts the electrical signals sent from the cross-connect side into optical signals and transmits
the optical signals.
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Figure 9-50 shows the application of the SL16. The SL16 boards can form a ring network or a
chain network in the system.
Figure 9-50 Networking and application of the SL16
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.15.3 Functions and Features
The SL16 receives and transmits 1xSTM-16 optical signals and processes overhead bytes.
Table 9-65 provides the functions and features of the SL16.
Table 9-65 Functions and features of the SL16
Function and
Feature
SL16
Basic functions Transmits and receives 1xSTM-16 optical signals.
Specifications
of the optical
interface
l Supports different types of standard optical interfaces, namely, the
L-16.2, L-16.2Je, V-16.2Je (with the booster amplifier (BA)), and
U-16.2Je (with the BA and pre-amplifier (PA)). The characteristics of
the optical interface of the L-16.2 type comply with ITU-T G.957 and
ITU-T G.692. The characteristics of the optical interfaces of the
L-16.2Je, V-16.2Je (with the BA), and U-16.2Je (with the BA and PA)
types comply with the standards defined by Huawei.
l Supports the output of the standard wavelengths that comply with ITU-
T G.692. The U-16.2Je optical interface can be directly connected to
the dense wavelength division multiplexing (DWDM) equipment.
Specifications
of the optical
module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting of
the on/off state of a laser.
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Function and
Feature
SL16
Service
processing
l Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c
concatenation services, VC-4-8c concatenation services, and VC-4-16c
concatenation services.
l The N2SL16 supports the AU-3 services.
Overhead
processing
l Processes the section overheads of the STM-16 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one channel of ECC communication.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Specifications
of the REG
The N2SL16 and N3SL16 support the setting and query of the REG
working mode.
Protection
schemes
l Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.
l Supports the fiber-shared MSP and SNCP and processes two sets of K
bytes. One SL16 supports a maximum of two MSP protection rings.
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l The N1SL16 supports inloops on VC-4 paths. The N3SL16 supports
inloops and outloops on paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l The N2SL16 and N3SL16 support the TCM function.
l Supports the upgrade of the board software without affecting services.
l The N2SL16 and N3SL16 support the TCM function.
l The N3SL16 supports the PRBS function.
l Supports the press-to-collect function in fault data collection.

9.15.4 Working Principle and Signal Flow
The SL16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, power module, and other modules.
Figure 9-51 shows the functional block diagram of the SL16.
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Figure 9-51 Functional block diagram of the SL16
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
155 MHz
Reference clock
K1 and K2
insertion/extraction
MSA HPT MST RST
-48 V/-60 V
Frame header
Cross-connect
unit
K1 and K2
Power
module
SCC unit
Backplane
2.488
Gbit/s
16x155
Mbit/s
LOS
Laser shutdown
DEMUX
IIC
2.488
Gbit/s
2.488
Gbit/s
2.488
Gbit/s
16x155
Mbit/s
MUX/
DEMUX
O/E
converting
module
.

.
.

.
E/O
SPI
155 MHz
PLL
MUX
O/E
E/O
O/E
SPI
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination IIC: inter-integrated circuit -

O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function of shutting down the laser.
MUX/DEMUX Module
l In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.
l In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
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In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
l MST sub-module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.
In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.
l MSA sub-module
In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.
l HPT sub-module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
9.15.5 Front Panel
The front panel of the SL16 has indicators, interfaces, a bar code, a laser safety class label, and
an APD alarm label.
Diagram of the Front Panel
Figure 9-52 shows the appearance of the front panel of the SL16.
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Figure 9-52 Front panel of the SL16
SL16
SL16
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
OUT
IN
! APD
Receiver
MAX:-9dBm

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SL16 has one optical interface. Table 9-66 describes the types and usage
of the optical interfaces of the SL16.
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Table 9-66 Optical interfaces of the SL16
Interface Type of Interface Usage
IN LC Receives optical signals.
OUT LC Transmits optical signals.

9.15.6 Valid Slots
The slots valid for the SL16 vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SL16 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SL16 can be installed in slots 58 and
1114.
9.15.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL16 indicates the type of optical interface.
Table 9-67 provides the relationship between the feature code of the SL16 and the type of optical
interface
Table 9-67 Relationship between the feature code of the SL16 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SL1601, SSN2SL1601
and SSN3SL1601
01 L-16.2
SSN1SL1602, SSN2SL1602
and SSN3SL1602
02 L-16.2Je
SSN1SL1603, SSN2SL1603
and SSN3SL1603
03 V-16.2Je
SSN1SL1604, SSN2SL1604
and SSN3SL1604
04 U-16.2

9.15.8 Parameter Settings
You can set the parameters for the SL16 by using the T2000.
You can set the following parameters for the SL16 by using the T2000:
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l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.15.9 Technical Specifications
The technical specifications of the SL16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-68 lists the parameters specified for the optical interfaces of the SL16.
Table 9-68 Parameters specified for the optical interfaces of the SL16
Parameter Value
Nominal bit
rate
2488320 kbit/s
Line code
pattern
NRZ
Application
code
L-16.2 L-16.2Je V-16.2Je (BA) U-16.2Je (BA+PA)
Transmissio
n distance
(km)
50 to 80 80 to 100 105 to 140 145 to 170
Type of fiber Single-
mode LC
Single-
mode LC
Single-mode LC Single-mode LC
Operating
wavelength
range (nm)
1500 to
1580
1530 to
1560
1530 to 1565 1550.12
Launched
optical
power range
(dBm)
-2 to +3 5 to 7 -2 to +3
(without
the BA)
13 to 15
(with the
BA)
-2 to +3
(without
the BA
or PA)
15 to 18
(with the
BA)
Receiver
sensitivity
(dBm)
-28 -28 -28 -28
(without
the PA
or BA)
-32 (with
the PA)
Minimum
overload
(dBm)
-9 -9 -9 -9
(without
the PA
or BA)
-10 (with
the PA)
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Parameter Value
Dispersion
tolerance (ps/
nm)
1200 to
1600
2000 2800 3400
Minimum
extinction
ratio (dB)
8.2 8.2 8.2 8.2
Note: The optical interface of the Le-16.2 type is the same as the optical interface of the
L-16.2Je type.
The launched optical power of the optical interface of the V-16.2Je type is measured when
the BA is added. The launched optical power of the optical interface of the U-16.2Je type is
measured when the BA and PA are added. When no amplifier is added, the launched optical
power of the optical interfaces of the V-16.2Je and U-16.2Je types ranges from -2 dBm to 3
dBm.

SL16 supports the colored optical interfaces that comply with ITU-T G.692. Table 9-69 list the
parameters specified for the colored optical interfaces.
Table 9-69 Parameters specified for the optical interfaces that comply with the standard
wavelengths specified in ITU-T G.692
Parameter Value
Nominal bit rate 2488320 kbit/s
Dispersion limit (km) 170 640.a
Mean launched optical
power (dBm)
-2 to +3 -5 to -1
Receiver sensitivity (dBm) -28 -28
Minimum overload (dBm) -9 -9
Maximum allowed
dispersion (ps/nm)
3400 10880
Minimum extinction ratio
(dB)
8.2 10

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SL16 are as follows:
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l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.1
Power Consumption
The maximum power consumption of the N1SL16 and N2SL16 at room temperature (25C) is
19 W.
The maximum power consumption of the N3SL16 at room temperature (25C) is 22 W.
9.16 SL16A
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SL16A (1xSTM-16 optical interface board). This topic also
describes how to configure and commission the SL16A.
9.16.1 Version Description
The SL16A is available in the following functional versions: N3, N2, and N1. The N1SL16A
and N2SL16A are discontinued.
9.16.2 Application
The SL16A is a line board. The SL16A can be used on the OptiX OSN equipment series to
transmit and receive STM-16 optical signals. The SL16A converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SL16A converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
9.16.3 Functions and Features
The SL16A receives and transmits 1xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
9.16.4 Working Principle and Signal Flow
The N1SL16A/N2SL16A/N3SL16A consists of the O/E converting module, MUX/DEMUX
module, SDH overhead processing module, logic and control module, and power module.
9.16.5 Front Panel
The front panel of the SL16A has indicators, interfaces, a bar code, a laser safety class label,
and an APD alarm label.
9.16.6 Jumpers and DIP Switches
The SL16A does not have any jumpers or DIP switches that are used for board settings.
9.16.7 Valid Slots
The SL16A must be installed in a valid slot in the subrack. Otherwise, the SL16A cannot work
normally.
9.16.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL16A indicates the type of optical interface.
9.16.9 Parameter Settings
You can set the parameters for the SL16A by using the T2000.
9.16.10 Technical Specifications
The technical specifications of the SL16A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
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9.16.1 Version Description
The SL16A is available in the following functional versions: N3, N2, and N1. The N1SL16A
and N2SL16A are discontinued.
Table 9-70 describes the versions of the SL16A.
Table 9-70 Versions of the SL16
Item Description
Functional versions The SL16A is available in the following functional versions: N3, N2,
and N1. The N1SL16A and N2SL16A are discontinued.
Differences l The N1SL16A does not support the TCM function or AU-3
services.
l The N2SL16A supports the TCM function and AU-3 services, but
the TCM function and AU-3 services cannot be available at the
same time.
l The N3SL16A supports the TCM function but does not support
AU-3 services.
Substitution l The N1SL16A and N2SL16A cannot be substituted with each
other.
l The N3SL16A supports the board version replacement function.
The N3SL16A can substitute for the N1SL16A.
When the AU-3 services are not configured, the N3SL16A can
substitute for the N2SL16A.
l After the N3SL16A substitutes for the N1SL16A or N2SL16A, the
configuration and service status of the N3SL16A are the same as
the configuration and service status of the N1SL16A or N2SL16A.

NOTE
In the case of the board of different versions, adhere to the following principles when configuring the MSP
or SNCP:
l You cannot configure the N1SL16A as the protection board if the working board is the N2SL16A or
N3SL16A on which only the TCM function is enabled. Otherwise, the services are interrupted when
a switching operation is performed.
l You cannot configure the N3SL16A or N1SL16A as the protection board if the working board is the
N2SL16A on which only the AU-3 services are configured. Otherwise, the services are interrupted
when a switching operation is performed.
9.16.2 Application
The SL16A is a line board. The SL16A can be used on the OptiX OSN equipment series to
transmit and receive STM-16 optical signals. The SL16A converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SL16A converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
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Figure 9-53 shows the application of the SL16A. The SL16A boards can form a ring network
or a chain network in the system.
Figure 9-53 Networking and application of the SL16A
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.16.3 Functions and Features
The SL16A receives and transmits 1xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
Table 9-71 provides the functions and features of the SL16A.
Table 9-71 Functions and features of the SL16A
Function and
Feature
SL16A
Basic functions Transmits and receives 1xSTM-16 optical signals.
Specifications of the
optical interface
Supports different types of standard optical interfaces, namely, the
I-16, S-16.1, L-16.1, and L-16.2. The characteristics of the optical
interfaces comply with ITU-T G.957 and ITU-T G.692.
Specifications of the
optical module
l Supports the detection and query of the information about the
optical module.
l Provides the ALS function. The optical interface supports the
setting of the on/off state of a laser.
l Supports the usage and monitoring of the SFP optical module,
which facilitates the maintenance and upgrading of the optical
module.
Service processing l Supports the VC-12 services, VC-3 services, VC-4 services,
VC-4-4c concatenation services, VC-4-8c concatenation
services, and VC-4-16c concatenation services.
l The N2SL16A supports the AU-3 services.
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Function and
Feature
SL16A
Overhead processing l Processes the section overheads of the STM-16 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one channel of ECC communication.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Specifications of the
REG
The N2SL16A and N3SL16A support the setting and query of the
REG working mode.
Protection schemes l Supports the two-fiber ring MSP.
l Supports the four-fiber ring MSP.
l Supports the linear MSP.
l Supports the SNCP.
l Supports the SNCMP.
l Supports the SNCTP.
l Supports the fiber-shared virtual trail protection.
l Supports the fiber-shared MSP and processes two sets of K bytes.
One SL16A supports a maximum of two MSP rings.
Maintenance features l Supports inloops and outloops at optical interfaces.
l The N1SL16A supports inloops on VC-4 paths. The N3SL16A
supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not
affect services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l The N2SL16A and N3SL16A support the TCM function.
l Supports the upgrade of the board software without affecting
services.
l The N3SL16A supports the PRBS function.
l Supports the press-to-collect function in fault data collection.

9.16.4 Working Principle and Signal Flow
The N1SL16A/N2SL16A/N3SL16A consists of the O/E converting module, MUX/DEMUX
module, SDH overhead processing module, logic and control module, and power module.
Figure 9-54 shows the functional block diagram of the N1SL16A/N2SL16A/N3SL16A.
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Figure 9-54 Functional block diagram of the N1SL16A/N2SL16A/N3SL16A
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
155 MHz
Reference clock
K1 and K2
insertion/extraction
MSA HPT MST RST
-48 V/-60 V
Frame header Cross-connect
unit
K1 and K2
Power
module
SCC unit
Backplane
2.488
Gbit/s
16x155
Mbit/s
LOS
Laser shutdown
DEMUX
IIC
2.488
Gbit/s
2.488
Gbit/s
2.488
Gbit/s
16x155
Mbit/s
MUX/
DEMUX
O/E
SPI
E/O
O/E
converting
module
155 MHz
PLL
MUX
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination - -

O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l Detects the R_LOS alarm and provides the function of shutting down the laser.
MUX/DEMUX Module
l In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.
l In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module terminates the RSOH. That is, the RST
sub-module detects the frame alignment bytes (A1 and A2), descrambles all the bytes
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except the first line of the RSOH, restores and checks the J0 byte, and checks the B1
byte.
In the transmit direction, the RST sub-module generates the RSOH. That is, the RST
sub-module writes bytes such as A1, A2, and J0, calculates and writes the B1 byte, and
scrambles all the bytes except the first line of the RSOH.
l MST sub-module
In the receive direction, the MST sub-module terminates the MSOH. That is, the MST
sub-module generates the MS_AIS alarm and detects the MS_RDI alarm after detecting
the K2 byte, and detects the MS_REI alarm and generates the B2_EXC alarm after
checking the B2 byte.
In the transmit direction, the MST sub-module generates the MSOH. That is, the MST
sub-module writes bytes such as E2, D4-D12, K1, K2, S1, and M1, and calculates and
writes the B2 byte.
l MSA sub-module
In the receive direction, the MSA sub-module de-interleaves the AUG, divides an AUG
into N AU-4s, detects the AU_LOP alarm and the AU_AIS alarm, and performs pointer
justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
l HPT sub-module
In the receive direction, the HPT sub-module terminates the POH. That is, the HPT sub-
module detects the HP_REI alarm after checking the B3 byte, generates the HP_TIM
alarm and the HP_SLM alarm and detects the HP_RDI alarm after detecting the J1 and
C2 bytes, and generates the HP_UNEQ alarm after detecting the C2 byte.
In the transmit direction, the HPT sub-module generates the POH. That is, the HPT sub-
module writes bytes such as J1 and C2, and calculates and writes the B3 byte.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not in position.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
9.16.5 Front Panel
The front panel of the SL16A has indicators, interfaces, a bar code, a laser safety class label,
and an APD alarm label.
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Diagram of the Front Panel
Figure 9-55 shows the appearance of the front panel of the SL16A.
Figure 9-55 Front panel of the SL16A
SL16A
SL16A
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
I
N
MAX:-9dBm
! APD
Receiver

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the SL16A has one optical interface. Table 9-72 describes the types and usage
of the optical interfaces of the SL16A.
Table 9-72 Optical interfaces of the SL16A
Interface Type of Interface Usage
IN LC Receives optical signals.
OUT LC Transmits optical signals.

9.16.6 Jumpers and DIP Switches
The SL16A does not have any jumpers or DIP switches that are used for board settings.
9.16.7 Valid Slots
The SL16A must be installed in a valid slot in the subrack. Otherwise, the SL16A cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SL16A vary with the cross-connect capacity of the subrack. The slots
valid for the SL16A are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SL16A can be installed in slots 58 and
1114.
9.16.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL16A indicates the type of optical interface.
Table 9-73 provides the relationship between the feature code of the SL16A and the type of
optical interface.
Table 9-73 Relationship between the feature code of the SL16A and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SL16A01,
SSN2SL16A01,
SSN3SL16A01
01 I-16
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Board Feature Code Type of Optical Interface
SSN1SL16A02,
SSN2SL16A02,
SSN3SL16A02
02 S-16.1
SSN1SL16A03,
SSN2SL16A03,
SSN3SL16A03
03 L-16.1
SSN1SL16A04,
SSN2SL16A04,
SSN3SL16A04
04 L-16.2

9.16.9 Parameter Settings
You can set the parameters for the SL16A by using the T2000.
You can set the following parameters for the SL16A by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.16.10 Technical Specifications
The technical specifications of the SL16A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-74 lists the parameters specified for the optical interfaces of the SL16A.
Table 9-74 Parameters specified for the optical interfaces of the SL16A
Parameter Value
Nominal bit
rate
2488320 kbit/s
Application
code
I-16 S-16.1 L-16.1 L-16.2
Transmission
distance (km)
0 to 2 2 to 15 25 to 40 50 to 80
Type of fiber Single-mode
LC
Single-mode
LC
Single-mode LC Single-mode LC
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Parameter Value
Operating
wavelength
range (nm)
1266 to 1360 1260 to 1360 1280 to 1335 1500 to 1580
Launched
optical power
range (dBm)
-10 to -3 -5 to 0 -2 to +3 -2 to +3
Receiver
sensitivity
(dBm)
-18 -18 -27 -28
Minimum
overload
(dBm)
-3 0 -9 -9
Dispersion
tolerance (ps/
nm)
12 - - 1200 to 1600
Minimum
extinction
ratio (dB)
8.2 8.2 8.2 8.2

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SL16A are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight of the N1SL16A (kg): 0.6
l Weight of the N2SL16A (kg): 1.1
l Weight of the N3SL16A (kg): 0.9
Power Consumption
The maximum power consumption of the N1SL16A at room temperature (25C) is 20 W.
The maximum power consumption of the N2SL16A at room temperature (25C) is 20 W.
The maximum power consumption of the N3SL16A at room temperature (25C) is 22 W.
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9.17 SLD16
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SLD16 (2xSTM-16 optical interface board). This topic also
describes how to configure and commission the SLD16.
9.17.1 Version Description
The SLD16 is available in one functional version, namely, N1. The N1SLD16 is discontinued.
9.17.2 Application
The SLD16 is a line board. The SLD16 can be used on the OptiX OSN equipment series to
transmit and receive STM-16 optical signals. The SLD16 converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SLD16 converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
9.17.3 Functions and Features
The SLD16 receives and transmits 2xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
9.17.4 Working Principle and Signal Flow
The SLD16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, and power module.
9.17.5 Front Panel
The front panel of the SLD16 has indicators, interfaces, a bar code, and a laser safety class label.
9.17.6 Jumpers and DIP Switches
The SLD16 does not have any jumpers or DIP switches that are used for board settings.
9.17.7 Valid Slots
The SLD16 must be installed in a valid slot in the subrack. Otherwise, the SLD16 cannot work
normally.
9.17.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLD16 indicates the type of optical interface.
9.17.9 Parameter Settings
You can set the parameters for the SLD16 by using the T2000.
9.17.10 Technical Specifications
The technical specifications of the SLD16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.17.1 Version Description
The SLD16 is available in one functional version, namely, N1. The N1SLD16 is discontinued.
9.17.2 Application
The SLD16 is a line board. The SLD16 can be used on the OptiX OSN equipment series to
transmit and receive STM-16 optical signals. The SLD16 converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
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SLD16 converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
Figure 9-56 shows the application of the SLD16. The SLD16 boards can form a ring network
or a chain network in the system.
Figure 9-56 Networking and application of the SLD16
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.17.3 Functions and Features
The SLD16 receives and transmits 2xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
Table 9-75 provides the functions and features of the SLD16.
Table 9-75 Functions and features of the SLD16
Function and
Feature
SLD16
Basic functions Transmits and receives 2xSTM-16 optical signals.
Specifications
of the optical
interface
l Supports different types of standard optical interfaces, namely, the I-16,
S-16.1, L-16.1, and L-16.2. The characteristics of the optical interfaces
comply with ITU-T G.957 and ITU-T G.692.
l Supports the output of the standard wavelengths that comply with ITU-
T G.692.
Specifications
of the optical
module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting of
the on/off state of a laser.
l Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
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Function and
Feature
SLD16
Service
processing
Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c
concatenation services, VC-4-8c concatenation services, and VC-4-16c
concatenation services.
Overhead
processing
l Processes the section overheads of the STM-16 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one or two channels of ECC communication.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Specifications
of the REG
Does not support the REG.
Protection
schemes
l Supports the two-fiber ring MSP.
l Supports the four-fiber ring MSP.
l Supports the linear MSP.
l Supports the SNCP.
l Supports the SNCMP.
l Supports the SNCTP.
l Supports the fiber-shared virtual trail protection.
l Supports the fiber-shared MSP and processes four sets of K bytes. A
single optical interface can process two sets of K bytes. One SLD16
supports a maximum of four MSP rings.
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the press-to-collect function in fault data collection.

9.17.4 Working Principle and Signal Flow
The SLD16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, and power module.
Figure 9-57 shows the functional block diagram of the SLD16 by describing how to process
1xSTM-16 signals.
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Figure 9-57 Functional block diagram of the SLD16
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
155 MHz
Reference clock
K1 and K2
insertion/extraction
MSA HPT MST RST
-48 V/-60 V
Frame header
Cross-connect
unit
K1 and K2
Power
module
SCC unit
Backplane
2.488
Gbit/s
16x155
Mbit/s
LOS
Laser shutdown
DEMUX
IIC
2.488
Gbit/s
2.488
Gbit/s
2.488
Gbit/s
16x155
Mbit/s
MUX/
DEMUX
O/E
converting
module
.

.
.

.
E/O
SPI
155 MHz
PLL
MUX
O/E
E/O
O/E
SPI
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination - -

O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l Detects the R_LOS alarm and provides the function of shutting down the laser.
MUX/DEMUX Module
l In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.
l In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module terminates the RSOH. That is, the RST
sub-module detects the frame alignment bytes (A1 and A2), descrambles all the bytes
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except the first line of the RSOH, restores and checks the J0 byte, and checks the B1
byte.
In the transmit direction, the RST sub-module generates the RSOH. That is, the RST
sub-module writes bytes such as A1, A2, and J0, calculates and writes the B1 byte, and
scrambles all the bytes except the first line of the RSOH.
l MST sub-module
In the receive direction, the MST sub-module terminates the MSOH. That is, the MST
sub-module generates the MS_AIS alarm and detects the MS_RDI alarm after detecting
the K2 byte, and detects the MS_REI alarm and generates the B2_EXC alarm after
checking the B2 byte.
In the transmit direction, the MST sub-module generates the MSOH. That is, the MST
sub-module writes bytes such as E2, D4-D12, K1, K2, S1, and M1, and calculates and
writes the B2 byte.
l MSA sub-module
In the receive direction, the MSA sub-module de-interleaves the AUG, divides an AUG
into N AU-4s, detects the AU_LOP alarm and the AU_AIS alarm, and performs pointer
justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
l HPT sub-module
In the receive direction, the HPT sub-module terminates the POH. That is, the HPT sub-
module detects the HP_REI alarm after checking the B3 byte, generates the HP_TIM
alarm and the HP_SLM alarm and detects the HP_RDI alarm after detecting the J1 and
C2 bytes, and generates the HP_UNEQ alarm after detecting the C2 byte.
In the transmit direction, the HPT sub-module generates the POH. That is, the HPT sub-
module writes bytes such as J1 and C2, and calculates and writes the B3 byte.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not in position.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
9.17.5 Front Panel
The front panel of the SLD16 has indicators, interfaces, a bar code, and a laser safety class label.
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Diagram of the Front Panel
Figure 9-58 shows the appearance of the front panel of the SLD16.
Figure 9-58 Front panel of the SLD16
SLD16
SLD16
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
O
U
T
2
I
N
2

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the SLD16 has two optical interfaces. Table 9-76 describes the types and
usage of the optical interfaces of the SLD16.
Table 9-76 Optical interfaces of the SLD16
Interface Type of Interface Usage
IN1IN2 LC Receives optical signals.
OUT1OUT2 LC Transmits optical signals.

9.17.6 Jumpers and DIP Switches
The SLD16 does not have any jumpers or DIP switches that are used for board settings.
9.17.7 Valid Slots
The SLD16 must be installed in a valid slot in the subrack. Otherwise, the SLD16 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SLD16 vary with the cross-connect capacity of the subrack. The slots
valid for the SLD16 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SLD16 can be installed in slots 7, 8, 11,
and 12.
9.17.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLD16 indicates the type of optical interface.
Table 9-77 provides the relationship between the feature code of the SLD16 and the type of
optical interface.
Table 9-77 Relationship between the feature code of the SLD16 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SLD1600 00 -
SSN1SLD1601 01 I-16
SSN1SLD1602 02 S-16.1
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Board Feature Code Type of Optical Interface
SSN1SLD1603 03 L-16.1
SSN1SLD1604 04 L-16.2

9.17.9 Parameter Settings
You can set the parameters for the SLD16 by using the T2000.
You can set the following parameters for the SLD16 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.17.10 Technical Specifications
The technical specifications of the SLD16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-78 lists the parameters specified for the optical interfaces of the SLD16.
Table 9-78 Parameters specified for the optical interfaces of the SLD16
Parameter Value
Nominal bit
rate
2488320 kbit/s
Application
code
I-16 S-16.1 L-16.1 L-16.2
Transmissio
n distance
(km)
0 to 2 2 to 15 25 to 40 50 to 80
Type of fiber Single-mode LC Single-mode LC Single-mode LC Single-mode LC
Operating
wavelength
range (nm)
1266 to 1360 1260 to 1360 1280 to 1335 1500 to 1580
Launched
optical
power range
(dBm)
-10 to -3 -5 to 0 -2 to +3 -2 to +3
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Parameter Value
Receiver
sensitivity
(dBm)
-18 -18 -27 -28
Minimum
overload
(dBm)
-3 0 -9 -9
Dispersion
tolerance
(ps/nm)
12 - - 1200 to 1600
Minimum
extinction
ratio (dB)
8.2 8.2 8.2 8.2

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SLD16 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.9
Power Consumption
The maximum power consumption of the SLD16 at room temperature (25C) is 23 W.
9.18 SLQ16
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SLQ16 (4xSTM-16 optical interface board). This topic also
describes how to configure and commission the SLQ16.
9.18.1 Version Description
The N2SLQ16 is discontinued.
9.18.2 Application
The SLQ16 is a line board. The SLQ16 can be used on the OptiX OSN equipment series to
transmit and receive STM-16 optical signals. The SLQ16 converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SLQ16 converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
9.18.3 Functions and Features
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The SLQ16 receives and transmits 4xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
9.18.4 Working Principle and Signal Flow
The SLQ16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, and power module.
9.18.5 Front Panel
The front panel of the SLQ16 has indicators, interfaces, a bar code, and a laser safety class label.
9.18.6 Jumpers and DIP Switches
The SLQ16 does not have any jumpers or DIP switches that are used for board settings.
9.18.7 Valid Slots
The slots valid for the SLQ16 vary with the cross-connect capacity of the subrack.
9.18.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ16 indicates the type of optical interface.
9.18.9 Parameter Settings
You can set the parameters for the SLQ16 by using the T2000.
9.18.10 Technical Specifications
The technical specifications of the SLQ16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.18.1 Version Description
The N2SLQ16 is discontinued.
Table 9-79 describes the versions of the SLQ16.
Table 9-79 Versions of the SLQ16
Item Description
Functional Versions
Differences l The N1SLQ16 does not support the TCM function or AU-3
services.
l The N2SLQ16 supports the TCM function and AU-3 services, but
the TCM function and AU-3 services cannot be available at the
same time.
Substitution When the AU-3 services and TCM function are not required, the
N1SLQ16 and N2SLQ16 can be substituted with each other.

NOTE
When you configure the MSP or SNCP, you cannot configure the N1SLQ16 as the protection board if the
working board is the N2SLQ16 on which the TCM function is enabled or AU-3 services are configured.
Otherwise, the services are interrupted when a switching operation is performed.
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9.18.2 Application
The SLQ16 is a line board. The SLQ16 can be used on the OptiX OSN equipment series to
transmit and receive STM-16 optical signals. The SLQ16 converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SLQ16 converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
Figure 9-59 shows the application of the SLQ16. The SLQ16 boards can form a ring network
or a chain network in the system.
Figure 9-59 Networking and application of the SLQ16
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.18.3 Functions and Features
The SLQ16 receives and transmits 4xSTM-16 optical signals, processes overhead bytes, and
performs the MSP.
Table 9-80 provides the functions and features of the SLQ16.
Table 9-80 Functions and features of the SLQ16
Function and
Feature
SLQ16
Basic functions Transmits and receives 4xSTM-16 optical signals.
Specifications of
the optical interface
Supports different types of standard optical interfaces, namely, the I-16,
S-16.1, L-16.1, and L-16.2. The characteristics of the optical interfaces
comply with ITU-T G.957 and ITU-T G.692.
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Function and
Feature
SLQ16
Specifications of
the optical module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
l Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
Service processing l Supports the VC-12 services, VC-3 services, VC-4 services,
VC-4-4c concatenation services, VC-4-8c concatenation services,
and VC-4-16c concatenation services.
l The N2SLQ16 supports the AU-3 services.
Overhead
processing
l Processes the section overheads of the STM-16 signals.
l Supports the configuration of the D1D12, E1, and E2 bytes as
transparent transmission bytes or into other unused overheads bytes.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one to four channels of ECC communication.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Specifications of
the REG
Does not support the REG.
Protection schemes l Supports the two-fiber ring MSP.
l Supports the four-fiber ring MSP.
l Supports the linear MSP.
l Supports the SNCP.
l Supports the SNCMP.
l Supports the SNCTP.
l Supports the fiber-shared virtual trail protection.
l Supports the fiber-shared MSP and processes eight sets of K bytes.
A single optical interface can process two sets of K bytes. One
SLQ16 supports a maximum of eight MSP rings.
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Function and
Feature
SLQ16
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l The N1SLQ16 supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting
services.
l Supports the press-to-collect function in fault data collection.
l The N2SLQ16 supports the TCM function.

9.18.4 Working Principle and Signal Flow
The SLQ16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, and power module.
Figure 9-60 shows the functional block diagram of the SLQ16 by describing how to process
1xSTM-16 signals.
Figure 9-60 Functional block diagram of the SLQ16
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
155 MHz
Reference clock
K1 and K2
insertion/extraction
MSA HPT MST RST
-48 V/-60 V
Frame header
Cross-connect
unit
K1 and K2
Power
module
SCC unit
Backplane
2.488
Gbit/s
16x155
Mbit/s
LOS
Laser shutdown
DEMUX
IIC
2.488
Gbit/s
2.488
Gbit/s
2.488
Gbit/s
16x155
Mbit/s
MUX/
DEMUX
O/E
converting
module
.

.
.

.
E/O
SPI
155 MHz
PLL
MUX
O/E
E/O
O/E
SPI
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination - -

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O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l Detects the R_LOS alarm and provides the function of shutting down the laser.
MUX/DEMUX Module
l In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.
l In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module terminates the RSOH. That is, the RST
sub-module detects the frame alignment bytes (A1 and A2), descrambles all the bytes
except the first line of the RSOH, restores and checks the J0 byte, and checks the B1
byte.
In the transmit direction, the RST sub-module generates the RSOH. That is, the RST
sub-module writes bytes such as A1, A2, and J0, calculates and writes the B1 byte, and
scrambles all the bytes except the first line of the RSOH.
l MST sub-module
In the receive direction, the MST sub-module terminates the MSOH. That is, the MST
sub-module generates the MS_AIS or MS_RDI alarm after detecting the K2 byte,
generates the B2_SD or B2_EXC alarm after checking the B2 byte, and reports the
MS_REI alarm to the opposite end.
In the transmit direction, the MST sub-module generates the MSOH. That is, the MST
sub-module writes bytes such as E2, D4-D12, K1, K2, S1, and M1, calculates the BIP
check value, and writes the B2 byte.
l MSA sub-module
In the receive direction, the MSA sub-module de-interleaves the AUG, divides an AUG
into N AU-4s, detects the AU_LOP alarm and the AU_AIS alarm, and performs pointer
justifications.
In the transmit direction, the MSA sub-module adds the VC-4 to the AU-PTR and
generates the AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
l HPT sub-module
In the receive direction, the HPT sub-module terminates the POH. That is, the HPT sub-
module reports the HP_REI alarm to the opposite end after checking the B3 byte,
generates the HP_TIM alarm and the HP_SLM alarm, as well as the HP_UNEQ alarm
if the VC-4 path is found unequipped, after detecting the J1 and C2 bytes, and reports
the HP_RDI alarm to the opposite end.
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In the transmit direction, the HPT sub-module generates the POH. That is, the HPT sub-
module writes bytes such as J1 and C2, calculates the BIP check value, and writes the
B3 byte.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Selects and traces the clock signal from the active and standby cross-connect units.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not in position.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
9.18.5 Front Panel
The front panel of the SLQ16 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-61 shows the appearance of the front panel of the N1SLQ16.
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Figure 9-61 Front panel of the N1SLQ16
SLQ16
SLQ16
ACT
PROG
SRV
STAT
O
U
T
1
I
N
1
CLASS 1
LASER
PRODUCT
O
U
T
4
I
N
4
O
U
T
3
I
N
3
O
U
T
2
I
N
2

Figure 9-62 shows the appearance of the front panel of the N2SLQ16.
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Figure 9-62 Front panel of the N2SLQ16
SLQ16
SLQ16
ACT
PROG
SRV
STAT
O
U
T
1
I
N
1
CLASS 1
LASER
PRODUCT
O
U
T
4
I
N
4
O
U
T
3
I
N
3
O
U
T
2
I
N
2

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SLQ16 has four optical interfaces. Table 9-81 describes the types and
usage of the optical interfaces of the SLQ16.
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Table 9-81 Optical interfaces of the SLQ16
Interface Type of Interface Usage
IN1IN4 LC Receives optical signals.
OUT1OUT4 LC Transmits optical signals.

9.18.6 Jumpers and DIP Switches
The SLQ16 does not have any jumpers or DIP switches that are used for board settings.
9.18.7 Valid Slots
The slots valid for the SLQ16 vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SLQ16 are as follows:
l When the cross-connect capacity is 200 Gbit/s,
The SLQ16 can be installed in slots 14, 15, and 16. In this case, two optical interfaces
can be configured.
The SLQ16 can be installed in slots 58 and 1114. In this case, four optical interfaces
can be configured.
9.18.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ16 indicates the type of optical interface.
Table 9-82 provides the relationship between the feature code of the SLQ16 and the type of
optical interface.
Table 9-82 Relationship between the feature code of the SLQ16 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SLQ1601,
SSN2SLQ1601
01 I-16
SSN1SLQ1602,
SSN2SLQ1602
02 S-16.1
SSN1SLQ1603,
SSN2SLQ1603
03 L-16.1
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Board Feature Code Type of Optical Interface
SSN1SLQ1604,
SSN2SLQ1604
04 L-16.2
SSN1SLQ16A10 10 I-16
SSN1SLQ16A11 11 S-16.1
SSN1SLQ16A12 12 L-16.1
SSN1SLQ16A13 13 L-16.2

9.18.9 Parameter Settings
You can set the parameters for the SLQ16 by using the T2000.
You can set the following parameters for the SLQ16 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.18.10 Technical Specifications
The technical specifications of the SLQ16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-83 lists the parameters specified for the optical interfaces of the SLQ16.
Table 9-83 Parameters specified for the optical interfaces of the SLQ16
Parameter Value
Nominal bit rate 2488320 kbit/s
Application code I-16 S-16.1 L-16.1 L-16.2
Transmission
distance (km)
0 to 2 2 to 15 25 to 40 50 to 80
Type of fiber Single-mode
LC
Single-mode
LC
Single-mode LC Single-mode
LC
Operating
wavelength range
(nm)
1266 to 1360 1260 to 1360 1280 to 1335 1500 to 1580
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Parameter Value
Launched optical
power range (dBm)
-10 to -3 -5 to 0 -2 to +3 -2 to +3
Receiver sensitivity
(dBm)
-18 -18 -27 -28
Minimum overload
(dBm)
-3 0 -9 -9
Dispersion tolerance
(ps/nm)
12 - - 1200 to 1600
Minimum extinction
ratio (dB)
8.2 8.2 8.2 8.2

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SLQ16 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight of the N1SLQ16 (kg): 0.9
l Weight of the N2SLQ16 (kg): 1.3
Power Consumption
The maximum power consumption of the N1SLQ16 at room temperature (25C) is 20 W.
The maximum power consumption of the N2SLQ16 at room temperature (25C) is 35 W.
9.19 SLO16
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SLO16 (8xSTM-16 optical interface board). This topic also
describes how to configure and commission the SLO16.
9.19.1 Version Description
The SLO16 is available in the following functional version: N1.
9.19.2 Application
The SLO16 is a line board. The SLO16 can be used on the OptiX OSN equipment series to
transmit and receive STM-16 optical signals. The SLO16 converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SLO16 converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
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9.19.3 Functions and Features
The SLO16 receives and transmits 8xSTM-16 optical signals, processes overhead bytes, and
performs the MSP protection.
9.19.4 Working Principle and Signal Flow
The SLO16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, and power module.
9.19.5 Front Panel
The front panel of the SLO16 has indicators, interfaces, a bar code, and a laser safety class label.
9.19.6 Jumpers and DIP Switches
The SLO16 does not have any jumpers or DIP switches that are used for board settings.
9.19.7 Valid Slots
The SLO16 must be installed in a valid slot in the subrack. Otherwise, the SLO16 cannot work
normally.
9.19.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLO16 indicates the type of optical interface.
9.19.9 Parameter Settings
You can set the parameters for the SLO16 by using the T2000.
9.19.10 Technical Specifications
The technical specifications of the SLO16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.19.1 Version Description
The SLO16 is available in the following functional version: N1.
9.19.2 Application
The SLO16 is a line board. The SLO16 can be used on the OptiX OSN equipment series to
transmit and receive STM-16 optical signals. The SLO16 converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SLO16 converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
Figure 9-63 shows the application of the SLO16. The SLO16 boards can form a ring network
or a chain network in the system.
Figure 9-63 Networking and application of the SLO16
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board
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9.19.3 Functions and Features
The SLO16 receives and transmits 8xSTM-16 optical signals, processes overhead bytes, and
performs the MSP protection.
Table 9-84 provides the functions and features of the SLO16.
Table 9-84 Functions and features of the SLO16
Function and
Feature
SLO16
Basic functions Transmits and receives 8xSTM-16 optical signals.
Specifications of
the optical interface
Supports different types of standard optical interfaces, namely, the I-16,
S-16.1, L-16.1, and L-16.2. The characteristics of the optical interfaces
comply with ITU-T G.957 and ITU-T G.692.
Specifications of
the optical module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
l Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
Service processing Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c
concatenation services, VC-4-8c concatenation services, and VC-4-16c
concatenation services.
Overhead
processing
l Processes the section overheads of the STM-16 signals.
l Supports the configuration of the D1D12, E1, and E2 bytes as
transparent transmission bytes or into other unused overheads bytes.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one to eight channels of ECC communication.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Specifications of
the REG
Does not support the REG.
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Function and
Feature
SLO16
Protection schemes l Supports the two-fiber ring MSP.
l Supports the four-fiber ring MSP.
l Supports the linear MSP.
l Supports the SNCP.
l Supports the SNCMP.
l Supports the SNCTP.
l Supports the fiber-shared virtual trail protection.
l Supports the fiber-shared MSP and processes 16 sets of K bytes. A
single optical interface can process two sets of K bytes. One SLO16
supports a maximum of 16 MSP rings.
l Supports the detection of standby SNCP channels and reports an
alarm when a standby SNCP channel is faulty.
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting
services.
l Supports the press-to-collect function in fault data collection.

9.19.4 Working Principle and Signal Flow
The SLO16 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, and power module.
Figure 9-64 shows the functional block diagram of the SLO16 by describing how to process
1xSTM-16 signals.
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Figure 9-64 Functional block diagram of the SLO16
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
155 MHz
Reference clock
K1 and K2
insertion/extraction
MSA HPT MST RST
-48 V/-60 V
Frame header
Cross-connect
unit
K1 and K2
Power
module
SCC unit
Backplane
2.488
Gbit/s
16x155
Mbit/s
LOS
Laser shutdown
DEMUX
IIC
2.488
Gbit/s
2.488
Gbit/s
2.488
Gbit/s
16x155
Mbit/s
MUX/
DEMUX
O/E
converting
module
.

.
.

.
E/O
SPI
155 MHz
PLL
MUX
O/E
E/O
O/E
SPI
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination - -

O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l Detects the R_LOS alarm and provides the function of shutting down the laser.
MUX/DEMUX Module
l In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.
l In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module terminates the RSOH. That is, the RST
sub-module detects the frame alignment bytes (A1 and A2), descrambles all the bytes
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except the first line of the RSOH, restores and checks the J0 byte, and checks the B1
byte.
In the transmit direction, the RST sub-module generates the RSOH. That is, the RST
sub-module writes bytes such as A1, A2, and J0, calculates and writes the B1 byte, and
scrambles all the bytes except the first line of the RSOH.
l MST sub-module
In the receive direction, the MST sub-module terminates the MSOH. That is, the MST
sub-module generates the MS_AIS or MS_RDI alarm after detecting the K2 byte,
generates the B2_SD or B2_EXC alarm after checking the B2 byte, and reports the
MS_REI alarm to the opposite end.
In the transmit direction, the MST sub-module generates the MSOH. That is, the MST
sub-module writes bytes such as E2, D4-D12, K1, K2, S1, and M1, calculates the BIP
check value, and writes the B2 byte.
l MSA sub-module
In the receive direction, the MSA sub-module de-interleaves the AUG, divides an AUG
into N AU-4s, detects the AU_LOP alarm and the AU_AIS alarm, and performs pointer
justifications.
In the transmit direction, the MSA sub-module adds the VC-4 to the AU-PTR and
generates the AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
l HPT sub-module
In the receive direction, the HPT sub-module terminates the POH. That is, the HPT sub-
module reports the HP_REI alarm to the opposite end after checking the B3 byte,
generates the HP_TIM alarm and the HP_SLM alarm, as well as the HP_UNEQ alarm
if the VC-4 path is found unequipped, after detecting the J1 and C2 bytes, and reports
the HP_RDI alarm to the opposite end.
In the transmit direction, the HPT sub-module generates the POH. That is, the HPT sub-
module writes bytes such as J1 and C2, calculates the BIP check value, and writes the
B3 byte.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Selects and traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not in position.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
9.19.5 Front Panel
The front panel of the SLO16 has indicators, interfaces, a bar code, and a laser safety class label.
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Diagram of the Front Panel
Figure 9-65 shows the appearance of the front panel of the SLO16.
Figure 9-65 Front panel of the SLO16
SLO16
SLO16
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
T
X
1
R
X
1
T
X
2
R
X
2
T
X
3
R
X
3
T
X
4
R
X
4
T
X
5
R
X
5
T
X
6
R
X
6
T
X
7
R
X
7
T
X
8
R
X
8

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the SLO16 has eight optical interfaces. Table 9-85 describes the types and
usage of the optical interfaces of the SLO16.
Table 9-85 Optical interfaces of the SLO16
Interface Type of Interface Usage
RX1RX8 LC Receives optical signals.
TX1TX8 LC Transmits optical signals.

9.19.6 Jumpers and DIP Switches
The SLO16 does not have any jumpers or DIP switches that are used for board settings.
9.19.7 Valid Slots
The SLO16 must be installed in a valid slot in the subrack. Otherwise, the SLO16 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SLO16 vary with the cross-connect capacity of the subrack. The slots
valid for the SLO16 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SLO16 can be installed in slots 7, 8, 11,
and 12 in the subrack.
9.19.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLO16 indicates the type of optical interface.
Table 9-86 provides the relationship between the feature code of the SLO16 and the type of
optical interface.
Table 9-86 Relationship between the feature code of the SLO16 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SLO1610 10 I-16
SSN1SLO1611 11 S-16.1
SSN1SLO1612 12 L-16.1
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Board Feature Code Type of Optical Interface
SSN1SLO1613 13 L-16.2

9.19.9 Parameter Settings
You can set the parameters for the SLO16 by using the T2000.
You can set the following parameters for the SLO16 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.19.10 Technical Specifications
The technical specifications of the SLO16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-87 lists the parameters specified for the optical interfaces of the SLO16.
Table 9-87 Parameters specified for the optical interfaces of the SLO16
Parameter Value
Nominal bit rate 2488320 kbit/s
Line code pattern NRZ
Application code I-16 S-16.1 L-16.1 L-16.2
Transmission
distance (km)
0 to 2 2 to 15 25 to 40 50 to 80
Type of fiber Single-mode
LC
Single-mode
LC
Single-mode LC Single-mode
LC
Operating
wavelength range
(nm)
1266 to 1360 1260 to 1360 1280 to 1335 1500 to 1580
Launched optical
power range (dBm)
-10 to -3 -5 to 0 -2 to +3 -2 to +3
Receiver sensitivity
(dBm)
-18 -18 -27 -28
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Parameter Value
Minimum overload
(dBm)
-3 0 -9 -9
Dispersion tolerance
(ps/nm)
12 - - 1200 to 1600
Minimum extinction
ratio (dB)
8.2 8.2 8.2 8.2

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SLO16 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the N1SLO16 at room temperature (25C) is 38 W.
9.20 SF16
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SF16 (1xSTM-16 optical interface board with the out-band FEC
function).
9.20.1 Version Description
The SF16 is available in one functional version, namely, N1.
9.20.2 Application
The SF16 is a line board. The SF16 can be used on the OptiX OSN equipment series to transmit
and receive STM-16 optical signals. The SF16 converts the received optical signals into
electrical signals and sends the electrical signals to the cross-connect side. In addition, the SF16
converts the electrical signals sent from the cross-connect side into optical signals and transmits
the optical signals.
9.20.3 Functions and Features
The SF16 receives and transmits 1xOTU1 optical signals (2.666 Gbit/s with the FEC function)
and processes overhead bytes.
9.20.4 Working Principle and Signal Flow
The SF16 consists of the O/E converting module, MUX/DEMUX module, FEC module, SDH
overhead processing module, logic and control module, DC/DC converter, and other modules.
9.20.5 Front Panel
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The front panel of the SF16 has indicators, interfaces, a bar code, and a laser safety class label.
9.20.6 Valid Slots
The slots valid for the SF16 vary with the cross-connect capacity of the subrack.
9.20.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SF16 indicates the type of optical interface.
9.20.8 Parameter Settings
You can set the parameters for the SF16 by using the T2000.
9.20.9 Technical Specifications
The technical specifications of the SF16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.20.1 Version Description
The SF16 is available in one functional version, namely, N1.
9.20.2 Application
The SF16 is a line board. The SF16 can be used on the OptiX OSN equipment series to transmit
and receive STM-16 optical signals. The SF16 converts the received optical signals into
electrical signals and sends the electrical signals to the cross-connect side. In addition, the SF16
converts the electrical signals sent from the cross-connect side into optical signals and transmits
the optical signals.
Figure 9-66 shows the application of the SF16. The SF16 boards can form a ring network or a
chain network in the system.
Figure 9-66 Networking and application of the SF16
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.20.3 Functions and Features
The SF16 receives and transmits 1xOTU1 optical signals (2.666 Gbit/s with the FEC function)
and processes overhead bytes.
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Table 9-88 provides the functions and features of the SF16.
Table 9-88 Functions and features of the SF16
Function and
Feature
SF16
Basic functions l Receives and transmits 1xOTU1 optical signals (2.666 Gbit/s with the
FEC function).
l Supports the enabling or disabling of the FEC function.
Specifications
of the optical
interface
l Supports different types of standard optical interfaces, namely, the
Ve-16.2c, Ve-16.2d, and Ve-16.2f. The characteristics of the optical
interfaces comply with the standards defined by Huawei.
l Supports the output of the standard wavelengths that comply with ITU-
T G.692 and can be directly connected to the DWDM equipment.
Specifications
of the optical
module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting of
the on/off state of a laser.
Service
processing
l Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c
concatenation services, VC-4-8c concatenation services, and VC-4-16c
concatenation services.
l Encapsulates and encodes the signals with the FEC function, and
processes overhead bytes, which comply with ITU-T G.709.
Overhead
processing
l Supports the processing of the OTU, ODU, and OPU overhead bytes,
performance monitoring, and alarm detection, which comply with ITU-
T G.709.
l Processes the section overheads of the STM-16 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one channel of ECC communication.
Alarms and
performance
events
l Reports various alarms and performance events.
l Supports the alarms and performance events that are related to the OTU
layer, ODU layer, OPU layer, and FEC function.
Specifications
of the REG
Does not support the REG.
Protection
schemes
l Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.
l Supports the fiber-shared MSP and SNCP and processes two sets of K
bytes. One SF16 supports a maximum of two MSP protection rings.
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Function and
Feature
SF16
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the press-to-collect function in fault data collection.

9.20.4 Working Principle and Signal Flow
The SF16 consists of the O/E converting module, MUX/DEMUX module, FEC module, SDH
overhead processing module, logic and control module, DC/DC converter, and other modules.
Figure 9-67 shows the functional block diagram of the SF16.
Figure 9-67 Functional block diagram of the SF16
2.666
Gbit/s
FEC
Logic and
control module
Cross-connect
unit
+3.3 V backup
power
16x155
Mbit/s
16x155
Mbit/s
SDH overhead processing
module
DCC
K1 and K2 insertion/
extraction
SCC unit
LOS
Laser shutdown SCC unit
High-speed
bus
+3.3 V
RST MST MSA HPT
O/E
-48 V/-60 V
DC/DC
converter
Fuse
Fuse
DC/DC
converter
Cross-connect
unit
Cross-connect
unit
155 MHz PLL
Cross-connect
unit
155 MHz Reference clock
16x166
Mbit/s
16x166
Mbit/s
166 MHz PLL
IIC
MUX
155 MHz PLL
DEMUX
-48 V/-60 V
Cross-connect
unit
K1 and K2
Communication
Frame header
S
P
I
E/O
2.666
Gbit/s
2.666
Gbit/s
2.666
Gbit/s
High-speed
bus
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination IIC: inter-integrated circuit -

The functional modules are described as follows:
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O/E Converting Module
l In the receive direction, the module converts the received 2.666 Gbit/s FEC optical signals
into electrical signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function of shutting down the laser.
MUX/DEMUX Module
l In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.
l In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the FEC module into high-rate electrical signals.
FEC Module
l In the downstream direction, the FEC encoding and decoding module receives 2.488 Gbit/
s SDH signals, which are sent by the SDH overhead processing module. After frame
searching, FEC encoding, data packet encapsulation, and scrambling, the 2.488 Gbit/s SDH
signals are converted into 2.666 Gbit/s signals and then transmitted to the MUX module.
l In the upstream direction, the reverse process is performed. The FEC encoding and
decoding module receives the 2.666 Gbit/s signals from the DEMUX module. After frame
searching, FEC encoding, data packets encapsulation, and scrambling in the FEC module,
the 2.488 Gbit/s signals are recovered and then transmitted to the SDH overhead processing
module. The frame format of the 2.666 Gbit/s signals complies with ITU G.709.
l The FEC processing module is connected to the logic and control module through a CPU
bus. The CPU controls the working modes of the FEC module by configuring the internal
register. The working mode can be the regenerator mode, namely, REG mode. The CPU
can monitor the performance through the internal register.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
l MST sub-module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.
In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.
l MSA sub-module
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In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.
l HPT sub-module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and the standby cross-connect unit.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
9.20.5 Front Panel
The front panel of the SF16 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-68 shows the appearance of the front panel of the SF16.
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Figure 9-68 Front panel of the SF16
SF16
SF16
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
OUT
IN

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SF16 has one optical interface. Table 9-89 describes the types and usage
of the optical interfaces of the SF16.
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NOTE
The SF16 uses the unswappable optical module.
Table 9-89 Optical interfaces of the SF16
Interface Type of
Interface
Usage
IN LC Receives optical signals.
OUT LC Transmits optical signals.

9.20.6 Valid Slots
The slots valid for the SF16 vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SF16 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SF16 can be installed in slots 58 and
1114.
9.20.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SF16 indicates the type of optical interface.
Table 9-90 provides the relationship between the feature code of the SF16 and the type of optical
interface.
Table 9-90 Relationship between the feature code of the SF16 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SF1600 00 Colored optical interface
SSN1SF1601 01 Ue-16.2c/Ue-16.2d/Ue-16.2f

9.20.8 Parameter Settings
You can set the parameters for the SF16 by using the T2000.
You can set the following parameters for the SF16 by using the T2000:
l J0
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l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.20.9 Technical Specifications
The technical specifications of the SF16 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-91 lists the parameters specified for the optical interfaces of the SF16.
Table 9-91 Parameters specified for the optical interfaces of the SF16
Parameter Value
Nominal bit rate 2666057.143 kbit/s
Processing capability 1xSTM-16 standard services or concatenation services
Line code pattern NRZ
Application code
a
Ue-16.2c Ue-16.2d Ue-16.2f
FEC + BA (14) +
PA
FEC + BA (17) +
PA
FEC + BA (17) + RA + PA
Type of fiber Single-mode LC Single-mode LC Single-mode LC
Operating
wavelength range
(nm)
1550.12
Launched optical
power range (dBm)
b
-5 to -1 -5 to -1 -5 to -1
Launched optical
power range (dBm)
c
13 to 15 13 to 15 15 to 18
Receiver sensitivity
(dBm)
b
-27.5 -27.5 -27.5
Receiver sensitivity
(dBm)
d
-37 -37 -42
Minimum overload
(dBm)
d
-10 -10 -10
Minimum extinction
ratio (dB)
b
10 10 10
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Parameter Value
a: The numbers in the brackets indicate the corresponding parameter values. For example,
"BA (14)" indicates that the optical power amplified by the BA is 14 dBm. "FEC + BA + PA
+ RA" indicates that the specifications of the optical interface are measured when the FEC,
BA, PA, and Raman amplifier are used.
b: The parameter values are applicable only to the optical modules. The parameter values of
the amplifier are not provided.
c: The parameter values are applicable to the BA.
d: The parameter values are applicable to the PA.

SF16 supports the colored optical interfaces that comply with ITU-T G.692. Table 9-92 list the
parameters specified for the colored optical interfaces.
Table 9-92 Parameters specified for the optical interfaces that comply with the standard
wavelengths specified in ITU-T G.692
Parameter Value
Nominal bit rate 2666057.143 kbit/s
Dispersion limit (km) 640
Mean launched optical
power (dBm)
-5 to -1
Receiver sensitivity (dBm) -28
Minimum overload (dBm) -9
Maximum allowed
dispersion (ps/nm)
10880
Minimum extinction ratio
(dB)
8.2

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SF16 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.1
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Power Consumption
The maximum power consumption of the SF16 at room temperature (25C) is 26 W.
9.21 SL64
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SL64 (1xSTM-64 optical interface board). This topic also
describes how to configure and commission the SL64.
9.21.1 Version Description
The SL64 is available in several functional versions. The N2SL64 is discontinued. The functions
provided by the functional versions are different.
9.21.2 Application
The SL64 is a line board. The SL64 can be used on the OptiX OSN equipment series to transmit
and receive STM-64 optical signals. The SL64 converts the received optical signals into
electrical signals and sends the electrical signals to the cross-connect side. In addition, the SL64
converts the electrical signals sent from the cross-connect side into optical signals and transmits
the optical signals.
9.21.3 Functions and Features
The SL64 receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
9.21.4 Working Principle and Signal Flow
The SL64 consists of the O/E converting module, MUX/DEMUX Module, SDH overhead
processing module, logic and control module, and power module.
9.21.5 Front Panel
The front panel of the SL64 has indicators, interfaces, a bar code, a laser safety class label, and
an APD alarm label.
9.21.6 Jumpers and DIP Switches
The SL64 does not have any jumpers or DIP switches that are used for board settings.
9.21.7 Valid Slots
The SL64 must be installed in a valid slot in the subrack. Otherwise, the SL64 cannot work
normally.
9.21.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL64 indicates the type of optical interface.
9.21.9 Parameter Settings
You can set the parameters for the SL64 by using the T2000.
9.21.10 Technical Specifications
The technical specifications of the SL64 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.21.1 Version Description
The SL64 is available in several functional versions. The N2SL64 is discontinued. The functions
provided by the functional versions are different.
Table 9-93 describes the versions of the SL64.
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Table 9-93 Versions of the SL64
Item Description
Functional versions The SL64 is available in the following functional versions: N2 and
N1.
Differences l The N1SL64 supports the board version replacement function, but
does not support the TCM function or AU-3 services.
l The N2SL64 does not support the board version replacement
function, but supports the TCM function and AU-3 services, the
TCM function and AU-3 services cannot be available at the same
time.

NOTE
l When you configure the MSP or SNCP, you cannot configure the N1SL64 as the protection board if
the working board is the N2SL64 on which the TCM function is enabled or AU-3 services are
configured. Otherwise, the services are interrupted when a switching operation is performed.
9.21.2 Application
The SL64 is a line board. The SL64 can be used on the OptiX OSN equipment series to transmit
and receive STM-64 optical signals. The SL64 converts the received optical signals into
electrical signals and sends the electrical signals to the cross-connect side. In addition, the SL64
converts the electrical signals sent from the cross-connect side into optical signals and transmits
the optical signals.
Figure 9-69 shows the application of the SL64. The SL64 boards can form a ring network or a
chain network in the system.
Figure 9-69 Networking and application of the SL64
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

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9.21.3 Functions and Features
The SL64 receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
Table 9-94 provides the functions and features of the SL64.
Table 9-94 Functions and features of the SL64
Function and
Feature
SL64
Basic functions Transmits and receives 1xSTM-64 optical signals.
Specifications of the
optical interface
l N1SL64/N2SL64 supports different types of standard optical
interfaces, namely, the I-64.2, S-64.2b, L-64.2b, Le-64.2, Ls-64.2,
and V-64.2b (BA + PA + dispersion compensation unit (DCU)).
The characteristics of the optical interfaces of the S-64.2b, L-64.2b,
Ls-64.2, and V-64.2b types comply with ITU-T G.691 and ITU-T
G.692. The characteristics of the optical interface of the Le-64.2
type comply with the standards defined by Huawei.
l Supports the output of the standard wavelengths that comply with
ITU-T G.692 and can be directly connected to the WDM
equipment.
Specifications of the
optical module
l Supports the detection and query of the information about the
optical module.
l Provides the ALS function. The optical interface supports the
setting of the on/off state of a laser.
Service processing l Supports the VC-12 services, VC-3 services, and VC-4 services.
l The N1SL64 and N2SL64 support the VC-4-4c concatenation
services, VC-4-8c concatenation services, Vc-4-16c concatenation
services, and VC-4-64c concatenation services.
l The N2SL64 supports the AU-3 services.
Overhead processing l Processes the section overheads of the STM-64 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one channel of ECC communication.
Alarms and
performance events
l Reports various alarms and performance events.
Specifications of the
REG
Supports the setting and query of the REG working mode.
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Function and
Feature
SL64
Protection schemes l Supports the two-fiber ring MSP.
l Supports the four-fiber ring MSP.
l Supports the linear MSP.
l Supports the SNCP.
l Supports the SNCMP.
l Supports the SNCTP.
l Supports the fiber-shared virtual trail protection.
l Supports the fiber-shared MSP and processes two sets of K bytes.
One SL64 supports a maximum of two MSP rings.
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l The N1SL64 supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not
affect services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l The N2SL64 supports the TCM function.
l Supports the upgrade of the board software without affecting
services.
l Supports the press-to-collect function in fault data collection.

9.21.4 Working Principle and Signal Flow
The SL64 consists of the O/E converting module, MUX/DEMUX Module, SDH overhead
processing module, logic and control module, and power module.
Figure 9-70 shows the functional block diagram of the N1SL64/N2SL64.
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Figure 9-70 Functional block diagram of the N1SL64/N2SL64
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
622 MHz
Reference clock
K1 and K2
insertion/extraction
MSA HPT MST RST
-48 V/-60 V
Frame header Cross-connect
unit
K1 and K2
Power
module
SCC unit
Backplane
9.953
Gbit/s
16x622
Mbit/s
LOS
Laser shutdown
DEMUX
IIC
9.953
Gbit/s
9.953
Gbit/s
9.953
Gbit/s
16x622
Mbit/s
MUX/
DEMUX
O/E
SPI
E/O
O/E
converting
module
622 MHz
PLL
MUX
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination - -

O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l Detects the R_LOS alarm and provides the function of shutting down the laser.
MUX/DEMUX Module
l In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.
l In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module terminates the RSOH. That is, the RST
sub-module detects the frame alignment bytes (A1 and A2), descrambles all the bytes
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except the first line of the RSOH, restores and checks the J0 byte, and checks the B1
byte.
In the transmit direction, the RST sub-module generates the RSOH. That is, the RST
sub-module writes bytes such as A1, A2, and J0, calculates and writes the B1 byte, and
scrambles all the bytes except the first line of the RSOH.
l MST sub-module
In the receive direction, the MST sub-module terminates the MSOH. That is, the MST
sub-module generates the MS_AIS or MS_RDI alarm after detecting the K2 byte,
generates the B2_SD or B2_EXC alarm after checking the B2 byte, and reports the
MS_REI alarm to the opposite end.
In the transmit direction, the MST sub-module generates the MSOH. That is, the MST
sub-module writes bytes such as E2, D4-D12, K1, K2, S1, and M1, calculates the BIP
check value, and writes the B2 byte.
l MSA sub-module
In the receive direction, the MSA sub-module de-interleaves the AUG, divides an AUG
into N AU-4s, detects the AU_LOP alarm and the AU_AIS alarm, and performs pointer
justifications.
In the transmit direction, the MSA sub-module adds the VC-4 to the AU-PTR and
generates the AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
l HPT sub-module
In the receive direction, the HPT sub-module terminates the POH. That is, the HPT sub-
module reports the HP_REI alarm to the opposite end after checking the B3 byte,
generates the HP_TIM alarm and the HP_SLM alarm, as well as the HP_UNEQ alarm
if the VC-4 path is found unequipped, after detecting the J1 and C2 bytes, and reports
the HP_RDI alarm to the opposite end.
In the transmit direction, the HPT sub-module generates the POH. That is, the HPT sub-
module writes bytes such as J1 and C2, calculates the BIP check value, and writes the
B3 byte.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not in position.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
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9.21.5 Front Panel
The front panel of the SL64 has indicators, interfaces, a bar code, a laser safety class label, and
an APD alarm label.
Diagram of the Front Panel
.
Figure 9-71 Appearance of the front panel of the SL64
SL64
SL64
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
OUT
IN
! APD
Receiver
MAX:-9dBm

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
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l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SL64 has one optical interface. Table 9-95 describes the types and usage
of the optical interfaces of the SL64.
Table 9-95 Optical interfaces of the SL64
Interface Type of Interface Usage
IN LC Receives optical signals.
OUT LC Transmits optical signals.

9.21.6 Jumpers and DIP Switches
The SL64 does not have any jumpers or DIP switches that are used for board settings.
9.21.7 Valid Slots
The SL64 must be installed in a valid slot in the subrack. Otherwise, the SL64 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SL64 vary with the cross-connect capacity of the subrack. The slots valid
for the SL64 are as follows:
9.21.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL64 indicates the type of optical interface.
Table 9-96 provides the relationship between the feature code of the SL64 and the type of optical
interface.
Table 9-96 Relationship between the feature code of the SL64 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SL6400 00 Fixed-wavelength optical
interface
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Board Feature Code Type of Optical Interface
SSN1SL6401 01 I-64.2
SSN1SL6402 02 S-64.2b
SSN1SL6403 03 Le-64.2
SSN1SL6404 04 Ls-64.2
SSN1SL6405 05 L-64.2b
SSN1SL6406 06 V-64.2b
SSN2SL6400 00 Fixed-wavelength optical
interface
SSN2SL6411 11 I-64.2
SSN2SL6412 12 S-64.2b
SSN2SL6413 13 Le-64.2
SSN2SL6404 04 Ls-64.2
SSN2SL6415 15 L-64.2b
SSN2SL6416 16 V-64.2b

9.21.9 Parameter Settings
You can set the parameters for the SL64 by using the T2000.
You can set the following parameters for the SL64 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.21.10 Technical Specifications
The technical specifications of the SL64 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-97 lists the parameters specified for the optical interfaces of the SL64.
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Table 9-97 Parameters specified for the optical interfaces of the SL64
Paramet
er
Value
Nominal
bit rate
9953280 kbit/s
Applicati
on code
I-64.1 I-64.2 S-64.
2b
L-64.2b (BA) Le-64
.2
Ls-64
.2
V-64.2b (BA +
PA + DCU)
a
Transmiss
ion
distance
(km)
0 to 2 0 to
25
2 to 40 35 to 80 35 to
60
55 to
80
80 to 120
Type of
fiber
Singl
e-
mode
LC
Singl
e-
mode
LC
Single
-mode
LC
Single-mode
LC
Singl
e-
mode
LC
Singl
e-
mode
LC
Single-mode LC
Operating
wavelengt
h range
(nm)
1290
to
1330
1530
to
1565
1530
to
1565
1530 to 1565 1530
to
1565
1530
to
1565
1550.12
Mean
launched
optical
power
(dBm)
-6 to
-1
-5 to
-1
-1 to
+2
-4 to +2
(without the
BA)
13 to 15 (with
the BA)
2 to 4 4 to 7 -4 to -1 (without
the BA, PA, or
DCU)
13 to 15 (with the
BA)
Receiver
sensitivity
(dBm)
-11 -14 -14 -14 -21 -21 -14 (without the
PA, BA, or DCU)
-26 (with the PA)
Minimum
overload
(dBm)
-1 -1 -1 -1 -8 -8 -1
Minimum
extinction
ratio (dB)
6 8.2 8.2 8.2 8.2 8.2 8.2
Maximum
dispersion
tolerance
(ps/nm)
6.6 500 800 1600 1200 1600
2040
c
a: "BA + PA + DCU" indicates that the specifications of the V-64.2b optical interface are
measured when the BA, PA, and DCU are used.
c: The dispersion coefficient is 17 ps/nm when signals are transmitted by the G.652 fibers at
the wavelength of 1550.12 nm. Hence, the dispersion tolerance is 2040 ps/nm for a 120-km
distance.

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SL64 supports the colored optical interfaces that comply with ITU-T G.692. Table 9-98 list the
parameters specified for the colored optical interfaces.
Table 9-98 Parameters specified for the optical interfaces that comply with the standard
wavelengths specified in ITU-T G.692
Parameter Value
Nominal bit rate 9953280 kbit/s
Dispersion limit (km) 40
Mean launched optical power (dBm) -4 to -1
Receiver sensitivity (dBm) -14
Minimum overload (dBm) -1
Maximum allowed dispersion (ps/
nm)
800
Minimum extinction ratio (dB) 10

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SL64 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.1
Power Consumption
The maximum power consumption of the N1SL64 at room temperature (25C) is 30 W.
The maximum power consumption of the N2SL64 at room temperature (25C) is 32 W.
9.22 SLD64
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SLD64 (2xSTM-64 optical interface board). This topic also
describes how to configure and commission the SLD64.
9.22.1 Version Description
The SLD64 is available in the following functional version: N1.
9.22.2 Application
The SLD64 is a line board. The SLD64 can be used on the OptiX OSN equipment series to
transmit and receive STM-64 optical signals. The SLD64 converts the received optical signals
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into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SLD64 converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
9.22.3 Functions and Features
The SLD64 receives and transmits 2xSTM-64 optical signals, processes overhead bytes, and
performs the MSP protection.
9.22.4 Working Principle and Signal Flow
The SLD64 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, and power module.
9.22.5 Front Panel
The front panel of the SLD64 has indicators, interfaces, a bar code, and a laser safety class label.
9.22.6 Jumpers and DIP Switches
The SLD64 does not have any jumpers or DIP switches that are used for board settings.
9.22.7 Valid Slots
The SLD64 must be installed in a valid slot in the subrack. Otherwise, the SLD64 cannot work
normally.
9.22.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLD64 indicates the type of optical interface.
9.22.9 Parameter Settings
You can set the parameters for the SLD64 by using the T2000.
9.22.10 Technical Specifications
The technical specifications of the SLD64 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.22.1 Version Description
The SLD64 is available in the following functional version: N1.
9.22.2 Application
The SLD64 is a line board. The SLD64 can be used on the OptiX OSN equipment series to
transmit and receive STM-64 optical signals. The SLD64 converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SLD64 converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
Figure 9-72 shows the application of the SLD64. The SLD64 boards can form a ring network
or a chain network in the system.
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Figure 9-72 Networking and application of the SLD64
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

9.22.3 Functions and Features
The SLD64 receives and transmits 2xSTM-64 optical signals, processes overhead bytes, and
performs the MSP protection.
Table 9-99 provides the functions and features of the SLD64.
Table 9-99 Functions and features of the SLD64
Function and
Feature
SLD64
Basic functions Provides two optical interfaces to transmit and receive 2xSTM-64
optical signals. Processes 2xSTM-64 standard services or concatenated
services, which are encapsulated in XFP format.
Specifications of
the optical interface
Supports different types of standard optical interfaces, namely, the
I-64.1 and S-64.2b. The characteristics of the optical interfaces comply
with ITU-T G.691.
Specifications of
the optical module
l Supports the query of the manufacturing information of the optical
module. The SLD64 also reports the performance events that
indicate the performance of the optical module.
l Supports the default off state of the laser, and the setting and query
of the on/off state of the laser.
Service processing Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c
concatenation services, VC-4-8c concatenation services, VC-4-16c
concatenation services, and VC-4-64c concatenation services.
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Function and
Feature
SLD64
Overhead
processing
l Processes the section overheads of the STM-64 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one or two channels of ECC communication.
Alarms and
performance events
Reports various alarms and performance events.
Specifications of
the REG
Does not support the REG.
Protection schemes l Supports the two-fiber ring MSP.
l Supports the four-fiber ring MSP.
l Supports the linear MSP.
l Supports the SNCP.
l Supports the SNCMP.
l Supports the SNCTP.
l Supports the fiber-shared virtual trail protection.
l Supports the fiber-shared MSP and processes four sets of K bytes.
A single optical interface can process two sets of K bytes. One
SLD64 supports a maximum of four MSP rings.
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting
services.
l Supports the press-to-collect function in fault data collection.

9.22.4 Working Principle and Signal Flow
The SLD64 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, and power module.
Figure 9-73 shows the functional block diagram of the SLD64.
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Figure 9-73 Functional block diagram of the SLD64
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
Cross-connect
unit
622 MHz
Reference clock
K1 and K2
insertion/extraction
MSA HPT MST RST
-48 V/-60 V
Frame header Cross-connect
unit
K1 and K2
Power
module
SCC unit
Backplane
9.953
Gbit/s
16x622
Mbit/s
LOS
Laser shutdown
DEMUX
IIC
9.953
Gbit/s
9.953
Gbit/s
9.953
Gbit/s
16x622
Mbit/s
MUX/
DEMUX
O/E
converting
module
.

.
.

.
O/E
E/O
SPI
O/E
SPI
E/O
622 MHz
PLL
MUX
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination - -

O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l Detects the R_LOS alarm and provides the function of shutting down the laser.
MUX/DEMUX Module
l In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.
l In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module terminates the RSOH. That is, the RST
sub-module detects the frame alignment bytes (A1 and A2), descrambles all the bytes
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except the first line of the RSOH, restores and checks the J0 byte, and checks the B1
byte.
In the transmit direction, the RST sub-module generates the RSOH. That is, the RST
sub-module writes bytes such as A1, A2, and J0, calculates and writes the B1 byte, and
scrambles all the bytes except the first line of the RSOH.
l MST sub-module
In the receive direction, the MST sub-module terminates the MSOH. That is, the MST
sub-module generates the MS_AIS or MS_RDI alarm after detecting the K2 byte,
generates the B2_SD or B2_EXC alarm after checking the B2 byte, and reports the
MS_REI alarm to the opposite end.
In the transmit direction, the MST sub-module generates the MSOH. That is, the MST
sub-module writes bytes such as E2, D4-D12, K1, K2, S1, and M1, calculates the BIP
check value, and writes the B2 byte.
l MSA sub-module
In the receive direction, the MSA sub-module de-interleaves the AUG, divides an AUG
into N AU-4s, detects the AU_LOP alarm and the AU_AIS alarm, and performs pointer
justifications.
In the transmit direction, the MSA sub-module adds the VC-4 to the AU-PTR and
generates the AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
l HPT sub-module
In the receive direction, the HPT sub-module terminates the POH. That is, the HPT sub-
module reports the HP_REI alarm to the opposite end after checking the B3 byte,
generates the HP_TIM alarm and the HP_SLM alarm, as well as the HP_UNEQ alarm
if the VC-4 path is found unequipped, after detecting the J1 and C2 bytes, and reports
the HP_RDI alarm to the opposite end
In the transmit direction, the HPT sub-module generates the POH. That is, the HPT sub-
module writes bytes such as J1 and C2, calculates the BIP check value, and writes the
B3 byte.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Selects and traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not in position.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
9.22.5 Front Panel
The front panel of the SLD64 has indicators, interfaces, a bar code, and a laser safety class label.
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Diagram of the Front Panel
Figure 9-74 shows the appearance of the front panel of the SLD64.
Figure 9-74 Front panel of the SLD64
SLD64
SLD64
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
OUT1
IN1
OUT2
IN2

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the SLD64 has two optical interfaces. Table 9-100 describes the types and
usage of the optical interfaces of the SLD64.
Table 9-100 Optical interfaces of the SLD64
Interface Type of Interface Usage
IN1IN2 LC Receives optical signals.
OUT1OUT2 LC Transmits optical signals.

9.22.6 Jumpers and DIP Switches
The SLD64 does not have any jumpers or DIP switches that are used for board settings.
9.22.7 Valid Slots
The SLD64 must be installed in a valid slot in the subrack. Otherwise, the SLD64 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SLD64 vary with the cross-connect capacity of the subrack. The slots
valid for the SLD64 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SLD64 can be installed in slots 7, 8, 11,
and 12.
9.22.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLD64 indicates the type of optical interface.
Table 9-101 provides the relationship between the feature code of the SLD64 and the type of
optical interface.
Table 9-101 Relationship between the feature code of the SLD64 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SLD6401 01 I-64.1
SSN1SLD6402 02 S-64.2b

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9.22.9 Parameter Settings
You can set the parameters for the SLD64 by using the T2000.
You can set the following parameters for the SLD64 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.22.10 Technical Specifications
The technical specifications of the SLD64 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-102 lists the parameters specified for the optical interfaces of the SLD64.
Table 9-102 Parameters specified for the optical interfaces of the SLD64
Parameter Value
Nominal bit rate 9953280 kbit/s
Application code I-64.1 S-64.2b
Transmission distance
(km)
0 to 2 2 to 40
Type of fiber Single-mode LC Single-mode LC
Operating wavelength
range (nm)
1290 to 1330 1530 to 1565
Mean launched optical
power (dBm)
-6 to -1 -1 to +2
Receiver sensitivity
(dBm)
-11 -14
Minimum overload
(dBm)
-1 -1
Minimum extinction
ratio (dB)
6 8.2
Maximum dispersion
tolerance (ps/nm)
6.6 800

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Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SLD64 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.2
Power Consumption
The maximum power consumption of the N1SLD64 at room temperature (25C) is 41 W.
9.23 SF64
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SF64 (1xSTM-64 optical interface board with the FEC function).
This topic also describes how to configure and commission the SF64.
9.23.1 Version Description
The SF64 is available in the following functional version: N1.
9.23.2 Application
The SF64 is a line board. The SF64 can be used on the OptiX OSN equipment series to transmit
and receive STM-64 optical signals. The SF64 converts the received optical signals into
electrical signals and sends the electrical signals to the cross-connect side. In addition, the SF64
converts the electrical signals sent from the cross-connect side into optical signals and transmits
the optical signals.
9.23.3 Functions and Features
The SF64 receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
9.23.4 Working Principle and Signal Flow
The SF64 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, and power module.
9.23.5 Front Panel
The front panel of the SF64 has indicators, interfaces, a bar code, and a laser safety class label.
9.23.6 Jumpers and DIP Switches
The SF64 does not have any jumpers or DIP switches that are used for board settings.
9.23.7 Valid Slots
The SF64 must be installed in a valid slot in the subrack. Otherwise, the SF64 cannot work
normally.
9.23.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SF64 indicates the type of optical interface.
9.23.9 Parameter Settings
You can set the parameters for the SF64 by using the T2000.
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9.23.10 Technical Specifications
The technical specifications of the SF64 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.23.1 Version Description
The SF64 is available in the following functional version: N1.
9.23.2 Application
The SF64 is a line board. The SF64 can be used on the OptiX OSN equipment series to transmit
and receive STM-64 optical signals. The SF64 converts the received optical signals into
electrical signals and sends the electrical signals to the cross-connect side. In addition, the SF64
converts the electrical signals sent from the cross-connect side into optical signals and transmits
the optical signals.
Figure 9-75 shows the application of the SF64. The SF64 boards can form a ring network or a
chain network in the system.
Figure 9-75 Networking and application of the SF64
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

The SF64 can be interconnected with the WDM equipment.
9.23.3 Functions and Features
The SF64 receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
Table 9-103 provides the functions and features of the SF64.
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Table 9-103 Functions and features of the SF64
Function and
Feature
SF64
Basic functions l Transmits and receives 1xSTM-64 optical signals.
l Supports the enabling or disabling of the FEC function.
Specifications of
the optical interface
l Supports different types of standard optical interfaces, namely, the
Ue-64.2c, Ue-64.2d, and Ue-64.2e. The characteristics of the optical
interfaces comply with the standards defined by Huawei.
l Supports the output of the standard wavelengths that comply with
ITU-T G.692 and can be directly connected to the DWDM
equipment.
Specifications of
the optical module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
Service processing Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c
concatenation services, VC-4-8c concatenation services, VC-4-16c
concatenation services, and VC-4-64c concatenation services.
Overhead
processing
l Processes the section overheads of the STM-64 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one channel of ECC communication.
Alarms and
performance events
Reports various alarms and performance events.
Specifications of
the REG
Supports the setting and query of the REG working mode.
Protection schemes l Supports the two-fiber ring MSP.
l Supports the four-fiber ring MSP.
l Supports the linear MSP.
l Supports the SNCP.
l Supports the SNCMP.
l Supports the SNCTP.
l Supports the fiber-shared virtual trail protection.
l Supports the fiber-shared MSP and processes two sets of K bytes.
One SF64 supports a maximum of two MSP rings.
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Function and
Feature
SF64
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting
services.
l Supports the press-to-collect function in fault data collection.

9.23.4 Working Principle and Signal Flow
The SF64 consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, and power module.
Figure 9-76 shows the functional block diagram of the SF64.
Figure 9-76 Functional block diagram of the SF64
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
622 MHz
PLL
Cross-connect
unit
622 MHz Reference clock
K1 and K2
insertion/extraction
MSA HPT MST RST
-48 V/-60 V
Frame header Cross-connect
unit
K1 and K2
Power
module
SCC unit
Backplane
10.71
Gbit/s
16x622
Mbit/s
LOS
Laser shutdown
DEMUX
IIC
10.71
Gbit/s
10.71
Gbit/s
10.71
Gbit/s
16x622
Mbit/s
MUX/
DEMUX
O/E
SPI
E/O
O/E
converting
module
FEC
622 MHz
PLL
16x669
Mbit/s
16x669
Mbit/s
669 MHz
PLL
MUX
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination - -

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O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l Detects the R_LOS alarm and provides the function of shutting down the laser.
MUX/DEMUX Module
l In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.
l In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module terminates the RSOH. That is, the RST
sub-module detects the frame alignment bytes (A1 and A2), descrambles all the bytes
except the first line of the RSOH, restores and checks the J0 byte, and checks the B1
byte.
In the transmit direction, the RST sub-module generates the RSOH. That is, the RST
sub-module writes bytes such as A1, A2, and J0, calculates and writes the B1 byte, and
scrambles all the bytes except the first line of the RSOH.
l MST sub-module
In the receive direction, the MST sub-module terminates the MSOH. That is, the MST
sub-module generates the MS_AIS or MS_RDI alarm after detecting the K2 byte,
generates the B2_SD or B2_EXC alarm after checking the B2 byte, and reports the
MS_REI alarm to the opposite end.
In the transmit direction, the MST sub-module generates the MSOH. That is, the MST
sub-module writes bytes such as E2, D4-D12, K1, K2, S1, and M1, calculates the BIP
check value, and writes the B2 byte.
l MSA sub-module
In the receive direction, the MSA sub-module de-interleaves the AUG, divides an AUG
into N AU-4s, detects the AU_LOP alarm and the AU_AIS alarm, and performs pointer
justifications.
In the transmit direction, the MSA sub-module adds the VC-4 to the AU-PTR and
generates the AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
l HPT sub-module
In the receive direction, the HPT sub-module terminates the POH. That is, the HPT sub-
module reports the HP_REI alarm to the opposite end after checking the B3 byte,
generates the HP_TIM alarm and the HP_SLM alarm, as well as the HP_UNEQ alarm
if the VC-4 path is found unequipped, after detecting the J1 and C2 bytes, and reports
the HP_RDI alarm to the opposite end.
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In the transmit direction, the HPT sub-module generates the POH. That is, the HPT sub-
module writes bytes such as J1 and C2, calculates the BIP check value, and writes the
B3 byte.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Selects and traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not in position.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
9.23.5 Front Panel
The front panel of the SF64 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-77 shows the appearance of the front panel of the SF64.
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Figure 9-77 Front panel of the SF64
SF64
SF64
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
OUT
IN

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SF64 has one optical interface. Table 9-104 describes the types and usage
of the optical interfaces of the SF64.
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Table 9-104 Optical interfaces of the SF64
Interface Type of Interface Usage
IN LC Receives optical signals.
OUT LC Transmits optical signals.

9.23.6 Jumpers and DIP Switches
The SF64 does not have any jumpers or DIP switches that are used for board settings.
9.23.7 Valid Slots
The SF64 must be installed in a valid slot in the subrack. Otherwise, the SF64 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SF64 vary with the cross-connect capacity of the subrack. The slots valid
for the SF64 are as follows:
9.23.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SF64 indicates the type of optical interface.
Table 9-105 provides the relationship between the feature code of the SF64 and the type of
optical interface.
Table 9-105 Relationship between the feature code of the SF64 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1SF6400 00 Fixed-wavelength optical
interface
SSN1SF6401 01 Ue-64.2c, Ue-64.2d, and
Ue-64.2e

9.23.9 Parameter Settings
You can set the parameters for the SF64 by using the T2000.
You can set the following parameters for the SF64 by using the T2000:
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l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.23.10 Technical Specifications
The technical specifications of the SF64 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-106 lists the parameters specified for the optical interfaces of the SF64.
Table 9-106 Specifications of optical interfaces of the SF64
Parameter Value
Nominal bit rate 10.709 Gbit/s
Line code
pattern
DRZ
Application
code
a
Ue-64.2c Ue-64.2d Ue-64.2e
FEC + BA (14 dB) +
PA
b
+ DCU (60 + 80)
FEC + BA (17 dB) + PA +
DCU (80 x 2)
FEC + BA (17 dB) +
RA + PA + DCU (60
x 3)
Type of fiber Single-mode LC
Operating
wavelength
range (nm)
1550.12
Launched
optical power
range (dBm)
c
-4 to -1
Minimum
extinction ratio
(dB)
10
a: The numbers in the brackets indicate the corresponding parameter values. For example,
"BA (14 dB)" indicates that the optical power amplified by the BA is 14 dBm.
b: "FEC + BA + PA + RA" indicates that the specifications of the optical interface are
measured when the FEC, BA, PA, and Raman amplifier are used.
c: The parameters are only for the optical modules. The parameters of the amplifier are not
provided.

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SF64 supports the colored optical interfaces that comply with ITU-T G.692. Table 9-107 list
the parameters specified for the colored optical interfaces.
Table 9-107 Parameters specified for the optical interfaces that comply with the standard
wavelengths specified in ITU-T G.692
Parameter Value
Nominal bit rate 10.709 Gbit/s
Dispersion limit (km) 40
Mean launched optical power (dBm) -4 to -1
Receiver sensitivity (dBm) -14
Minimum overload (dBm) -1
Maximum allowed dispersion (ps/
nm)
800
Minimum extinction ratio (dB) 10

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SF64 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight of the SF64 (kg): 1.1
Power Consumption
At room temperature (25C), the maximum power consumption of the SF64 is 33 W.
9.24 SF64A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the SF64A (1xSTM-64 optical interface board with the FEC function).
9.24.1 Version Description
The SF64A is available in one functional version, namely, N1.
9.24.2 Application
The SF64A is a line board. The SF64A can be used on the OptiX OSN equipment series to
transmit and receive STM-64 optical signals. The SF64A converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SF64A converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
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9.24.3 Functions and Features
The SF64A receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
9.24.4 Working Principle and Signal Flow
The SF64A consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, power module, and other modules.
9.24.5 Front Panel
The front panel of the SF64A has indicators, interfaces, a bar code, and a laser safety class label.
9.24.6 Valid Slots
The slots valid for the SF64A vary with the cross-connect capacity of the subrack.
9.24.7 Parameter Settings
You can set the parameters for the SF64A by using the T2000.
9.24.8 Technical Specifications
The technical specifications of the SF64A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.24.1 Version Description
The SF64A is available in one functional version, namely, N1.
9.24.2 Application
The SF64A is a line board. The SF64A can be used on the OptiX OSN equipment series to
transmit and receive STM-64 optical signals. The SF64A converts the received optical signals
into electrical signals and sends the electrical signals to the cross-connect side. In addition, the
SF64A converts the electrical signals sent from the cross-connect side into optical signals and
transmits the optical signals.
Figure 9-78 shows the application of the SF64A. The SF64A boards can form a ring network
or a chain network in the system.
Figure 9-78 Networking and application of the SF64A
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

The SF64A can also be used for interconnecting with the WDM equipment.
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9.24.3 Functions and Features
The SF64A receives and transmits 1xSTM-64 optical signals and processes overhead bytes.
Table 9-108 provides the functions and features of the SF64A.
Table 9-108 Functions and features of the SF64A
Function and
Feature
SF64A
Basic functions l Transmits and receives 1xSTM-64 optical signals.
l Supports the enabling or disabling of the FEC function.
Specifications of
the optical interface
l Supports different types of standard optical interfaces, namely, the
Ue-64.2c, Ue-64.2d, and Ue-64.2e. The characteristics of the optical
interfaces comply with the standards defined by Huawei.
l Supports the output of the standard wavelengths that comply with
ITU-T G.692 and can be directly connected to the DWDM
equipment. Supports the variable-wavelength DWDM.
Specifications of
the optical module
l Supports the detection and query of the information about the optical
module.
l Provides the ALS function. The optical interface supports the setting
of the on/off state of a laser.
Service processing Supports the VC-12 services, VC-3 services, VC-4 services, VC-4-4c
concatenation services, VC-4-8c concatenation services, VC-4-16c
concatenation services, and VC-4-64c concatenation services.
Overhead
processing
l Processes the section overheads of the STM-64 signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one channel of ECC communication.
Alarms and
performance events
Reports various alarms and performance events.
Specifications of
the REG
Supports the setting and query of the REG working mode.
Protection schemes l Supports the two-fiber ring MSP, four-fiber ring MSP, linear MSP,
SNCP, SNCTP, and SNCMP.
l Supports the fiber-shared MSP and SNCP and processes two sets of
K bytes. One SF64A supports a maximum of two MSP protection
rings.
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Function and
Feature
SF64A
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting
services.
l Supports the press-to-collect function in fault data collection.

9.24.4 Working Principle and Signal Flow
The SF64A consists of the O/E converting module, MUX/DEMUX module, SDH overhead
processing module, logic and control module, power module, and other modules.
Figure 9-79 shows the functional block diagram of the SF64A.
Figure 9-79 Functional block diagram of the SF64A
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
622 MHz
PLL
Cross-connect
unit
622 MHz Reference clock
K1 and K2
insertion/extraction
MSA HPT MST RST
-48 V/-60 V
Frame header Cross-connect
unit
K1 and K2
Power
module
SCC unit
Backplane
10.71
Gbit/s
16x622
Mbit/s
LOS
Laser shutdown
DEMUX
IIC
10.71
Gbit/s
10.71
Gbit/s
10.71
Gbit/s
16x622
Mbit/s
MUX/
DEMUX
O/E
SPI
E/O
O/E
converting
module
FEC
622 MHz
PLL
16x669
Mbit/s
16x669
Mbit/s
669 MHz
PLL
MUX
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination IIC: inter-integrated circuit -

The functional modules are described as follows:
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O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l The SPI detects the R_LOS alarm and provides the function of shutting down the laser.
MUX/DEMUX Module
l In the receive direction, the DEMUX part demultiplexes the high-rate electrical signals into
multiple parallel electrical signals and restores the clock signal at the same time.
l In the transmit direction, the MUX part multiplexes the parallel electrical signals received
from the SDH overhead processing module into high-rate electrical signals.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), performs descrambling, restores the regenerator section trace byte (J0), detects a
J0 mismatch, and counts BIP-8 errored blocks.
In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, performs scrambling, and performs BIP-8 calculation and insertion.
l MST sub-module
In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores
the MS_REI, and detects the MS_RDI, MS_AIS, and MS-EXC.
In the transmit direction, the MST sub-module performs BIP-24 calculation and
insertion and inserts the MS_REI, MS_RDI, and MS_AIS.
The MST sub-module extracts or inserts the K1, K2, E2, D4D12, S1, B2, and M1
bytes.
l MSA sub-module
In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the
LOP and AIS, and performs pointer justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4 pointer and the AU_AIS.
l HPT sub-module
Terminates the overheads.
Restores the J1 path trace message.
Restores the REI information.
Detects the HP_RDI (monitors the status of the path).
Detects the UNEQ and AIS (monitors the signal label).
Counts the VC-4 BIP-8 errored blocks.
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Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not online.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
9.24.5 Front Panel
The front panel of the SF64A has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-80 shows the appearance of the front panel of the SF64A.
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Figure 9-80 Front panel of the SF64A
SF64A
SF64A
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
OUT
IN

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SF64A has one optical interface. Table 9-109 describes the types and
usage of the optical interfaces of the SF64A.
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Table 9-109 Optical interfaces of the SF64A
Interface Type of
Interface
Usage
IN LC Receives optical signals.
OUT LC Transmits optical signals.

9.24.6 Valid Slots
The slots valid for the SF64A vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the SF64A are as follows:
l When the cross-connect capacity is 200 Gbit/s, the SF64A can be installed in slots 7, 8, 11,
and 12.
9.24.7 Parameter Settings
You can set the parameters for the SF64A by using the T2000.
You can set the following parameters for the SF64A by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.24.8 Technical Specifications
The technical specifications of the SF64A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-110 lists the parameters specified for the optical interfaces of the SF64A.
Table 9-110 Specifications of optical interfaces of the SF64A
Parameter Value
Nominal bit rate 10709225 kbit/s
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Parameter Value
Application code Ue-64.2c Ue-64.2d Ue-64.2e
Meaning of the
code
a
FEC + BA (14 dB) +
PA + DCU (60 + 80)
c
FEC + BA (17 dB) +
PA + DCU (80 x 2)
FEC + BA (17 dB) +
RA + PA + DCU (60
x 3)
Operating
wavelength range
(nm)
1550.12 1550.12 1550.12
Type of fiber Single-mode LC
Launched optical
power range (dBm)
b
-4 to -1 -4 to -1 -4 to -1
Receiver
sensitivity (dBm)
b
-14 -14 -14
Minimum overload
(dBm)
b
-1 -1 -1
Minimum
extinction ratio
(dB)
b
10 10 10
Dispersion
tolerance (ps/nm)
b
800 800 800
a: The numbers in the brackets indicate the corresponding parameter values. For example,
"BA (14 dB)" indicates that the optical power amplified by the BA is 14 dBm. "FEC + BA +
PA + RA" indicates that the specifications of the optical interface are measured when the
FEC, BA, PA, and Raman amplifier (RA) are used.
b: The parameter values are applicable only to the optical modules. The parameter values of
the amplifier and dispersion compensation unit (DCU) are not provided.
c: The parameter values indicate the distances that correspond to different dispersion
compensation values.

SF64A supports the colored optical interfaces that comply with ITU-T G.692. Table 9-111 list
the parameters specified for the colored optical interfaces.
Table 9-111 Parameters specified for the optical interfaces that comply with the standard
wavelengths specified in ITU-T G.692
Parameter Value
Nominal bit rate 10.709 Gbit/s
Dispersion limit (km) 80
Mean launched optical power (dBm) -4 to -1
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Parameter Value
Receiver sensitivity (dBm) -14
Minimum overload (dBm) 0
Maximum allowed dispersion (ps/
nm)
800
Minimum extinction ratio (dB) 13.5

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SF64A are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.1
Power Consumption
At room temperature (25C), the maximum power consumption of the SF64A is 33 W.
9.25 SLQ41
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SLQ41 (4xSTM-4/STM-1 optical interface board). This topic also
describes how to configure and commission the SLQ41.
9.25.1 Version Description
The SLQ41 is available in one functional version, namely, N3. The SLQ41 supports the auto-
sensing of optical interfaces.
9.25.2 Application
The SLQ41 is a line board. The SLQ41 can be used on the OptiX OSN equipment series to
transmit and receive STM-1/STM-4 optical signals. The SLQ41 converts the received optical
signals into electrical signals and sends the electrical signals to the cross-connect side. In
addition, the SLQ41 converts the electrical signals sent from the cross-connect side into optical
signals and transmits the optical signals.
9.25.3 Functions and Features
The SLQ41 transmits and receives STM-1 or STM-4 optical signals, performs O/E conversion
for the STM-1 or STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm
signals on the line.
9.25.4 Working Principle and Signal Flow
The SLQ41 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, and power module.
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9.25.5 Front Panel
The front panel of the SLQ41 has indicators, interfaces, a bar code, and a laser safety class label.
9.25.6 Jumpers and DIP Switches
The SLQ41 does not have any jumpers or DIP switches that are used for board settings.
9.25.7 Valid Slots
The SLQ41 must be installed in a valid slot in the subrack. Otherwise, the SLQ41 cannot work
normally.
9.25.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ41 indicates the type of optical interface.
9.25.9 Parameter Settings
You can set the parameters for the SLQ41 by using the T2000.
9.25.10 Technical Specifications
The technical specifications of the SLQ41 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.25.1 Version Description
The SLQ41 is available in one functional version, namely, N3. The SLQ41 supports the auto-
sensing of optical interfaces.
9.25.2 Application
The SLQ41 is a line board. The SLQ41 can be used on the OptiX OSN equipment series to
transmit and receive STM-1/STM-4 optical signals. The SLQ41 converts the received optical
signals into electrical signals and sends the electrical signals to the cross-connect side. In
addition, the SLQ41 converts the electrical signals sent from the cross-connect side into optical
signals and transmits the optical signals.
Figure 9-81 shows the application of the SLQ41. The SLQ41 boards can form a ring network
or a chain network in the system.
Figure 9-81 Networking and application of the SLQ41
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Cross-connect and timing board

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9.25.3 Functions and Features
The SLQ41 transmits and receives STM-1 or STM-4 optical signals, performs O/E conversion
for the STM-1 or STM-4 optical signals, extracts and inserts overhead bytes, and generates alarm
signals on the line.
Table 9-112 provides the functions and features of the SLQ41.
Table 9-112 Functions and features of the SLQ41
Function and
Feature
SLQ41
Basic functions Transmits and receives 4xSTM-1 or 4xSTM-4 optical signals.
Specifications of the
optical interface
The STM-1 optical module or STM-4 optical module can be used.
l When the STM-1 optical module is used, the SLQ41 supports
different types of standard optical interfaces, namely, the I-1,
S-1.1, L-1.1, L-1.2, and Ve-1.2. The characteristics of the optical
interfaces of the I-1, S-1.1, L-1.1, and L-1.2 types comply with
ITU-T G.957. The characteristics of the optical interface of the
Ve-1.2 type comply with the standards defined by Huawei.
l When the STM-4 optical module is used, the SLQ41 supports
different types of standard optical interfaces, namely, the I-4,
S-4.1, L-4.1, L-4.2, and Ve-4.2. The characteristics of the optical
interfaces of the I-4, S-4.1, L-4.1, and L-4.2 types comply with
ITU-T G.957. The characteristics of the optical interface of the
Ve-4.2 type comply with the standards defined by Huawei.
Specifications of the
optical module
l Supports the detection and query of the information about the
optical module.
l Supports the usage and detection of the SFP optical module, which
facilitates the maintenance and upgrading of the optical module.
l Provides the ALS function. The optical interface supports the
setting of the on/off state of a laser.
Service processing l When the STM-1 optical module is used, the SLQ41 supports the
VC-12 services, VC-3 services, and VC-4 services.
l When the STM-4 optical module is used, the SLQ41 supports the
VC-12 services, VC-3 services, VC-4 services, and VC-4-4c
concatenation services.
Overhead processing l Processes the section overheads of the STM-1 signals or STM-4
signals.
l Supports the transparent transmission and termination of the path
overheads.
l Supports the setting and query of the J0, J1, J2, and C2 bytes.
l Supports one to four channels of ECC communication.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
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Function and
Feature
SLQ41
Protection schemes l Supports the two-fiber ring MSP.
l Supports the four-fiber ring MSP.
l Supports the linear MSP.
l Supports the SNCP.
l Supports the SNCMP.
l Supports the SNCTP.
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports inloops and outloops on VC-4 paths.
l Supports warm resets and cold resets. The warm reset does not
affect services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting
services.
l Supports the press-to-collect function in fault data collection.

9.25.4 Working Principle and Signal Flow
The SLQ41 consists of the O/E converting module, CDR module, SDH overhead processing
module, logic and control module, and power module.
This topic describes the working principle and signal flow of the SLQ41 by describing how to
process STM-1/STM-4 signals.
Figure 9-82 shows the functional block diagram of the SLQ41.
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Figure 9-82 Functional block diagram of the SLQ41
Logic and
control module
Cross-connect
unit A
+3.3 V backup power
+3.3 V
SDH overhead
processing module
DCC
SCC unit
LOS
Laser shutdown
Communication
High-speed
bus
+3.3 V
-48 V/-60 V
Power
module
Fuse
Fuse
Cross-connect
unit
Cross-connect
unit B
High-speed
bus
155 MHz
PLL
Cross-connect
unit
Reference clock
K1 and K2
insertion/extraction
MSA HPT MST RST
IIC
CDR
.

.

.

.
.

.

.

.
CDR
-48 V/-60 V
STM-1/
STIM-4
O/E
E/O
SPI
O/E
SPI
Frame header
Cross-connect
unit
K1 and K2
STM-1/
STIM-4
E/O
Power
module
SCC unit
O/E converting
module
Backplane
PLL: phase-locked loop SPI: SDH physical interface SDH: synchronous digital hierarchy
RST: regenerator section
termination
MST: multiplex section termination MSA: multiplex section adaptation
HPT: higher order path termination CDR: clock data restoration -

O/E Converting Module
l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l Detects the R_LOS alarm and provides the function of shutting down the laser.
CDR Module
This module restores the clock signal.
SDH Overhead Processing Module
This module includes the RST, MST, MSA, and HPT sub-modules. This module provides the
inloop and outloop functions.
l RST sub-module
In the receive direction, the RST sub-module terminates the RSOH. That is, the RST
sub-module detects the frame alignment bytes (A1 and A2), descrambles all the bytes
except the first line of the RSOH, restores and checks the J0 byte, and checks the B1
byte.
In the transmit direction, the RST sub-module generates the RSOH. That is, the RST
sub-module writes bytes such as A1, A2, and J0, calculates and writes the B1 byte, and
scrambles all the bytes except the first line of the RSOH.
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l MST sub-module
In the receive direction, the MST sub-module terminates the MSOH. That is, the MST
sub-module generates the MS_AIS alarm and detects the MS_RDI alarm after detecting
the K2 byte, and detects the MS_REI alarm and generates the B2_EXC alarm after
checking the B2 byte.
In the transmit direction, the MST sub-module generates the MSOH. That is, the MST
sub-module writes bytes such as E2, D4-D12, K1, K2, S1, and M1, and calculates and
writes the B2 byte.
l MSA sub-module
In the receive direction, the MSA sub-module de-interleaves the AUG, divides an AUG
into N AU-4s, detects the AU_LOP alarm and the AU_AIS alarm, and performs pointer
justifications.
In the transmit direction, the MSA sub-module assembles the AUG and generates the
AU-4. N AU-4s are multiplexed into an AUG through byte interleaving.
l HPT sub-module
In the receive direction, the HPT sub-module terminates the POH. That is, the HPT sub-
module detects the HP_REI alarm after checking the B3 byte, generates the HP_TIM
alarm and the HP_SLM alarm and detects the HP_RDI alarm after detecting the J1 and
C2 bytes, and generates the HP_UNEQ alarm after detecting the C2 byte.
In the transmit direction, the HPT sub-module generates the POH. That is, the HPT sub-
module writes bytes such as J1 and C2, and calculates and writes the B3 byte.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Controls the laser.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not in position.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
9.25.5 Front Panel
The front panel of the SLQ41 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 9-83 shows the appearance of the front panel of the SLQ41.
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Figure 9-83 Front panel of the SLQ41
SLQ41
SLQ41
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SLQ41 has four optical interfaces. Table 9-113 describes the types and
usage of the optical interfaces of the SLQ41.
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Table 9-113 Optical interfaces of the SLQ41
Interface Type of Interface Usage
IN1IN4 LC Receives optical signals.
OUT1OUT4 LC Transmits optical signals.

9.25.6 Jumpers and DIP Switches
The SLQ41 does not have any jumpers or DIP switches that are used for board settings.
9.25.7 Valid Slots
The SLQ41 must be installed in a valid slot in the subrack. Otherwise, the SLQ41 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
l When the cross-connect capacity is 200 Gbit/s, the slots valid for the SLQ41 are as follows:
The SLQ41 can be installed in slots 14, 15, and 16. In this case, one or two optical
interfaces can be configured.
The SLQ41 can be installed in slots 58 and 1114. In this case, one to four optical
interfaces can be configured.
9.25.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SLQ41 indicates the type of optical interface.
Table 9-114 provides the relationship between the feature code of the SLQ41 and the type of
optical interface.
Table 9-114 Relationship between the feature code of the SLQ41 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN3SLQ414 14 I-4
SSN3SLQ410 10 S-4.1
SSN3SLQ411 11 L-4.1
SSN3SLQ412 12 L-4.2
SSN3SLQ413 13 Ve-4.2
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Board Feature Code Type of Optical Interface
SSN3SLQ114 14 I-1
SSN3SLQ110 10 S-1.1
SSN3SLQ111 11 L-1.1
SSN3SLQ112 12 L-1.2
SSN3SLQ113 13 Ve-1.2

9.25.9 Parameter Settings
You can set the parameters for the SLQ41 by using the T2000.
You can set the following parameters for the SLQ41 by using the T2000:
l J0
l J1
l J2
l C2
For the description of each parameter, see 25 Parameter Settings.
9.25.10 Technical Specifications
The technical specifications of the SLQ41 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
The SLQ41 supports the STM-1 and STM-4 optical modules.
Table 9-115 lists the parameters specified for the optical interfaces of the SLQ41 when the
STM-1 optical module is used.
Table 9-115 Parameters specified for the optical interfaces of the SLQ41 when the STM-1 optical module is used
Parameter Value
Nominal bit rate 155520 kbit/s
Line code
pattern
NRZ
Application
code
I-1 S-1.1 L-1.1 L-1.2 Ve-1.2
Transmission
distance (km)
0 to 2 2 to 15 20 to 40 60 to 80 80 to 100
Type of fiber Single-mode LC Single-mode LC Single-mode LC Single-mode LC Single-mode LC
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Parameter Value
Operating
wavelength
range (nm)
1260 to 1360 1261 to 1360 1263 to 1360 1480 to 1580 1480 to 1580
Launched
optical power
range (dBm)
-15 to -8 -15 to -8 -5 to 0 -5 to 0 -3 to 0
Receiver
sensitivity
(dBm)
-23 -28 -34 -34 -34
Minimum
overload (dBm)
-8 -8 -10 -10 -10
Minimum
extinction ratio
(dB)
8.2 8.2 10 10 10

Table 9-116 lists the parameters specified for the optical interfaces of the SLQ41 when the
STM-4 optical module is used.
Table 9-116 Parameters specified for the optical interfaces of the SLQ41 when the STM-4
optical module is used
Parameter Value
Nominal bit rate 622080 kbit/s
Line code pattern NRZ
Application code I-4 S-4.1 L-4.1 L-4.2 Ve-4.2
Transmission
distance (km)
0 to 2 2 to 15 20 to 40 50 to 80 80 to 100
Operating
wavelength range
(nm)
1261 to
1360
1274 to
1356
1280 to
1335
1480 to
1580
1480 to
1580
Type of fiber Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-
mode LC
Single-
mode LC
Mean launched
optical power
(dBm)
-15 to -8 -15 to -8 -3 to -2 -3 to -2 -3 to -2
Receiver
sensitivity (dBm)
-23 -28 -28 -28 -34
Minimum
overload (dBm)
-8 -8 -8 -8 -13
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Parameter Value
Minimum
extinction ratio
(dB)
8.2 8.2 10 10 10.5

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the SLQ41 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.6
Power Consumption
The maximum power consumption of the SLQ41 at room temperature (25C) is 12 W.
9.26 EU04
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EU04 (4xSTM-1 electrical interface board).
9.26.1 Version Description
The EU04 is available in one functional version, namely, N1.
9.26.2 Application
The EU04 is an STM-1 electrical interface board. The EU04 can be used on the OptiX OSN
equipment series to transmit and receive signals for the STM-1 electrical processing board.
9.26.3 Functions and Features
The EU04 receives and transmits 4xSTM-1 electrical signals. The EU04 must work with the
SEP.
9.26.4 Working Principle and Signal Flow
The EU04 consists of the interface module, switch matrix module, and power module.
9.26.5 Front Panel
The front panel of the EU04 has interfaces and a bar code.
9.26.6 Valid Slots
The EU04 can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the subrack and works
as the interface board of the SEP.
9.26.7 Technical Specifications
The technical specifications of the EU04 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
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9.26.1 Version Description
The EU04 is available in one functional version, namely, N1.
9.26.2 Application
The EU04 is an STM-1 electrical interface board. The EU04 can be used on the OptiX OSN
equipment series to transmit and receive signals for the STM-1 electrical processing board.
9.26.3 Functions and Features
The EU04 receives and transmits 4xSTM-1 electrical signals. The EU04 must work with the
SEP.
9.26.4 Working Principle and Signal Flow
The EU04 consists of the interface module, switch matrix module, and power module.
Figure 9-84 shows the functional block diagram of the EU04 by describing how to process
1xSTM-1 signals.
Figure 9-84 Functional block diagram of the EU04
Switch
matrix
module
STM-1 electrical
signal
SEP
Backplane
Interface
module
+3.3 V power
+3.3 V
Power
module
Fuse
SEP
TSB4/TSB8
TSB4/TSB8
Cross-connect board
STM-1 electrical
signal

Interface Module
The interface module receives and transmits the STM-1 electrical signals.
Switch Matrix Module
In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the SEP. When the TPS is performed, the switch matrix module
transmits the signal to the TSB4 or TSB8 for bridging.
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In the transmit direction, the switch matrix module performs the reverse process.
Power Module
The power module provides all the modules of the EU04 with the required DC voltages.
9.26.5 Front Panel
The front panel of the EU04 has interfaces and a bar code.
Diagram of the Front Panel
Figure 9-85 shows the appearance of the front panel of the EU04.
Figure 9-85 Front panel of the EU04
EUO4
EUO4
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Interfaces
The front panel of the EU04 has four pairs of electrical interfaces.
Table 9-117 describes the types and usage of the interfaces of the EU04.
Table 9-117 Interfaces of the EU04
Interface Type of Interface Usage
IN1IN4 SMB Receives the 1st to the 4th channels of STM-1
electrical signals.
OUT1OUT4 SMB Transmits the 1st to the 4th channels of STM-1
electrical signals.

9.26.6 Valid Slots
The EU04 can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the subrack and works
as the interface board of the SEP.
Table 9-118 lists the slots valid for the SEP and the corresponding slots for the EU04.
Table 9-118 Slots valid for the SEP and the corresponding slots for the EU04
Slot Valid for the SEP Corresponding Slot for the EU04
Slot 2 Slot 19
Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33
Slot 16 Slot 35

9.26.7 Technical Specifications
The technical specifications of the EU04 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
Table 9-119 lists the parameters specified for the electrical interfaces of the EU04.
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Table 9-119 Parameters specified for the electrical interfaces of the EU04
Parameter Value
Nominal bit rate 155520 kbit/s
Line code pattern CMI
Signal bit rate at the output interface Complies with ITU-T G.703.
Allowed frequency deviation at the input
interface
Allowed attenuation at the input interface

Mechanical Specifications
The mechanical specifications of the EU04 are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
The maximum power consumption of the EU04 at room temperature (25C) is 6 W.
9.27 EU08
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EU08 (8xSTM-1 electrical interface board).
9.27.1 Version Description
The EU08 is available in one functional version, namely, N1.
9.27.2 Application
The EU08 is an STM-1 electrical interface board. The EU08 can be used on the OptiX OSN
equipment series to transmit and receive signals for the STM-1 electrical processing board.
9.27.3 Functions and Features
The EU08 receives and transmits 8xSTM-1 electrical signals. The EU08 must work with the
SLH1 or SEP1.
9.27.4 Working Principle and Signal Flow
The EU08 consists of the interface module, switch matrix module, and power module.
9.27.5 Front Panel
The front panel of the EU08 has interfaces and a bar code.
9.27.6 Valid Slots
The slots valid for the EU08 vary with the cross-connect capacity of the subrack.
9.27.7 Technical Specifications
The technical specifications of the EU08 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
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9.27.1 Version Description
The EU08 is available in one functional version, namely, N1.
9.27.2 Application
The EU08 is an STM-1 electrical interface board. The EU08 can be used on the OptiX OSN
equipment series to transmit and receive signals for the STM-1 electrical processing board.
9.27.3 Functions and Features
The EU08 receives and transmits 8xSTM-1 electrical signals. The EU08 must work with the
SLH1 or SEP1.
9.27.4 Working Principle and Signal Flow
The EU08 consists of the interface module, switch matrix module, and power module.
Figure 9-86 shows the functional block diagram of the EU08.
Figure 9-86 Functional block diagram of the EU08
+3.3 V power
+3.3 V
TSB8
Interface
module
Cross-connect board
Backplane
Power
module
Switch
matrix
module
STM-1 electrical
signal
SEP/SLH1
TSB8
Fuse
STM-1 electrical
signal
SEP/SLH1

Interface Module
The interface module receives and transmits the STM-1 electrical signals.
Switch Matrix Module
In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the SLH1 or SEP1. When the TPS is performed, the switch matrix
module transmits the signal to the TSB8 for bridging.
In the transmit direction, the switch matrix module performs the reverse process.
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Power Module
The power module provides all the modules of the EU08 with the required DC voltages.
9.27.5 Front Panel
The front panel of the EU08 has interfaces and a bar code.
Diagram of the Front Panel
Figure 9-87 shows the appearance of the front panel of the EU08.
Figure 9-87 Front panel of the EU08
EUO8
EUO8
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Interfaces
The front panel of the EU08 has eight pairs of electrical interfaces.
Table 9-120 describes the types and usage of the interfaces of the EU08.
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Table 9-120 Interfaces of the EU08
Interface Type of
Interface
Usage
IN1IN8 SMB Receives the 1st to the 8th channels of STM-1
electrical signals.
OUT1OUT8 SMB Transmits the 1st to the 8th channels of STM-1
electrical signals.

9.27.6 Valid Slots
The slots valid for the EU08 vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the EU08 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the EU08 can be installed in slots 1926
and 2936.
Table 9-121 lists the slots valid for the SLH1 and the corresponding slots for the EU08. The
EU08 installed in the slot with a smaller number accesses the 1st to the 8th channels of STM-1
electrical signals. The EU08 installed in the slot with a larger number accesses the 9th to the
16th channels of STM-1 electrical signals.
Table 9-121 Slots valid for the SLH1 and the corresponding slots for the EU08
Slot Valid for the SLH1 Corresponding Slot for the EU08
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

Table 9-122 lists the slots valid for the SEP and the corresponding slots for the EU08.
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Table 9-122 Slots valid for the SEP and the corresponding slots for the EU08
Slot Valid for the SEP Corresponding Slot for the EU08
Slot 2 Slot 19
Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33
Slot 16 Slot 35

9.27.7 Technical Specifications
The technical specifications of the EU08 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
Table 9-123 lists the parameters specified for the electrical interfaces of the EU08.
Table 9-123 Parameters specified for the electrical interfaces of the EU08
Parameter Value
Nominal bit rate 155520 kbit/s
Line code pattern CMI
Signal bit rate at the
output interface
Complies with ITU-T G.703.
Allowed frequency
deviation at the input
interface
Allowed attenuation at
the input interface
Input jitter tolerance

Mechanical Specifications
The mechanical specifications of the EU08 are as follows:
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l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
The maximum power consumption of the EU08 at room temperature (25C) is 11 W.
9.28 OU08
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the OU08 (8xSTM-1 optical interface board).
9.28.1 Version Description
The OU08 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to the connector type for the optical interfaces and whether the
optical module is swappable.
9.28.2 Application
The OU08 is an STM-1 optical interface board. The OU08 can be used on the OptiX OSN
equipment series to transmit and receive signals for the STM-1 optical processing board.
9.28.3 Functions and Features
The OU08 receives and transmits 8xSTM-1 optical signals. The OU08 must work with the SLH1
or SEP1.
9.28.4 Working Principle and Signal Flow
The OU08 consists of the interface module and power module.
9.28.5 Front Panel
The front panel of the OU08 has interfaces and a bar code.
9.28.6 Valid Slots
The slots valid for the OU08 vary with the cross-connect capacity of the subrack.
9.28.7 Technical Specifications
The technical specifications of the OU08 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
9.28.1 Version Description
The OU08 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to the connector type for the optical interfaces and whether the
optical module is swappable.
Table 9-124 describes the versions of the OU08.
Table 9-124 Versions of the OU08
Item Description
Functional
versions
The OU08 is available in two functional versions, namely, N1 and
N2.
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Item Description
Common points The working principle of the N1OU08 is the same as the working
principle of the N2OU08.
Differences The optical interface of the N1OU08 uses the LC connector, whereas
the optical interface of the N2OU08 uses the SC connector. The
N1OU08 uses the swappable optical module, whereas the N2OU08
does not use the swappable optical module.
Substitution None.

9.28.2 Application
The OU08 is an STM-1 optical interface board. The OU08 can be used on the OptiX OSN
equipment series to transmit and receive signals for the STM-1 optical processing board.
9.28.3 Functions and Features
The OU08 receives and transmits 8xSTM-1 optical signals. The OU08 must work with the SLH1
or SEP1.
9.28.4 Working Principle and Signal Flow
The OU08 consists of the interface module and power module.
Figure 9-88 shows the functional block diagram of the OU08.
Figure 9-88 Functional block diagram of the OU08
STM-1 optical
signal
SEP/SLH1
+3.3 V power
+3.3 V Fuse
Backplane
Interface
module
Power
module
STM-1 optical
signal
SEP/SLH1

Interface Module
In the receive direction, the interface module performs O/E conversion for the STM-1 signals
and transmits the signals to the SLH1 or SEP1.
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In the transmit direction, the interface module performs E/O conversion for the STM-1 signals
and transmits the signals to the optical interface.
Power Module
The power module provides all the modules of the OU08 with the required DC voltages.
9.28.5 Front Panel
The front panel of the OU08 has interfaces and a bar code.
Diagram of the Front Panel
Figure 9-89 shows the appearance of the front panel of the N1OU08.Figure 9-90 shows the
appearance of the front panel of the N2OU08.
Figure 9-89 Front panel of the N1OU08
OU08
OU08
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CLASS 1
LASER
PRODUCT

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Figure 9-90 Front panel of the N2OU08
OU08
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Interfaces
The front panel of the N1OU08/N2OU08 has eight optical interfaces.
Table 9-125 describes the types and usage of the interfaces of the N1OU08. Table 9-126
describes the types and usage of the interfaces of the N2OU08.
Table 9-125 Interfaces of the N1OU08
Interface Type of
Interface
Usage
IN1IN8 LC Receives the 1st to the 8th channels of STM-1
optical signals.
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Interface Type of
Interface
Usage
OUT1OUT8 LC Transmits the 1st to the 8th channels of STM-1
optical signals.

Table 9-126 Interfaces of the N2OU08
Interface Type of
Interface
Usage
IN1IN8 SC Receives the 1st to the 8th channels of STM-1
optical signals.
OUT1OUT8 SC Transmits the 1st to the 8th channels of STM-1
optical signals.

9.28.6 Valid Slots
The slots valid for the OU08 vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
l When the cross-connect capacity is 200 Gbit/s, the OU08 can be installed in slots 1926
and 2936.
Table 9-127 lists the slots valid for the SLH1 and the corresponding slots for the OU08. The
OU08 installed in the slot with a smaller number accesses the 1st to the 8th channels of STM-1
optical signals. The OU08 installed in the slot with a larger number accesses the 9th to the 16th
channels of STM-1 optical signals.
Table 9-127 Slots valid for the SLH1 and the corresponding slots for the OU08
Slot Valid for the SLH1 Corresponding Slot for the OU08
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
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Slot Valid for the SLH1 Corresponding Slot for the OU08
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

Table 9-128 lists the slots valid for the SEP1 and the corresponding slots for the OU08.
Table 9-128 Slots valid for the SEP1 and the corresponding slots for the OU08
Slot Valid for the SEP1 Corresponding Slot for the OU08
Slot 2 Slot 19
Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33
Slot 16 Slot 35

9.28.7 Technical Specifications
The technical specifications of the OU08 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 9-129 lists the parameters specified for the optical interfaces of the OU08.
Table 9-129 Parameters specified for the optical interfaces of the OU08
Parameter Value
Nominal bit rate 155520 kbit/s
Line code pattern NRZ
Application code S-1.1
Operating wavelength
range (nm)
N1OU08: 1260-1360
N2OU08: 1261-1360
Type of fiber Single-mode LC
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Parameter Value
Mean launched optical
power (dBm)
-15 to -8
Receiver sensitivity
(dBm)
-28

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the OU08 are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
The maximum power consumption of the OU08 at room temperature (25C) is 6 W.
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10 PDH Boards
About This Chapter
The PDH boards include the PDH service interface boards and PDH service processing boards,
to access and process E1/T1 signals, E3/T3 signals, E4/STM-1 electrical signals, and DDN
signals.
10.1 PQ1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PQ1 (63xE1 service processing board). This topic also describes
how to configure and commission the PQ1.
10.2 PQM
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PQM (63xE1/T1 service processing board). This topic also
describes how to configure and commission the PQM.
10.3 PL3
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PL3 (3xE3/T3 service processing board). This topic also describes
how to configure and commission the PL3.
10.4 PL3A
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PL3A (3xE3/T3 service processing board with the interfaces on
the front panel). This topic also describes how to configure and commission the PL3A.
10.5 PD3
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PD3 (6xE3/T3 service processing board).
10.6 PQ3
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PQ3 (12xE3/T3 service processing board).
10.7 DX1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the DX1 (DDN service accessing and converging board). This topic
also describes how to configure and commission the DX1.
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10.8 DXA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the DXA (DDN service converging and processing board).
10.9 SPQ4
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SPQ4 (4xE4/STM-1 electrical processing board). This topic also
describes how to configure and commission the SPQ4.
10.10 D12B
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D12B (32xE1/T1 access board).
10.11 D12S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D12S (32xE1/T1 switching access board).
10.12 D75S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D75S (32xE1 switching access board).
10.13 D34S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D34S (6xE3/T3 switching access board).
10.14 C34S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the C34S (3xE3/T3 switching access board).
10.15 MU04
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the MU04 (4xE4/STM-1 electrical interface board).
10.16 DM12
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the DM12 (DDN service interface board).
10.17 TSB4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TSB4 (4-channel electrical interface protection switching board).
10.18 TSB8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TSB8 (8-channel electrical interface protection switching board).
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10.1 PQ1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PQ1 (63xE1 service processing board). This topic also describes
how to configure and commission the PQ1.
10.1.1 Version Description
The PQ1 is available in the following functional versions: N1 and N2. The difference between
the functional versions is with regard to their functions. The N1PQ1 is discontinued.
10.1.2 Application
The PQ1 is a PDH processing board. The PQ1 can be used on the OptiX OSN equipment series
to add and drop PDH signals. To access and process 63xE1 signals, the PQ1 must be used with
the interface board.
10.1.3 Functions and Features
The PQ1 processes E1 signals, processes overhead bytes, reports alarms and performance events,
provides maintenance features, and supports the TPS protection.
10.1.4 Working Principle and Signal Flow
The PQ1 consists of the interface module, mapping/demapping module, interface converting
module, logic and control module, and power module.
10.1.5 Front Panel
The front panel of the PQ1 has indicators.
10.1.6 Jumpers and DIP Switches
The PQ1 does not have any jumpers or DIP switches that are used for board settings.
10.1.7 Valid Slots
The PQ1 must be installed in a valid slot in the subrack. Otherwise, the PQ1 cannot work
normally.
10.1.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the PQ1 indicates the type of interface impedance.
10.1.9 Board Protection
The PQ1 supports the 1:N (N2) TPS protection.
10.1.10 Parameter Settings
You can set parameters for the PQ1 by using the T2000.
10.1.11 Technical Specifications
The technical specifications of the PQ1 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.
10.1.1 Version Description
The PQ1 is available in the following functional versions: N1 and N2. The difference between
the functional versions is with regard to their functions. The N1PQ1 is discontinued.
Table 10-1 describes the versions of the PQ1.
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Table 10-1 Versions of the PQ1
Item Description
Functional versions The PQ1 is available in the following functional versions: N1 and N2.
Differences The N2PQ1 supports the E13 function and the board version
replacement function.
The N2PQ1 does not perform the tributary re-timing function.
Substitution When the tributary re-timing function is not required, the N1PQ1A
can be replaced with the N2PQ1A.
When the tributary re-timing function is not required, the N1PQ1B
can be replaced with the N2PQ1B.
Note: The PQ1 boards are classified into the PQ1A boards (75 ohms) and PQ1B boards (120
ohms) according to the interface impedance. When the interface impedance is not considered,
the PQ1A and PQ1B are called PQ1 hereafter.

10.1.2 Application
The PQ1 is a PDH processing board. The PQ1 can be used on the OptiX OSN equipment series
to add and drop PDH signals. To access and process 63xE1 signals, the PQ1 must be used with
the interface board.
Figure 10-1 shows the application of the PQ1. The PQ1 adds tributary signals to line signals
and drops line signals to tributary signals.
Figure 10-1 Networking and application of the PQ1
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Tributary board
Cross-connect and timing board

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10.1.3 Functions and Features
The PQ1 processes E1 signals, processes overhead bytes, reports alarms and performance events,
provides maintenance features, and supports the TPS protection.
Table 10-2 provides the functions and features of the PQ1.
Table 10-2 Functions and features of the PQ1
Function
and
Feature
PQ1
N1PQ1 N2PQ1
Basic
functions
Processes 63xE1
signals.
Processes 63xE1 signals.
Service
processing
Processes 63xE1
electrical signals
when working with
the interface board.
l Processes 63xE1 electrical signals when working
with the interface board.
l Supports the E13 function, which is used to converge
E1 services into E3 services.
Overhead
processing
Supports the processing of the path overheads at the VC-12 level, such as the
J2 byte.
Alarms and
performanc
e events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Maintenan
ce features
l Supports inloops and outloops at electrical interfaces.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the PRBS function.
l The N1PQ1 does not support the CRC function, but the N2PQ1 supports the
CRC function.
Protection
schemes
Supports the TPS protection when working with the interface board.
l The N1PQ1 supports hybrid protection. When the working board is the
N1PQ1, the protection board can be the N1PQ1, N2PQ1, or N1PQM.
l The N2PQ1 does not support hybrid protection. When the working board is
the N2PQ1, the protection board can only be the N2PQ1.

10.1.4 Working Principle and Signal Flow
The PQ1 consists of the interface module, mapping/demapping module, interface converting
module, logic and control module, and power module.
Figure 10-2 shows the functional block diagram of the PQ1.
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Figure 10-2 Functional block diagram of the PQ1
E1
E1
Mapping/
Demapping
module
Logic and
control module
Cross-connect
unit A
155 Mbit/s
155 Mbit/s
LOS
63x2 Mbit/s
SCC unit
Communication
Frame header
Outloop/Inloop
control
Interface
converting
module
2 MHz
OSC
+3.3 V backup power
+3.3 V
Power
module
Fuse
Fuse
-48 V/-60 V
Reference
clock
Cross-connect
unit
LIU
LIU
PPI
63x2 Mbit/s Cross-connect
unit B
Cross-connect
unit
High-speed
bus
High-speed
bus
-48V/-60V
Power
module
Interface
module
155 MHz
PLL
Backplane
LIU: logic interface unit PPI: PDH physical interface
OSC: oscillator -

Figure 10-3 shows the functional block diagram of the mapping/demapping module.
Figure 10-3 Functional block diagram of the mapping/demapping module
E1
STM-1
PDH AIS
detector
Mapping/demapping module
LPA LPT HPA HPT
LPOH(V5/J2/N2/
K4) insertion
TU-AIS/TU-
LOP detector
E1 STM-1
LPA LPT HPA HPT
LPOH(V5/J2/N2/
K4) extraction

Interface Module
The interface module consists of LIUs and provides the inloop and outloop functions. The
interface module performs the following functions:
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l Encodes and decodes signals.
l Restores the data signal and the clock signal.
l Processes the PDH LOS signals.
Mapping/Demapping Module
l LPA sub-module
The 2 Mbit/s (1.5 Mbit/s) plesiochronous stream is inserted in a VC-12 container to be
adapted so that the stream can be transported to the synchronous network for check of the
PDH AIS.
l LPT sub-module
The virtual container (VC-12) is formatted. The VC-12 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C-12 container and POH. The POH contains nine octets equally distributed within the frame
bytes for VC-12, namely, V5, J2, N2, and K4.
l HPA sub-module
The HPA sub-module generates and processes the channel-level TU-PTR. In the receive
direction, the signals are split into VC-12s, which are located and isolated in TU-12s. The
TU-PTR is processed. TU-AIS and TU-LOP alarms are monitored. In the transmit
direction, VC-12s are located precisely and added with the TU-PTR. Sixty-three TU-12s
are multiplexed into a VC-4 by bytes interleaving. The sequence is as follows: TUG2-
>TUG3->VC-4
l HPT sub-module
The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C4 container and POH.
l MST sub-module and RST sub-module
These sub-modules are required to create a proprietary STM1 signal so that the E1
mapping/demapping module can interface with the multiplex unit.
Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Control the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
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10.1.5 Front Panel
The front panel of the PQ1 has indicators.
Diagram of the Front Panel
Figure 10-4 shows the appearance of the front panel of the PQ1.
Figure 10-4 Front panel of the PQ1
PQ1
PQ1
ACT
PROG
STAT
SRV

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
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l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the PQ1 does not have an interface.
The D75S, D12S, and D12B provide 75-ohm or 120-ohm E1 interfaces for the PQ1. For details,
see the topics that describe the D75S, D12S, and D12B.
10.1.6 Jumpers and DIP Switches
The PQ1 does not have any jumpers or DIP switches that are used for board settings.
10.1.7 Valid Slots
The PQ1 must be installed in a valid slot in the subrack. Otherwise, the PQ1 cannot work
normally.
The PQ1 can be installed in slots 15 and 1316 in the main subrack.
Table 10-3 lists the slots valid for the PQ1 and the corresponding slots for the D75S, D12S, and
D12B in the main subrack.
Table 10-3 Slots valid for the PQ1 and the corresponding slots for the D75S, D12S, and D12B
in the main subrack
Slot Valid for the PQ1 Corresponding Slots for the D75S, D12S,
and D12B
Slot 1 Without an interface board
Slot 2 Slot 19 (132 channels of services)
Slot 20 (3363 channels of services)
Slot 3 Slot 21 (132 channels of services)
Slot 22 (3363 channels of services)
Slot 4 Slot 23 (132 channels of services)
Slot 24 (3363 channels of services)
Slot 5 Slot 25 (132 channels of services)
Slot 26 (3363 channels of services)
Slot 13 Slot 29 (132 channels of services)
Slot 30 (3363 channels of services)
Slot 14 Slot 31 (132 channels of services)
Slot 32 (3363 channels of services)
Slot 15 Slot 33 (132 channels of services)
Slot 34 (3363 channels of services)
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Slot Valid for the PQ1 Corresponding Slots for the D75S, D12S,
and D12B
Slot 16 Slot 35 (132 channels of services)
Slot 36 (3363 channels of services)

NOTE
l Slot 1 can house a protection board for the TPS protection. The board in slot 1 protects the boards in
slots 25 and 1316.
l If the interface board for the boards in slots 25 and 1316 is the D12B, the boards in slots 25 and
1316 cannot be protected by the TPS protection scheme.
10.1.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the PQ1 indicates the type of interface impedance.
Table 10-4 provides the relationship between the feature code of the PQ1 and the type of
interface impedance.
Table 10-4 Relationship between the feature code of the PQ1 and the type of interface impedance
Board Feature Code Type of Interface Impedance
SSN1PQ1A01 and SSN2PQ1A01 A01 75-ohm
SSN1PQ1B01 and SSN2PQ1B01 B01 120-ohm

10.1.9 Board Protection
The PQ1 supports the 1:N (N2) TPS protection.
Protection Principle
The PQ1 boards work with the D75S or D12S boards to realize 1:N (N8) TPS protection.
Figure 10-5 shows the TPS protection provided by the PQ1. When the cross-connect and timing
board detects that a working PQ1 is faulty, the cross-connect and timing board issues a service
switching command to control the interface board to switch the services from the faulty PQ1 to
the protection PQ1, which realizes the protection of the services.
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Figure 10-5 TPS protection provided by the PQ1
Switching
control bus
Protection bus
2 1 2 1 2 1 2 1
Service signal Service signal
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Hardware Configuration
Table 10-5 shows the slot configuration for the 1:8 TPS protection of the PQ1.
Table 10-5 Slot configuration for the 1:8 TPS protection of the PQ1
Working Board Protection Board Slot Configuration
PQ1A (75-ohm) PQ1A (75-ohm) Slot 1 can house a protection board.
The board in slot 1 protects the boards
in slots 25 and 1316. Figure 10-6
shows the slot configuration for the 1:8
TPS protection of the PQ1.
PQ1B (120-ohm) PQ1B (120-ohm) or PQM

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Figure 10-6 Slot configuration for the 1:8 TPS protection of the PQ1
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10.1.10 Parameter Settings
You can set parameters for the PQ1 by using the T2000.
You can set the following parameters for the PQ1 by using the T2000:
l J2 byte
l V5 byte
l Tributary loopback
l Service loading indication
For the description of each parameter, see 25 Parameter Settings.
10.1.11 Technical Specifications
The technical specifications of the PQ1 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.
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Parameters Specified for Electrical Interfaces
The D75S, D12S, or D12B provides electrical interfaces for the PQ1. For the parameters
specified for the electrical interfaces, see Technical Specifications Of The D75S, Technical
Specifications Of The D12S and Technical Specifications Of The D12B.
Mechanical Specifications
The mechanical specifications of the PQ1 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the N1PQ1 at room temperature (25C) is 19 W.
The maximum power consumption of the N2PQ1 at room temperature (25C) is 13 W.
10.2 PQM
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PQM (63xE1/T1 service processing board). This topic also
describes how to configure and commission the PQM.
10.2.1 Version Description
The PQM is available in one functional version, namely, N1.
10.2.2 Application
The PQM is a PDH processing board. The PQM can be used on the OptiX OSN equipment series
to add and drop PDH signals. To access and process 63xE1/T1 signals, the PQM must be used
with the interface board.
10.2.3 Functions and Features
The PQM processes E1/T1 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
10.2.4 Working Principle and Signal Flow
The PQM consists of the interface module, mapping/demapping module, interface converting
module, logic and control module, and power module.
10.2.5 Front Panel
The front panel of the PQM has indicators.
10.2.6 Jumpers and DIP Switches
The PQM does not have any jumpers or DIP switches that are used for board settings.
10.2.7 Valid Slots
The PQM must be used with the D12S or D12B. In addition, the PQM must be installed in a
valid slot in the subrack. Otherwise, the PQM cannot work normally.
10.2.8 Feature Code
The PQM does not have a feature code.
10.2.9 Board Protection
The PQM supports the 1:N TPS protection.
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10.2.10 Parameter Settings
You can set the parameters for the PQM by using the T2000.
10.2.11 Technical Specifications
The technical specifications of the PQM include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
10.2.1 Version Description
The PQM is available in one functional version, namely, N1.
10.2.2 Application
The PQM is a PDH processing board. The PQM can be used on the OptiX OSN equipment series
to add and drop PDH signals. To access and process 63xE1/T1 signals, the PQM must be used
with the interface board.
Figure 10-7 shows the application of the PQM. The PQM adds tributary signals to line signals
and drops line signals to tributary signals.
Figure 10-7 Networking and application of the PQM
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Tributary board
Cross-connect and timing board

10.2.3 Functions and Features
The PQM processes E1/T1 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
Table 10-6 provides the functions and features of the PQM.
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Table 10-6 Functions and features of the PQM
Function
and Feature
PQM
Basic
functions
Processes 63xE1/T1 signals.
Service
processing
Accesses and processes 63xE1/T1 electrical signals when working with the
interface board. Each channel can be configured as E1 or T1.
Overhead
processing
Supports the processing of the path overheads at the VC-12 level, such as
the J2 byte.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Maintenance
features
l Supports inloops and outloops at electrical interfaces.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the PRBS function.
l Supports the CRC function.
Protection
schemes
Supports the TPS protection when working with the interface board.
l When the working board is the N1PQ1, the protection board can be the
N1PQ1, N2PQ1 or N1PQM. In this case, the hybrid protection is
provided.
l When the working board is the N1PQM, the protection board can only be
the N1PQM.

10.2.4 Working Principle and Signal Flow
The PQM consists of the interface module, mapping/demapping module, interface converting
module, logic and control module, and power module.
Figure 10-8 shows the functional block diagram of the PQM.
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Figure 10-8 Functional block diagram of the PQM
E1/T1
E1/T1
Mapping/
Demapping
module
Logic and
control module
Cross-connect
unit A
155 Mbit/s
155 Mbit/s
LOS
63x1.5 Mbit/s
63x2 Mbit/s
SCC unit
Communication
Frame header
Outloop/Inloop
control
Interface
converting
module
1.5 MHz/2 MHz
OSC
+3.3 V backup power
+3.3 V
Power
module
Fuse
Fuse
-48 V/-60 V
Reference
clock
Cross-connect
unit
LIU
LIU
PPI
63x1.5 Mbit/s
63x2 Mbit/s
Cross-connect
unit B
Cross-connect
unit
High-speed
bus
High-speed
bus
-48V/-60V
Power
module
Interface
module
155 MHz
PLL
Backplane
LIU: logic interface unit PPI: PDH physical interface
OSC: oscillator -

Figure 10-9 shows the functional block diagram of the mapping/demapping module.
Figure 10-9 Functional block diagram of the mapping/demapping module
E1/T1
STM-1
PDH AIS
detector
Mapping/demapping module
LPA LPT HPA HPT
LPOH(V5/J2/N2/
K4) insertion
TU-AIS/TU-
LOP detector
STM-1
LPA LPT HPA HPT
LPOH(V5/J2/N2/
K4) extraction
E1/T1

Interface Module
The interface module consists of LIUs and provides the inloop and outloop functions. The
interface module performs the following functions:
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l Encodes and decodes signals.
l Restores the data signal and the clock signal.
l Processes the PDH LOS signals.
Mapping/Demapping Module
l LPA sub-module
The 2 Mbit/s (1.5 Mbit/s) plesiochronous stream is inserted in a VC-12 container to be
adapted so that the stream can be transported to the synchronous network for check of the
PDH AIS.
l LPT sub-module
The virtual container (VC-12) is formatted. The VC-12 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C-12 container and POH. The POH contains nine octets equally distributed within the frame
bytes for VC-12, namely, V5, J2, N2, and K4.
l HPA sub-module
The HPA sub-module generates and processes the channel-level TU-PTR. In the receive
direction, the signals are split into VC-12s, which are located and isolated in TU-12s. The
TU-PTR is processed. TU-AIS and TU-LOP alarms are monitored. In the transmit
direction, VC-12s are located precisely and added with the TU-PTR. Sixty-three TU-12s
are multiplexed into a VC-4 by bytes interleaving. The sequence is as follows: TUG2-
>TUG3->VC-4
l HPT sub-module
The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C4 container and POH.
l MST sub-module and RST sub-module
These sub-modules are required to create a proprietary STM1 signal so that the E1
mapping/demapping module can interface with the multiplex unit.
Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Control the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
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10.2.5 Front Panel
The front panel of the PQM has indicators.
Diagram of the Front Panel
Figure 10-10 shows the appearance of the front panel of the PQM.
Figure 10-10 Front panel of the PQM
PQM
PQM
ACT
PROG
STAT
SRV

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
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l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the PQM does not have an interface. The D12S and D12B provide 120-ohm
E1 interfaces or 100-ohm T1 interfaces for the PQM. For details, see the topics that describe the
D12S and D12B.
10.2.6 Jumpers and DIP Switches
The PQM does not have any jumpers or DIP switches that are used for board settings.
10.2.7 Valid Slots
The PQM must be used with the D12S or D12B. In addition, the PQM must be installed in a
valid slot in the subrack. Otherwise, the PQM cannot work normally.
The PQM board can be installed in slots 15 and 1316 in the main subrack.
Table 10-7 lists the slots valid for the PQM and the corresponding slots for the D12S and D12B
in the main subrack.
Table 10-7 Slots valid for the PQM and the corresponding slots for the D12S and D12B in the
main subrack
Slot Valid for the PQM Corresponding Slots for the D12S and
D12B
Slot 1 Without an interface board
Slot 2 Slot 19 (132 channels of services)
Slot 20 (3363 channels of services)
Slot 3 Slot 21 (132 channels of services)
Slot 22 (3363 channels of services)
Slot 4 Slot 23 (132 channels of services)
Slot 24 (3363 channels of services)
Slot 5 Slot 25 (132 channels of services)
Slot 26 (3363 channels of services)
Slot 13 Slot 29 (132 channels of services)
Slot 30 (3363 channels of services)
Slot 14 Slot 31 (132 channels of services)
Slot 32 (3363 channels of services)
Slot 15 Slot 33 (132 channels of services)
Slot 34 (3363 channels of services)
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Slot Valid for the PQM Corresponding Slots for the D12S and
D12B
Slot 16 Slot 35 (132 channels of services)
Slot 36 (3363 channels of services)

NOTE
l Slot 1 can house a protection board for the TPS protection. The board in slot 1 protects the boards in
slots 25 and 1316.
l If the interface board for the boards in slots 25 and 1316 is the D12B, the boards in slots 25 and
1316 cannot be protected by the TPS protection scheme.
10.2.8 Feature Code
The PQM does not have a feature code.
10.2.9 Board Protection
The PQM supports the 1:N TPS protection.
Protection Principle
The PQM boards can work with the D12S boards to realize 1:N (N8) TPS protection.
Figure 10-11 shows the TPS protection provided by the PQM.
Figure 10-11 TPS protection provided by the PQM (E1 services are provided as an example)
Switching
control bus
Protection bus
2 1 2 1 2 1 2 1
Service signal Service signal
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When the cross-connect and timing board detects that a working PQM is faulty, the cross-connect
and timing board issues a service switching command. Then, the interface board switches the
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services from the faulty PQM to the protection PQM, which realizes the protection of the
services.
Hardware Configuration
Table 10-8 shows the slot configuration for the 1:8 TPS protection of the PQM.
Table 10-8 Slot configuration for the 1:8 TPS protection of the PQM
Working
Board
Protection Board Slot Configuration
PQM (E1) PQM (E1) Slot 1 can house a protection board. The board
in slot 1 protects the boards in slots 25 and
1316. Figure 10-12 shows the slot
configuration for the 1:8 TPS protection of the
PQM.
PQM (T1) PQM (T1)

Figure 10-12 Slot configuration for the 1:8 TPS protection of the PQM
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10-21
10.2.10 Parameter Settings
You can set the parameters for the PQM by using the T2000.
You can set the following parameters for the PQM by using the T2000:
l J2 byte
l V5 byte
l Tributary loopback
For the description of each parameter, see 25 Parameter Settings.
10.2.11 Technical Specifications
The technical specifications of the PQM include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
The D12S or D12B provides electrical interfaces for the PQM. For the parameters specified for
the electrical interfaces, see Technical Specifications Of The D12S and Technical Specifications
Of The D12B.
Mechanical Specifications
The mechanical specifications of the PQM are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the PQM at room temperature (25C) is 22 W.
10.3 PL3
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PL3 (3xE3/T3 service processing board). This topic also describes
how to configure and commission the PL3.
10.3.1 Version Description
The PL3 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to their functions. The N1PL3 is discontinued.
10.3.2 Application
The PL3 is a PDH processing board. The PL3 can be used on the OptiX OSN equipment series
to add and drop PDH signals. To access and process 3xE3/T3 signals, the PL3 must be used with
the interface board.
10.3.3 Functions and Features
The PL3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
10.3.4 Working Principle and Signal Flow
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The PL3 consists of the interface module, mapping/demapping module, interface converting
module, logic and control module, and power module.
10.3.5 Front Panel
The front panel of the PL3 has indicators.
10.3.6 Jumpers and DIP Switches
The PL3 does not have any jumpers or DIP switches that are used for board settings.
10.3.7 Valid Slots
The PL3 must be used with the C34S. In addition, the PL3 must be installed in a valid slot in
the subrack. Otherwise, the PL3 cannot work normally.
10.3.8 Feature Code
The IFSD1 does not have a feature code.
10.3.9 Board Protection
The PL3 supports the 1:N TPS protection.
10.3.10 Parameter Settings
You can set the parameters for the PL3 by using the T2000.
10.3.11 Technical Specifications
The technical specifications of the PL3 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.
10.3.1 Version Description
The PL3 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to their functions. The N1PL3 is discontinued.
Table 10-9 describes the versions of the PL3.
Table 10-9 Versions of the PL3
Item Description
Functional versions The PL3 is available in two functional versions, namely, N1 and N2.
Differences The N1PL3 does not support the E13/M13 function.
The N2PL3 supports the E13/M13 function.
The N2PL3 supports the board version replacement function and can
replace the N1PL3. After the N2PL3 replaces the N1PL3, the
configuration and service status of the N2PL3 are the same as the
configuration and service status of the N1PL3.
Substitution The N2PL3 can replace the N1PL3.

10.3.2 Application
The PL3 is a PDH processing board. The PL3 can be used on the OptiX OSN equipment series
to add and drop PDH signals. To access and process 3xE3/T3 signals, the PL3 must be used with
the interface board.
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Figure 10-13 shows the application of the PL3. The PL3 adds tributary signals to line signals
and drops line signals to tributary signals.
Figure 10-13 Networking and application of the PL3
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Tributary board
Cross-connect and timing board

10.3.3 Functions and Features
The PL3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
Table 10-10 provides the functions and features of the PL3.
Table 10-10 Functions and features of the PL3
Function and
Feature
PL3
Basic functions Processes 3xE3/T3 signals.
Service processing Accesses and processes 3xE3/T3 electrical signals.
Overhead
processing
Supports the setting and query of all the path overhead bytes at the VC-3
level.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
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Function and
Feature
PL3
Maintenance
features
l Supports inloops and outloops at electrical interfaces.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting
services.
l The N2PL3 supports the PRBS function.
l The N1PL3 does not support the CRC function, but the N2PL3
supports the CRC function.
Protection
schemes
Supports the TPS protection when working with the interface board
and the switching and bridging board.

10.3.4 Working Principle and Signal Flow
The PL3 consists of the interface module, mapping/demapping module, interface converting
module, logic and control module, and power module.
Figure 10-14 shows the functional block diagram of the PL3.
Figure 10-14 Functional block diagram of the PL3
E3/T3
E3/T3
Mapping/
Demapping
module
Logic and
control module
Cross-connect
unit A
2x155 Mbit/s
2x155 Mbit/s
LOS
3x34 Mbit/s
3x45 Mbit/s
SCC unit
Communication
Frame header
Outloop/Inloop
control
Interface
converting
module
34 MHz/45 MHz
OSC
+3.3 V backup power
+3.3 V
Power
module
Fuse
Fuse
-48 V/-60 V
Reference
clock
Cross-connect
unit
LIU
LIU
PPI
3x34 Mbit/s
3x45 Mbit/s
Cross-connect
unit B
Cross-connect
unit
High-speed
bus
High-speed
bus
-48V/-60V
Power
module
Interface
module
155 MHz
PLL
Backplane
LIU: logic interface unit PPI: PDH physical interface
OSC: oscillator -
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Figure 10-15 shows the functional block diagram of the mapping/demapping module.
Figure 10-15 Functional block diagram of the mapping/demapping module
E3/T3
STM-1
PDH AIS
detector
Mapping/demapping module
LPA LPT HPA HPT
LPOH (J1/C2/
B3) insertion
TU-AIS/TU-
LOP detector
E3/T3
STM-1
LPA
LPT HPA HPT
LPOH (J1/C2/
B3) extraction
LPA: low order path adaptation LPT: low order path termination
HPA: high order path adaptation HPT: high order path termination

Interface Module
The interface module consists of LIUs and provides the inloop and outloop functions. The
interface module performs the following functions:
l Encodes and decodes signals.
l Restores the data signal and the clock signal.
l Processes the P_LOS alarm.
Mapping/Demapping Module
l LPA sub-module
The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted
so that the stream can be transported to the synchronous network.
l LPT sub-module
The virtual container (VC-3) is formatted. The VC-3 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C-3 container and POH. The POH contains nine octets equally distributed within the frame
bytes for VC-3, namely, J1, B3, C2, G1, F2, H4, F3, K3, and N1.
l HPA sub-module
The HPA sub-module generates and processes the channel-level TU-PTR. In the receive
direction, the signals are split into VC-3s, which are located and isolated in TU-3s. The
TU-PTR is processed. In the transmit direction, VC-3s are located precisely and added with
the TU-PTR. Three TUG-3s are multiplexed into a VC-4 by bytes interleaving. The
sequence is as follows: TU-3->TUG3->VC-4
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l HPT sub-module
The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C4 container and POH.
l MST sub-module and RST sub-module
These sub-modules are required to create a proprietary STM1 signal so that the interface
converting module can be connected.
Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
10.3.5 Front Panel
The front panel of the PL3 has indicators.
Diagram of the Front Panel
Figure 10-16 shows the appearance of the front panel of the PL3.
OptiX OSN 3500 Intelligent Optical Transmission System
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Figure 10-16 Front panel of the PL3
PL3
PL3
ACT
PROG
STAT
SRV
Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the PL3 does not have an interface.
The C34S provides E3/T3 interfaces for the PL3. For details, see the topic that describes the
C34S.
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10.3.6 Jumpers and DIP Switches
The PL3 does not have any jumpers or DIP switches that are used for board settings.
10.3.7 Valid Slots
The PL3 must be used with the C34S. In addition, the PL3 must be installed in a valid slot in
the subrack. Otherwise, the PL3 cannot work normally.
The PL3 can be installed in slots 25 and 1316 in the main subrack.
The PL3 must be used with the C34S.
Table 10-11 lists the slots valid for the PL3 and the corresponding slots for the C34S in the main
subrack.
Table 10-11 Slots valid for the PL3 and the corresponding slots for the C34S in the main subrack
Slot Valid for the PL3 Corresponding Slot for the C34S
Slot 2 Slot 19
Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33
Slot 16 Slot 35

10.3.8 Feature Code
The IFSD1 does not have a feature code.
10.3.9 Board Protection
The PL3 supports the 1:N TPS protection.
Protection Principle
The PL3 can be configured into two 1:N (N3) TPS protection groups when the PL3 works
with the C34S and TSB8/TSB4.
Figure 10-17 shows the TPS protection provided by the PL3.
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Figure 10-17 TPS protection provided by the PL3 in the OptiX OSN 1500B subrack
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l Normal state
When each working board functions normally, the traffic signal is directly transmitted to
the corresponding working board through position 1 of the control switch on the interface
board.
l Switching state
When a working board detects a failure and requires the switching operation, the control
switch of the corresponding interface board switches from position 1 to position 2. At the
same time, the control switch of the protection switching board switches to the
corresponding position so that the protection board can protect the failed working board.
Hardware Configuration
Table 10-12 shows the slot configuration for the 1:3 TPS protection of the PL3.
Table 10-12 Slot configuration for the 1:3 TPS protection of the PL3
Working
Board
Protection Board Slot Configuration
PL3 (E3) PL3 (E3)/PD3 (E3) If the working board is the PL3, the PD3
can be the protection board. Figure 10-18
shows the slot configuration for the 1:3 TPS
protection of the PL3.
PL3 (T3) PL3 (T3)/PD3 (T3)

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Figure 10-18 Slot configuration for the two 1:3 TPS protection groups of the PL3
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In Figure 10-18, the board in slot 2 protects the boards in slots 35. The board in slot 16 protects
the boards in slots 1315.
Table 10-13 lists the slots for the PL3, C34S, and TSB8/TSB4.
Table 10-13 Slots for the PL3, C34S, and TSB8/TSB4
Board Protection Group 1 Protection Group 2
PL3 (working board) Slots 3, 4, and 5 Slots 13, 14, and 15
PL3 (protection board) Slot 2 Slot 16
TSB8/TSB4 Slot 19 Slot 35
C34S Slots 21, 23, and 25 Slots 29, 31, and 33

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10.3.10 Parameter Settings
You can set the parameters for the PL3 by using the T2000.
You can set the following parameters for the PL3 by using the T2000:
l J1 byte
l C2 byte
l Tributary loopback
l Service loading indication
l Path service type
For the description of each parameter, see 25 Parameter Settings.
10.3.11 Technical Specifications
The technical specifications of the PL3 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
The C34S provides electrical interfaces for the PL3. For the parameters specified for the
electrical interfaces, see Technical Specifications Of The C34S.
Mechanical Specifications
The mechanical specifications of the PL3 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight of the N1PL3 (kg): 1.0
l Weight of the N2PL3 (kg): 0.9
Power Consumption
The maximum power consumption of the N1PL3 at room temperature (25C) is 15 W.
The maximum power consumption of the N2PL3 at room temperature (25C) is 12 W.
10.4 PL3A
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the PL3A (3xE3/T3 service processing board with the interfaces on
the front panel). This topic also describes how to configure and commission the PL3A.
10.4.1 Version Description
The PL3A is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the E13/M13 function. The N1PL3A is
discontinued.
10.4.2 Application
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The PL3A is a PDH processing board. The PL3A can be used on the OptiX OSN equipment
series to add and drop PDH signals. To access and process 3xE3/T3 signals, the PL3A uses the
interfaces on its front panel.
10.4.3 Functions and Features
The PL3A processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
10.4.4 Working Principle and Signal Flow
The PL3A consists of the interface module, mapping/demapping module, interface converting
module, logic and control module, and power module.
10.4.5 Front Panel
The front panel of the PL3A has indicators and interfaces.
10.4.6 Jumpers and DIP Switches
The PL3A does not have any jumpers or DIP switches that are used for board settings.
10.4.7 Valid Slots
The PL3A must be installed in a valid slot in the subrack. Otherwise, the PL3A cannot work
normally.
10.4.8 Feature Code
The IFSD1 does not have a feature code.
10.4.9 Parameter Settings
You can set the parameters for the PL3A by using the T2000.
10.4.10 Technical Specifications
The technical specifications of the PL3A include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
10.4.1 Version Description
The PL3A is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the E13/M13 function. The N1PL3A is
discontinued.
Table 10-14 describes the versions of the PL3A.
Table 10-14 Versions of the PL3A
Item Description
Functional versions The PL3A is available in two functional versions, namely, N1 and
N2.
Differences The N1PL3A does not support the E13/M13 function.
The N2PL3A supports the E13/M13 function.
The N2PL3A supports the board version replacement function and
can replace the N1PL3A. After the N2PL3A replaces the N1PL3A,
the configuration and service status of the N2PL3A are the same as
the configuration and service status of the N1PL3A.
Substitution The N2PL3A can replace the N1PL3A.

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10.4.2 Application
The PL3A is a PDH processing board. The PL3A can be used on the OptiX OSN equipment
series to add and drop PDH signals. To access and process 3xE3/T3 signals, the PL3A uses the
interfaces on its front panel.
Figure 10-19 shows the application of the PL3A. The PL3A adds tributary signals to line signals
and drops line signals to tributary signals.
Figure 10-19 Networking and application of the PL3A
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Tributary board
Cross-connect and timing board

10.4.3 Functions and Features
The PL3A processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
Table 10-15 provides the functions and features of the PL3A.
Table 10-15 Functions and features of the PL3A
Function and
Feature
PL3A
Basic functions l Processes 3xE3/T3 signals.
l The N2PL3A supports the E13 function, which is used to converge
E1 services into E3 services.
l The N2PL3A supports the M13 function, which is used to
converge T1 services into T3 services.
Service processing Accesses and processes 3xE3/T3 electrical signals.
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Function and
Feature
PL3A
Overhead
processing
Supports the setting and query of all the path overhead bytes at the
VC-3 level.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Maintenance
features
l Supports inloops and outloops at electrical interfaces.
l Supports warm resets and cold resets. The warm reset does not
affect services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting
services.
l The N2PL3A supports the PRBS function.
l The N1PLS3A does not support the CRC function, but the
N2PL3A supports the CRC function.

10.4.4 Working Principle and Signal Flow
The PL3A consists of the interface module, mapping/demapping module, interface converting
module, logic and control module, and power module.
Figure 10-20 shows the functional block diagram of the PL3A.
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Figure 10-20 Functional block diagram of the PL3A
E3/T3
E3/T3
Mapping/
Demapping
module
Logic and
control module
Cross-connect
unit A
2x155 Mbit/s
2x155 Mbit/s
LOS
3x34 Mbit/s
3x45 Mbit/s
SCC unit
Communication
Frame header
Outloop/Inloop
control
Interface
converting
module
34 MHz/45 MHz
OSC
+3.3 V backup power
+3.3 V
Power
module
Fuse
Fuse
-48 V/-60 V
Reference
clock
Cross-connect
unit
LIU
LIU
PPI
3x34 Mbit/s
3x45 Mbit/s
Cross-connect
unit B
Cross-connect
unit
High-speed
bus
High-speed
bus
-48V/-60V
Power
module
Interface
module
155 MHz
PLL
Backplane
LIU: logic interface unit PPI: PDH physical interface
OSC: oscillator -

Figure 10-21 shows the functional block diagram of the mapping/demapping module.
Figure 10-21 Functional block diagram of the mapping/demapping module
E3/T3
STM-1
PDH AIS
detector
Mapping/demapping module
LPA LPT HPA HPT
LPOH (J1/C2/
B3) insertion
TU-AIS/TU-
LOP detector
E3/T3
STM-1
LPA
LPT HPA HPT
LPOH (J1/C2/
B3) extraction
LPA: low order path adaptation LPT: low order path termination
HPA: high order path adaptation HPT: high order path termination

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Interface Module
The interface module consists of LIUs and provides the inloop and outloop functions. The
interface module performs the following functions:
l Encodes and decodes signals.
l Restores the data signal and the clock signal.
l Processes the P_LOS alarm.
Mapping/Demapping Module
l LPA sub-module
The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted
so that the stream can be transported to the synchronous network.
l LPT sub-module
The virtual container (VC-3) is formatted. The VC-3 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C-3 container and POH. The POH contains nine octets equally distributed within the frame
bytes for VC-3, namely, J1, B3, C2, G1, F2, H4, F3, K3, and N1.
l HPA sub-module
The HPA sub-module generates and processes the channel-level TU-PTR. In the receive
direction, the signals are split into VC-3s, which are located and isolated in TU-3s. The
TU-PTR is processed. In the transmit direction, VC-3s are located precisely and added with
the TU-PTR. Three TUG-3s are multiplexed into a VC-4 by bytes interleaving. The
sequence is as follows: TU-3->TUG3->VC-4
l HPT sub-module
The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C4 container and POH.
l MST sub-module and RST sub-module
These sub-modules are required to create a proprietary STM1 signal so that the interface
converting module can be connected.
Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
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Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
10.4.5 Front Panel
The front panel of the PL3A has indicators and interfaces.
Diagram of the Front Panel
Figure 10-22 shows the appearance of the front panel of the PL3A.
Figure 10-22 Front panel of the PL3A
PL3A
PL3A
ACT
PROG
STAT
SRV
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3

Indicators
The front panel of the board has the following indicators:
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l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the PL3A has three pairs of 75-ohm unbalanced interfaces, which are of the
SMB type.
10.4.6 Jumpers and DIP Switches
The PL3A does not have any jumpers or DIP switches that are used for board settings.
10.4.7 Valid Slots
The PL3A must be installed in a valid slot in the subrack. Otherwise, the PL3A cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the PL3A vary with the cross-connect capacity of the subrack. The slots valid
for the PL3A are as follows:
l
l When the cross-connect capacity is 200 Gbit/s, the PL3A can be installed in slots 18 and
1117 in the main subrack.
10.4.8 Feature Code
The IFSD1 does not have a feature code.
10.4.9 Parameter Settings
You can set the parameters for the PL3A by using the T2000.
You can set the following parameters for the PL3A by using the T2000:
l J1 byte
l C2 byte
l Tributary loopback
l Service loading indication
l Path service type
For the description of each parameter, see 25 Parameter Settings.
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10.4.10 Technical Specifications
The technical specifications of the PL3A include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
Table 10-16 lists the parameters specified for the electrical interfaces of the PL3A.
Table 10-16 Parameters specified for the electrical interfaces of the PL3A
Nominal Bit
Rate
Line Code
Pattern
Signal Bit
Rate at the
Output
Interface
Allowed
Frequency
Deviation
at the
Input
Interface
Allowed
Attenuatio
n at the
Input
Interface
Input
Jitter
Tolerance
34368 kbit/s HDB3 Complies with ITU-T G.703.
44736 kbit/s B3ZS Complies with ITU-T G.703.

Mechanical Specifications
The mechanical specifications of the PL3A are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight of the N1PL3A (kg): 1.0
l Weight of the N2PL3A (kg): 0.9
Power Consumption
The maximum power consumption of the N1PL3A at room temperature (25C) is 15 W.
The maximum power consumption of the N2PL3A at room temperature (25C) is 12 W.
10.5 PD3
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PD3 (6xE3/T3 service processing board).
10.5.1 Version Description
The PD3 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the E13/M13 function. The N1PD3 is
no longer manufactured.
10.5.2 Application
The PD3 is a PDH processing board. The PD3 can be used on the OptiX OSN equipment series
to add and drop PDH signals. To access and process 6xE3/T3 signals, the PD3 must be used
with the interface board.
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10.5.3 Functions and Features
The PD3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
10.5.4 Working Principle and Signal Flow
The PD3 consists of the PPI module, E3/T3 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
10.5.5 Front Panel
The front panel of the PD3 has indicators.
10.5.6 Valid Slots
The PD3 must be used with the D34S.
10.5.7 Board Protection
The PD3 supports the 1:N TPS protection.
10.5.8 Parameter Settings
You can set the parameters for the PD3 by using the T2000.
10.5.9 Technical Specifications
The technical specifications of the PD3 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.
10.5.1 Version Description
The PD3 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to whether they support the E13/M13 function. The N1PD3 is
no longer manufactured.
Table 10-17 describes the versions of the PD3.
Table 10-17 Versions of the PD3
Item Description
Functional versions The PD3 is available in two functional versions, namely, N1 and N2.
Differences l The N1PD3 does not support the E13/M13 function.
l The N2PD3 supports the E13/M13 function.
l The N2PD3 supports the board version replacement function and
can replace the N1PD3. After the N2PD3 replaces the N1PD3, the
configuration and service status of the N2PD3 are the same as the
configuration and service status of the N1PD3.
Substitution The N2PD3 can replace the N1PD3.

10.5.2 Application
The PD3 is a PDH processing board. The PD3 can be used on the OptiX OSN equipment series
to add and drop PDH signals. To access and process 6xE3/T3 signals, the PD3 must be used
with the interface board.
Figure 10-23 shows the application of the PD3. The PD3 adds tributary signals to line signals
and drops tributary signals from line signals.
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Figure 10-23 Networking and application of the PD3
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Tributary board
Cross-connect and timing board

10.5.3 Functions and Features
The PD3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
Table 10-18 provides the functions and features of the PD3.
Table 10-18 Functions and features of the PD3
Function
and Feature
PD3
Basic
functions
Processes 6xE3/T3 signals.
Service
processing
l Accesses and processes 6xE3/T3 electrical signals.
l The N2PD3 supports the E13 function, which is used to converge E1
services into E3 services.
l The N2PD3 supports the M13 function, which is used to converge T1
services into T3 services.
Overhead
processing
Supports the setting and query of all the path overhead bytes at the VC-3
level.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
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Function
and Feature
PD3
Maintenance
features
l Supports inloops and outloops at electrical interfaces.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the PRBS function.
l The N1PD3 does not support the CRC function, but the N2PD3 supports
the CRC function.
Protection
schemes
Supports the TPS protection when working with the interface board and the
switching and bridging board.

10.5.4 Working Principle and Signal Flow
The PD3 consists of the PPI module, E3/T3 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
Figure 10-24 shows the functional block diagram of the PD3.
Figure 10-24 Functional block diagram of the PD3
E3/T3
E3/T3
E3/T3
mapping/
demapping
module
Logic and
control module
Cross-connect unit A
2x155 Mbit/s
LOS
6x34 Mbit/s/
6x45 Mbit/s
SCC Unit
Communication
Frame header
Outloop/Inloop
control
Interface
converting
module
34 MHz/
45 MHz
OSC
+3.3 V backup power
+3.3 V
DC/DC
converter
Fuse
Fuse
-48 V/-60 V
-48 V/-60 V
DC/DC
converter
155 MHz
PLL
Reference
clock
Cross-connect unit
LIU
LIU
P
P
I
Cross-connect unit B
High-
speed bus
Cross-connect unit
High-
speed bus
2x155 Mbit/s 6x45 Mbit/s
6x34 Mbit/s/
OSC: Oscillator PPI: PDH physical interface

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Figure 10-25 shows the functional block diagram of the E3/T3 mapping/demapping module.
Figure 10-25 Functional block diagram of the E3/T3 mapping/demapping module
E3/T3
STM-1
PDH AIS
detector
Mapping/demapping module
LPA LPT HPA HPT
LPOH (J1/C2/
B3) insertion
TU-AIS/TU-
LOP detector
E3/T3
STM-1
LPA
LPT HPA HPT
LPOH (J1/C2/
B3) extraction
LPA: Low order path adaptation LPT: Low order path termination
HPA: High order path adaptation HPT: High order path termination

The functional modules are described as follows:
PPI Module
The PPI module consists of LIUs and provides the inloop and outloop functions. The PPI module
performs the following functions:
l Encodes and decodes signals.
l Restores the data signal and the clock signal.
l Processes the P_LOS alarm.
E3/T3 Mapping/Demapping Module
l LPA sub-module
l The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted
so that the stream can be transported to the synchronous network.
l LPT sub-module
l The virtual container (VC-3) is formatted. The VC-3 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
VC-3 container and POH. The POH contains nine octets equally distributed within the
frame bytes for VC-3, namely, J1, B3, C2, G1, F2, H4, F3, K3, and N1.
l HPA sub-module
l The HPA sub-module generates and processes the channel-level TU-PTR. In the receive
direction, the signals are split into VC-3s, which are located and isolated in TU-3s. The
TU-PTR is processed. In the transmit direction, VC-3s are located precisely and added with
the TU-PTR. Three TUG-3s are multiplexed into a VC-4 by bytes interleaving. The
sequence is as follows: TU-3->TUG3->VC-4
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l HPT sub-module
l The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C4 container and POH.
l MST sub-module and RST sub-module
l These sub-modules are required to create a proprietary STM1 signal so that the interface
converting module can be connected.
Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
10.5.5 Front Panel
The front panel of the PD3 has indicators.
Diagram of the Front Panel
Figure 10-26 shows the appearance of the front panel of the PD3.
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Figure 10-26 Front panel of the PD3
PD3
PD3
ACT
PROG
STAT
SRV

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the PD3 does not have an interface.
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The D34S provides E3/T3 interfaces for the PD3. For details, see the topic that describes the
D34S.
10.5.6 Valid Slots
The PD3 must be used with the D34S.
The PD3 can be installed in slots 25 and 1316 in the main subrack.
Table 10-19 lists the slots valid for the PD3 and the corresponding slots for the D34S in the
main subrack.
Table 10-19 Slots valid for the PD3 and the corresponding slots for the D34S in the main subrack
Slot Valid for the PD3 Corresponding Slot for the D34S
Slot 2 Slot 19
Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33
Slot 16 Slot 35

10.5.7 Board Protection
The PD3 supports the 1:N TPS protection.
Protection Principle
The PD3 can be configured into two 1:N (N3) TPS protection groups when the PD3 works
with the D34S and TSB8. Figure 10-27 shows the TPS protection provided by the PD3.
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Figure 10-27 TPS protection provided by the PD3
TSB8
Slot 2
Slot 9/10
1 2 3 1 2
1 2 1 2
Slot 3 Slot 4 Slot 5
PD3
D34S
6xE3/T3 6xE3/T3 6xE3/T3
D34S D34S
PD3
PD3
PD3
Switching
control
signal
Working Working Working Protection
Failed
Cross-
connect
and timing
board

l Normal state
When each working board functions normally, the traffic signal is directly transmitted to
the PD3 through position 1 of the control switch on the D34S.
l Switching state
When a working board detects a failure and requires the switching operation, the control
switch of the corresponding D34S switches from position 1 to position 2. At the same time,
the control switch of the TSB8 switches to the corresponding position so that the protection
board can protect the failed working board.
Hardware Configuration
Table 10-20 shows the slot configuration for the 1:3 TPS protection of the PD3.
Table 10-20 Slot configuration for the 1:3 TPS protection of the PD3
Working
Board
Protection Board Slot Configuration
PD3 (E3) PD3 (E3) Figure 10-28 shows the slot configuration for
the 1:3 TPS protection of the PD3.
PD3 (T3) PD3 (T3)

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Figure 10-28 Slot configuration for the 1:3 TPS protection of the PD3
S
L
O
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9
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0
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FAN
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3
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4
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5
S
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O
T
6
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L
O
T
7
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O
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8
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1
9
S
L
O
T
2
0
S
L
O
T
2
1
S
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2
2
S
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O
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2
3
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T
2
4
S
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2
5
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2
6
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1
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L
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1
1
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1
2
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1
3
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1
4
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1
5
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1
6
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1
7
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1
8
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2
7
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8
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2
9
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3
0
S
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3
1
S
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3
2
S
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O
T
3
3
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3
4
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3
5
S
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3
6
S
L
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3
7
FAN FAN
G
S
C
C
T
S
B
8
D
3
4
S
D
3
4
S
D
3
4
S
P
I
U
P
I
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A
U
X
D
3
4
S
D
3
4
S
D
3
4
S
T
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B
8
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P
r
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c
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2
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g

1
P
r
o
t
e
c
t
i
o
n

1
W
o
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k
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g

2
Fiber routing area
W
o
r
k
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n
g

1
W
o
r
k
i
n
g

1
W
o
r
k
i
n
g

2
W
o
r
k
i
n
g

2

In Figure 10-28, the board in slot 2 protects the boards in slots 35. The board in slot 16 protects
the boards in slots 1315.
Table 10-21 lists the slots for the PD3, D34S, and TSB8.
Table 10-21 Slots for the PD3, D34S, and TSB8
Board Protection Group 1 Protection Group 2
PD3 (working board) Slots 35 Slots 1315
PD3 (protection board) Slot 2 Slot 16
TSB8 Slot 19 Slot 35
D34S Slots 21, 23, and 25 Slots 29, 31, and 33

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10.5.8 Parameter Settings
You can set the parameters for the PD3 by using the T2000.
You can set the following parameters for the PD3 by using the T2000:
l J1 byte
l C2 byte
l Tributary loopback
l Service loading indication
l Path service type
For the description of each parameter, see 25 Parameter Settings.
10.5.9 Technical Specifications
The technical specifications of the PD3 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
The C34S provides electrical interfaces for the PD3. For the parameters specified for the
electrical interfaces, see Technical Specifications Of The D34S.
Mechanical Specifications
The mechanical specifications of the PD3 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.1
Power Consumption
The maximum power consumption of the N1PD3 at room temperature (25C) is 19 W.
The maximum power consumption of the N2PD3 at room temperature (25C) is 12 W.
10.6 PQ3
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PQ3 (12xE3/T3 service processing board).
10.6.1 Version Description
The PQ3 is available in one functional version, namely, N2.
10.6.2 Application
The PQ3 is a PDH processing board. The PQ3 can be used on the OptiX OSN equipment series
to add and drop PDH signals. To access and process 12xE3/T3 signals, the PQ3 must be used
with the interface board.
10.6.3 Functions and Features
The PQ3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
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10.6.4 Working Principle and Signal Flow
The PQ3 consists of the PPI module, E3/T3 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
10.6.5 Front Panel
The front panel of the PQ3 has indicators.
10.6.6 Valid Slots
The PQ3 can be installed in slots 25 and 1316, and must be used with the D34S.
10.6.7 Board Protection
The PQ3 supports the 1:N TPS protection.
10.6.8 Parameter Settings
You can set the parameters for the PQ3 by using the T2000.
10.6.9 Technical Specifications
The technical specifications of the PQ3 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.
10.6.1 Version Description
The PQ3 is available in one functional version, namely, N2.
10.6.2 Application
The PQ3 is a PDH processing board. The PQ3 can be used on the OptiX OSN equipment series
to add and drop PDH signals. To access and process 12xE3/T3 signals, the PQ3 must be used
with the interface board.
Figure 10-29 shows the application of the PQ3. The PQ3 adds tributary signals to line signals
and drops tributary signals from line signals.
Figure 10-29 Networking and application of the PQ3
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Tributary board
Cross-connect and timing board

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10.6.3 Functions and Features
The PQ3 processes E3/T3 signals, processes overhead bytes, reports alarms and performance
events, provides maintenance features, and supports the TPS protection.
Table 10-22 provides the functions and features of the PQ3.
Table 10-22 Functions and features of the PQ3
Function and
Feature
PQ3
Basic functions Processes 12xE3/T3 signals.
Service
processing
l Accesses and processes 12xE3/T3 electrical signals.
l Supports the E13 function, which is used to converge E1 services into
E3 services.
l Supports the M13 function, which is used to converge T1 services into
T3 services.
Overhead
processing
Supports the setting and query of all the path overhead bytes at the VC-3
level.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Maintenance
features
l Supports inloops and outloops at electrical interfaces.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Supports the PRBS function.
l Supports the CRC function.
Protection
schemes
Supports the TPS protection when working with the interface board and the
switching and bridging board.

10.6.4 Working Principle and Signal Flow
The PQ3 consists of the PPI module, E3/T3 mapping/demapping module, interface converting
module, logic and control module, DC/DC converter, and other modules.
Figure 10-30 shows the functional block diagram of the PQ3.
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Figure 10-30 Functional block diagram of the PQ3
E3/T3
E3/T3
E3/T3
mapping/
demapping
module
Logic and
control module
Cross-connect unit A
2x155 Mbit/s
LOS
12x34 Mbit/s/
12x45 Mbit/s
SCC Unit
Communication
Frame header
Outloop/Inloop
control
Interface
converting
module
34 MHz/
45 MHz
OSC
+3.3 V backup power
+3.3 V
DC/DC
converter
Fuse
Fuse
-48 V/-60 V
-48 V/-60 V
DC/DC
converter
155 MHz
PLL
Reference
clock
Cross-connect unit
LIU
LIU
P
P
I
Cross-connect unit B
High-
speed bus
Cross-connect unit
High-
speed bus
2x155 Mbit/s 12x45 Mbit/s
12x34 Mbit/s/
OSC: Oscillator PPI: PDH physical interface

Figure 10-31 shows the functional block diagram of the E3/T3 mapping/demapping module.
Figure 10-31 Functional block diagram of the E3/T3 mapping/demapping module
E3/T3
STM-1
PDH AIS
detector
Mapping/demapping module
LPA LPT HPA HPT
LPOH (J1/C2/
B3) insertion
TU-AIS/TU-
LOP detector
E3/T3
STM-1
LPA
LPT HPA HPT
LPOH (J1/C2/
B3) extraction
LPA: Low order path adaptation LPT: Low order path termination
HPA: High order path adaptation HPT: High order path termination

The functional modules are described as follows:
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PPI Module
The PPI module consists of LIUs and provides the inloop and outloop functions. The PPI module
performs the following functions:
l Encodes and decodes signals.
l Restores the data signal and the clock signal.
l Processes the P_LOS alarm.
E3/T3 Mapping/Demapping Module
l LPA sub-module
l The 45 Mbit/s (34 Mbit/s) plesiochronous stream is inserted in a C3 container to be adapted
so that the stream can be transported to the synchronous network.
l LPT sub-module
l The virtual container (VC-3) is formatted. The VC-3 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
VC-3 container and POH. The POH contains nine octets equally distributed within the
frame bytes for VC-3, namely, J1, B3, C2, G1, F2, H4, F3, K3, and N1.
l HPA sub-module
l The HPA sub-module generates and processes the channel-level TU-PTR. In the receive
direction, the signals are split into VC-3s, which are located and isolated in TU-3s. The
TU-PTR is processed. In the transmit direction, VC-3s are located precisely and added with
the TU-PTR. Three TUG-3s are multiplexed into a VC-4 by bytes interleaving. The
sequence is as follows: TU-3->TUG3->VC-4
l HPT sub-module
l The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are
distributed within a 125 us interval (for example, one STM1 period), and consists of the
C4 container and POH.
l MST sub-module and RST sub-module
l These sub-modules are required to create a proprietary STM1 signal so that the interface
converting module can be connected.
Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
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DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
10.6.5 Front Panel
The front panel of the PQ3 has indicators.
Diagram of the Front Panel
Figure 10-32 shows the appearance of the front panel of the PQ3.
Figure 10-32 Front panel of the PQ3
PQ3
PQ3
ACT
PROG
STAT
SRV

Indicators
The front panel of the board has the following indicators:
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l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the PQ3 does not have an interface.
The D34S provides E3/T3 interfaces for the PQ3. For details, see the topic that describes the
D34S.
10.6.6 Valid Slots
The PQ3 can be installed in slots 25 and 1316, and must be used with the D34S.
Table 10-23 lists the slots valid for the PQ3 and the corresponding slots for the D34S.
Table 10-23 Slots valid for the PQ3 and the corresponding slots for the D34S
Slot Valid for the PQ3 Corresponding Slot for the D34S
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

10.6.7 Board Protection
The PQ3 supports the 1:N TPS protection.
Protection Principle
The PQ3 boards can be configured into two 1:N (N3) TPS protection groups when the PQ3
boards work with two D34S boards and two TSB8 boards. Figure 10-33 shows the TPS
protection provided by the PQ3.
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Figure 10-33 TPS protection provided by the PQ3
12xE3/T3
1 2 1 2
12xE3/T3
Slot 5
3 1 2
Slot 2
PQ3
3 1 2
12xE3/T3
D34S
1 2 1 2
12xE3/T3
Slot 3
Slot 9/10
12xE3/T3
TSB8
1 2
PQ3
1 2
12xE3/T3
Slot 4
TSB8 D34S D34S D34S D34S D34S
PQ3 PQ3
Switching
control
signal
Working
Working
Working
Failed
Protection
Cross-
connect
and timing
board

l Normal state
When each working board functions normally, the traffic signal is directly transmitted to
the PQ3 through position 1 of the control switch on the D34S.
l Switching state
When a working board detects a failure and requires the switching operation, the control
switch of the corresponding D34S switches from position 1 to position 2. At the same time,
the control switch of the TSB8 switches to the corresponding position so that the protection
board can protect the failed working board.
Hardware Configuration
NOTE
When you configure the N2PQ3 as the TPS protection board, two TSB8 boards are required.
Table 10-24 shows the slot configuration for the 1:3 TPS protection of the PQ3.
Table 10-24 Slot configuration for the 1:3 TPS protection of the PQ3
Working
Board
Protection Board Slot Configuration
PQ3 (E3) PQ3 (E3) Figure 10-34 shows the slot configuration for
the 1:3 TPS protection of the PQ3.
PQ3 (T3) PQ3 (T3)

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Figure 10-34 Slot configuration for the two 1:3 TPS protection groups of the PQ3
Fiber routing area
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In Figure 10-34, the board in slot 2 protects the boards in slots 35. The board in slot 16 protects
the boards in slots 1315.
Table 10-25 lists the slots for the PQ3, D34S, and TSB8.
Table 10-25 Slots for the PQ3, D34S, and TSB8
Board Protection Group 1 Protection Group 2
PQ3 (working board) Slots 35 Slots 1315
PQ3 (protection board) Slot 2 Slot 16
TSB8 Slots 19 and 20 Slots 35 and 36
D34S Slots 2126 Slots 2934

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10.6.8 Parameter Settings
You can set the parameters for the PQ3 by using the T2000.
You can set the following parameters for the PQ3 by using the T2000:
l J1 byte
l C2 byte
l Tributary loopback
l Service loading indication
l Path service type
For the description of each parameter, see 25 Parameter Settings.
10.6.9 Technical Specifications
The technical specifications of the PQ3 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
The D34S provides electrical interfaces for the PQ3. For the parameters specified for the
electrical interfaces, see Technical Specifications Of The D34S.
Mechanical Specifications
The mechanical specifications of the PQ3 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.9
Power Consumption
The maximum power consumption of the PQ3 at room temperature (25C) is 13 W.
10.7 DX1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the DX1 (DDN service accessing and converging board). This topic
also describes how to configure and commission the DX1.
10.7.1 Version Description
The DX1 is available in one functional version, namely, N1.
10.7.2 Application
The DX1 is a DDN service processing board. The DX1 can be used on the OptiX OSN equipment
series to add and converge the DDN services. To access eight channels of Nx64 kbit/s signals
and eight channels of framed E1 services and to cross-connect the 48 channels of Nx64 kbit/s
signals on the system side, the DX1 must be used with the interface board.
10.7.3 Functions and Features
The DX1 cross-connects 48xE1 signals at the 64 kbit/s level on the system side.
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10.7.4 Working Principle and Signal Flow
The DX1 consists of the interface and frame processing module, encoding/decoding module,
timeslot cross-connect module, framing/deframing module, mapping/demapping module, logic
and control module, and power module.
10.7.5 Front Panel
The front panel of the DX1 has indicators.
10.7.6 Jumpers and DIP Switches
The DX1 does not have any jumpers or DIP switches that are used for board settings.
10.7.7 Valid Slots
The DX1 must be used with the DM12. In addition, the DX1 must be installed in a valid slot in
the subrack. Otherwise, the DX1 cannot work normally.
10.7.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the DX1 indicates the type of interface impedance.
10.7.9 Board Protection
The DX1 supports the 1:N TPS protection.
10.7.10 Parameter Settings
You can set the parameters for the DX1 by using the T2000.
10.7.11 Technical Specifications
The technical specifications of the DX1 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.
10.7.1 Version Description
The DX1 is available in one functional version, namely, N1.
10.7.2 Application
The DX1 is a DDN service processing board. The DX1 can be used on the OptiX OSN equipment
series to add and converge the DDN services. To access eight channels of Nx64 kbit/s signals
and eight channels of framed E1 services and to cross-connect the 48 channels of Nx64 kbit/s
signals on the system side, the DX1 must be used with the interface board.
Figure 10-35 shows the application of the DX1. The DX1 adds DDN service signals to line
signals and drops line signals to DDN service signals.
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Figure 10-35 Networking and application of the DX1
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Tributary board
Cross-connect and timing board

10.7.3 Functions and Features
The DX1 cross-connects 48xE1 signals at the 64 kbit/s level on the system side.
Table 10-26 provides the functions and features of the DX1.
Table 10-26 Functions and features of the DX1
Function
and
Feature
DX1
Basic
functions
l Processes eight channels of Nx64 kbit/s services and eight channels of
framed E1 services.
l Cross-connects 48 channels of Nx64 kbit/s signals on the system side.
Service
processing
l Accesses eight channels of Nx64 kbit/s and eight channels of framed E1
services and realizes the 1:N TPS protection when working with the DM12.
l One DX1 board needs to work with two DM12 boards.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Maintenance
features
l Supports inloops and outloops at electrical interfaces.
l Supports the PRBS function.
l Supports the CRC function.
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Function
and
Feature
DX1
Connectors The DB28 connectors and DB44 connectors are present on the front panel of
the DM12. The DB28 connector is used for the Nx64 kbit/s signals, and the
DB44 connector is used for the framed E1 signals.
Protection
schemes
Supports the TPS protection when working with the interface board.

10.7.4 Working Principle and Signal Flow
The DX1 consists of the interface and frame processing module, encoding/decoding module,
timeslot cross-connect module, framing/deframing module, mapping/demapping module, logic
and control module, and power module.
Figure 10-36 shows the functional block diagram of the DX1.
Figure 10-36 Functional block diagram of the DX1
64 kbit/s
timeslot
cross-connect
module
Framing/
Deframing
module
Mapping/
Demapping
module for
48 channels
of signals
Logic and
control module
Framed E1
encoding/
decoding and
frame processing
module
Backplane
Nx64 kbit/s
interface
and frame
processing
module
+3.3 V backup power
+3.3 V
Power
module
Fuse
Fuse
Power
module
Framed E1
interface
module
DM12
DX1
DM12
Backplane
Power
Power
4xNx64 kbit/s
8xFrame E1
-48 V/-60 V
-48 V/-60 V
Cross-connect
unit
SCC unit
Nx64 kbit/s
interface
module
Nx64 kbit/s
interface
module
Framed E1
interface
module
4xNx64 kbit/s

In the Transmit Direction
The mapping/demapping module demaps the VC-4 signals sent from the SDH cross-connect
unit and sends the demapped signals to the framing/deframing module. Then, the framing/
deframing module converts the signals into the framed E1 signals and sends the framed E1
signals to the timeslot cross-connect module. Finally, the timeslot cross-connect module cross-
connects and grooms the signals at the 64 kbit/s granularity, and transmits the signals that need
to be dropped on the local NE to the interface module.
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In the Receive Direction
The DX1 accesses eight channels of framed E1 signals from the framed E1 interface module of
the DM12 and eight channels of Nx64 kbit/s signals from the Nx64 kbit/s interface module of
the DM12. In addition, the DX1 restores the data signal and clock signal.
In the case of the framed E1 signals, the DX1 decodes the signals and processes the frames. In
the case of the Nx64 kbit/s signals, the DX1 converts the signals and processes the frames. Then,
the DX1 transmits the signals to the 64 kbit/s timeslot cross-connect module. The timeslot cross-
connect module cross-connects and grooms the signals at the 64 kbit/s granularity, and transmits
the signals to the framing/deframing module. Finally, the framing/deframing module maps the
signals into VC-4s and transmits the signals to the SDH cross-connect unit.
Logic and Control Module
The logic and control module performs the board communication, board control, and service
configuration functions. In addition, the logic and control module traces and selects the clock
signals and frame header signals sent from the active and standby cross-connect boards.
Power Module
The power module provides all the modules of the DX1 with the required DC voltages.
10.7.5 Front Panel
The front panel of the DX1 has indicators.
Diagram of the Front Panel
Figure 10-37 shows the appearance of the front panel of the DX1.
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Figure 10-37 Front panel of the DX1
DX1
DX1
STAT
ACT
PROG
SRV

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the DX1 does not have an interface.
One DX1 board needs to work with two DM12 boards to receive and transmit the framed E1
signals and Nx64 kbit/s signals. For details, see the topic that describes the DM12.
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10.7.6 Jumpers and DIP Switches
The DX1 does not have any jumpers or DIP switches that are used for board settings.
10.7.7 Valid Slots
The DX1 must be used with the DM12. In addition, the DX1 must be installed in a valid slot in
the subrack. Otherwise, the DX1 cannot work normally.
The DX1 can be installed in slots 15 and 1316.
Table 10-27 lists the slots valid for the DX1 and the corresponding slots for the DM12.
Table 10-27 Slots valid for the DX1 and the corresponding slots for the DM12
Slot Valid for the DX1 Corresponding Slot for the DM12
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

NOTE
l Slot 1 can house a protection board for the TPS protection. The board in slot 1 protects the boards in
slots 25 and 1316.
l One DX1 needs to work with two DM12 boards to access eight channels of Nx64 kbit/s signals. The
DM12 in the slot with a smaller slot number is used to access eight channels of framed E1 signals and
four channels of Nx64 kbit/s signals. The DM12 in the slot with a larger slot number is used to access
four channels of Nx64 kbit/s signals.
10.7.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the DX1 indicates the type of interface impedance.
Table 10-28 provides the relationship between the feature code of the DX1 and the type of
interface impedance.
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Table 10-28 Relationship between the feature code of the DX1 and the type of interface
impedance
Board Feature Code Type of Interface Impedance
SSN1DX1A01 A01 75-ohm
SSN1DX1B01 B01 120-ohm

10.7.9 Board Protection
The DX1 supports the 1:N TPS protection.
Protection Principle
The DX1 can be configured into one 1:N (N8) TPS protection group when the DX1 works
with the DM12.
Figure 10-38 shows the TPS protection provided by the DX1.
Figure 10-38 TPS protection provided by the DX1
Switching
control bus
Protection bus
2 1 2 1 2 1 2 1
Service signal Service signal
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Protection bus

When the cross-connect and timing board detects that a working DX1 is faulty, the cross-connect
and timing board issues a service switching command to control the interface board to switch
the services from the faulty board to the protection board, which realizes the protection of the
services.
Hardware Configuration
Figure 10-39 shows the slot configuration for the 1:8 TPS protection of the DX1.
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Figure 10-39 Slot configuration for the 1:8 TPS protection of the DX1
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In Figure 10-39, the board in slot 1 protects the boards in slots 25 and 1316.
Table 10-29 lists the slots for the DX1 and DM12.
Table 10-29 Slots for the DX1 and DM12
Board Protection Group
DX1 (working board) Slots 25 and 1316
DX1 (protection board) Slot 1
DM12 Slots 1926 and 2936

10.7.10 Parameter Settings
You can set the parameters for the DX1 by using the T2000.
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You can set the following parameters for the DX1 by using the T2000:
l J2 byte
l Tributary loopback
l Service loading indication
l Protocol mode of serial ports
l DDN clock source management
For the description of each parameter, see 25 Parameter Settings.
10.7.11 Technical Specifications
The technical specifications of the DX1 include the parameters specified for electrical interfaces,
mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
The DM12 provides electrical interfaces for the DX1. For the parameters specified for the
electrical interfaces, see Technical Specifications Of The DM12.
Mechanical Specifications
The mechanical specifications of the DX1 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the DX1 at room temperature (25C) is 15 W.
10.8 DXA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the DXA (DDN service converging and processing board).
10.8.1 Version Description
The DXA is available in one functional version, namely, N1.
10.8.2 Application
The DXA is a DDN service processing board. The DXA can be used on the OptiX OSN
equipment series to access and converge DDN services. To cross-connect the 63 channels of
Nx64 kbit/s signals and framed E1 signals on the system side, the DXA board must be used with
the interface board.
10.8.3 Functions and Features
The DXA cross-connects 63xE1 signals at the 64 kbit/s level on the system side.
10.8.4 Working Principle and Signal Flow
The DXA consists of the timeslot cross-connect module, framing/deframing module, mapping/
demapping module, logic and control module, and power module.
10.8.5 Front Panel
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The front panel of the DXA has indicators.
10.8.6 Valid Slots
The slots valid for the DXA vary with the cross-connect capacity of the subrack.
10.8.7 Parameter Settings
You can set the parameters for the DXA by using the T2000.
10.8.8 Technical Specifications
The technical specifications of the DXA include the mechanical specifications and power
consumption.
10.8.1 Version Description
The DXA is available in one functional version, namely, N1.
10.8.2 Application
The DXA is a DDN service processing board. The DXA can be used on the OptiX OSN
equipment series to access and converge DDN services. To cross-connect the 63 channels of
Nx64 kbit/s signals and framed E1 signals on the system side, the DXA board must be used with
the interface board.
Figure 10-40 shows the application of the DXA. The DXA adds DDN service signals to line
signals and drops DDN signals from line signals.
Figure 10-40 Networking and application of the DXA
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Tributary board
Cross-connect and timing board

10.8.3 Functions and Features
The DXA cross-connects 63xE1 signals at the 64 kbit/s level on the system side.
Table 10-30 provides the functions and features of the DXA.
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Table 10-30 Functions and features of the DXA
Function and
Feature
DXA
Basic functions Cross-connects 63 channels of framed E1 signals.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Maintenance
features
Supports inloops and outloops.
Supports the CRC function.

10.8.4 Working Principle and Signal Flow
The DXA consists of the timeslot cross-connect module, framing/deframing module, mapping/
demapping module, logic and control module, and power module.
Figure 10-41 shows the functional block diagram of the DXA.
Figure 10-41 Functional block diagram of the DXA
64 kbit/s
timeslot
cross-
connect
module
Framing/
Deframing
module
Signal
mapping/
demapping
module
Logic and
control module
Backplane
Cross-
connect unit
+3.3 V
backup power
+3.3 V
-48 V/-60 V Power
module
Fuse
Fuse
-48 V/-60 V
SCC unit
Power
module

In the Transmit Direction
The mapping/demapping module demaps the VC-4 signals sent from the SDH cross-connect
unit and sends the demapped signals to the framing/deframing module. Then, the framing/
deframing module converts the signals into the framed E1 signals and sends the framed E1
signals to the timeslot cross-connect module. Finally, the timeslot cross-connect module cross-
connects and grooms the signals at the 64 kbit/s granularity.
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In the Receive Direction
The timeslot cross-connect module cross-connects and grooms the signals at the 64 kbit/s
granularity, and transmits the signals to the framing/deframing module. Then, the framing/
deframing module maps the signals into VC-4s and transmits the signals to the SDH cross-
connect unit.
Logic and Control Module
The logic and control module performs the board communication, board control, and service
configuration functions. In addition, the logic and control module traces and selects the clock
signals and frame header signals sent from the active and standby cross-connect boards.
Power Module
The power module provides all the modules of the DX1 with the required DC voltages.
10.8.5 Front Panel
The front panel of the DXA has indicators.
Diagram of the Front Panel
Figure 10-42 shows the appearance of the front panel of the DXA.
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Figure 10-42 Front panel of the DXA
DXA
DXA
ACT
PROG
STAT
SRV

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the DXA does not have an interface.
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10.8.6 Valid Slots
The slots valid for the DXA vary with the cross-connect capacity of the subrack.
The slots valid for the DXA are as follows:
l When the cross-connect capacity is 200 Gbit/s, the DXA can be installed in slots 18 and
1117.
10.8.7 Parameter Settings
You can set the parameters for the DXA by using the T2000.
You can set the following parameters for the DXA by using the T2000:
l J2 byte
l Tributary loopback
l Service loading indication
l Protocol mode of serial ports
l DDN clock source management
For the description of each parameter, see 25 Parameter Settings.
10.8.8 Technical Specifications
The technical specifications of the DXA include the mechanical specifications and power
consumption.
Mechanical Specifications
The mechanical specifications of the DXA are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.8
Power Consumption
The maximum power consumption of the DXA at room temperature (25C) is 10 W.
10.9 SPQ4
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the SPQ4 (4xE4/STM-1 electrical processing board). This topic also
describes how to configure and commission the SPQ4.
10.9.1 Version Description
The SPQ4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to their functions. The N1SPQ4 is discontinued.
10.9.2 Application
The SPQ4 is a PDH processing board. The SPQ4 can be used on the OptiX OSN equipment
series to transmit and receive E4/STM-1 electrical signals. To access and process 4xE4/STM-1
electrical signals, the SPQ4 must be used with the interface board.
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10.9.3 Functions and Features
The SPQ4 processes 4xE4/STM-1 electrical signals, processes overhead bytes, reports alarms
and performance events, provides maintenance features, and supports protection schemes.
10.9.4 Working Principle and Signal Flow
The SPQ4 consists of the interface module, mapping/demapping module, SDH overhead
processing module, interface converting module, logic and control module, and power module.
10.9.5 Front Panel
The front panel of the SPQ4 has indicators.
10.9.6 Jumpers and DIP Switches
The SPQ4 does not have any jumpers or DIP switches that are used for board settings.
10.9.7 Valid Slots
The SPQ4 must be used with the MU04. In addition, the SPQ4 must be installed in a valid slot
in the subrack. Otherwise, the SPQ4 cannot work normally.
10.9.8 Feature Code
The IFSD1 does not have a feature code.
10.9.9 Board Protection
The SPQ4 supports the 1:N TPS protection.
10.9.10 Parameter Settings
You can set the parameters for the SPQ4 by using the T2000.
10.9.11 Technical Specifications
The technical specifications of the SPQ4 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
10.9.1 Version Description
The SPQ4 is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to their functions. The N1SPQ4 is discontinued.
Table 10-31 describes the versions of the SPQ4.
Table 10-31 Versions of the SPQ4
Item Description
Functional versions The SPQ4 is available in two functional versions, namely, N1 and N2.
Differences The equipment of the V100R001 and V100R002 versions supports
the N1SPQ4. The equipment of the V100R003 and later versions
supports the N2SPQ2.
Substitution The N1SPQ4 can be replaced with the N2SPQ4. When the N1SPQ4
is replaced with the N2SPQ4, the NE software needs to be upgraded.

10.9.2 Application
The SPQ4 is a PDH processing board. The SPQ4 can be used on the OptiX OSN equipment
series to transmit and receive E4/STM-1 electrical signals. To access and process 4xE4/STM-1
electrical signals, the SPQ4 must be used with the interface board.
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Figure 10-43 shows the application of the SPQ4. The SPQ4 adds tributary signals to line signals
and drops line signals to tributary signals.
Figure 10-43 Networking and application of the SPQ4
NE1
NE2 NE4
NE3
MSP ring
Service flow
Line board
Tributary board
Cross-connect and timing board

10.9.3 Functions and Features
The SPQ4 processes 4xE4/STM-1 electrical signals, processes overhead bytes, reports alarms
and performance events, provides maintenance features, and supports protection schemes.
Table 10-32 provides the functions and features of the SPQ4.
Table 10-32 Functions and features of the SPQ4
Function and
Feature
SPQ4
Basic functions Processes 4xSTM-1/E4 signals.
Service
processing
Accesses and processes 4xE4/STM-1 electrical signals. The E4 signals
and STM-1 signals are compatible on each channel. Supports the VC-12
services, VC-3 services, and VC-4 services.
Overhead
processing
l Processes the section overheads of the STM-1 signals, such as B1, B2,
K1, K2, M1, F1, and D1D12.
l Supports the transparent transmission and termination of the path
overhead bytes including J1, B3, C2, G1, and H4.
l Supports the setting and query of the J0, J1, and C2 bytes.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
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Function and
Feature
SPQ4
Maintenance
features
l Supports inloops and outloops at optical interfaces.
l Supports warm resets and cold resets. The warm reset does not affect
services.
l Supports the query of the manufacturing information of the board.
l Supports the in-service loading of the FPGA.
l Supports the upgrade of the board software without affecting services.
l Does not support the CRC function.
Protection
schemes
l Supports the TPS protection when working with the interface board
and the switching and bridging board.
l Supports the two-fiber ring MSP.
l Supports the linear MSP.
l Supports the SNCP.

10.9.4 Working Principle and Signal Flow
The SPQ4 consists of the interface module, mapping/demapping module, SDH overhead
processing module, interface converting module, logic and control module, and power module.
Figure 10-44 shows the functional block diagram of the SPQ4. Figure 10-45 shows the
functional block diagram of the mapping/demapping module. Figure 10-46 shows the functional
block diagram of the SDH overhead processing module.
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Figure 10-44 Functional block diagram of the SPQ4
E4/STM-1
Mapping/
Demapping
module
Logic and
control module
Cross-connect
unit A
4x155 Mbit/s
LOS
4x139 Mbit/s
SCC unit
Communication
Frame header
Outloop/Inloop control
Interface
converting
module
34 MHz
OSC
+3.3 V backup power
+3.3 V
Power
module
Fuse
Fuse
-48 V/-60 V
Reference
clock Cross-connect
unit
LIU
LIU
P
P
I
/
S
P
I
Cross-connect
unit B
Cross-connect
unit
High-speed
bus
High-speed
bus
-48 V/-60 V Power
module
Interface
module
4x155 Mbit/s 4x155 Mbit/s
SDH
overhead
processing
module
EN 140 Mbit/s/155 Mbit/s
DCC
SCC unit
K1 and K2
Cross-connect
unit
155 MHz
PLL
Backplane
LIU: logic interface unit PPI: PDH physical interface
OSC: oscillator -

Figure 10-45 Functional block diagram of the mapping/demapping module
139 Mbit/s
Mapping/demapping module
PDH AIS
detector
E4 AIS
insertion
J1/C2/B3
139 Mbit/s
E4 AIS
insertion
155 Mbit/s
155 Mbit/s
LPA HPT PG MST RST
RST MST HPT LPA SIPO

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Figure 10-46 Functional block diagram of the SDH overhead processing module
155 Mbit/s
155 Mbit/s
SDH overhead processing module
DCC
K1 and K2 insertion/
extraction
SCC unit
155 Mbit/s
RST MST MSA HPT
Cross-connect unit
155 Mbit/s

Interface Module
The PPI module consists of LIUs and provides the inloop and outloop functions. The PPI module
performs the following functions:
l Encodes and decodes signals.
l Restores the data signal and the clock signal.
l Processes the PDH LOS signals.
The SPI module consists of LIUs and provides the inloop and outloop functions. The SPI module
performs the following functions:
l Encodes and decodes signals.
l Restores the data signal and the clock signal.
l Processes the R_LOS signals.
SDH Overhead Processing Module and Mapping/Demapping Module
SDH Overhead Processing Module (155 Mbit/s SDH Signals)
The SDH overhead processing module performs the functions that are required to manage 155
Mbit/s SDH signals.
RST Sub-Module
l In the receive direction, the RST sub-module detects the frame alignment bytes (A1 and
A2), restores the regenerator section trace byte (J0), detects a J0 mismatch, and counts
BIP-8 errored blocks.
l In the transmit direction, the RST sub-module inserts the frame alignment bytes, inserts
the J0 byte, and performs BIP-8 calculation and byte insertion.
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MST Sub-Module
l In the receive direction, the MST sub-module counts BIP-24 errored blocks, restores the
MS_REI, and detects the MS_RDI and MS_AIS.
l In the transmit direction, the MST sub-module performs BIP-24 calculation and insertion
and inserts the MS_REI, MS_RDI, and MS_AIS.
l The MST sub-module extracts or inserts the K1 byte and K2 byte.
MSA Sub-Module
l In the receive direction, the MSA sub-module interprets the AU-4 pointer, detects the LOP
and AIS, and performs pointer justifications.
l In the transmit direction, the MSA sub-module assembles the AUG and generates the AU-4
pointer and the AU_AIS.
HPT Sub-Module
l Terminates the overheads.
l Restores the J1 path trace message.
l Restores the REI information.
l Detects the HP_RDI (monitors the status of the path).
l Detects the UNEQ and AIS (monitors the signal label).
l Counts the VC-4 BIP-8 errored blocks.
Mapping/Demapping Module (140 Mbit/s PDH Signals)
The mapping/demapping module performs the functions that are required to manage 140 Mbit/
s PDH signals.
LPA Sub-Module
The 140 Mbit/s plesiochronous stream is inserted in a C4 container to be adapted so that the
stream can be transported to the synchronous network. The PDH AIS is monitored and the E4
AIS in inserted.
HPT Sub-Module
The virtual container (VC-4) is formatted. The VC-4 is structured so that its octets are distributed
within a 125 us interval (for example, one STM1 period), and consists of the C4 container and
POH. The POH contains nine octets equally distributed within the frame. The following
overhead bytes can be extracted: J1, B3. C2, G1, F2, H4, F3, K3, and N1. The E4 AIS can be
inserted in the downstream direction.
Pointer generator (PG)
A fixed pointer value is inserted in the SOH to structure the AU-4 signal.
MST Sub-Module and RST Sub-Module
These sub-modules are required to create a proprietary STM1 signal so that the interface
converting module can be connected. In the receive direction, these sub-modules detect the frame
alignment bytes (A1 and A2).
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Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
l Manages and configures the other modules of the board.
l Performs inter-board communication through the internal Ethernet interface.
l Traces the clock signal from the active and standby cross-connect units.
l Passes the orderwire and ECC bytes through an ADM that consists of two paired slots when
the GSCC is not in position.
l Selects the clock signal and frame header signal from the active and standby cross-connect
units.
l Controls the indicators on the board.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
10.9.5 Front Panel
The front panel of the SPQ4 has indicators.
Diagram of the Front Panel
Figure 10-47 shows the appearance of the front panel of the SPQ4.
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Figure 10-47 Front panel of the SPQ4
SPQ4
SPQ4
ACT
PROG
STAT
SRV

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the SPQ4 does not have an interface. Hence, the SPQ4 needs to work with
the MU04 to receive and transmit the E4/STM-1 signals. For details, see the topic that describes
the MU04.
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10.9.6 Jumpers and DIP Switches
The SPQ4 does not have any jumpers or DIP switches that are used for board settings.
10.9.7 Valid Slots
The SPQ4 must be used with the MU04. In addition, the SPQ4 must be installed in a valid slot
in the subrack. Otherwise, the SPQ4 cannot work normally.
The SPQ4 can be installed in slots 25 and 1316.
Table 10-33 lists the slots valid for the SPQ4 and the corresponding slots for the MU04.
Table 10-33 Slots valid for the SPQ4 and the corresponding slots for the MU04
Slot Valid for the SPQ4 Corresponding Slot for the MU04
Slot 2 Slot 19
Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33
Slot 16 Slot 35

10.9.8 Feature Code
The IFSD1 does not have a feature code.
10.9.9 Board Protection
The SPQ4 supports the 1:N TPS protection.
Protection Principle
The SPQ4 can be configured into two 1:N (N3) TPS protection groups when the SPQ4 works
with the MU04 and TSB8/TSB4.
Figure 10-48 shows the TPS protection provided by the SPQ4.
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Figure 10-48 TPS protection provided by the SPQ4
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l Normal state
When each working board functions normally, the traffic signal is directly transmitted to
the working board through position 1 of the control switch on the interface board.
l Switching state
When a working board detects a failure and requires the switching operation, the control
switch of the corresponding interface board switches from position 1 to position 2. At the
same time, the control switch of the protection switching board switches to the
corresponding position so that the protection board can protect the failed working board.
Hardware Configuration
Figure 10-49 shows the slot configuration for the 1:3 TPS protection of the SPQ4.
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Figure 10-49 Slot configuration for the two 1:3 TPS protection groups of the SPQ4
S
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In Figure 10-49, the board in slot 2 protects the boards in slots 35. The board in slot 16 protects
the boards in slots 1315.
Table 10-34 lists the slots for the SPQ4, MU04, and TSB8/TSB4.
Table 10-34 Slots for the SPQ4, MU04, and TSB8/TSB4
Board Protection Group 1 Protection Group 2
SPQ4 (working
board)
Slots 35 Slots 1315
SPQ4 (protection
board)
Slot 2 Slot 16
MU04 Slots 21, 23, and 25 Slots 29, 31, and 33
TSB8/TSB4 Slot 19 Slot 35

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10.9.10 Parameter Settings
You can set the parameters for the SPQ4 by using the T2000.
You can set the following parameters for the SPQ4 by using the T2000:
l J1 byte
l C2 byte
For the description of each parameter, see 25 Parameter Settings.
10.9.11 Technical Specifications
The technical specifications of the SPQ4 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
The MU04 provides electrical interfaces for the SPQ4. For the parameters specified for the
electrical interfaces, see Technical Specifications Of The MU04.
Mechanical Specifications
The mechanical specifications of the SPQ4 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.9
Power Consumption
The maximum power consumption of the SPQ4 at room temperature (25C) is 24 W.
10.10 D12B
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D12B (32xE1/T1 access board).
10.10.1 Version Description
The D12B is available in one functional version, namely, N1.
10.10.2 Application
The D12B is a PDH interface board. The D12B can be used on the OptiX OSN equipment series
to transmit and receive signals for the PDH processing board. To access and process signals, the
interface board must be used with its corresponding processing board.
10.10.3 Functions and Features
The D12B receives and transmits 32xE1/T1 electrical signals. The D12B must work with the
PQ1, or PQM.
10.10.4 Working Principle and Signal Flow
The D12B has the interface module.
10.10.5 Front Panel
The front panel of the D12B has interfaces and a bar code.
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10.10.6 Valid Slots
The D12B can work as the interface board of the PQ1, or PQM.
10.10.7 Technical Specifications
The technical specifications of the D12B include the parameters specified for the electrical
interfaces, mechanical specifications and power consumption.
10.10.1 Version Description
The D12B is available in one functional version, namely, N1.
10.10.2 Application
The D12B is a PDH interface board. The D12B can be used on the OptiX OSN equipment series
to transmit and receive signals for the PDH processing board. To access and process signals, the
interface board must be used with its corresponding processing board.
10.10.3 Functions and Features
The D12B receives and transmits 32xE1/T1 electrical signals. The D12B must work with the
PQ1, or PQM.
10.10.4 Working Principle and Signal Flow
The D12B has the interface module.
Figure 10-50 shows the functional block diagram of the D12B by describing how to process
1xE1/T1 signals.
Figure 10-50 Functional block diagram of the D12B
E1/T1 electrical signal
PQ1/PQM/PO1
Backplane
Interface
module
PQ1/PQM/PO1
E1/T1 electrical signal

Interface Module
The interface module receives and transmits the E1/T1 electrical signals.
10.10.5 Front Panel
The front panel of the D12B has interfaces and a bar code.
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Diagram of the Front Panel
Figure 10-51 shows the appearance of the front panel of the D12B.
Figure 10-51 Front panel of the D12B
D12B
D12B
9
~
1
6
1
7
~
2
4
2
5
~
3
2
1
~
8

Interfaces
The front panel of the D12B has four DB44 interfaces. Table 10-35 describes the types and
usage of the interfaces of the D12B.
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Table 10-35 Interfaces of the D12B
Interface Type of
Interface
Usage
18 DB44 Receives the 1st to the 8th channels of E1/T1
signals.
916 DB44 Receives the 9th to the 16th channels of E1/T1
signals.
1724 DB44 Receives the 17th to the 24th channels of E1/T1
signals.
2532 DB44 Receives the 25th to the 32nd channels of E1/T1
signals.

Table 10-36 provides the pin assignments of the DB44 interface.
Table 10-36 Pin assignments of the DB44 interface
Front View Pin Usage Pin Usage
44
1
15
16
30
31
38 Receives the 1st
channel of signals
(R1).
34 Receives the 5th
channel of signals
(R5).
23 19
37 Receives the 2nd
channel of signals
(R2).
33 Receives the 6th
channel of signals
(R6).
22 18
36 Receives the 3rd
channel of signals
(R3).
32 Receives the 7th
channel of signals
(R7).
21 17
35 Receives the 4th
channel of signals
(R4).
31 Receives the 8th
channel of signals
(R8).
20 16
15 Transmits the 1st
channel of signals
(T1).
11 Transmits the 5th
channel of signals
(T5).
30 26
14 Transmits the 2nd
channel of signals
(T2).
10 Transmits the 6th
channel of signals
(T6).
29 25
13 Transmits the 3rd
channel of signals
(T3).
9 Transmits the 7th
channel of signals
(T7).
28 24
12 Transmits the 4th
channel of signals
(T4).
8 Transmits the 8th
channel of signals
(T8).
27 7

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10.10.6 Valid Slots
The D12B can work as the interface board of the PQ1, or PQM.
The D12B can be installed in slots 1926 and 2936 in the main subrack.
Table 10-37 lists the slots valid for the PQ1/PQM and the corresponding slots for the D12B.
The D12B installed in the slot with a smaller number accesses the 1st to the 32nd channels of
E1/T1 electrical signals. The D12B installed in the slot with a larger number accesses the 33rd
to the 63rd channels of E1/T1 electrical signals.
Table 10-37 Slots valid for the PQ1/PQM and the corresponding slots for the D12B
Slot Valid for the PQ1/PQM Corresponding Slot for the D12B
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

10.10.7 Technical Specifications
The technical specifications of the D12B include the parameters specified for the electrical
interfaces, mechanical specifications and power consumption.
Parameters Specified for Electrical Interfaces
Table 10-38 Parameters specified for the electrical interfaces of the D12B
Parameter Value
Type of electrical
interface
1544 kbit/s 2048 kbit/s
Line code pattern B8ZS and
AMI
HDB3
Signal bit rate at the
output interface
Complies with ITU-T G.703.
Allowed frequency
deviation at the
input interface
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Parameter Value
Allowed attenuation
at the input interface
Input jitter tolerance

Mechanical Specifications
The mechanical specifications of the D12B are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.3
Power Consumption
The maximum power consumption of the D12B at room temperature (25C) is 0 W.
10.11 D12S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D12S (32xE1/T1 switching access board).
10.11.1 Version Description
The D12S is available in one functional version, namely, N1.
10.11.2 Application
The D12S is a PDH interface switching board. The D12S can be used on the OptiX OSN
equipment series to transmit and receive signals for the PDH processing board. In addition, when
the corresponding PDH processing board is configured with the TPS protection, the interface
switching board is required to perform the TPS protection.
10.11.3 Functions and Features
The D12S receives and transmits 32xE1/T1 electrical signals. The D12S must work with the
PQ1, or PQM.
10.11.4 Working Principle and Signal Flow
The D12S consists of the interface module, switch matrix module, and power access circuit.
10.11.5 Front Panel
The front panel of the D12S has interfaces and a bar code.
10.11.6 Valid Slots
The D12S can be installed in slots 1926 and 2936 in the main subrack. The D12S works as
the interface board of the PQ1, or PQM.
10.11.7 Technical Specifications
The technical specifications of the D12S include the parameters specified for the electrical
interfaces, mechanical specifications and power consumption.
10.11.1 Version Description
The D12S is available in one functional version, namely, N1.
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10.11.2 Application
The D12S is a PDH interface switching board. The D12S can be used on the OptiX OSN
equipment series to transmit and receive signals for the PDH processing board. In addition, when
the corresponding PDH processing board is configured with the TPS protection, the interface
switching board is required to perform the TPS protection.
10.11.3 Functions and Features
The D12S receives and transmits 32xE1/T1 electrical signals. The D12S must work with the
PQ1, or PQM.
10.11.4 Working Principle and Signal Flow
The D12S consists of the interface module, switch matrix module, and power access circuit.
Figure 10-52 shows the functional block diagram of the D12S by describing how to process
1xE1/T1 signals.
Figure 10-52 Functional block diagram of the D12S
Switch
matrix
module
E1/T1 electrical
signal
PQ1/PQM
Backplane
Interface
module
Cross-connect board
E1/T1 electrical
signal
PQ1/PQM
+3.3 V power
+3.3 V Fuse

Interface Module
The interface module receives and transmits the E1/T1 electrical signals.
Switch Matrix Module
In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the PQ1 or PQM. When the TPS is performed, the switch matrix
module transmits the signal to the protection board for bridging.
In the transmit direction, the switch matrix module performs the reverse process.
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Power Access Circuit
The power access circuit provides all the modules of the D12S with the required DC voltages.
10.11.5 Front Panel
The front panel of the D12S has interfaces and a bar code.
Diagram of the Front Panel
Figure 10-53 shows the appearance of the front panel of the D12S.
Figure 10-53 Front panel of the D12S
D12S
D12S
9
~
1
6
1
7
~
2
4
2
5
~
3
2
1
~
8

Interfaces
The front panel of the D12S has four DB44 interfaces. Table 10-39 describes the types and
usage of the interfaces of the D12S.
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Table 10-39 Interfaces of the D12S
Interface Type of
Interface
Usage
18 DB44 Receives the 1st to the 8th channels of E1/T1
signals.
916 DB44 Receives the 9th to the 16th channels of E1/T1
signals.
1724 DB44 Receives the 17th to the 24th channels of E1/T1
signals.
2532 DB44 Receives the 25th to the 32nd channels of E1/T1
signals.

Table 10-40 provides the pin assignments of the DB44 interface.
Table 10-40 Pin assignments of the DB44 interface
Front View Pin Usage Pin Usage
44
1
15
16
30
31
38 Receives the 1st
channel of signals
(R1).
34 Receives the 5th
channel of signals
(R5).
23 19
37 Receives the 2nd
channel of signals
(R2).
33 Receives the 6th
channel of signals
(R6).
22 18
36 Receives the 3rd
channel of signals
(R3).
32 Receives the 7th
channel of signals
(R7).
21 17
35 Receives the 4th
channel of signals
(R4).
31 Receives the 8th
channel of signals
(R8).
20 16
15 Transmits the 1st
channel of signals
(T1).
11 Transmits the 5th
channel of signals
(T5).
30 26
14 Transmits the 2nd
channel of signals
(T2).
10 Transmits the 6th
channel of signals
(T6).
29 25
13 Transmits the 3rd
channel of signals
(T3).
9 Transmits the 7th
channel of signals
(T7).
28 24
12 Transmits the 4th
channel of signals
(T4).
8 Transmits the 8th
channel of signals
(T8).
27 7

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10.11.6 Valid Slots
The D12S can be installed in slots 1926 and 2936 in the main subrack. The D12S works as
the interface board of the PQ1, or PQM.
Table 10-41 lists the slots valid for the PQ1/PQM and the corresponding slots for the D12S.
The D12S installed in the slot with a smaller number accesses the 1st to the 32nd channels of
E1/T1 electrical signals. The D12S installed in the slot with a larger number accesses the 33rd
to the 63rd channels of E1/T1 electrical signals.
Table 10-41 Slots valid for the PQ1/PQM and the corresponding slots for the D12S
Slot Valid for the PQ1/PQM Corresponding Slot for the D12S
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

10.11.7 Technical Specifications
The technical specifications of the D12S include the parameters specified for the electrical
interfaces, mechanical specifications and power consumption.
Parameters Specified for Electrical Interfaces
Table 10-42 Parameters specified for the electrical interfaces of the D12S
Parameter Value
Type of electrical
interface
1544 kbit/s 2048 kbit/s
Line code pattern B8ZS and
AMI
HDB3
Signal bit rate at the
output interface
Complies with ITU-T G.703.
Allowed frequency
deviation at the
input interface
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Parameter Value
Allowed attenuation
at the input interface
Input jitter tolerance

Mechanical Specifications
The mechanical specifications of the D12S are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
At room temperature (25C), the maximum power consumption of the D12S is 0 W.
10.12 D75S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D75S (32xE1 switching access board).
10.12.1 Version Description
The D75S is available in one functional version, namely, N1.
10.12.2 Application
The D75S is a PDH interface switching board. The D75S can be used on the OptiX OSN
equipment series to transmit and receive signals for the PDH processing board. In addition, when
the corresponding PDH processing board is configured with the TPS protection, the interface
switching board is required to perform the TPS protection.
10.12.3 Functions and Features
The D75S receives and transmits 32xE1 electrical signals. The D75S must work with the PQ1.
10.12.4 Working Principle and Signal Flow
The D75S consists of the interface module, switch matrix module, and power access circuit.
10.12.5 Front Panel
The front panel of the D75S has interfaces and a bar code.
10.12.6 Valid Slots
The D75S can work as the interface board of the PQ1.
10.12.7 Technical Specifications
The technical specifications of the D75S include the parameters specified for the electrical
interfaces, mechanical specifications and power consumption.
10.12.1 Version Description
The D75S is available in one functional version, namely, N1.
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10.12.2 Application
The D75S is a PDH interface switching board. The D75S can be used on the OptiX OSN
equipment series to transmit and receive signals for the PDH processing board. In addition, when
the corresponding PDH processing board is configured with the TPS protection, the interface
switching board is required to perform the TPS protection.
10.12.3 Functions and Features
The D75S receives and transmits 32xE1 electrical signals. The D75S must work with the PQ1.
10.12.4 Working Principle and Signal Flow
The D75S consists of the interface module, switch matrix module, and power access circuit.
Figure 10-54 shows the functional block diagram of the D75S by describing how to process
1xE1 signals.
Figure 10-54 Functional block diagram of the D75S
Switch
matrix
module
E1 electrical signal
Backplane
Interface
module
Cross-connect board
PQ1
E1 electrical signal PQ1
+3.3 V power
+3.3 V Fuse

Interface Module
The interface module receives and transmits the E1 electrical signals.
Switch Matrix Module
In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the PQ1. When the TPS is performed, the switch matrix module
transmits the signal to the protection board for bridging.
In the transmit direction, the switch matrix module performs the reverse process.
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Power Access Circuit
The power access circuit provides all the modules of the D75S with the required DC voltages.
10.12.5 Front Panel
The front panel of the D75S has interfaces and a bar code.
Diagram of the Front Panel
Figure 10-55 shows the appearance of the front panel of the D75S.
Figure 10-55 Front panel of the D75S
D75S
D75S
9
~
1
6
1
7
~
2
4
2
5
~
3
2
1
~
8

Interfaces
The front panel of the D75S has four DB44 interfaces. Table 10-43 describes the types and
usage of the interfaces of the D75S.
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Table 10-43 Interfaces of the D75S
Interface Type of
Interface
Usage
18 DB44 Receives the 1st to the 8th channels of E1 signals.
916 DB44 Receives the 9th to the 16th channels of E1
signals.
1724 DB44 Receives the 17th to the 24th channels of E1
signals.
2532 DB44 Receives the 25th to the 32nd channels of E1
signals.

Table 10-44 provides the pin assignments of the DB44 interface.
Table 10-44 Pin assignments of the DB44 interface
Front View Pin Usage Pin Usage
44
1
15
16
30
31
38 Receives the 1st
channel of signals
(R1).
34 Receives the 5th
channel of signals
(R5).
23 19
37 Receives the 2nd
channel of signals
(R2).
33 Receives the 6th
channel of signals
(R6).
22 18
36 Receives the 3rd
channel of signals
(R3).
32 Receives the 7th
channel of signals
(R7).
21 17
35 Receives the 4th
channel of signals
(R4).
31 Receives the 8th
channel of signals
(R8).
20 16
15 Transmits the 1st
channel of signals
(T1).
11 Transmits the 5th
channel of signals
(T5).
30 26
14 Transmits the 2nd
channel of signals
(T2).
10 Transmits the 6th
channel of signals
(T6).
29 25
13 Transmits the 3rd
channel of signals
(T3).
9 Transmits the 7th
channel of signals
(T7).
28 24
12 Transmits the 4th
channel of signals
(T4).
8 Transmits the 8th
channel of signals
(T8).
27 7

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10.12.6 Valid Slots
The D75S can work as the interface board of the PQ1.
The D75S can be installed in slots 1926 and 2936 in the main subrack.
Table 10-45 lists the slots valid for the PQ1 and the corresponding slots for the D75S. The D75S
installed in the slot with a smaller number accesses the 1st to the 32nd channels of E1 electrical
signals. The D75S installed in the slot with a larger number accesses the 33rd to the 63rd channels
of E1 electrical signals.
Table 10-45 Slots valid for the PQ1 and the corresponding slots for the D75S
Slot Valid for the PQ1 Corresponding Slot for the D75S
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

10.12.7 Technical Specifications
The technical specifications of the D75S include the parameters specified for the electrical
interfaces, mechanical specifications and power consumption.
Parameters Specified for Electrical Interfaces
Table 10-46 Parameters specified for the electrical interfaces of the D75S
Parameter Value
Type of electrical
interface
2048 kbit/s
Line code pattern HDB3
Signal bit rate at the
output interface
Complies with ITU-T G.703.
Allowed frequency
deviation at the
input interface
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Parameter Value
Allowed attenuation
at the input interface
Input jitter tolerance

Mechanical Specifications
The mechanical specifications of the D75S are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
At room temperature (25C), the maximum power consumption of the D75S is 0 W.
10.13 D34S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the D34S (6xE3/T3 switching access board).
10.13.1 Version Description
The D34S is available in one functional version, namely, N1.
10.13.2 Application
The D34S is a PDH interface switching board. The D34S can be used on the OptiX OSN
equipment series to transmit and receive signals for the PDH processing board. In addition, when
the corresponding PDH processing board is configured with the TPS protection, the interface
switching board is required to perform the TPS protection.
10.13.3 Functions and Features
The D34S receives and transmits 6xE3/T3 electrical signals. The D34S must work with the PD3
or PQ3.
10.13.4 Working Principle and Signal Flow
The D34S consists of the interface module, switch matrix module, and power access circuit.
10.13.5 Front Panel
The front panel of the D34S has interfaces and a bar code.
10.13.6 Valid Slots
The D34S can be installed in slots 1926 and 2936 in the subrack.
10.13.7 Technical Specifications
The technical specifications of the D34S include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
10.13.1 Version Description
The D34S is available in one functional version, namely, N1.
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10.13.2 Application
The D34S is a PDH interface switching board. The D34S can be used on the OptiX OSN
equipment series to transmit and receive signals for the PDH processing board. In addition, when
the corresponding PDH processing board is configured with the TPS protection, the interface
switching board is required to perform the TPS protection.
10.13.3 Functions and Features
The D34S receives and transmits 6xE3/T3 electrical signals. The D34S must work with the PD3
or PQ3.
10.13.4 Working Principle and Signal Flow
The D34S consists of the interface module, switch matrix module, and power access circuit.
Figure 10-56 shows the functional block diagram of the D34S by describing how to process
1xE3/T3 signals.
Figure 10-56 Functional block diagram of the D34S
E3/T3 electrical
signal
PD3/PQ3
PD3/PQ3
TSB8
TSB8
Interface
module
Switch
matrix
module
Backplane
Cross-connect board
E3/T3 electrical
signal
+3.3 V power
+3.3 V Fuse

Interface Module
The interface module receives and transmits the E3/T3 electrical signals.
Switch Matrix Module
In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the PD3 or PQ3. When the TPS is performed, the switch matrix
module transmits the signal to the TSB8 for bridging.
In the transmit direction, the switch matrix module performs the reverse process.
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Power Access Circuit
The power access circuit provides all the modules of the D34S with the required DC voltages.
10.13.5 Front Panel
The front panel of the D34S has interfaces and a bar code.
Diagram of the Front Panel
Figure 10-57 shows the appearance of the front panel of the D34S.
Figure 10-57 Front panel of the D34S
D34S
D34S
I
N
6
O
U
T
6
I
N
5
O
U
T
5
I
N
4
O
U
T
4
I
N
3
O
U
T
3
I
N
2
O
U
T
2
I
N
1
O
U
T
1

Interfaces
The front panel of the D34S has six pairs of electrical interfaces.
Table 10-47 describes the types and usage of the interfaces of the D34S.
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Table 10-47 Interfaces of the D34S
Interface Type of
Interface
Usage
IN1IN6 SMB Receives the 1st to the 6th channels of E3/T3
electrical signals.
OUT1OUT6 SMB Transmits the 1st to the 6th channels of E3/T3
electrical signals.

10.13.6 Valid Slots
The D34S can be installed in slots 1926 and 2936 in the subrack.
10.13.7 Technical Specifications
The technical specifications of the D34S include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
Table 10-48 lists the parameters specified for the electrical interfaces of the D34S.
Table 10-48 Parameters specified for the electrical interfaces of the D34S
Parameter Value
Nominal bit rate 34368 kbit/s and 44736 kbit/s
Line code pattern HDB3 (E3) and B3ZS (T3)
Signal bit rate at the output interface Complies with ITU-T G.703.
Allowed frequency deviation at the input
interface
Allowed attenuation at the input
interface
Input jitter tolerance

Mechanical Specifications
The mechanical specifications of the D34S are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
At room temperature (25C), the maximum power consumption of the D34S is 0 W.
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10.14 C34S
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the C34S (3xE3/T3 switching access board).
10.14.1 Version Description
The C34S is available in one functional version, namely, N1.
10.14.2 Application
The C34S is a PDH interface switching board. The C34S can be used on the OptiX OSN
equipment series to transmit and receive signals for the PDH processing board. In addition, when
the corresponding PDH processing board is configured with the TPS protection, the interface
switching board is required to perform the TPS protection.
10.14.3 Functions and Features
The C34S receives and transmits 3xE3/T3 electrical signals. The C34S must work with the PL3.
10.14.4 Working Principle and Signal Flow
The C34S consists of the interface module, switch matrix module, and power access circuit.
10.14.5 Front Panel
The front panel of the C34S has interfaces and a bar code.
10.14.6 Valid Slots
The C34S can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the main subrack.
10.14.7 Technical Specifications
The technical specifications of the C34S include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
10.14.1 Version Description
The C34S is available in one functional version, namely, N1.
10.14.2 Application
The C34S is a PDH interface switching board. The C34S can be used on the OptiX OSN
equipment series to transmit and receive signals for the PDH processing board. In addition, when
the corresponding PDH processing board is configured with the TPS protection, the interface
switching board is required to perform the TPS protection.
10.14.3 Functions and Features
The C34S receives and transmits 3xE3/T3 electrical signals. The C34S must work with the PL3.
10.14.4 Working Principle and Signal Flow
The C34S consists of the interface module, switch matrix module, and power access circuit.
Figure 10-58 shows the functional block diagram of the C34S by describing how to process
1xE3/T3 signals.
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Figure 10-58 Functional block diagram of the C34S
Switch
matrix
module
E3/T3 electrical
signal
PL3
Backplane
Interface
module
PL3
TSB4/TSB8
TSB4/TSB8
Cross-connect board
E3/T3 electrical
signal
+3.3 V power
+3.3 V Fuse

Interface Module
The interface module receives and transmits the E3/T3 electrical signals.
Switch Matrix Module
In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the PL3. When the TPS is performed, the switch matrix module
transmits the signal to the TSB4 or TSB8 for bridging.
In the transmit direction, the switch matrix module performs the reverse process.
Power Access Circuit
The power access circuit provides all the modules of the C34S with the required DC voltages.
10.14.5 Front Panel
The front panel of the C34S has interfaces and a bar code.
Diagram of the Front Panel
Figure 10-59 shows the appearance of the front panel of the C34S.
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Figure 10-59 Front panel of the C34S
C34S
C34S
I
N
3
O
U
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3
I
N
2
O
U
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2
I
N
1
O
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T
1

Interfaces
The front panel of the C34S has three pairs of electrical interfaces.
Table 10-49 describes the type and usage of the interface of the C34S.
Table 10-49 Interfaces of the C34S
Interface Type of Interface Usage
IN1IN3 SMB Receives the 1st to the 3rd channels of E3/T3
electrical signals.
OUT1OUT3 SMB Transmits the 1st to the 3rd channels of E3/T3
electrical signals.

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10.14.6 Valid Slots
The C34S can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the main subrack.
Table 10-50 lists the slots valid for the PL3 and the corresponding slots for the C34S.
Table 10-50 Slots valid for the PL3 and the corresponding slots for the C34S
Slot Valid for the PL3 Corresponding Slot for the C34S
Slot 2 Slot 19
Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33
Slot 16 Slot 35

10.14.7 Technical Specifications
The technical specifications of the C34S include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
Table 10-51 lists the parameters specified for the electrical interfaces of the C34S.
Table 10-51 Parameters specified for the electrical interfaces of the C34S
Parameter Value
Nominal bit rate 34368 kbit/s and 44736 kbit/s
Line code pattern HDB3 (E3) and B3ZS (T3)
Signal bit rate at the output
interface
Complies with ITU-T G.703.
Allowed frequency
deviation at the input
interface
Allowed attenuation at the
input interface
Input jitter tolerance

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Mechanical Specifications
The mechanical specifications of the C34S are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.3
Power Consumption
At room temperature (25C), the maximum power consumption of the C34S is 0 W.
10.15 MU04
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the MU04 (4xE4/STM-1 electrical interface board).
10.15.1 Version Description
The MU04 is available in one functional version, namely, N1.
10.15.2 Application
The MU04 is an E4/STM-1 electrical interface board. The MU04 can be used on the OptiX OSN
equipment series to transmit and receive signals for the E4/STM-1 electrical processing board.
10.15.3 Functions and Features
The MU04 receives and transmits 4xE4/STM-1 electrical signals. The MU04 must work with
the SPQ4.
10.15.4 Working Principle and Signal Flow
The MU04 consists of the interface module, switch matrix module, and power module.
10.15.5 Front Panel
The front panel of the MU04 has interfaces and a bar code.
10.15.6 Valid Slots
The MU04 can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the subrack and works
as the interface board of the SPQ4.
10.15.7 Technical Specifications
The technical specifications of the MU04 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
10.15.1 Version Description
The MU04 is available in one functional version, namely, N1.
10.15.2 Application
The MU04 is an E4/STM-1 electrical interface board. The MU04 can be used on the OptiX OSN
equipment series to transmit and receive signals for the E4/STM-1 electrical processing board.
10.15.3 Functions and Features
The MU04 receives and transmits 4xE4/STM-1 electrical signals. The MU04 must work with
the SPQ4.
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10.15.4 Working Principle and Signal Flow
The MU04 consists of the interface module, switch matrix module, and power module.
Figure 10-60 shows the functional block diagram of the MU04 by describing how to process
1xE4/STM-1 signals.
Figure 10-60 Functional block diagram of the MU04
+3.3 V power
+3.3 V
TSB4/TSB8
Cross-connect board
Backplane
Power
module
Switch
matrix
module
E4/STM-1 electrical
signal SPQ4
TSB4/TSB8
Fuse
SPQ4
E4/STM-1 electrical
signal
Interface
module

Interface Module
The interface module receives and transmits the E4/STM-1 electrical signals.
Switch Matrix Module
In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the SPQ4. When the TPS is performed, the switch matrix module
transmits the signal to the TSB4 or TSB8 for bridging.
In the transmit direction, the switch matrix module performs the reverse process.
Power Module
The power module provides all the modules of the MU04 with the required DC voltages.
10.15.5 Front Panel
The front panel of the MU04 has interfaces and a bar code.
Diagram of the Front Panel
Figure 10-61 shows the appearance of the front panel of the MU04.
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Figure 10-61 Front panel of the MU04
MUO4
MUO4
I
N
4
O
U
T
4
I
N
3
O
U
T
3
I
N
2
O
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T
2
I
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1
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1

Interfaces
The front panel of the MU04 has four pairs of electrical interfaces.
Table 10-52 describes the types and usage of the interfaces of the MU04.
Table 10-52 Interfaces of the MU04
Interface Type of
Interface
Usage
IN1IN4 SMB Receives the 1st to the 4th channels of E4/STM-1
electrical signals.
OUT1OUT4 SMB Transmits the 1st to the 4th channels of E4/STM-1
electrical signals.

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10.15.6 Valid Slots
The MU04 can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the subrack and works
as the interface board of the SPQ4.
Table 10-53 lists the slots valid for the SPQ4 and the corresponding slots for the MU04.
Table 10-53 Slots valid for the SPQ4 and the corresponding slots for the MU04
Slot Valid for the SPQ4 Corresponding Slot for the MU04
Slot 2 Slot 19
Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33
Slot 16 Slot 35

10.15.7 Technical Specifications
The technical specifications of the MU04 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
Table 10-54 lists the parameters specified for the electrical interfaces of the MU04.
Table 10-54 Parameters specified for the electrical interfaces of the MU04
Parameter Value
Nominal bit rate 139264 kbit/s and 155520 kbit/s
Line code pattern CMI
Signal bit rate at the output
interface
Complies with ITU-T G.703.
Allowed frequency
deviation at the input
interface
Allowed attenuation at the
input interface

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Mechanical Specifications
The mechanical specifications of the MU04 are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
The maximum power consumption of the MU04 at room temperature (25C) is 2 W.
10.16 DM12
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the DM12 (DDN service interface board).
10.16.1 Version Description
The DM12 is available in one functional version, namely, N1.
10.16.2 Application
The DM12 is a DDN service interface board. The DM12 can be used on the OptiX OSN
equipment series to transmit and receive electrical signals of the DDN service.
10.16.3 Functions and Features
The DM12 receives and transmits four channels of Nx64 kbit/s signals and eight channels of
framed E1 electrical signals. The DM12 must work with the DX1.
10.16.4 Working Principle and Signal Flow
The DM12 consists of the interface module, switch matrix module, and power module.
10.16.5 Front Panel
The front panel of the DM12 has interfaces and a bar code.
10.16.6 Valid Slots
The DM12 can be installed in slots 1926 and 2936 in the subrack and works as the interface
board of the DX1.
10.16.7 Technical Specifications
The technical specifications of the DM12 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
10.16.1 Version Description
The DM12 is available in one functional version, namely, N1.
10.16.2 Application
The DM12 is a DDN service interface board. The DM12 can be used on the OptiX OSN
equipment series to transmit and receive electrical signals of the DDN service.
10.16.3 Functions and Features
The DM12 receives and transmits four channels of Nx64 kbit/s signals and eight channels of
framed E1 electrical signals. The DM12 must work with the DX1.
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10.16.4 Working Principle and Signal Flow
The DM12 consists of the interface module, switch matrix module, and power module.
Figure 10-62 shows the functional block diagram of the DM12 by describing how to process
one channel of Nx64 kbit/s or framed E1 electrical signals.
Figure 10-62 Functional block diagram of the DM12
DX1
+3.3 V backup power
+3.3 V Fuse
DX1
Nx64 kbit/s/
Framed E1
electrical signal Interface
module
Switch
matrix
module
Cross-connect board
Backplane
Power
module
Nx64 kbit/s/
Framed E1
electrical signal

Interface Module
The interface module receives and transmits the Nx64 kbit/s or framed E1 electrical signals.
Switch Matrix Module
In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the DX1. When the TPS is performed, the switch matrix module
transmits the signal to the protection DX1 for bridging.
In the transmit direction, the switch matrix module performs the reverse process.
Power Module
The power module provides all the modules of the DM12 with the required DC voltages.
10.16.5 Front Panel
The front panel of the DM12 has interfaces and a bar code.
Diagram of the Front Panel
Figure 10-63 shows the appearance of the front panel of the DM12.
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Figure 10-63 Front panel of the DM12
DM12
DM12
E
1
(
1
-
8
)
D
D
N
1
D
D
N
2
D
D
N
3
D
D
N
4

Interfaces
The front panel of the DM12 has DB44 and DB28 interfaces. Table 10-55 describes the types
and usage of the interfaces of the DM12.
Table 10-55 Interfaces of the DM12
Interface Type of
Interface
Usage
E1 (18) DB44 Accesses eight channels of framed E1 signals.
DDN1DDN4 DB28 Accesses the 1st to the 4th channels of Nx64
kbit/s signals.

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Table 10-56 provides the pin assignments of the DB44 interface.
Table 10-56 Pin assignments of the DB44 interface
Front View Pin Usage Pin Usage
44
1
15
16
30
31

30 Transmits the
1st channel of
signals (T1).
8 Transmits the 8th
channel of signals
(T8).
15 7
29 Transmits the
2nd channel of
signals (T2).
36 Receives the 3rd
channel of signals
(R3).
14 21
28 Transmits the
3rd channel of
signals (T3).
35 Receives the 4th
channel of signals
(R4).
13 20
27 Transmits the
4th channel of
signals (T4).
34 Receives the 5th
channel of signals
(R5).
12 19
26 Transmits the
5th channel of
signals (T5).
33 Receives the 6th
channel of signals
(R6).
11 18
25 Transmits the
6th channel of
signals (T6).
32 Receives the 7th
channel of signals
(R7).
10 17
24 Transmits the
7th channel of
signals (T7).
31 Receives the 8th
channel of signals
(R8).
9 16
38 Receives the 1st
channel of
signals (R1).
4439 and
61
Grounding
23
37 Receives the
2nd channel of
signals (R2).
22

Table 10-57 provides the pin assignments of the DB28 interface.
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Table 10-57 Pin assignments of the DB28 interface
Front View Pin Usage Pin Usage
28
1

1 Transmits data
signals.
19 Receives data
signals.
2 20
3 Transmits
clock signals.
21 Grounding
4 22 Receives the
loopback control
signal.
11 Detects the
carrier.
23 Permits the
transmission.
12 24
13 Requests for
transmission.
25 Receives the DCE
ready signal.
14 26
15 Receives the
clock to be
used in the
transmit
direction from
the external
equipment.
27 Transmits the DTE
ready signal.
16 28
17 Receives clock
signals.
- -
18

10.16.6 Valid Slots
The DM12 can be installed in slots 1926 and 2936 in the subrack and works as the interface
board of the DX1.
Table 10-58 lists the slots valid for the DX1 and the corresponding slots for the DM12. The
DM12 installed in the slot with a smaller number accesses eight channels of framed E1 signals
and four channels of Nx64 kbit/s signals. The DM12 installed in the slot with a larger number
accesses only four channels of Nx64 kbit/s signals.
Table 10-58 Slots valid for the DX1 and the corresponding slots for the DM12
Slot Valid for the DX1 Corresponding Slot for the DM12
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
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Slot Valid for the DX1 Corresponding Slot for the DM12
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

10.16.7 Technical Specifications
The technical specifications of the DM12 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
Table 10-59 lists the parameters specified for the electrical interfaces of the DM12.
Table 10-59 Parameters specified for the electrical interfaces of the DM12
Interface Type Description of the Interface Specification of the Interface
Framed E1
interface (DB44)
Framed E1 signals The physical and electrical
characteristics of the interface
comply with ITU-T G.703. The
frame structure of the interface
complies with ITU-T G.704.
NX64 kbit/s
interface (DB28)
V.35 interface Complies with ITU-T V.35.
V.24 interface Complies with ITU-T V.24.
X.21 interface Complies with ITU-T X.21.
RS-449 interface Complies with EIA RS-449
(RS-423A and RS-422A).
RS-530 interface Complies with EIA RS-530.
RS-530A interface Complies with EIA RS-530A.

Mechanical Specifications
The mechanical specifications of the DM12 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
At room temperature (25C), the maximum power consumption of the DM12 is 0 W.
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10.17 TSB4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TSB4 (4-channel electrical interface protection switching board).
10.17.1 Version Description
The TSB4 is available in one functional version, namely, N1.
10.17.2 Application
The TSB4 is a PDH electrical interface protection switching board. The TSB4 can be used on
the OptiX OSN equipment series to realize the TPS protection on the PDH board.
10.17.3 Functions and Features
The TSB4 is used to provide the TPS protection.
10.17.4 Working Principle and Signal Flow
The TSB4 consists of the switch matrix module and power module.
10.17.5 Front Panel
The front panel of the TSB4 has a bar code.
10.17.6 Valid Slots
When the TSB4 works with different processing boards and interface boards to realize the TPS
protection, the TSB4 can be installed in different slots.
10.17.7 Technical Specifications
The technical specifications of the TSB4 include the mechanical specifications and power
consumption.
10.17.1 Version Description
The TSB4 is available in one functional version, namely, N1.
10.17.2 Application
The TSB4 is a PDH electrical interface protection switching board. The TSB4 can be used on
the OptiX OSN equipment series to realize the TPS protection on the PDH board.
10.17.3 Functions and Features
The TSB4 is used to provide the TPS protection.
The TSB4 can work with the MU04, C34S, or EU04 to realize the TPS protection on different
processing boards.
l The TSB4 can work with the MU04 to realize the TPS protection on the SPQ4.
l The TSB4 can work with the C34S to realize the TPS protection on the PL3.
l The TSB4 can work with the EU04 to realize the TPS protection on the SEP.
10.17.4 Working Principle and Signal Flow
The TSB4 consists of the switch matrix module and power module.
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Figure 10-64 shows the functional block diagram of the TSB4.
Figure 10-64 Functional block diagram of the TSB4
Standby processing board
Interface board 1
+3.3 V Fuse
Backplane
Backplane
Cross-connect board
+3.3 V backup power
Switch matrix
module
Power
module
Interface board 2
Interface board 3

Switch Matrix Module
In the receive direction, the switch matrix module selects signals from one of the three interface
boards according to the TPS protection control signal sent from the cross-connect board, and
transmits the signals to the standby processing board.
In the transmit direction, the switch matrix module performs the reverse process.
Power Module
The power module provides all the modules of the TSB4 with the required DC voltages.
10.17.5 Front Panel
The front panel of the TSB4 has a bar code.
Diagram of the Front Panel
Figure 10-65 shows the appearance of the front panel of the TSB4.
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Figure 10-65 Front panel of the TSB4
TSB4
TSB4

10.17.6 Valid Slots
When the TSB4 works with different processing boards and interface boards to realize the TPS
protection, the TSB4 can be installed in different slots.
The TSB4 can be installed in slots 19 and 35 in the main subrack.
Table 10-60 lists the slots valid for the TSB4 and the corresponding slots for the SPQ4 and
MU04.
Table 10-60 Slots valid for the TSB4 and the corresponding slots for the SPQ4 and MU04
Slot Valid for the TSB4 Slot Valid for the SPQ4 Corresponding Slot for the
MU04
Slot 19 Slot 3 Slot 21
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Slot Valid for the TSB4 Slot Valid for the SPQ4 Corresponding Slot for the
MU04
Slot 4 Slot 23
Slot 5 Slot 25
Slot 35 Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33

Table 10-61 lists the slots valid for the TSB4 and the corresponding slots for the SEP1 and
EU04.
Table 10-61 Slots valid for the TSB4 and the corresponding slots for the SEP1 and EU04
Slot Valid for the TSB4 Slot Valid for the SEP1 Corresponding Slot for
the EU04
Slot 19 Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 35 Slot 6 Slot 29
Slot 13 Slot 31
Slot 14 Slot 33

NOTE
The SEP1 is displayed as SEP or SEP1 on the T2000. When the interfaces are available on the front panel
of the SEP1, the SEP1 is displayed as SEP1 on the T2000. When the SEP1 works with the interface board
to realize the TPS protection, the SEP1 is displayed as SEP on the T2000.
Table 10-62 lists the slots valid for the TSB4 and the corresponding slots for the PL3 and C34S.
Table 10-62 Slots valid for the TSB4 and the corresponding slots for the PL3 and C34S
Slot Valid for the TSB4 Slot Valid for the PL3 Corresponding Slot for
the C34S
Slot 19 Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 35 Slot 13 Slot 29
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Slot Valid for the TSB4 Slot Valid for the PL3 Corresponding Slot for
the C34S
Slot 14 Slot 31
Slot 15 Slot 33

10.17.7 Technical Specifications
The technical specifications of the TSB4 include the mechanical specifications and power
consumption.
Mechanical Specifications
The mechanical specifications of the TSB4 are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.3
Power Consumption
The maximum power consumption of the TSB4 at room temperature (25C) is 3 W.
10.18 TSB8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TSB8 (8-channel electrical interface protection switching board).
10.18.1 Version Description
The TSB8 is available in one functional version, namely, N1.
10.18.2 Application
The TSB8 is a PDH electrical interface protection switching board. The TSB8 can be used on
the OptiX OSN equipment series to realize the TPS protection on the PDH board.
10.18.3 Functions and Features
The TSB8 is used to provide the TPS protection.
10.18.4 Working Principle and Signal Flow
The TSB8 consists of the switch matrix module and power module.
10.18.5 Front Panel
The front panel of the TSB8 has a bar code.
10.18.6 Valid Slots
The TSB8 can be installed in slots 19, 20, 35, and 36 in the main subrack.
10.18.7 Technical Specifications
The technical specifications of the TSB8 include the mechanical specifications and power
consumption.
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10.18.1 Version Description
The TSB8 is available in one functional version, namely, N1.
10.18.2 Application
The TSB8 is a PDH electrical interface protection switching board. The TSB8 can be used on
the OptiX OSN equipment series to realize the TPS protection on the PDH board.
10.18.3 Functions and Features
The TSB8 is used to provide the TPS protection.
The TSB8 can work with the MU04, C34S, D34S, EU04,, EU08, or ETS8 to realize the TPS
protection on different processing boards.
l The TSB8 can work with the MU04 to realize the TPS protection on the SPQ4.
l The TSB8 can work with the C34S to realize the TPS protection on the PL3.
l The TSB8 can work with the D34S to realize the TPS protection on the PD3.
l The TSB8 can work with the D34S to realize the TPS protection on the PQ3.
l The TSB8 can work with the EU04 to realize the TPS protection on the SEP1.
l The TSB8 can work with the EU08 to realize the TPS protection on the SLH1/SEP1.
l The TSB8 can work with the ETS8 to realize the TPS protection on the EFS0.
10.18.4 Working Principle and Signal Flow
The TSB8 consists of the switch matrix module and power module.
Figure 10-66 shows the functional block diagram of the TSB8 by describing how to process
one channel of signals.
Figure 10-66 Functional block diagram of the TSB8
Standby processing board
Interface board 1
+3.3 V Fuse
Backplane
Backplane
Cross-connect board
+3.3 V backup power
Switch matrix
module
Power
module
Interface board 2
Interface board 3

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Switch Matrix Module
In the receive direction, the switch matrix module selects signals from one of the three interface
boards according to the TPS protection control signal sent from the cross-connect board, and
transmits the signals to the standby processing board.
In the transmit direction, the switch matrix module performs the reverse process.
Power Module
The power module provides all the modules of the TSB8 with the required DC voltages.
10.18.5 Front Panel
The front panel of the TSB8 has a bar code.
Diagram of the Front Panel
Figure 10-67 shows the appearance of the front panel of the TSB8.
Figure 10-67 Front panel of the TSB8
TSB8
TSB8
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10.18.6 Valid Slots
The TSB8 can be installed in slots 19, 20, 35, and 36 in the main subrack.
Table 10-63 lists the slots valid for the TSB8 and the corresponding slots for the SPQ4 and
MU04.
Table 10-63 Slots valid for the TSB8 and the corresponding slots for the SPQ4 and MU04
Slot Valid for the TSB8 Slot Valid for the SPQ4 Corresponding Slot for the
MU04
Slot 19 Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 35 Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33

Table 10-64 lists the slots valid for the TSB8 and the corresponding slots for the PL3 and C34S.
Table 10-64 Slots valid for the TSB8 and the corresponding slots for the PL3 and C34S
Slot Valid for the TSB8 Slot Valid for the PL3 Corresponding Slot for
the C34S
Slot 19 Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 35 Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33

Table 10-65 lists the slots valid for the TSB8 and the corresponding slots for the PD3 and D34S.
Table 10-65 Slots valid for the TSB8 and the corresponding slots for the PD3 and D34S
Slot Valid for the TSB8 Slot Valid for the PD3 Corresponding Slot for
the D34S
Slot 19 Slot 3 Slot 21
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Slot Valid for the TSB8 Slot Valid for the PD3 Corresponding Slot for
the D34S
Slot 4 Slot 23
Slot 5 Slot 25
Slot 35 Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33

Table 10-66 lists the slots valid for the TSB8 and the corresponding slots for the PQ3 and D34S.
Table 10-66 Slots valid for the TSB8 and the corresponding slots for the PQ3 and D34S
Slot Valid for the TSB8 Slot Valid for the PQ3 Corresponding Slot for the
D34S
Slots 19 and 20 Slots 25 Slots 2126
Slots 35 and 36 Slots 1316 Slots 2934

Table 10-67 lists the slots valid for the TSB8 and the corresponding slots for the SEP1 and
EU04.
Table 10-67 Slots valid for the TSB8 and the corresponding slots for the SEP1 and EU04
Slot Valid for the TSB8 Slot Valid for the SEP1 Corresponding Slot for
the EU04
Slot 19 Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 35 Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33

Table 10-68 lists the slots valid for the TSB8 and the corresponding slots for the SEP1 and
EU08.
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Table 10-68 Slots valid for the TSB8 and the corresponding slots for the SEP1 and EU08
Slot Valid for the TSB8 Slot Valid for the SEP1 Corresponding Slot for
the EU08
Slot 19 Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 35 Slot 6 Slot 29
Slot 13 Slot 31
Slot 14 Slot 33

Table 10-69 lists the slots valid for the TSB8 and the corresponding slots for the SLH1 and
EU08.
Table 10-69 Slots valid for the TSB8 and the corresponding slots for the SLH1 and EU08
Slot Valid for the TSB8 Slot Valid for the SLH1 Corresponding Slot for
the EU08
Slot 19 and 20 Slot 3 Slot 21 and 22
Slot 4 Slot 23 and 24
Slot 5 Slot 25 and 26
Slot 35 and 36 Slot 6 Slot 29 and 30
Slot 13 Slot 31 and 32
Slot 14 Slot 33 and 34

NOTE
The SEP1 is displayed as SEP or SEP1 on the T2000. When the interfaces are available on the front panel
of the SEP1, the SEP1 is displayed as SEP1 on the T2000. When the SEP1 works with the interface board
to realize the TPS protection, the SEP1 is displayed as SEP on the T2000.
Table 10-70 lists the slots valid for the TSB8 and the corresponding slots for the EFS0 and
ETS8.
Table 10-70 Slots valid for the TSB8 and the corresponding slots for the EFS0 and ETS8
Slot Valid for the TSB8 Slot Valid for the EFS0 Corresponding Slot for
the ETS8
Slot 19 Slot 3 Slot 21
Slot 4 Slot 23
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Slot Valid for the TSB8 Slot Valid for the EFS0 Corresponding Slot for
the ETS8
Slot 5 Slot 25
Slot 35 Slot 6 Slot 29
Slot 13 Slot 31
Slot 14 Slot 33

10.18.7 Technical Specifications
The technical specifications of the TSB8 include the mechanical specifications and power
consumption.
Mechanical Specifications
The mechanical specifications of the TSB8 are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.3
Power Consumption
At room temperature (25C), the maximum power consumption of the TSB8 is 0 W.
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11 EoS Boards
About This Chapter
The EoS/EoP boards include the interface boards and processing boards for FE and GE services.
11.1 EFT8
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EFT8 (8xFE/16xFE transparent transmission board). This topic
also describes how to configure and commission the EFT8.
11.2 EFT8A
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EFT8A (8xFE transparent transmission board). This topic also
describes how to configure and commission the EFT8A.
11.3 EGT2
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EGT2 (2xGE transparent transmission board). This topic also
describes how to configure and commission the EGT2.
11.4 EFS0
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EFS0 (8xFE switching and processing board). This topic also
describes how to configure and commission the EFS0.
11.5 EFS0A
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EFS0A (16xFE switching and processing board). This topic also
describes how to configure and commission the EFS0A.
11.6 EFS4
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EFS4 (4xFE switching and processing board). This topic also
describes how to configure and commission the EFS4.
11.7 EGS2
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EGS2 (2xGE switching and processing board). This topic also
describes how to configure and commission the EGS2.
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11.8 EMS2
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EMS2 (2xGE and 16xFE switching and processing board). This
topic also describes how to configure and commission the EMS2.
11.9 EMS4
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EMS4 (4xGE and 16xFE switching and processing board). This
topic also describes how to configure and commission the EMS4.
11.10 EGS4
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EGS4 (4xGE switching and processing board). This topic also
describes how to configure and commission the EGS4.
11.11 EAS2
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EAS2 (2-port 10xGE Layer 2 switching and processing board).
This topic also describes how to configure and commission the EAS2.
11.12 EFF8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EFF8 (8x100M Ethernet optical interface board).
11.13 EFF8A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EFF8A (8x100M Ethernet optical interface board).
11.14 ETF8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ETF8 (8x100M Ethernet twisted pair interface board).
11.15 ETF8A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ETF8A (8x100M Ethernet twisted pair interface board).
11.16 ETS8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ETS8 (8x10/100M Ethernet twisted pair interface switching
board).
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11.1 EFT8
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EFT8 (8xFE/16xFE transparent transmission board). This topic
also describes how to configure and commission the EFT8.
11.1.1 Version Description
The EFT8 is available in one functional version, namely, N1.
11.1.2 Application
The EFT8 is used to access Ethernet services, manage bandwidths, and converge Ethernet
services.
11.1.3 Functions and Features
The EFT8 supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
11.1.4 Working Principle and Signal Flow
The EFT8 consists of the Ethernet access module, mapping module, interface converting
module, logic and control module, clock module, and power module.
11.1.5 Front Panel
The front panel of the EFT8 has indicators, interfaces, and a bar code.
11.1.6 Jumpers and DIP Switches
The EFT8 does not have any jumpers or DIP switches that are used for board settings.
11.1.7 Valid Slots
The EFT8 must be installed in a valid slot in the subrack. Otherwise, the EFT8 cannot work
normally.
11.1.8 Feature Code
The EFT8 does not have the feature code.
11.1.9 Parameter Settings
You can set parameters for the EFT8 by using the T2000.
11.1.10 Technical Specifications
The technical specifications of the EFT8 include the Ethernet performance specifications,
mechanical specifications, and power consumption.
11.1.1 Version Description
The EFT8 is available in one functional version, namely, N1.
11.1.2 Application
The EFT8 is used to access Ethernet services, manage bandwidths, and converge Ethernet
services.
Figure 11-1 shows the typical networking and application of the EFT8. The EFT8 realizes point-
to-point transparent transmission of Ethernet services. The EFT8 provides the following
functions by using the interfaces on the board: data receipt, data transmission, data mapping,
and traffic control. In addition, the EFT8 performs port-based point-to-point transparent
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transmission, encapsulation/decapsulation, overhead bytes and pointers processing, virtual
concatenation, SDH mapping/demapping, and LCAS function.
Figure 11-1 Networking and application of the EFT8
NE1
NE2 NE4
NE3
User A2
User B2
User B1
User A1
NMS
PORT 1
PORT 2
PORT 2
PORT 1
Service flow
Line board
Cross-connect and
timing board
Data board
MSP ring

11.1.3 Functions and Features
The EFT8 supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
Table 11-1 provides the functions and features of the EFT8.
Table 11-1 Functions and features of the EFT8
Function and
Feature
EFT8
Basic functions Transmits 8xFE or 16xFE services.
Functions when
being used with the
interface board
l Accesses 8 Ethernet signals through the electrical interface
independently.
l Accesses 16 Ethernet signals through the electrical interface when
the EFT8 is used with the ETF8.
l Accesses 8 Ethernet optical signals and 8 Ethernet electrical signals
when the EFT8 is used with the EFF8.
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Function and
Feature
EFT8
Specifications of the
optical interface
l Supports 10BASE-T/100BASE-TX signals when the EFT8 is used
with the ETF8.
l Supports 100BASE-FX/100BASE-TX signals when the EFT8 is
used with the EFF8. The optical interfaces comply with IEEE
802.3u.
Format of service
frames
l Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG formats.
l Ports 14 and 912 support the frame with a length ranging from
64 bytes to 1535 bytes. Ports 58 and 1316 support the frame with
a length ranging from 64 bytes to 9600 bytes. The board supports
the Jumbo frame with a length not more than 9600 bytes.
Maximum uplink
bandwidth
The maximum uplink bandwidth is 1.25 Gbit/s. The EFT8 can adapt
to the bandwidth of the slot.
VCTRUNKs Number of supported VCTRUNKs: 16
Configuration principles are as follows:
l A VCTRUNK can be bound with a maximum of three VC-3s or a
maximum of 63 VC-12s.
l A VCTRUNK can be bound with the VC-12 path or VC-3 path at
one time. A VCTRUNK should not be bound with VC-12 and VC-3
paths at the same time.
l Different VCTRUNKs can be bound with paths at different levels.
l VCTRUNK 1VCTRUNK 8 can be bound with VC-3s 112 or
VC-12s 163.
l VCTRUNK 9VCTRUNK 16 can be bound with VC-3s 1324 or
VC-12s 64126.
l A VCTRUNK cannot be bound with VC-12s numbered 163 and
VC-3s numbered 1012 at the same time. In addition, a VCTRUNK
cannot be bound with VC-12s numbered 64126 and VC-3s
numbered 2224 at the same time.
Mapping
granularities
Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X3)
granularities.
Encapsulation
format
Supports the HDLC, LAPS, and GFP-F protocols.
EPL services Supports the PORT-based transparent transmission.
MTU Supports the setting of the packet length, which ranges from 1518
bytes to 1535 bytes. After the setting becomes valid, the length of the
packets that enter or exit the IP ports is restricted by the pre-set MTU.
MPLS Does not support the MPLS.
VLAN Supports VLAN transparent transmission.
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Function and
Feature
EFT8
Link aggregation
function
Does not support the link aggregation function.
ETH-OAM function Does not support the ETH-OAM function.
QoS function Does not support the QoS function.
LCAS function Dynamically increases or decreases the bandwidth and protects the
bandwidth in compliance with ITU-T G.7042.
LPT function Supports the P2P LPT in GFP bearer mode.
Flow control
function
Supports the FE port-based flow control function that complies with
IEEE 802.3x.
High-precision time
(IEEE 1588 V2)
Does not support the high-precision time.
Test frames Receives and transmits GFP test frames.
Port mirroring Does not support the port mirroring function.
Loopback function l Supports inloops at the PHY layer on Ethernet ports.
l Supports inloops and outloops at the MAC layer on Ethernet ports.
l Supports inloops and outloops at the VC-3 level.
Protection schemes Supports the following protection schemes at the Ethernet network
level:
l LCAS
l LPT
Ethernet
performance
monitoring
Supports Ethernet performance monitoring at the port level.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.

11.1.4 Working Principle and Signal Flow
The EFT8 consists of the Ethernet access module, mapping module, interface converting
module, logic and control module, clock module, and power module.
Figure 11-2 shows the functional block diagram of the EFT8 by describing how to process 1xFE
signals.
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Figure 11-2 Functional block diagram of the EFT8
Ethernet
access
module
Logic and
control module
SCC unit
FE
Communication
Cross-connect unit
Reference clock and frame header
Clock module
77
MHz
155
MHz
LOS
Interface
converting
module
ENCP
DENCP
Mapping module
VCP
Laser
shutdown
-48 V/-60 V
+3.3 V backup power
+3.3 V
+3.3 V
-48 V/-60 V Power
module
Fuse
Fuse
125
Power
module
MHz
50
MHz
Backplane
Cross-connect unit
SCC unit
ENCP: data encapsulation module DENCP: decapsulation module
VCP: virtual concatenation processing module

Ethernet Access Module
In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, HDLC, or
GFP format. The concatenation is performed. Then, the Ethernet signals are converted into SDH
signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.
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Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l Manages and configures other modules of the board.
l Implements inter-board communication through the internal Ethernet interface.
The control module also contains basic logic units. This module performs the following
functions:
l Writes and reads the register.
l Provides interfaces for the CPU.
l Checks and selects the clock.
l Performs phase discrimination and frequency division on the clock.
l Checks the in-service state of the cross-connect, SCC, and line boards.
l Controls the shutting down of the optical module.
l Implements communication.
l Controls indicators.
Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
11.1.5 Front Panel
The front panel of the EFT8 has indicators, interfaces, and a bar code.
Diagram of the Front Panel
Figure 11-3 shows the appearance of the front panel of the EFT8.
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Figure 11-3 Front panel of the EFT8
EFT8
EFT8
ACT
PROG
STAT
SRV
FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Connection status indicator (LINK) one color (green)
l Data receiving and transmission indicator (ACT) one color (orange)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the EFT8 has eight FE interfaces. Table 11-2 describes the types and usage
of the interfaces of the EFT8.
Table 11-2 Interfaces of the EFT8
Interface Type of
Interface
Usage
FE1 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE2 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE3 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE4 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE5 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE6 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE7 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE8 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.

Table 11-3 describes the pins of the RJ-45 connector.
Table 11-3 Pins of the RJ-45 connector
Pin Description
1 Positive data transmit end
2 Negative data transmit end
3 Positive data receive end
4 Grounding
5 Grounding
6 Negative data receive end
7 Grounding
8 Grounding

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11.1.6 Jumpers and DIP Switches
The EFT8 does not have any jumpers or DIP switches that are used for board settings.
NOTE
The daughter board of the EFT4 has only one push-button switch, which is used for resetting the board.
When the EFT4 operates normally, do not push the switch. Otherwise, a cold reset is performed on the
board and the services may be lost.
11.1.7 Valid Slots
The EFT8 must be installed in a valid slot in the subrack. Otherwise, the EFT8 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the EFT8 vary with the cross-connect capacity of the subrack and whether
the EFT8 works with an interface board.
The slots valid for the EFT8 are as follows:
l When the EFT8 does not work with an interface board:
The EFT8 can be installed in slots 16 and 1316. In this case, the bandwidth is 622 Mbit/
s.
l When the EFT8 works with an interface board:
When the cross-connect capacity is 200 Gbit/s, the EFT8 can be installed in slots 25
and 1316. In this case, the bandwidth is 1.25 Gbit/s.
11.1.8 Feature Code
The EFT8 does not have the feature code.
11.1.9 Parameter Settings
You can set parameters for the EFT8 by using the T2000.
You can set the following main parameters for the EFT8 by using the T2000:
l Working mode
l LCAS
l Maximum frame length
l Mapping protocol
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
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11.1.10 Technical Specifications
The technical specifications of the EFT8 include the Ethernet performance specifications,
mechanical specifications, and power consumption.
Ethernet Performance Specifications
NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EFT8 board of the N1 version.
Figure 11-4 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, and latency specifications of the EFT8.
Figure 11-4 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, and latency specifications
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer
Port 1 Port 2
Port 1
Port 2

Figure 11-5 shows the connection for testing the back-to-back specifications of the EFT8.
Figure 11-5 Connection for testing the back-to-back specifications
Tested
equipment 1
Data network
performance
analyzer
Port 1 Port 2

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Table 11-4 lists the throughput specifications of the EFT8. Table 11-5 lists the packet loss ratio
in the case of overloading of the EFT8. Table 11-6 lists the latency specifications of the EFT8.
Table 11-7 lists the back-to-back specifications of the EFT8.
NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured and 63 VC-12s are bound on the FE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-4 lists the throughput specifications of the EFT8. The values are obtained when the
SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.
l The test duration is set to 60 seconds.
Table 11-4 Throughput specifications of the EFT8
Frame Size
(Byte)
Passed Rate
(%)
(01,01,01) to
(01,01,02) (pks/
sec)
(01,01,02) to
(01,01,01) (pks/
sec)
Total (pks/
sec)
64 100.00 148810 148810 297620
128 100.00 84459 84459 168918
256 100.00 45290 45290 90580
512 100.00 23496 23496 46992
1024 100.00 11973 11973 23946
1280 100.00 9615 9615 19230
1518 100.00 8127 8127 16254

Table 11-5 lists the packet loss ratio in the case of overloading of the EFT8. The values are
obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The tested traffic starts from the throughput and increases to 100% in 10% steps.
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l The test duration is set to 60 seconds.
Table 11-5 Packet loss ratio in the case of overloading of the EFT8
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) (%)
(01,01,02) to
(01,01,01) (%)
Average (%)
64 100.00 0.000 0.000 0.000
128 100.00 0.000 0.000 0.000
256 100.00 0.000 0.000 0.000
512 100.00 0.000 0.000 0.000
1024 100.00 0.000 0.000 0.000
1280 100.00 0.000 0.000 0.000
1518 100.00 0.000 0.000 0.000

Table 11-6 lists the latency specifications of the EFT8. The values are obtained when the
SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The test duration is set to 60 seconds.
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
Table 11-6 Latency specifications of the EFT8
Frame
Size
(Byte)
Rate
Tested
(%)
(01,01,01) to
(01,01,02) (us)-
CT (us)
Average
(CT) (us)
(01,01,01) to
(01,01,02)
(us)-S&F (us)
Average
(S&F) (us)
64 100.00 506.4 506.4 501.2 501.2
128 100.00 518.8 518.8 508.5 508.5
256 100.00 536.2 536.2 515.8 515.8
512 100.00 578.9 578.9 538.0 538.0
1024 100.00 653.4 653.4 571.4 571.4
1280 100.00 688.1 688.1 585.6 585.6
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Frame
Size
(Byte)
Rate
Tested
(%)
(01,01,01) to
(01,01,02) (us)-
CT (us)
Average
(CT) (us)
(01,01,01) to
(01,01,02)
(us)-S&F (us)
Average
(S&F) (us)
1518 100.00 720.6 720.6 599.1 599.1

Table 11-7 lists the back-to-back specifications of the EFT8. The values are obtained when the
SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 2 seconds, and the number of repetitions is set to
a value more than 50 on the Smart Application.
l The tested traffic is set to the wire speed.
l The test duration is set to 10 seconds.
Table 11-7 Back-to-back specifications of the EFT8
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) Burst
Size (Number of
Frames)
(01,01,02) to
(01,01,01)
(Number of
Frames)
Total
(Number of
Frames)
64 100.00 297620 297620 595240
128 100.00 168918 168918 337836
256 100.00 90580 90580 181160
512 100.00 46992 46992 93984
1024 100.00 23946 23946 47892
1280 100.00 19230 19230 38460
1518 100.00 16254 16254 32508

Mechanical Specifications
The mechanical specifications of the EFT8 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the EFT8 at room temperature (25C) is 26 W.
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11.2 EFT8A
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EFT8A (8xFE transparent transmission board). This topic also
describes how to configure and commission the EFT8A.
11.2.1 Version Description
The EFT8A is available in one functional version, namely, N1.
11.2.2 Application
The EFT8A is used to access Ethernet services, manage bandwidths, and converge Ethernet
services.
11.2.3 Functions and Features
The EFT8A supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
11.2.4 Working Principle and Signal Flow
The EFT8A consists of the Ethernet access module, mapping module, interface converting
module, logic and control module, clock module, and power module.
11.2.5 Front Panel
The front panel of the EFT8A has indicators, interfaces, and a bar code.
11.2.6 Jumpers and DIP Switches
The EFT8A does not have any jumpers or DIP switches that are used for board settings.
11.2.7 Valid Slots
The EFT8A must be installed in a valid slot in the subrack. Otherwise, the EFT8A cannot work
normally.
11.2.8 Feature Code
The EFT8A does not have the feature code.
11.2.9 Parameter Settings
You can set parameters for the EFT8A by using the T2000.
11.2.10 Technical Specifications
The technical specifications of the EFT8A include the Ethernet performance specifications,
mechanical specifications, and power consumption.
11.2.1 Version Description
The EFT8A is available in one functional version, namely, N1.
11.2.2 Application
The EFT8A is used to access Ethernet services, manage bandwidths, and converge Ethernet
services.
Figure 11-6 shows the typical networking and application of the EFT8A. The EFT8A realizes
point-to-point transparent transmission of Ethernet services. The EFT8A provides the following
functions by using the interfaces on the board: data receipt, data transmission, data mapping,
and traffic control. In addition, the EFT8A performs port-based point-to-point transparent
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transmission, encapsulation/decapsulation, overhead bytes and pointers processing, virtual
concatenation, SDH mapping/demapping, and LCAS function.
Figure 11-6 Networking and application of the EFT8A
NE1
NE2 NE4
NE3
User A2
User B2
User B1
User A1
NMS
PORT 1
PORT 2
PORT 2
PORT 1
Service flow
Line board
Cross-connect and
timing board
Data board
MSP ring

11.2.3 Functions and Features
The EFT8A supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
Table 11-8 provides the functions and features of the EFT8A.
Table 11-8 Functions and features of the EFT8A
Function and
Feature
EFT8A
Basic functions Transparently transmits 8xFE services.
Functions when
being used with the
interface board
Accesses 8xFE signals by providing interfaces on the front panel.
Specifications of the
optical interface
l Supports 10BASE-T/100BASE-TX signals.
l The optical interfaces comply with IEEE 802.3u.
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Function and
Feature
EFT8A
Format of service
frames
l Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG formats.
l The first four ports support the frame with a length ranging from
64 bytes to 1535 bytes and the last four ports support the frame with
a length ranging from 64 bytes to 9600 bytes.
l Supports the Jumbo frame with a length less than 9600 bytes.
Maximum uplink
bandwidth
622 Mbit/s
VCTRUNKs Number of supported VCTRUNKs: 8
Configuration principles are as follows:
l A VCTRUNK can be bound with a maximum of three VC-3s or a
maximum of 63 VC-12s.
l A VCTRUNK can be bound with the VC-12 path or VC-3 path at
one time. A VCTRUNK should not be bound with VC-12 and VC-3
paths at the same time.
l Different VCTRUNKs can be bound with paths at different levels.
l A VCTRUNK cannot be bound with VC-12s numbered 163 and
VC-3s numbered 1012 at the same time.
Mapping
granularities
Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X3)
granularities.
Encapsulation
format
Supports the HDLC, LAPS, and GFP-F protocols.
EPL services Supports the PORT-based transparent transmission.
MTU Supports the setting of the packet length, which ranges from 1518
bytes to 1535 bytes. After the setting becomes valid, the length of the
packets that enter or exit the IP ports is restricted by the pre-set MTU.
MPLS Does not support the MPLS.
VLAN Supports VLAN transparent transmission.
Link aggregation
function
Does not support the link aggregation function.
ETH-OAM function Does not support the ETH-OAM function.
QoS function Does not support the QoS function.
LCAS function Dynamically increases or decreases the bandwidth and protects the
bandwidth in compliance with ITU-T G.7042.
LPT function Supports the P2P LPT in GFP bearer mode.
Flow control
function
Supports the FE interface-based flow control function that complies
with IEEE 802.3x.
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Function and
Feature
EFT8A
High-precision time
(IEEE 1588 V2)
Does not support the high-precision time.
Test frames Receives and transmits GFP test frames.
Port mirroring Does not support the port mirroring function.
Loopback function l Supports inloops at the PHY layer on Ethernet ports.
l Supports inloops and outloops at the MAC layer on Ethernet ports.
l Supports inloops and outloops at the VC-3 level.
Protection schemes Supports the following protection schemes at the Ethernet network
level:
l LCAS
l LPT
Ethernet
performance
monitoring
Supports Ethernet performance monitoring at the port level.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.

11.2.4 Working Principle and Signal Flow
The EFT8A consists of the Ethernet access module, mapping module, interface converting
module, logic and control module, clock module, and power module.
Figure 11-7 shows the functional block diagram of the EFT8A by describing how to process
1xFE signals.
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Figure 11-7 Functional block diagram of the EFT8A
Ethernet
access
module
Logic and
control module
SCC unit
FE
Communication
Cross-connect unit
Reference clock and frame header
Clock
module
77
MHz
155
MHz
LOS
Interface
converting
module
ENCP
DENCP
Mapping module
VCP
-48 V/-60 V
+3.3 V backup power
+3.3 V
+3.3 V -48 V/-60 V Power
module
Fuse
Fuse
125
Power
module
MHz
50
MHz
Backplane
Cross-connect unit
SCC unit
ENCP: data encapsulation module DENCP: decapsulation module
VCP: virtual concatenation processing module

Ethernet Access Module
In the receive direction, the Ethernet access module accesses the Ethernet electrical signals from
Ethernet equipment such as switches or routers. At the PHY layer, the electrical signals are
decoded and the ETH_LOS alarm is detected. The electrical signals are converted from serial
signals into parallel signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded.
Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, HDLC, or
GFP format. The concatenation is performed. Then, the Ethernet signals are converted into SDH
signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.
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Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l Manages and configures other modules of the board.
l Implements inter-board communication through the internal Ethernet interface.
The control module also contains basic logic units. This module performs the following
functions:
l Writes and reads the register.
l Provides interfaces for the CPU.
l Checks and selects the clock.
l Performs phase discrimination and frequency division on the clock.
l Checks the in-service state of the cross-connect, SCC, and line boards.
l Implements communication.
l Controls indicators.
Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
11.2.5 Front Panel
The front panel of the EFT8A has indicators, interfaces, and a bar code.
Diagram of the Front Panel
Figure 11-8 shows the appearance of the front panel of the EFT8A.
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Figure 11-8 Front panel of the EFT8A
EFT8A
EFT8A
ACT
PROG
STAT
SRV
FE1
FE2
FE3
FE4
FE5
FE6
FE7
FE8

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Connection status indicator (LINK) one color (green)
l Data receiving and transmission indicator (ACT) one color (orange)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the EFT8A has eight FE interfaces. Table 11-9 describes the types and usage
of the interfaces of the EFT8A.
Table 11-9 Interfaces of the EFT8A
Interface Type of
Interface
Usage
FE1 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE2 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE3 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE4 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE5 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE6 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE7 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE8 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.

Table 11-10 describes the pins of the RJ-45 connector.
Table 11-10 Pins of the RJ-45 connector
Pin Description
1 Positive data transmit end
2 Negative data transmit end
3 Positive data receive end
4 Grounding
5 Grounding
6 Negative data receive end
7 Grounding
8 Grounding

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11.2.6 Jumpers and DIP Switches
The EFT8A does not have any jumpers or DIP switches that are used for board settings.
NOTE
The daughter board of the EFT4 has only one push-button switch, which is used for resetting the board.
When the EFT4 operates normally, do not push the switch. Otherwise, a cold reset is performed on the
board and the services may be lost.
11.2.7 Valid Slots
The EFT8A must be installed in a valid slot in the subrack. Otherwise, the EFT8A cannot work
normally.
The EFT8A can be installed in slots 18 and 1116 in the subrack. In this case, the bandwidth
is 622 Mbit/s.
11.2.8 Feature Code
The EFT8A does not have the feature code.
11.2.9 Parameter Settings
You can set parameters for the EFT8A by using the T2000.
You can set the following main parameters for the EFT8A by using the T2000:
l Working mode
l LCAS
l Maximum frame length
l Mapping protocol
l Byte packet
l CRC error frame
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
11.2.10 Technical Specifications
The technical specifications of the EFT8A include the Ethernet performance specifications,
mechanical specifications, and power consumption.
Ethernet Performance Specifications
NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EFT8A board of the N1 version.
Figure 11-9 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, and latency specifications of the EFTA.
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Figure 11-9 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, and latency specifications
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer
Port 1 Port 2
Port 1
Port 2

Figure 11-10 shows the connection for testing the back-to-back specifications of the EFT8A.
Figure 11-10 Connection for testing the back-to-back specifications
Tested
equipment 1
Data network
performance
analyzer
Port 1 Port 2

Table 11-11 lists the throughput specifications of the EFT8A. Table 11-12 lists the packet loss
ratio in the case of overloading of the EFT8A. Table 11-13 lists the latency specifications of the
EFT8A. Table 11-14 lists the back-to-back specifications of the EFT8A.
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NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured and 63 VC-12s are bound on the FE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-11 lists the throughput specifications of the EFT8A. The values are obtained when the
SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.
l The test duration is set to 60 seconds.
Table 11-11 Throughput specifications of the EFT8A
Frame Size
(Byte)
Passed Rate
(%)
(01,01,01) to
(01,01,02) (pks/
sec)
(01,01,02) to
(01,01,01) (pks/
sec)
Total (pks/
sec)
64 100.00 148810 148810 297620
128 100.00 84459 84459 168918
256 100.00 45290 45290 90580
512 100.00 23496 23496 46992
1024 100.00 11973 11973 23946
1280 100.00 9615 9615 19230
1518 100.00 8127 8127 16254

Table 11-12 lists the packet loss ratio in the case of overloading of the EFT8A. The values are
obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The tested traffic starts from the throughput and increases to 100% in 10% steps.
l The test duration is set to 60 seconds.
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Table 11-12 Packet loss ratio in the case of overloading of the EFT8A
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) (%)
(01,01,02) to
(01,01,01) (%)
Average (%)
64 100.00 0.000 0.000 0.000
128 100.00 0.000 0.000 0.000
256 100.00 0.000 0.000 0.000
512 100.00 0.000 0.000 0.000
1024 100.00 0.000 0.000 0.000
1280 100.00 0.000 0.000 0.000
1518 100.00 0.000 0.000 0.000

Table 11-13 lists the latency specifications of the EFT8A. The values are obtained when the
SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The test duration is set to 60 seconds.
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
Table 11-13 Latency specifications of the EFT8A
Frame
Size
(Byte)
Rate
Tested
(%)
(01,01,01) to
(01,01,02) (us)-
CT (us)
Average
(CT) (us)
(01,01,01) to
(01,01,02)
(us)-S&F (us)
Average
(S&F) (us)
64 100.00 506.4 506.4 501.2 501.2
128 100.00 518.8 518.8 508.5 508.5
256 100.00 536.2 536.2 515.8 515.8
512 100.00 578.9 578.9 538.0 538.0
1024 100.00 653.4 653.4 571.4 571.4
1280 100.00 688.1 688.1 585.6 585.6
1518 100.00 720.6 720.6 599.1 599.1

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Table 11-14 lists the back-to-back specifications of the EFT8A. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 2 seconds, and the number of repetitions is set to
a value more than 50 on the Smart Application.
l The tested traffic is set to the wire speed.
l The test duration is set to 10 seconds.
Table 11-14 Back-to-back specifications of the EFT8A
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) Burst
Size (Number of
Frames)
(01,01,02) to
(01,01,01)
(Number of
Frames)
Total
(Number of
Frames)
64 100.00 297620 297620 595240
128 100.00 168918 168918 337836
256 100.00 90580 90580 181160
512 100.00 46992 46992 93984
1024 100.00 23946 23946 47892
1280 100.00 19230 19230 38460
1518 100.00 16254 16254 32508

Mechanical Specifications
The mechanical specifications of the EFT8A are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the EFT8A at room temperature (25C) is 26 W.
11.3 EGT2
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EGT2 (2xGE transparent transmission board). This topic also
describes how to configure and commission the EGT2.
11.3.1 Version Description
The EGT2 is available in two functional versions, namely, N1 and N2.
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11.3.2 Application
The EGT2 is used to access Ethernet services, manage bandwidths, and converge Ethernet
services.
11.3.3 Functions and Features
The EGT2 supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
11.3.4 Working Principle and Signal Flow
The EGT2 consists of the Ethernet access module, mapping module, interface converting
module, logic and control module, clock module, and power module.
11.3.5 Front Panel
The front panel of the EGT2 has indicators, interfaces, a bar code, and a laser safety class label.
11.3.6 Jumpers and DIP Switches
The EGT2 does not have any jumpers or DIP switches that are used for board settings.
11.3.7 Valid Slots
The EGT2 must be installed in a valid slot in the subrack. Otherwise, the EGT2 cannot work
normally.
11.3.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGT2 indicates the type of interface.
11.3.9 Parameter Settings
You can set parameters for the EGT2 by using the T2000.
11.3.10 Technical Specifications
The technical specifications of the EGT2 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.
11.3.1 Version Description
The EGT2 is available in two functional versions, namely, N1 and N2.
Table 11-15 describes the versions of the EGT2.
Table 11-15 Versions of the EGT2
Item Description
Functional versions The EGT2 is available in two functional versions, namely, N1 and
N2.
Differences None
Substitution The N2EGT2 can substitute for the N1EGT2.

11.3.2 Application
The EGT2 is used to access Ethernet services, manage bandwidths, and converge Ethernet
services.
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Figure 11-11 shows the typical networking and application of the EGT2. The EGT2 realizes
point-to-point transparent transmission of Ethernet services. The EGT2 provides the following
functions by using the interfaces on the board: data receipt, data transmission, data mapping,
and traffic control. In addition, the EGT2 performs port-based point-to-point transparent
transmission, encapsulation/decapsulation, overhead bytes and pointers processing, virtual
concatenation, SDH mapping/demapping, and LCAS function.
Figure 11-11 Networking and application of the EGT2
NE1
NE2 NE4
NE3
User A2
User B2
User B1
User A1
NMS
PORT 1
PORT 2
PORT 2
PORT 1
Service flow
Line board
Cross-connect and
timing board
Data board
MSP ring

11.3.3 Functions and Features
The EGT2 supports the transparent transmission of Ethernet services, LCAS function, and test
frames.
Table 11-16 provides the functions and features of the EGT2.
Table 11-16 Functions and features of the EGT2
Function and
Feature
EGT2
Basic functions Transparently transmits 2xGE services.
Functions when
being used with the
interface board
Accesses 2xGE signals by providing interfaces on the front panel.
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Function and
Feature
EGT2
Specifications of the
optical interface
l Supports the 1000BASE-SX/LX/ZX/VX Ethernet optical
interfaces. The optical interfaces support the auto-negotiation
function in compliance with IEEE 802.3z. The optical interfaces
use the SFP optical module and support hot swapping. When the
multi-mode optical fiber is used, the maximum transmission
distance is 550 m. When the single-mode optical fiber is used, the
maximum transmission distance is 10 km. The optical modules
that can meet different requirements for the transmission distance
such as 40 km and 80 km can also be used.
l The N2EGT2 also supports the 1000BASE-T RJ-45 Ethernet
electrical interface. The electrical interface supports the auto-
negotiation function. The negotiated rate can be 10 Mbit/s, 100
Mbit/s, or 1000 Mbit/s. The N2EGT2 uses the SFP electrical
interface and supports hot swapping. The maximum transmission
distance is 100 m.
Format of service
frames
l Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG formats.
l Supports the frame with a length ranging from 64 bytes to 9600
bytes.
l Supports the Jumbo frame with a length less than 9600 bytes.
Maximum uplink
bandwidth
The maximum uplink bandwidth is 2.5 Gbit/s. The EGT2 can adapt
to the bandwidth of the slot.
VCTRUNKs Number of supported VCTRUNKs: 2
Configuration principles are as follows:
l A VCTRUNK can be bound with a maximum of eight VC-4s or a
maximum of 24 VC-3s. A VCTRUNK can be bound with VC-4s
numbered 114 or VC-3s numbered 148.
l The virtual concatenation modes of the two VCTRUNKs of the
board should be the same. That is, the two VCTRUNKs should be
of the VC-4 virtual concatenation or of the VC-3 virtual
concatenation.
Mapping
granularities
Supports VC-4, VC-3, VC3-Xv (X24), and VC4-Xv (X8)
granularities.
Encapsulation format Supports the HDLC, LAPS, and GFP-F protocols.
EPL services Supports the PORT-based transparent transmission.
MTU Supports the setting of the packet length, which ranges from 1518
bytes to 9600 bytes. After the setting becomes valid, the length of the
packets that enter or exit the IP ports is restricted by the pre-set MTU.
MPLS Does not support the MPLS.
VLAN Supports the VLAN transparent transmission.
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Function and
Feature
EGT2
Link aggregation
function
Does not support the link aggregation function.
ETH-OAM function Does not support the ETH-OAM function.
QoS function Does not support the QoS function.
LCAS function Dynamically increases or decreases the bandwidth and protects the
bandwidth in compliance with ITU-T G.7042.
LPT function Supports the P2P LPT in GFP bearer mode.
Flow control function Supports the GE port-based flow control function that complies with
IEEE 802.3x.
High-precision time
(IEEE 1588 V2)
Does not support the high-precision time.
Test frames Receives and transmits Ethernet test frames.
Port mirroring The N2EGT2 supports ingress mirroring.
Loopback function Supports inloops on Ethernet ports (at the PHY layer or MAC layer).
Protection schemes Supports the following protection schemes at the Ethernet network
level:
l LCAS
l LPT
Ethernet
performance
monitoring
Supports Ethernet performance monitoring at the port level.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.

11.3.4 Working Principle and Signal Flow
The EGT2 consists of the Ethernet access module, mapping module, interface converting
module, logic and control module, clock module, and power module.
Figure 11-12 shows the functional block diagram of the EGT2 by describing how to process
1xGE signals.
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Figure 11-12 Functional block diagram of the EGT2
Ethernet
access
module
Logic and
control module
SCC unit
GE
Communication
Cross-connect unit
Reference clock and frame header
Clock module
77
MHz
155
MHz
LOS
Interface
converting
module
DENCP
Mapping module
VCP
Laser
shutdown
-48 V/-60 V
+3.3 V backup power
+3.3 V
+3.3 V
-48 V/-60 V Power
module
Fuse
Fuse
125
Power
module
MHz
50
MHz
Backplane
ENCP
Cross-connect unit
SCC unit
ENCP: data encapsulation module DENCP: decapsulation module
VCP: virtual concatenation processing module

Ethernet Access Module
In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, HDLC, or
GFP format. The concatenation is performed. Then, the Ethernet signals are converted into SDH
signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.
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Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l Manages and configures other modules of the board.
l Implements inter-board communication through the internal Ethernet interface.
The control module also contains basic logic units. This module performs the following
functions:
l Writes and reads the register.
l Provides interfaces for the CPU.
l Checks and selects the clock.
l Performs phase discrimination and frequency division on the clock.
l Checks the in-service state of the cross-connect, SCC, and line boards.
l Controls the shutting down of the optical module.
l Implements communication.
l Controls indicators.
Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
11.3.5 Front Panel
The front panel of the EGT2 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 11-13 shows the appearance of the front panel of the N1EGT2/N2EGT2 that is installed
with the GE optical interface.
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Figure 11-13 Front panel of the N1EGT2/N2EGT2 that is installed with the GE optical interface
EGT2
EGT2
ACT
PROG
SRV
STAT
O
U
T
1
I
N
1
CLASS 1
LASER
PRODUCT
O
U
T
2
I
N
2
LINK1
ACT1
LINK2
ACT2

The N2EGT2 can also be installed with the GE electrical interface. Figure 11-14 shows the
appearance of the front panel of the N2EGT2 that is installed with the GE electrical interface.
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Figure 11-14 Front panel of the N2EGT2 that is installed with the GE electrical interface
EGT2
EGT2
ACT
PROG
SRV
STAT
LINK1
ACT1
LINK2
ACT2
O
U
T
1
I
N
1
O
U
T
2
I
N
2

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Connection status indicator (LINK) one color (green)
l Data receiving and transmission indicator (ACT) one color (orange)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the N1EGT2/N2EGT2 has two GE optical interfaces. Table 11-17 describes
the types and usage of the optical interfaces of the N1EGT2/N2EGT2.
Table 11-17 Optical interfaces of the N1EGT2/N2EGT2
Interface Type of Interface Usage
IN1/OUT1 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.
IN2/OUT2 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.

The two GE electrical interfaces of the N2EGT2 are of the same type and have the same usage.
Table 11-18 describes the types and usage of the electrical interfaces of the N2EGT2.
Table 11-18 Electrical interfaces of the N2EGT2
Interface Type of Interface Usage
GE RJ-45 (swappable) Transmits and receives 1000BASE-T signals.

Table 11-19 provides the pin assignments of the RJ-45 interface of the N2EGT2.
Table 11-19 Pin assignments of the RJ-45 interface of the N2EGT2
Pin Description
1 BI_DA+
2 BI_DA
3 BI_DB+
4 BI_DC+
5 BI_DC
6 BI_DB
7 BI_DD+
8 BI_DD

11.3.6 Jumpers and DIP Switches
The EGT2 does not have any jumpers or DIP switches that are used for board settings.
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11.3.7 Valid Slots
The EGT2 must be installed in a valid slot in the subrack. Otherwise, the EGT2 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The EGT2 can be installed in slots 18 and 1116 in the subrack.
l When the cross-connect capacity is 200 Gbit/s, the slots valid for the EGT2 are as follows:
The N1EGT2 can be installed in slots 14, 58, 1114, and 1516. When the N1EGT2
is installed in slots 14 and 1516, the bandwidth is 1.25 Gbit/s. When the N1EGT2 is
installed in slots 58 and 1114, the bandwidth is 2.5 Gbit/s.
The N2EGT2 can be installed in slots 18 and 1116. In this case, the bandwidth is 2.5
Gbit/s.
11.3.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGT2 indicates the type of interface.
Table 11-20 provides the relationship between the feature code of the EGT2 and the type of
interface.
Table 11-20 Relationship between the feature code of the EGT2 and the type of interface
Board Feature Code Type of Interface
SSN1EGT210 and
SSN2EGT210
10 1000BASE-SX (0.5 km)
SSN1EGT211 and
SSN2EGT211
11 1000BASE-LX (10 km)
SSN1EGT212 and
SSN2EGT212
12 1000BASE-VX (40 km)
SSN1EGT213 and
SSN2EGT213
13 1000BASE-ZX (80 km)
SSN2EGT214 14 1000BASE-T (100 m)

11.3.9 Parameter Settings
You can set parameters for the EGT2 by using the T2000.
You can set the following main parameters for the EGT2 by using the T2000:
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l Working mode
l LCAS
l Maximum frame length
l Mapping protocol
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
11.3.10 Technical Specifications
The technical specifications of the EGT2 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.
Parameters Specified for Optical Interfaces
Table 11-21 lists the parameters specified for the optical interfaces of the EGT2.
Table 11-21 Parameters specified for the optical interfaces of the EGT2
Parameter Value
Type of optical
interface
1000BASE-
ZX (80 km)
1000BASE-VX
(40 km)
1000BASE-
LX (10 km)
1000BASE-SX
(0.5 km)
Type of fiber Single-mode
LC
Single-mode
LC
Single-mode
LC
Multi-mode LC
Launched
optical power
range (dBm)
-2 to 5 -5 to 0 -11 to -3 -9.5 to 0
Operating
wavelength
range (nm)
1500 to 1580 1275 to 1350 1270 to 1355 770 to 860
Minimum
overload (dBm)
-3 -3 -3 0
Receiver
sensitivity
(dBm)
-23 -22 -19 -17
Minimum
extinction ratio
(dB)
9 9 9 9

Ethernet Performance Specifications
NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EGT2 board of the N1 version.
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Figure 11-15 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, and latency specifications of the N1EGT2.
Figure 11-15 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, and latency specifications of the N1EGT2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer
Port 1 Port 2
Port 1
Port 2

Figure 11-16 shows the connection for testing the back-to-back specifications of the N1EGT2.
Figure 11-16 Connection for testing the back-to-back specifications of the N1EGT2
Tested
equipment 1
Data network
performance
analyzer
Port 1 Port 2

Table 11-22 lists the throughput specifications of the N1EGT2. Table 11-23 lists the packet
loss ratio in the case of overloading of the N1EGT2. Table 11-24 lists the latency specifications
of the N1EGT2. Table 11-25 lists the back-to-back specifications of the N1EGT2.
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NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured and 24 VC-3s are bound on the GE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-22 lists the throughput specifications of the N1EGT2. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.
l The test duration is set to 60 seconds.
Table 11-22 Throughput specifications of the N1EGT2
Frame Size
(Byte)
Passed Rate
(%)
(01,02,01) to
(01,02,02) (pks/
sec)
(01,02,02) to
(01,02,01) (pks/
sec)
Total (pks/
sec)
64 100.00 1488095 1488095 2976190
128 100.00 844595 844595 1689190
256 100.00 452899 452899 905798
512 100.00 234962 234962 469924
1024 100.00 119732 119732 239464
1280 100.00 96154 96154 192308
1518 100.00 81274 81274 162548

Table 11-23 lists the packet loss ratio in the case of overloading of the N1EGT2. The values are
obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The tested traffic starts from the throughput and increases to 100% in 10% steps.
l The test duration is set to 60 seconds.
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Table 11-23 Packet loss ratio in the case of overloading of the N1EGT2
Frame Size
(Byte)
Rate Tested
(%)
(01,02,01) to
(01,02,02) (%)
(01,02,02) to
(01,02,01) (%)
Average (%)
64 100.00 0.000 0.000 0.000
128 100.00 0.000 0.000 0.000
256 100.00 0.000 0.000 0.000
512 100.00 0.000 0.000 0.000
1024 100.00 0.000 0.000 0.000
1280 100.00 0.000 0.000 0.000
1518 100.00 0.000 0.000 0.000

Table 11-24 lists the latency specifications of the N1EGT2. The values are obtained when the
SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The test duration is set to 60 seconds.
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
Table 11-24 Latency specifications of the N1EGT2
Frame
Size
(Byte)
Rate
Tested
(%)
(01,02,01) to
(01,02,02) (us)-
CT (us)
Average
(CT) (us)
(01,02,02) to
(01,02,01)
(us)-S&F (us)
Average
(S&F) (us)
64 100.00 35.7 35.7 35.2 35.2
128 100.00 37.1 37.1 36.1 36.1
256 100.00 39.5 39.5 37.4 37.4
512 100.00 44.1 44.1 40.1 40.1
1024 100.00 53.2 53.2 45.1 45.1
1280 100.00 57.6 57.6 47.4 47.4
1518 100.00 61.9 61.9 49.7 49.7

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Table 11-25 lists the back-to-back specifications of the N1EGT2. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 2 seconds, and the number of repetitions is set to
a value more than 50 on the Smart Application.
l The tested traffic is set to the wire speed.
l The test duration is set to 10 seconds.
Table 11-25 Back-to-back specifications of the N1EGT2
Frame Size
(Byte)
Rate Tested
(%)
(01,02,01) to
(01,02,02) Burst
Size (Number of
Frames)
(01,02,02) to
(01,02,01)
(Number of
Frames)
Total
(Number of
Frames)
64 100.00 2976190 2976190 5952380
128 100.00 1689190 1689190 3378380
256 100.00 905798 905798 1811596
512 100.00 469924 469924 939848
1024 100.00 239464 239464 478928
1280 100.00 192308 192308 384616
1518 100.00 162548 162548 325096

NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EGT2 board of the N2 version.
Figure 11-17 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, latency specifications, and back-to-back specifications of the
N2EGT2.
Figure 11-17 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications of the N2EGT2
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer
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Table 11-26 lists the throughput specifications of the N2EGT2. Table 11-27 lists the packet
loss ratio in the case of overloading of the N2EGT2. Table 11-28 lists the latency specifications
of the N2EGT2. Table 11-29 lists the back-to-back specifications of the N2EGT2.
NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured and two VC-3s are bound on the GE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-26 lists the throughput specifications of the N2EGT2. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.
l The test duration is set to 60 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 15
l Maximum rate (%): 15
l Mode: Uni-directional
Table 11-26 Throughput specifications of the N2EGT2
Frame Size
(byte)
Passed Rate (%) (01,05,02) to (01,05,01)
(pks/sec)
Total (pks/sec)
64 11.23 167112 334224
128 10.48 88527 177054
256 9.75 44138 88276
512 9.74 22894 45788
1024 9.75 11674 23348
1280 9.75 9373 18746
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Frame Size
(byte)
Passed Rate (%) (01,05,02) to (01,05,01)
(pks/sec)
Total (pks/sec)
1518 9.75 7922 15844

Table 11-27 lists the packet loss ratio in the case of overloading of the N2EGT2. The values are
obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The tested traffic starts from the throughput and increases to 100% in 10% steps.
l The test duration is set to 60 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 11.23
l Maximum rate (%): 10.00
l Resolution rate (%): None
l Mode: Uni-directional
Table 11-27 Packet loss ratio in the case of overloading of the N2EGT2
Frame Size
(byte)
Rate Tested (%) (01,05,02) to (01,05,01)
(%)
Average (%)
64 11.23 0.000 0.000
128 10.48 0.000 0.000
256 9.75 0.000 0.000
512 9.74 0.000 0.000
1024 9.75 0.000 0.000
1280 9.75 0.000 0.000
1518 9.75 0.000 0.000

Table 11-28 lists the latency specifications of the N2EGT2. The values are obtained when the
SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The test duration is set to 100 seconds.
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
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when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
l Measure on one receiving card only
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 11.23
l Maximum rate (%): 10.00
l Resolution rate (%): None
l Mode: Uni-directional
Table 11-28 Latency specifications of the N2EGT2
Frame
Size
(byte)
Rate
Tested
(%)
(01,05,02) to
(01,05,01) (us)-
CT (us)
Average
(CT) (us)
(01,05,02) to
(01,05,01)
(us)-S&F (us)
Average
(S&F) (us)
64 11.23 92.7 92.7 92.1 92.1
128 10.48 97.7 97.7 96.6 96.6
256 9.75 109.5 109.5 107.5 107.5
512 9.74 133.1 133.1 129.0 129.0
1024 9.75 178.8 178.8 170.6 170.6
1280 9.75 204.1 204.1 193.9 193.9
1518 9.75 224.0 224.0 211.9 211.9

Table 11-29 lists the back-to-back specifications of the N2EGT2. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 2 seconds, and the number of repetitions is set to
a value more than 1 on the SmartApplication.
l The tested traffic is set to the wire speed.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
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l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 11.23
l Maximum rate (%): 10.00
l Resolution rate (%): None
l Mode: Uni-directional
Table 11-29 Back-to-back specifications of the N2EGT2
Frame Size
(byte)
Rate Tested (%) (01,05,02) to (01,05,01)
Burst Size (frames)
Total (frames)
64 11.23 334224 668448
128 10.48 177054 354108
256 9.75 88276 176552
512 9.74 45754 91508
1024 9.75 23348 46696
1280 9.75 18752 37504
1518 9.75 15848 31696

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the EGT2 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.9
Power Consumption
The maximum power consumption of the N1EGT2 at room temperature (25C) is 29 W.
The maximum power consumption of the N2EGT2 at room temperature (25C) is 15 W.
11.4 EFS0
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EFS0 (8xFE switching and processing board). This topic also
describes how to configure and commission the EFS0.
11.4.1 Version Description
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The EFS0 is available in several functional versions. Select a functional board according to
actual requirements.
11.4.2 Application
The EFS0 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
11.4.3 Functions and Features
The EFS0 supports the Layer 2 switching, MPLS, and broadcast functions.
11.4.4 Working Principle and Signal Flow
The EFS0 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
11.4.5 Front Panel
The front panel of the EFS0 has indicators and a bar code.
11.4.6 Jumpers and DIP Switches
The EFS0 does not have any jumpers or DIP switches that are used for board settings.
11.4.7 Valid Slots
The EFS0 must be installed in a valid slot in the subrack. Otherwise, the EFS0 cannot work
normally.
11.4.8 Feature Code
The EFS0 does not have the feature code.
11.4.9 Board Protection
The EFS0 supports the 1:1 TPS protection.
11.4.10 Parameter Settings
You can set parameters for the EFS0 by using the T2000.
11.4.11 Technical Specifications
The technical specifications of the EFS0 include the dimensions, weight, and power
consumption.
11.4.1 Version Description
The EFS0 is available in several functional versions. Select a functional board according to
actual requirements.
The EFS0 is available in the following functional versions: N1, N2, N4, and N5. The
N2EFS0/N1EFS0 is discontinued.
Table 11-30 describes the versions of the EFS0.
Table 11-30 Versions of the EFS0
Item Description
Functional
versions
The EFS0 is available in the following functional versions: N1, N2, N4,
and N5.
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Item Description
Differences l The maximum uplink bandwidth of the N1EFS0 is 622 Mbit/s.
l The maximum uplink bandwidth of the N2EFS0/N4EFS0/N5EFS0 is
1.25 Gbit/s.
l Supports flow classification based on PORT, PORT+VLAN ID, and
PORT+VLAN ID+VLAN PRI.
l The number of VCTRUNKs supported by the N1EFS0 is 12.
l The number of VCTRUNKs supported by the N5EFS0, N4EFS0 and
N2EFS0 is 24.
Substitution The N2EFS0 supports the board version replacement function and can
replace the N1EFS0.
The N4EFS0 supports the board version replacement function and can
replace the N2EFS0/N1EFS0.
The N5EFS0 supports the board version replacement function and can
replace the N4EFS0/N2EFS0/N1EFS0.

11.4.2 Application
The EFS0 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
Figure 11-18 shows the typical networking and application of the EFS0. The EFS0 accesses
and converges Ethernet services, and provides the Ethernet data with the following data features:
Layer 2 switching, port isolation, flow classification, traffic control, VLAN management, and
priority configuration. In addition, the EFS0 performs encapsulation/decapsulation, virtual
concatenation, and SDH mapping/demapping for data. The EFS0 can be interconnected with
the bandwidth access equipment and the data communication equipment at the same time, thus
to provide a network-level solution.
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Figure 11-18 Networking and application of the EFS0
NE1
NE2 NE4
NE3
User A2
User B2
User B1
User A1
NMS
PORT 1
VLAN 100
PORT 2
VLAN 100
PORT 2
VLAN 100
PORT 1 VLAN 100
Service flow
Line board
Cross-connect and
timing board
Data board
MSP ring

11.4.3 Functions and Features
The EFS0 supports the Layer 2 switching, MPLS, and broadcast functions.
Table 11-31 provides the functions and features of the EFS0.
Table 11-31 Functions and features of the EFS0
Function and Feature EFS0
Basic functions Processes 8xFE services and supports the convergence of 60x10
Mbit/s or 6x100 Mbit/s services.
Functions when being
used with the interface
board
l Accesses 8xFE signals through the electrical interface when
the EFS0 is used with the ETF8.
l Accesses 8xFE signals through the optical interface when the
EFS0 is used with the EFF8.
l Provides the TPS protection for the 8xFE signals through the
electrical interface when the EFS0 is used with the ETS8 and
TSB8.
l The N5EFS0 can access 8xFE signals through the electrical
interface when it is used with the ETF8A.
l The N5EFS0 can access 8xFE signals through the optical
interface when it is used with the EFF8A.
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Function and Feature EFS0
Specifications of the
optical interface
l Supports 10BASE-T/100BASE-TX signals when the EFS0 is
used with the ETF8.
l Supports 100BASE-FX signals when the EFS0 is used with
the EFF8. The optical interfaces comply with IEEE 802.3u.
l The N5EFS0 supports 10BASE-T/100BASE-TX signals
when it is used with the ETF8A.
l The N5EFS0 supports 100BASE-FX signals when it is used
with the EFF8A. The optical interfaces comply with IEEE
802.3u.
Format of service frames l Supports Ethernet II, IEEE 802.3, and IEEE 802.1 q/p formats.
l Supports the frame with a length ranging from 64 bytes to 9600
bytes.
l Supports the Jumbo frame with a length less than 9600 bytes.
Maximum uplink
bandwidth
l The maximum uplink bandwidth of the N1EFS0 is 622 Mbit/
s.
l The maximum uplink bandwidth of the N2EFS0/N4EFS0/
N5EFS0 is 1.25 Gbit/s.
l The EFS0 can adapt to the bandwidth of the slot.
VCTRUNKs The number of supported VCTRUNKs is as follows:
l The number of VCTRUNKs supported by the N1EFS0 is 12.
l The number of VCTRUNKs supported by the N2EFS0/
N4EFS0/N5EFS0 is 24.
Configuration principles are as follows:
l VCTRUNK 1VCTRUNK 12 can be bound with VC-4s
numbered 14 only. VCTRUNK 13VCTRUNK 24 can be
bound with VC-4s numbered 58 only.
l VC-4s numbered 4 and 8 support the binding of VC-3 and
VC-12 paths. The other VC-4s support the binding of VC-3
paths only.
l A VC-4 cannot be bound with VC-3 and VC-12 paths at the
same time.
Mapping granularities Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X
12) granularities.
Encapsulation format Supports the GFP-F encapsulation.
l The N1EFS0/N2EFS0 supports the GFP-F, LAPS, and HDLC
encapsulation.
l The N4EFS0 and N5EFS0 support the GFP-F encapsulation
only.
EPL services Supports the PORT-based transparent transmission.
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Function and Feature EFS0
EVPL services Supports PORT+VLAN-based EVPL services that use the frame
encapsulation formats of MartinioE and stack VLAN.
EPLAN services l Supports the point-to-multipoint (P2MP) converging service
that is based on Layer 2.
l Supports the Layer 2 forwarding function.
l Supports switching on the client and SDH sides.
l Supports the self-learning of the source MAC address. The
capacity of the MAC address table is 16K. The aging time of
the MAC address can be set and queried.
l Supports the configuration of the static MAC route.
l The N1EFS0/N2EFS0 does not support the query of the
dynamic MAC address. The N4EFS0/N5EFS0 supports the
query of the dynamic MAC address.
l Supports the creation, deletion, and query of the VB. The
maximum number of supported VBs is 16. The maximum
number of logical ports for each VB is 30.
l Queries the number of actually learnt MAC addresses based
on VB+VLAN or VB+LP.
l Supports the EPLAN services that are based on the IEEE
802.1d MAC bridge.
EVPLAN services l Supports EVPLAN virtual bridges.
l Supports data isolation based on VB+VLAN.
l Supports the setting of a maximum of 4096 VLAN services.
l Supports the EVPLAN services that are based on the IEEE
802.1q virtual bridge.
MTU Supports the setting of the packet length, which ranges from 1518
bytes to 9600 bytes. After the setting becomes valid, the length
of the packets that exit the IP ports is restricted by the pre-set
MTU.
MPLS Supports the MPLS.
VLAN Supports 4k VLANs. The VLAN technology complies with IEEE
802.1q/p.
Rapid spanning tree
protocol (RSTP)
Supports the broadcast packet suppression function and RSTP
that comply with IEEE 802.1w.
Link aggregation
function
The N1EFS0 does not support the link aggregation function. The
N2EFS0, N4EFS0, and N5EFS0 support manual link
aggregation.
Multicast function
(IGMP snooping)
Supports the multicast function.
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Function and Feature EFS0
ETH-OAM function l The N1EFS0 and N2EFS0 do not support the ETH-OAM
function.
l The N4EFS0 and N5EFS0 support continuity check (CC) for
the multicast service, loopback (LB) test for the unicast
service, link trace (LT) test, loop detection (LD), auto-
negotiation, fault diagnosis, and link performance detection.
The ETH-OAM function complies with IEEE 802.1ag and
IEEE 802.3ah.
QoS function l Supports the CAR. The granularity is 64 kbit/s.
l The N1EFS0 supports the service classification based on
PORT, PORT+VLAN ID, or PORT+VLAN PRI.
l The N2EFS0, N4EFS0, and N5EFS0 support the flow
classification based on PORT, PORT++VLAN ID, or PORT
+VLAN ID+VLAN PRI.
LCAS function Dynamically increases or decreases the bandwidth and protects
the bandwidth in compliance with ITU-T G.7042.
LPT function l The N1EFS0/N2EFS0 supports the point-to-point (P2P) LPT.
l The N4EFS0/N5EFS0 supports the P2P LPT and P2MP LPT.
Flow control function Supports the port-based flow control function that complies with
IEEE 802.3x.
High-precision time
(IEEE 1588 V2)
Does not support the high-precision time.
Test frames Receives and transmits Ethernet test frames.
Loopback function l Supports inloops on Ethernet ports (at the PHY layer or MAC
layer).
l The N1EFS0, N2EFS0 and N4EFS0 support inloops and
outloops at the VC-3 level. The N5EFS0 does not support
inloops and outloops at the VC-3 level.
Protection schemes Supports the following protection schemes at the Ethernet
equipment level and network level:
l The N2EFS0/N4EFS0/N5EFS0 supports TPS
l STP/RSTP
l LCAS
l LPT
l LAG
Ethernet performance
monitoring
Supports Ethernet performance monitoring at the port level.
Alarms and performance
events
Reports various alarms and performance events, which facilitates
the management and maintenance of the equipment.
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11.4.4 Working Principle and Signal Flow
The EFS0 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
Figure 11-19 shows the functional block diagram of the EFS0 by describing how to process
1xFE signals.
Figure 11-19 Functional block diagram of the EFS0
Ethernet
access
module
FE
Interface
converting
module
Mapping module
Control
Data
Switch
fabric
Network
processor
Network processor module
Logic and
control module
SCC unit
Communication
Reference clock and frame header
Clock module
77
MHz
125 155
MHz
LOS
Laser
shutdown
50
MHz
Cross-connect unit
+3.3 V backup power
+3.3 V
Power
module
Fuse
Fuse
-48 V/-60 V
-48 V/-60 V Power
module
E
N
C
P
V
C
P
D
E
N
C
P
MHz
Backplane
Cross-connect unit
SCC unit
ENCP: data encapsulation module DENCP: decapsulation module
VCP: virtual concatenation processing module

Ethernet Access Module
In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
Network Processor Module
The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
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After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The following formats are supported:
l Multi-protocol label switching (MPLS)
l L2 MPLS VPN
l Ethernet/VLAN
In the receive direction, services are mapped and forwarded after the Tunnel and VC tags are
added according to the service configuration. In the transmit direction, the Tunnel or VC tag is
extracted based on the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module supports the following functions:
l Flow sense and flow classification
l Unicast, multicast, and broadcast of the flow
l Setting of data priorities
l Weighted fair queuing (WFQ)
l Four classes of service (CoSs)
Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is performed. Then, the Ethernet signals are converted into SDH signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.
Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l Manages and configures other modules of the board.
l Implements inter-board communication through the internal Ethernet interface.
The control module also contains basic logic units. This module performs the following
functions:
l Writes and reads the register.
l Provides interfaces for the CPU.
l Checks and selects the clock.
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l Performs phase discrimination and frequency division on the clock.
l Checks the in-service state of the cross-connect, SCC, and line boards.
l Controls the shutting down of the optical module.
l Implements communication.
l Controls indicators.
Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
11.4.5 Front Panel
The front panel of the EFS0 has indicators and a bar code.
Diagram of the Front Panel
Figure 11-20 shows the appearance of the front panel of the EFS0.
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Figure 11-20 Front panel of the EFS0
EFS0
EFS0
ACT
PROG
STAT
SRV

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the EFS0 has no interfaces. The interfaces are available on the ETF8 or on
the EFF8. When the N5EFS0 is used with the ETF8A or EFF8A, the interfaces are available on
the ETF8A or on the EFF8A.
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11.4.6 Jumpers and DIP Switches
The EFS0 does not have any jumpers or DIP switches that are used for board settings.
11.4.7 Valid Slots
The EFS0 must be installed in a valid slot in the subrack. Otherwise, the EFS0 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The EFS0 must be used with the ETF8, EFF8, and ETS8. When the ETS8 is used as the interface
board, the TSB8 must be used as the bridging board. For the slots valid for the EFS0, ETS8, and
TSB8 when the EFS0 works with the ETS8 and TSB8, see 11.4.9 Board Protection.
The N5EFS0 can be used with the ETF8A and EFF8A. When the N5EFS0 works with the ETF8A
or EFF8A, the slots valid for the N5EFS0 are the same as the slots valid for the N5EFS0 when
the N5EFS0 works with the ETF8 or EFF8.
The slots valid for the EFS0 vary with the version of the board and the cross-connect capacity
of the subrack. The slots valid for the board are as follows:
l When the cross-connect capacity is 200 Gbit/s, the N1EFS0 can be installed in slots 25
and 1316. In this case, the bandwidth is 622 Mbit/s.
l When the cross-connect capacity is 200 Gbit/s, the N2EFS0, N4EFS0, and N5EFS0 can
be installed in slots 25 and 1316. In this case, the bandwidth is 1.25 Gbit/s.
Table 11-32 lists the slots valid for the EFS0 and the corresponding slots for the ETF8 and EFF8.
Table 11-32 Slots valid for the EFS0 and the corresponding slots for the ETF8 and EFF8
Slot Valid for the EFS0 Corresponding Slot for the ETF8 and EFF8
Slot 2 Slot 19
Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33
Slot 16 Slot 35

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11.4.8 Feature Code
The EFS0 does not have the feature code.
11.4.9 Board Protection
The EFS0 supports the 1:1 TPS protection.
Figure 11-21 shows the slot configuration for the 1:1 TPS protection for the EFS0.
Figure 11-21 Slot configuration for the 1:1 TPS protection for the EFS0
S
L
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1
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r
k
i
n
g

2
P
r
o
t
e
c
t
i
o
n

2

In Figure 11-21, the board in slot 2 protects the board in slot 3 and the board in slot 16 protects
the board in slot 15. The ETS8 is used with the working EFS0 and the TSB8 is used with the
protection EFS0. Table 11-33 lists the slots for the EFS0, ETS8, and TSB8.
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Table 11-33 Slots for the EFS0, ETS8, and TSB8
Board Protection Group 1 Protection Group 2
EFS0 (protection) Slot 2 Slot 16
EFS0 (working) Slot 3 Slot 15
TSB8 Slot 19 Slot 35
ETS8 Slot 21 Slot 33

11.4.10 Parameter Settings
You can set parameters for the EFS0 by using the T2000.
You can set the following main parameters for the EFS0 by using the T2000:
l Working mode
l LCAS
l Maximum frame length
l Mapping protocol
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
11.4.11 Technical Specifications
The technical specifications of the EFS0 include the dimensions, weight, and power
consumption.
Ethernet Performance Specifications
NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EFS0 board of the N4 version.
Figure 11-22 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, latency specifications, and back-to-back specifications of the
N4EFS0.
Figure 11-22 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications of the N4EFS0
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer
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Table 11-34 lists the throughput specifications of the N4EFS0. Table 11-35 lists the packet loss
ratio in the case of overloading of the N4EFS0. Table 11-36 lists the latency specifications of
the N4EFS0. Table 11-37 lists the back-to-back specifications of the N4EFS0.
NOTE
l The specifications vary according to the configuration and networking of the test environment, port
rate, and VC services bound on the VCG side. The specifications that are obtained in the actual
environment are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured and five VC-12s are bound on the FE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-34 lists the throughput specifications of the N4EFS0. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.
l The test duration is set to 60 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 10.00
l Maximum rate (%): 12.00
l Mode: bidirectional
Table 11-34 Throughput specifications of the N4EFS0
Frame Size
(Byte)
Passed Rate
(%)
(01,02,03) to
(01,02,05) (pks/
sec)
(01,02,05) to
(01,02,03) (pks/
sec)
Total (pks/
sec)
64 11.48 17088 17088 34176
128 11.25 9502 9502 19004
256 11.13 5042 5042 10084
512 11.12 2613 2613 5226
1024 11.07 1326 1326 2652
1280 11.10 1067 1067 2134
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Frame Size
(Byte)
Passed Rate
(%)
(01,02,03) to
(01,02,05) (pks/
sec)
(01,02,05) to
(01,02,03) (pks/
sec)
Total (pks/
sec)
1518 11.12 904 904 1808

Table 11-35 lists the packet loss ratio in the case of overloading of the N4EFS0. The values are
obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The tested traffic starts from the throughput and increases to 100% in 10% steps.
l The test duration is set to 60 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 11-35 Packet loss ratio in the case of overloading of the N4EFS0
Frame Size
(Byte)
Rate Tested
(%)
(01,02,03) to
(01,02,05) (%)
(01,02,05) to
(01,02,03) (%)
Average (%)
64 100.00 88.507 88.507 88.507
128 100.00 88.730 88.745 88.737
256 100.00 88.851 88.831 88.841
512 100.00 88.876 88.846 88.861
1024 100.00 88.901 88.890 88.895
1280 100.00 88.878 88.878 88.878
1518 100.00 88.850 88.844 88.847

Table 11-36 lists the latency specifications of the N4EFS0. The values are obtained when the
SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The test duration is set to 60 seconds.
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l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
l CT: cut through or FIFO; S&F: store forward or LIFO
l Measure on one receiving card only. Mode: SmartMetrics Comp. Mode
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 10.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 11-36 Latency specifications of the N4EFS0
Frame
Size
(Byte)
Rate
Tested
(%)
(01,02,03) to
(01,02,05) (us)-
CT (us)
Average
(CT) (us)
(01,02,03) to
(01,02,05)
(us)-S&F (us)
Average
(S&F) (us)
64 10.00 561.4 561.4 556.2 556.2
128 10.00 644.4 644.4 634.2 634.2
256 10.00 738.4 738.4 718.0 718.0
512 10.00 948.8 948.8 907.9 907.9
1024 10.00 1371.5 1371.5 1289.6 1289.6
1280 10.00 1604.1 1604.1 1501.7 1501.7
1518 10.00 1790.4 1790.4 1669.0 1669.0

Table 11-37 lists the back-to-back specifications of the N4EFS0. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 2 seconds, and the number of repetitions is set to
a value more than 50 on the Smart Application.
l The tested traffic is set to the wire speed.
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l The test duration is set to 10 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 11-37 Back-to-back specifications of the N4EFS0
Frame Size
(Byte)
Rate Tested
(%)
(01,02,03) to
(01,02,05) Burst
Size (Number of
Frames)
(01,02,05) to
(01,02,03)
(Number of
Frames)
Total
(Number of
Frames)
64 100.00 1333 1335 2668
128 100.00 848 850 1698
256 100.00 586 587 1173
512 100.00 445 447 892
1024 100.00 224 224 448
1280 100.00 211 212 423
1518 100.00 201 201 402

NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EFS0 board of the N5 version.
Figure 11-23 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, latency specifications, and back-to-back specifications of the
N5EFS0.
Figure 11-23 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications of the N5EFS0
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer
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Table 11-38 lists the throughput specifications of the N5EFS0. Table 11-39 lists the packet loss
ratio in the case of overloading of the N5EFS0. Table 11-40 lists the latency specifications of
the N5EFS0. Table 11-41 lists the back-to-back specifications of the N5EFS0.
NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured 3 VC-3s are bound on the FE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-38 lists the throughput specifications of the N5EFS0. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The permitted packet loss ratio is set to 0% and the resolution rate is set to 1%.
l The test duration is set to 5 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): None
l Mode: Uni-directional
Table 11-38 Throughput specifications of the N5EFS0
Frame Size
(byte)
Passed Rate (%) (01,06,01) to (01,06,02)
(pks/sec)
Total (pks/sec)
64 100.00 148810 148810
128 100.00 84459 84459
256 100.00 45290 45290
512 100.00 23496 23496
1024 100.00 11973 11973
1280 100.00 9615 9615
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Frame Size
(byte)
Passed Rate (%) (01,06,01) to (01,06,02)
(pks/sec)
Total (pks/sec)
1518 100.00 8127 8127

Table 11-39 lists the packet loss ratio in the case of overloading of the N5EFS0. The values are
obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The tested traffic starts from the throughput and increases to 100% in 10% steps.
l The test duration is set to 5 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): None
l Mode: Uni-directional
Table 11-39 Packet loss ratio in the case of overloading of the N5EFS0
Frame Size
(byte)
Rate Tested (%) (01,06,01) to (01,06,02)
(%)
Average (%)
64 100.00 0.000 0.000
128 100.00 0.000 0.000
256 100.00 0.000 0.000
512 100.00 0.000 0.000
1024 100.00 0.000 0.000
1280 100.00 0.000 0.000
1518 100.00 0.000 0.000

Table 11-40 lists the latency specifications of the N5EFS0. The values are obtained when the
SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The test duration is set to 5 seconds.
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
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when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
l CT: Cut Through (or FIFO),S&F: Store & Forward (or LIFO)
l Measure on one receiving card only, Mode: SmartMetrics Comp. Mode
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): None
l Mode: Uni-directional
Table 11-40 Latency specifications of the N5EFS0
Frame
Size
(byte)
Rate
Tested
(%)
(01,06,01) to
(01,06,02) (us)-
CT (us)
Average
(CT) (us)
(01,06,01) to
(01,06,02)
(us)-S&F (us)
Average
(S&F) (us)
64 100.00 124.3 124.3 119.2 119.2
128 100.00 137.4 137.4 127.2 127.2
256 100.00 169.6 169.6 149.2 149.2
512 100.00 211.5 211.5 170.6 170.6
1024 100.00 294.4 294.4 212.4 212.4
1280 100.00 334.5 334.5 232.1 232.1
1518 100.00 368.7 368.7 247.3 247.3

Table 11-41 lists the back-to-back specifications of the N5EFS0. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 2 seconds, and the number of repetitions is set to
a value more than 50 on the SmartApplication.
l The tested traffic is set to the wire speed.
l Minimum frame size (byte): 64
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l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): None
l Mode: Uni-directional
Table 11-41 Back-to-back specifications of the N5EFS0
Frame Size
(byte)
Rate Tested (%) (01,01,03) to (01,01,06)
Burst Size (frames)
Total (frames)
64 100.00 297620 297620
128 100.00 168918 168918
256 100.00 90580 90580
512 100.00 46992 46992
1024 100.00 23946 23946
1280 100.00 19230 19230
1518 100.00 16254 16254

Mechanical Specifications
The mechanical specifications of the EFS0 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight of the N1EFS0 (kg): 1.0
l Weight of the N2EFS0 (kg): 1.0
l Weight of the N4EFS0 (kg): 1.0
l Weight of the N5EFS0 (kg): 0.6
Power Consumption
The maximum power consumption of the N1EFS0 at room temperature (25C) is 35 W.
The maximum power consumption of the N2EFS0 at room temperature (25C) is 35 W.
The maximum power consumption of the N4EFS0 at room temperature (25C) is 35 W.
The maximum power consumption of the N5EFS0 at room temperature (25C) is 22 W.
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11.5 EFS0A
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EFS0A (16xFE switching and processing board). This topic also
describes how to configure and commission the EFS0A.
11.5.1 Version Description
The EFS0A is available in one functional version, namely, N1.
11.5.2 Application
The EFS0A is used to access Ethernet services, manage bandwidths, and realize Layer 2
switching of Ethernet services.
11.5.3 Functions and Features
The EFS0A supports the Layer 2 switching, MPLS, and broadcast functions.
11.5.4 Working Principle and Signal Flow
The EFS0A consists of the Ethernet access module, network processor module, mapping
module, interface converting module, logic and control module, clock module, and power
module.
11.5.5 Front Panel
The front panel of the EFS0A has indicators and a bar code.
11.5.6 Jumpers and DIP Switches
The EFS0A does not have any jumpers or DIP switches that are used for board settings.
11.5.7 Valid Slots
The EFS0A must be installed in a valid slot in the subrack. Otherwise, the EFS0A cannot work
normally.
11.5.8 Feature Code
The EFS0A does not have the feature code.
11.5.9 Board Protection
The EFS0A supports the 1:1 TPS protection.
11.5.10 Parameter Settings
You can set parameters for the EFS0A by using the T2000.
11.5.11 Technical Specifications
The technical specifications of the EFS0A include the dimensions, weight, and power
consumption.
11.5.1 Version Description
The EFS0A is available in one functional version, namely, N1.
11.5.2 Application
The EFS0A is used to access Ethernet services, manage bandwidths, and realize Layer 2
switching of Ethernet services.
Figure 11-24 shows the typical networking and application of the EFS0A. The EFS0A accesses
and converges Ethernet services, and provides the Ethernet data with the following data features:
Layer 2 switching, port isolation, flow classification, traffic control, VLAN management, and
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priority configuration. In addition, the EFS0A performs encapsulation/decapsulation, virtual
concatenation, and SDH mapping/demapping for data. The EFS0A can be interconnected with
the bandwidth access equipment and the data communication equipment at the same time, thus
to provide a network-level solution.
Figure 11-24 Networking and application of the EFS0A
NE1
NE2 NE4
NE3
User A2
User B2
User B1
User A1
NMS
PORT 1
VLAN 100
PORT 2
VLAN 100
PORT 2
VLAN 100
PORT 1 VLAN 100
Service flow
Line board
Cross-connect and
timing board
Data board
MSP ring

11.5.3 Functions and Features
The EFS0A supports the Layer 2 switching, MPLS, and broadcast functions.
Table 11-42 provides the functions and features of the EFS0A.
Table 11-42 Functions and features of the EFS0A
Function and
Feature
EFS0A
Basic functions Processes 16xFE services.
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Function and
Feature
EFS0A
Functions when being
used with the interface
board
l Accesses 16xFE signals through the electrical interface when the
EFS0A is used with the ETF8.
l Accesses 16xFE signals through the optical interface when the
EFS0A is used with the EFF8.
l Provides the TPS protection for the 16xFE signals through the
electrical interface when the EFS0A is used with the ETS8 and
TSB8.
Specifications of the
optical interface
l Supports 10BASE-T/100BASE-TX signals when the EFS0A is
used with the ETF8.
l Supports 100BASE-FX signals when the EFS0A is used with the
EFF8. The optical interfaces comply with IEEE 802.3u.
Format of service
frames
l Supports Ethernet II, IEEE 802.3, and IEEE 802.1 q/p formats.
l Supports the frame with a length ranging from 64 bytes to 9600
bytes.
l Supports the Jumbo frame with a length less than 9600 bytes.
Maximum uplink
bandwidth
The maximum uplink bandwidth is 2.5 Gbit/s.
The EFS0A can adapt to the bandwidth of the slot.
VCTRUNKs Number of supported VCTRUNKs: 32
Configuration principles are as follows:
l VC-4s numbered 4, 8, 12, and 16 support the binding of VC-3 and
VC-12 paths. The other VC-4s support the binding of VC-3 paths
only.
l A VC-4 cannot be bound with VC-3 and VC-12 paths at the same
time.
Mapping granularities Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X12)
granularities.
Encapsulation format Supports the GFP-F protocol.
EPL services Supports the PORT-based transparent transmission.
EVPL services Supports PORT+VLAN-based EVPL services that use the frame
encapsulation formats of MartinioE and stack VLAN.
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Function and
Feature
EFS0A
EPLAN services l Supports the P2MP converging service that is based on Layer 2.
l Supports the Layer 2 forwarding function.
l Supports switching on the client and SDH sides.
l Supports the self-learning of the source MAC address. The
capacity of the MAC address table is 16K. The aging time of the
MAC address can be set and queried.
l Supports the configuration of the static MAC route.
l The N1EFS0, N2EFS0, and N5EFS0 support the query of the
dynamic MAC address.
l Support the query of the dynamic MAC address.
l Supports the creation, deletion, and query of the VB. The
maximum number of supported VBs is 16. The maximum number
of logical ports for each VB is 30.
l Queries the number of actually learnt MAC addresses based on
VB+VLAN or VB+LP.
l Supports the EPLAN services that are based on the IEEE 802.1d
MAC bridge.
EVPLAN services l Supports EVPLAN virtual bridges.
l Supports data isolation based on VB+VLAN.
l Supports the setting of a maximum of 4096 VLAN services.
l Supports the EVPLAN services that are based on the IEEE 802.1q
virtual bridge.
MTU Supports the setting of the packet length, which ranges from 1518
bytes to 9600 bytes. After the setting becomes valid, the length of
the packets that enter or exit the IP ports is restricted by the pre-set
MTU.
MPLS Supports the MPLS.
VLAN Supports 4k VLANs. The VLAN technology complies with IEEE
802.1q/p.
RSTP Supports the broadcast packet suppression function and RSTP that
comply with IEEE 802.1w.
Link aggregation
function
Supports manual link aggregation.
Multicast function
(IGMP snooping)
Supports the multicast function.
ETH-OAM function Supports CC for the multicast service, LB test for the unicast service,
LT test, LD, auto-negotiation, fault diagnosis, and link performance
detection.
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Function and
Feature
EFS0A
QoS function l Supports the CAR. The granularity is 64 kbit/s.
l Supports the flow classification based on PORT, PORT+VLAN
ID, or PORT+VLAN ID+VLAN PRI.
LCAS function Dynamically increases or decreases the bandwidth and protects the
bandwidth in compliance with ITU-T G.7042.
LPT function Supports the P2P LPT and P2MP LPT.
Flow control function Supports the port-based flow control function that complies with
IEEE 802.3x.
High-precision time
(IEEE 1588 V2)
Does not support the high-precision time.
Test frames Receives and transmits Ethernet test frames.
Port mirroring Supports ingress mirroring.
Loopback function Supports inloops on Ethernet ports (at the PHY layer or MAC layer).
Protection schemes Supports the following protection schemes at the Ethernet network
level:
l STP/RSTP
l LCAS
l LPT
l LAG
Ethernet performance
monitoring
Supports Ethernet performance monitoring at the port level.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.

11.5.4 Working Principle and Signal Flow
The EFS0A consists of the Ethernet access module, network processor module, mapping
module, interface converting module, logic and control module, clock module, and power
module.
Figure 11-25 shows the functional block diagram of the EFS0A by describing how to process
1xFE signals.
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Figure 11-25 Functional block diagram of the EFS0A
Ethernet
access
module
FE
Interface
converting
module
Mapping module
Control
Data
Switch
fabric
Network
processor
Network processor module
Logic and
control module
SCC unit
Communication
Reference clock and frame header
Clock module
77
MHz
125 155
MHz
LOS
Laser
shutdown
50
MHz
Cross-connect unit
+3.3 V backup power
+3.3 V
Power
module
Fuse
Fuse
-48 V/-60 V
-48 V/-60 V Power
module
E
N
C
P
V
C
P
D
E
N
C
P
MHz
Backplane
Cross-connect unit
SCC unit
ENCP: data encapsulation module DENCP: decapsulation module
VCP: virtual concatenation processing module

Ethernet Access Module
In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
Network Processor Module
The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The following formats are supported:
l MPLS
l L2 MPLS VPN
l Ethernet/VLAN
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In the receive direction, services are mapped and forwarded after the Tunnel and VC tags are
added according to the service configuration. In the transmit direction, the Tunnel or VC tag is
extracted based on the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module supports the following functions:
l Flow sense and flow classification
l Unicast, multicast, and broadcast of the flow
l Setting of data priorities
l WFQ
l Four CoSs
Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is performed. Then, the Ethernet signals are converted into SDH signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.
Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l Manages and configures other modules of the board.
l Implements inter-board communication through the internal Ethernet interface.
The control module also contains basic logic units. This module performs the following
functions:
l Writes and reads the register.
l Provides interfaces for the CPU.
l Checks and selects the clock.
l Performs phase discrimination and frequency division on the clock.
l Checks the in-service state of the cross-connect, SCC, and line boards.
l Controls the shutting down of the optical module.
l Implements communication.
l Controls indicators.
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Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
11.5.5 Front Panel
The front panel of the EFS0A has indicators and a bar code.
Diagram of the Front Panel
Figure 11-26 shows the appearance of the front panel of the EFS0A.
Figure 11-26 Front panel of the EFS0A
EFS0A
EFS0A
ACT
PROG
STAT
SRV
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Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the EFS0A has no interfaces. The interfaces are available on the ETF8 board
or on the EFF8 board.
11.5.6 Jumpers and DIP Switches
The EFS0A does not have any jumpers or DIP switches that are used for board settings.
11.5.7 Valid Slots
The EFS0A must be installed in a valid slot in the subrack. Otherwise, the EFS0A cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The EFS0A can be used with the ETF8, EFF8, and ETS8. When the ETS8 is used as the interface
board, the TSB8 must be used as the bridging board. For the slots valid for the EFS0A, ETS8,
and TSB8 when the EFS0A works with the ETS8 and TSB8, see 11.5.9 Board Protection.
The slots valid for the EFS0A vary with the cross-connect capacity of the subrack. The slots
valid for the EFS0A are as follows:
l When the cross-connect capacity is 200 Gbit/s, the EFS0A can be installed in slots 25 and
1316 in the subrack. In this case, the bandwidth is 2.5 Gbit/s.
Table 11-43 lists the slots valid for the EFS0A and the corresponding slots for the ETF8 and
EFF8.
Table 11-43 Slots valid for the EFS0A and the corresponding slots for the ETF8 and EFF8
Slot Valid for the EFS0A Corresponding Slot for the ETF8 and EFF8
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
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Slot Valid for the EFS0A Corresponding Slot for the ETF8 and EFF8
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

11.5.8 Feature Code
The EFS0A does not have the feature code.
11.5.9 Board Protection
The EFS0A supports the 1:1 TPS protection.
Figure 11-27 shows the slot configuration for the 1:1 TPS protection for the EFS0A.
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Figure 11-27 Slot configuration for the 1:1 TPS protection for the EFS0A
S
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7
FAN FAN
G
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A
U
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C
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E
T
S
8
T
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B
8
T
S
B
8
E
T
S
8
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8
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T
S
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8
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r
o
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2
P
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2

The board in slot 2 protects the board in slots 3 and the board in slot 16 protects the board in slot
15. The ETS8 is used with the working EFS0A and the TSB8 is used with the protection EFS0A.
Table 11-44 lists the slots for the EFS0A, ETS8, and TSB8.
Table 11-44 Slots for the EFS0A, ETS8, and TSB8
Board Protection Group 1 Protection Group 2
EFS0A (protection) Slot 2 Slot 16
EFS0A (working) Slot 3 Slot 15
TSB8 Slots 19 and 20 Slots 35 and 36
ETS8 Slots 21 and 22 Slots 33 and 34

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11.5.10 Parameter Settings
You can set parameters for the EFS0A by using the T2000.
You can set the following main parameters for the EFS0A by using the T2000:
l Working mode
l LCAS
l Maximum frame length
l Mapping protocol
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
11.5.11 Technical Specifications
The technical specifications of the EFS0A include the dimensions, weight, and power
consumption.
Ethernet Performance Specifications
NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EFS0A board of the N1 version.
Figure 11-28 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, latency specifications, and back-to-back specifications of the EFS0A.
Figure 11-28 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer

Table 11-45 lists the throughput specifications of the EFS0A. Table 11-46 lists the packet loss
ratio in the case of overloading of the EFS0A. Table 11-47 lists the latency specifications of the
EFS0A. Table 11-48 lists the back-to-back specifications of the EFS0A.
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NOTE
l The specifications vary according to the configuration and networking of the test environment, port
rate, and VC services bound on the VCG side. The specifications that are obtained in the actual
environment are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured, one VC-3 is bound on the FE port, and the MAC port is set to auto-negotiation mode.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-45 lists the throughput specifications of the EFS0A. The values are obtained when the
SmartApplication is set as follows:
l Test duration (sec): 3
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 53.33
l Maximum rate (%): 54.00
l Resolution rate (%): 0.01
l Mode: bidirectional
Table 11-45 Throughput specifications of the EFS0A
Frame Size
(Byte)
Passed Rate
(%)
(01,11,01) to
(01,11,02) (pks/
sec)
(01,11,02) to
(01,11,01) (pks/
sec)
Total (pks/
sec)
64 53.50 79618 79618 159236
128 51.21 43253 43253 86506
256 49.95 22624 22624 45248
512 49.31 11585 11585 23170
1024 49.14 5884 5884 11768
1280 49.15 4726 4726 9452
1518 49.19 3998 3998 7996

Table 11-46 lists the packet loss ratio in the case of overloading of the EFS0A. The values are
obtained when the SmartApplication is set as follows:
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l Test duration (sec): 10
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 11-46 Packet loss ratio in the case of overloading of the EFS0A
Frame Size
(Byte)
Rate Tested
(%)
(01,11,01) to
(01,11,02) (%)
(01,11,02) to
(01,11,01) (%)
Average (%)
64 100.00 46.497 46.497 46.497
128 100.00 48.820 48.820 48.820
256 100.00 50.127 50.127 50.127
512 100.00 50.804 50.804 50.804
1024 100.00 51.115 51.115 51.115
1280 100.00 51.159 51.159 51.159
1518 100.00 51.176 51.176 51.176

Table 11-47 lists the latency specifications of the EFS0A. The values are obtained when the
SmartApplication is set as follows:
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
l CT: cut through or FIFO; S&F: store forward or LIFO
l Measure on one receiving card only. Mode: SmartMetrics Comp. Mode
l Test duration (sec): 100
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
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l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 11-47 Latency specifications of the EFS0A
Frame
Size
(Byte)
Rate
Tested
(%)
(01,11,01) to
(01,11,02) (us)-
CT (us)
Average
(CT) (us)
(01,11,01) to
(01,11,02)
(us)-S&F (us)
Average
(S&F) (us)
64 40.00 164.3 164.3 159.2 159.2
128 40.00 199.0 199.0 188.8 188.8
256 40.00 247.0 247.0 226.6 226.6
512 40.00 357.6 357.6 357.6 357.6
1024 40.00 514.8 514.8 432.9 432.9
1280 40.00 613.1 613.1 510.7 510.7
1518 40.00 699.4 699.4 578.0 578.0

Table 11-48 lists the back-to-back specifications of the EFS0A. The values are obtained when
the SmartApplication is set as follows:
l Test duration (sec): 2
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 11-48 Back-to-back specifications of the EFS0A
Frame Size
(Byte)
Rate Tested
(%)
(01,11,01) to
(01,11,02) Burst
Size (Number of
Frames)
(01,11,02) to
(01,11,01)
(Number of
Frames)
Total
(Number of
Frames)
64 100.00 353 353 706
128 100.00 342 342 684
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Frame Size
(Byte)
Rate Tested
(%)
(01,11,01) to
(01,11,02) Burst
Size (Number of
Frames)
(01,11,02) to
(01,11,01)
(Number of
Frames)
Total
(Number of
Frames)
256 100.00 380 380 761
512 100.00 368 368 736
1024 100.00 282 282 564
1280 100.00 279 279 559
1518 100.00 291 291 582

Mechanical Specifications
The mechanical specifications of the EFS0A are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.7
Power Consumption
The maximum power consumption of the EFS0A at room temperature (25C) is 32 W.
11.6 EFS4
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EFS4 (4xFE switching and processing board). This topic also
describes how to configure and commission the EFS4.
11.6.1 Version Description
The EFS4 is available in three functional versions, namely, N1, N2 and N3. The difference
between the three versions is their different maximum uplink bandwidths. The N1EFS4 is
discontinued.
11.6.2 Application
The EFS4 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
11.6.3 Functions and Features
The EFS4 supports the Layer 2 switching, MPLS, and broadcast functions.
11.6.4 Working Principle and Signal Flow
The EFS4 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
11.6.5 Front Panel
The front panel of the EFS4 has indicators, interfaces, and a bar code.
11.6.6 Jumpers and DIP Switches
The EFS4 does not have any jumpers or DIP switches that are used for board settings.
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11.6.7 Valid Slots
The EFS4 must be installed in a valid slot in the subrack. Otherwise, the EFS4 cannot work
normally.
11.6.8 Feature Code
The EFS4 does not have the feature code.
11.6.9 Parameter Settings
You can set parameters for the EFS4 by using the T2000.
11.6.10 Technical Specifications
The technical specifications of the EFS4 include the dimensions, weight, and power
consumption.
11.6.1 Version Description
The EFS4 is available in three functional versions, namely, N1, N2 and N3. The difference
between the three versions is their different maximum uplink bandwidths. The N1EFS4 is
discontinued.
Table 11-49 describes the versions of the EFS4.
Table 11-49 Versions of the EFS4
Item Description
Functional versions The EFS4 is available in three functional versions, namely, N1, N2
and N3.
Differences l The maximum uplink bandwidth of the N1EFS4 is 622 Mbit/s.
l The maximum uplink bandwidth of the N2EFS4/N3EFS4 is 1.25
Gbit/s.
l The N2EFS4 and N3EFS4 support the board version replacement
function.
Substitution l The N2EFS4 can substitute for the N1EFS4.
l The N3EFS4 can substitute for the N2EFS4 and N1EFS4.

11.6.2 Application
The EFS4 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
Figure 11-29 shows the typical networking and application of the EFS4. The EFS4 accesses
and converges Ethernet services, and provides the Ethernet data with the following data features:
Layer 2 switching, port isolation, flow classification, traffic control, VLAN management, and
priority configuration. In addition, the EFS4 performs encapsulation/decapsulation, virtual
concatenation, and SDH mapping/demapping for data. The EFS4 can be interconnected with
the bandwidth access equipment and the data communication equipment at the same time, thus
to provide a network-level solution.
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Figure 11-29 Networking and application of the EFS4
NE1
NE2 NE4
NE3
User A2
User B2
User B1
User A1
NMS
PORT 1
VLAN 100
PORT 2
VLAN 100
PORT 2
VLAN 100
PORT 1 VLAN 100
Service flow
Line board
Cross-connect and
timing board
Data board
MSP ring

11.6.3 Functions and Features
The EFS4 supports the Layer 2 switching, MPLS, and broadcast functions.
Table 11-50 provides the functions and features of the EFS4.
Table 11-50 Functions and features of the EFS4
Function and
Feature
EFS4
Basic functions Processes 4xFE services.
Functions when
being used with the
interface board
Accesses 4xFE signals by providing interfaces on the front panel.
Specifications of
the optical interface
Supports 10BASE-T/100BASE-TX signals. The optical interfaces
comply with IEEE 802.3u.
Format of service
frames
l Supports Ethernet II, IEEE 802.3, and IEEE 802.1 q/p formats.
l Supports the frame with a length ranging from 64 bytes to 9600 bytes
and supports the Jumbo frame with a length less than 9600 bytes.
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Function and
Feature
EFS4
Maximum uplink
bandwidth
l The maximum uplink bandwidth of the N1EFS4 is 622 Mbit/s.
l The maximum uplink bandwidth of the N2EFS4 and N3EFS4 is 1.25
Gbit/s.
l The EFS4 can adapt to the bandwidth of the slot.
VCTRUNKs l The number of VCTRUNKs supported by the N1EFS4 is 12.
l The number of VCTRUNKs supported by the N2EFS4 and N3EFS4
is 24.
Configuration principles are as follows:
l VCTRUNK 1VCTRUNK 12 can be bound with VC-4s numbered
14 only. VCTRUNK 13VCTRUNK 24 can be bound with VC-4s
numbered 58 only.
l VC-4s numbered 4 and 8 support the binding of VC-3 and VC-12
paths. The other VC-4s support the binding of VC-3 paths only.
l A VC-4 cannot be bound with VC-3 and VC-12 paths at the same
time.
Mapping
granularities
Supports VC-12, VC-3, VC-12-Xv (X63), and VC-3-Xv (X12)
granularities.
Encapsulation
format
Supports the GFP-F protocol.
EPL services Supports the PORT-based transparent transmission.
EVPL services Supports PORT+VLAN-based EVPL services that use the frame
encapsulation formats of MartinioE and stack VLAN.
EPLAN services l Supports the P2MP converging service that is based on Layer 2.
l Supports the Layer 2 forwarding function.
l Supports switching on the client and SDH sides.
l Supports the self-learning of the source MAC address. The capacity
of the MAC address table is 16K. The aging time of the MAC
address can be set and queried.
l Supports the configuration of the static MAC route.
l The N1EFS4 and N3EFS4 support the query of the dynamic MAC
address.
l The N2EFS4 does not support the query of the dynamic MAC
address.
l Supports the creation, deletion, and query of the VB. The maximum
number of supported VBs is 16. The maximum number of logical
ports for each VB is 30.
l Queries the number of actually learnt MAC addresses based on VB
+VLAN or VB+LP.
l Supports the EPLAN services that are based on the IEEE 802.1d
MAC bridge.
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Function and
Feature
EFS4
EVPLAN services l Supports EVPLAN virtual bridges.
l Supports data isolation based on VB+VLAN.
l Supports the setting of a maximum of 4096 VLAN services.
l Supports the EVPLAN services that are based on the IEEE 802.1q
virtual bridge.
MTU Supports the setting of the packet length, which ranges from 1518 bytes
to 9600 bytes. After the setting becomes valid, the length of the packets
that exit the IP ports is restricted by the pre-set MTU.
MPLS Supports the MPLS.
VLAN Supports 4k VLANs. The VLAN technology complies with IEEE
802.1q/p.
RSTP Supports the broadcast packet suppression function and RSTP that
comply with IEEE 802.1w.
Link aggregation Supports manual link aggregation.
Multicast function
(IGMP snooping)
Supports the multicast function.
ETH-OAM
function
l The N1EFS4 does not support the ETH-OAM function.
l The N2EFS4 and N3EFS4 support CC for the multicast service, LB
test for the unicast service, LT test, LD, auto-negotiation, fault
diagnosis, and link performance detection. The ETH-OAM function
complies with IEEE 802.1ag and IEEE 802.3ah.
QoS function l Supports the CAR. The granularity is 64 kbit/s.
l The N1EFS4 supports the service classification based on PORT,
PORT+VLAN ID, or PORT+VLAN PRI.
l The N2EFS4 and N3EFS4 support the flow classification based on
PORT, PORT++VLAN ID, or PORT+VLAN ID+VLAN PRI.
LCAS function Dynamically increases or decreases the bandwidth and protects the
bandwidth in compliance with ITU-T G.7042.
LPT function l The N1EFS4 supports the P2P LPT.
l The N2EFS4 and N3EFS4 support the P2P LPT and P2MP LPT.
Flow control
function
Supports the port-based flow control function that complies with IEEE
802.3x.
High-precision time
(IEEE 1588 V2)
Does not support the high-precision time.
Test frames Receives and transmits Ethernet test frames.
Port mirroring Does not support the port mirroring function.
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Function and
Feature
EFS4
Loopback function Supports inloops on Ethernet ports (at the PHY layer or MAC layer).
Protection schemes Supports the following protection schemes at the Ethernet network
level:
l STP/RSTP
l LCAS
l LPT
l LAG
Ethernet
performance
monitoring
Supports Ethernet performance monitoring at the port level.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.

11.6.4 Working Principle and Signal Flow
The EFS4 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
Figure 11-30 shows the functional block diagram of the EFS4 by describing how to process
1xFE signals.
Figure 11-30 Functional block diagram of the EFS4
Ethernet
access
module
FE
Interface
converting
module
Mapping module
Control
Data
Switch
fabric
Network
processor
Network processor module
Logic and
control module
SCC unit
Communication
Reference clock and frame header
Clock module
77
MHz
125 155
MHz
LOS
50
MHz
Cross-connect unit
+3.3 V backup power
+3.3 V
Power
module
Fuse
Fuse
-48 V/-60 V
-48 V/-60 V Power
module
E
N
C
P
V
C
P
D
E
N
C
P
MHz
Backplane
Cross-connect unit
SCC unit
ENCP: data encapsulation module DENCP: decapsulation module
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VCP: virtual concatenation processing module

Ethernet Access Module
In the receive direction, the Ethernet access module accesses the Ethernet electrical signals from
Ethernet equipment such as switches or routers. At the PHY layer, the electrical signals are
decoded and the ETH_LOS alarm is detected. The electrical signals are converted from serial
signals into parallel signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded.
Network Processor Module
The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The following formats are supported:
l MPLS
l L2 MPLS VPN
l Ethernet/VLAN
In the receive direction, services are mapped and forwarded after the Tunnel and VC tags are
added according to the service configuration. In the transmit direction, the Tunnel or VC tag is
extracted based on the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module supports the following functions:
l Flow sense and flow classification
l Unicast, multicast, and broadcast of the flow
l Setting of data priorities
l WFQ
l Four CoSs
Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is performed. Then, the Ethernet signals are converted into SDH signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.
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Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l Manages and configures other modules of the board.
l Implements inter-board communication through the internal Ethernet interface.
The control module also contains basic logic units. This module performs the following
functions:
l Writes and reads the register.
l Provides interfaces for the CPU.
l Checks and selects the clock.
l Performs phase discrimination and frequency division on the clock.
l Checks the in-service state of the cross-connect, SCC, and line boards.
l Implements communication.
l Controls indicators.
Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
11.6.5 Front Panel
The front panel of the EFS4 has indicators, interfaces, and a bar code.
Diagram of the Front Panel
Figure 11-31 shows the appearance of the front panel of the EFS4.
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Figure 11-31 Front panel of the EFS4
EFS4
EFS4
ACT
PROG
STAT
SRV
FE1
FE2
FE3
FE4

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Connection status indicator (LINK) one color (green)
l Data receiving and transmission indicator (ACT) one color (orange)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the EFS4 has four FE interfaces. Table 11-51 describes the types and usage
of the interfaces of the EFS4.
Table 11-51 Interfaces of the EFS4
Interface Type of
Interface
Usage
FE1 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE2 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE3 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE4 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.

Table 11-52 describes the pins of the RJ-45 connector.
Table 11-52 Pins of the RJ-45 connector
Pin Description
1 Positive data transmit end
2 Negative data transmit end
3 Positive data receive end
4 Grounding
5 Grounding
6 Negative data receive end
7 Grounding
8 Grounding

11.6.6 Jumpers and DIP Switches
The EFS4 does not have any jumpers or DIP switches that are used for board settings.
11.6.7 Valid Slots
The EFS4 must be installed in a valid slot in the subrack. Otherwise, the EFS4 cannot work
normally.
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NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the EFS4 vary with the cross-connect capacity of the subrack.
The relation between the slots valid for the EFS4 and the bandwidth is as follows:
l When the cross-connect capacity is 200 Gbit/s, the EFS4 can be installed in slots 18 and
1117.
When the N1EFS4 is installed in slots 18 and 1117, the bandwidth is 622 Mbit/s.
When the N2EFS4 or N3EFS4 is installed in slots 18 and 1117, the bandwidth is 1.25
Gbit/s.
11.6.8 Feature Code
The EFS4 does not have the feature code.
11.6.9 Parameter Settings
You can set parameters for the EFS4 by using the T2000.
You can set the following main parameters for the EFS4 by using the T2000:
l Working mode
l LCAS
l Maximum frame length
l Mapping protocol
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
11.6.10 Technical Specifications
The technical specifications of the EFS4 include the dimensions, weight, and power
consumption.
Ethernet Performance Specifications
NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EFS4 board of the N2 version.
Figure 11-32 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, latency specifications, and back-to-back specifications of the
N2EFS4.
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Figure 11-32 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications of the N2EFS4
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer

Table 11-53 lists the throughput specifications of the N2EFS4. Table 11-54 lists the packet loss
ratio in the case of overloading of the N2EFS4. Table 11-55 lists the latency specifications of
the N2EFS4. Table 11-56 lists the back-to-back specifications of the N2EFS4.
NOTE
l The specifications vary according to the configuration and networking of the test environment, port
rate, and VC services bound on the VCG side. The specifications that are obtained in the actual
environment are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured and five VC-12s are bound on the FE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-53 lists the throughput specifications of the N2EFS4. The values are obtained when
the SmartApplication is set as follows:
l Test duration (sec): 10
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 10.00
l Maximum rate (%): 15.00
l Resolution rate (%): 0.01
l Mode: bidirectional
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Table 11-53 Throughput specifications of the N2EFS4
Frame Size
(Byte)
Passed Rate
(%)
(01,02,03) to
(01,02,05) (pks/
sec)
(01,02,05) to
(01,02,03) (pks/
sec)
Total (pks/
sec)
64 11.41 16984 16984 33968
128 11.18 9441 9441 18882
256 11.10 5026 5026 10052
512 11.09 2605 2605 5210
1024 11.00 1317 1317 2634
1280 11.09 1066 1066 2132
1518 11.07 900 900 1800

Table 11-54 lists the packet loss ratio in the case of overloading of the N2EFS4. The values are
obtained when the SmartApplication is set as follows:
l Test duration (sec): 10
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 11-54 Packet loss ratio in the case of overloading of the N2EFS4
Frame Size
(Byte)
Rate Tested
(%)
(01,02,03) to
(01,02,05) (%)
(01,02,05) to
(01,02,03) (%)
Average (%)
64 100.00 88.510 88.513 88.512
128 100.00 88.724 88.729 88.726
256 100.00 88.858 88.859 88.859
512 100.00 88.858 88.861 88.859
1024 100.00 88.888 88.914 88.901
1280 100.00 88.895 88.875 88.885
1518 100.00 88.870 88.871 88.870

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Table 11-55 lists the latency specifications of the N2EFS4. The values are obtained when the
SmartApplication is set as follows:
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
l CT: cut through or FIFO; S&F: store forward or LIFO
l Measure on one receiving card only. Mode: SmartMetrics Comp. Mode
l Test duration (sec): 10
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 10.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 11-55 Latency specifications of the N2EFS4
Frame
Size
(Byte)
Rate
Tested
(%)
(01,02,03) to
(01,02,05) (us)-
CT (us)
Average
(CT) (us)
(01,02,03) to
(01,02,05)
(us)-S&F (us)
Average
(S&F) (us)
64 10.00 586.1 586.1 581.0 581.0
128 10.00 644.4 644.4 634.2 634.2
256 10.00 726.3 726.3 705.9 705.9
512 10.00 969.0 969.0 928.1 928.1
1024 10.00 1382.6 1382.6 1300.6 1300.6
1280 10.00 1609.0 1609.0 1506.6 1506.6
1518 10.00 1804.9 1804.9 1683.4 1683.4

Table 11-56 lists the back-to-back specifications of the N2EFS4. The values are obtained when
the SmartApplication is set as follows:
l Test duration (sec): 10
l Minimum frame size (byte): 64
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l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 11-56 Back-to-back specifications of the N2EFS4
Frame Size
(Byte)
Rate Tested
(%)
(01,02,03) to
(01,02,05) Burst
Size (Number of
Frames)
(01,02,05) to
(01,02,03)
(Number of
Frames)
Total
(Number of
Frames)
64 100.00 1337 1339 2676
128 100.00 852 852 1704
256 100.00 583 583 1166
512 100.00 441 441 882
1024 100.00 225 228 453
1280 100.00 210 210 420
1518 100.00 200 200 400

NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EFS4 board of the N3 version.
Figure 11-33 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, latency specifications, and back-to-back specifications of the
N3EFS4.
Figure 11-33 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications of the N3EFS4
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer
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Table 11-57 lists the throughput specifications of the N3EFS4. Table 11-58 lists the packet loss
ratio in the case of overloading of the N3EFS4. Table 11-59 lists the latency specifications of
the N3EFS4. Table 11-60 lists the back-to-back specifications of the N3EFS4.
NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured and three VC-3s are bound on the FE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-57 lists the throughput specifications of the N3EFS4. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The permitted packet loss ratio is set to 0% and the resolution rate is set to 1%.
l The test duration is set to 5 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 100
l Maximum rate (%): None
l Mode: Uni-directional
Table 11-57 Throughput specifications of the N3EFS4
Frame Size
(byte)
Passed Rate (%) (01,04,01) to (01,04,02)
(pks/sec)
Total (pks/sec)
64 100.00 148810 148810
128 100.00 84459 84459
256 100.00 45290 45290
512 100.00 23496 23496
1024 100.00 11973 11973
1280 100.00 9615 9615
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Frame Size
(byte)
Passed Rate (%) (01,04,01) to (01,04,02)
(pks/sec)
Total (pks/sec)
1518 100.00 8127 8127

Table 11-58 lists the packet loss ratio in the case of overloading of the N3EFS4. The values are
obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The tested traffic starts from the throughput and increases to 100% in 10% steps.
l The test duration is set to 5 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): None
l Mode: Uni-directional
Table 11-58 Packet loss ratio in the case of overloading of the N3EFS4
Frame Size
(byte)
Rate Tested (%) (01,04,01) to (01,04,02)
(%)
Average (%)
64 100.00 0.000 0.000
128 100.00 0.000 0.000
256 100.00 0.000 0.000
512 100.00 0.000 0.000
1024 100.00 0.000 0.000
1280 100.00 0.000 0.000
1518 100.00 0.000 0.000

Table 11-59 lists the latency specifications of the N3EFS4. The values are obtained when the
SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The test duration is set to 5 seconds.
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
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when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
l Measure on one receiving card only
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): None
l Mode: Uni-directional
Table 11-59 Latency specifications of the N3EFS4
Frame
Size
(byte)
Rate
Tested
(%)
(01,04,01) to
(01,04,02) (us)-
CT (us)
Average
(CT) (us)
(01,04,01) to
(01,04,02)
(us)-S&F (us)
Average
(S&F) (us)
64 100.00 129.3 129.3 124.2 124.2
128 100.00 142.6 142.6 132.4 132.4
256 100.00 171.1 171.1 150.6 150.6
512 100.00 215.7 215.7 174.7 174.7
1024 100.00 298.4 298.4 216.5 216.5
1280 100.00 339.8 339.8 237.4 237.4
1518 100.00 374.7 374.7 253.3 253.3

Table 11-60 lists the back-to-back specifications of the N3EFS4. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 2 seconds, and the number of repetitions is set to
a value more than 1 on the SmartApplication.
l The tested traffic is set to the wire speed.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
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l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): None
l Mode: Uni-directional
Table 11-60 Back-to-back specifications of the N3EFS4
Frame Size
(byte)
Rate Tested (%) (01,01,03) to (01,01,06)
Burst Size (frames)
Total (frames)
64 100.00 297620 297620
128 100.00 168918 168918
256 100.00 90580 90580
512 100.00 46992 46992
1024 100.00 23946 23946
1280 100.00 19230 19230
1518 100.00 16254 16254

Mechanical Specifications
The mechanical specifications of the EFS4 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight of the N1EFS4 (kg): 1.0
l Weight of the N2EFS4 (kg): 1.0
l Weight of the N3EFS4 (kg): 0.6
Power Consumption
The maximum power consumption of the N1EFS4 at room temperature (25C) is 30 W.
The maximum power consumption of the N2EFS4 at room temperature (25C) is 30 W.
The maximum power consumption of the N3EFS4 at room temperature (25C) is 18 W.
11.7 EGS2
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EGS2 (2xGE switching and processing board). This topic also
describes how to configure and commission the EGS2.
11.7.1 Version Description
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The EGS2 is available in two functional versions, namely, N2 and N3.
11.7.2 Application
The EGS2 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
11.7.3 Functions and Features
The EGS2 supports the Layer 2 switching, MPLS, and broadcast functions.
11.7.4 Working Principle and Signal Flow
The EGS2 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
11.7.5 Front Panel
The front panel of the EGS2 has indicators, interfaces, a bar code, and a laser safety class label.
11.7.6 Jumpers and DIP Switches
The EGS2 does not have any jumpers or DIP switches that are used for board settings.
11.7.7 Valid Slots
The EGS2 must be installed in a valid slot in the subrack. Otherwise, the EGS2 cannot work
normally.
11.7.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGS2 indicates the type of interface.
11.7.9 Parameter Settings
You can set parameters for the EGS2 by using the T2000.
11.7.10 Technical Specifications
The technical specifications of the EGS2 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.
11.7.1 Version Description
The EGS2 is available in two functional versions, namely, N2 and N3.
Table 11-61 describes the versions of the EGS2.
Table 11-61 Versions of the EGS2
Item Description
Functional version The EGS2 is available in two functional versions, namely, N2 and N3.
Difference l The N2EGS2 supports the point-to-point LPT function.
l The N3EGS2 supports the point-to-point LPT function and the
point-to-multipoint LPT function.
l The N3EGS2 supports the board version replacement function.
Substitution The N3EGS2 can substitute for the N2EGS2.

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11.7.2 Application
The EGS2 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
Figure 11-34 shows the typical networking and application of the EGS2. The EGS2 accesses
and converges Ethernet services, and provides the Ethernet data with the following data features:
Layer 2 switching, port isolation, flow classification, traffic control, VLAN management, and
priority configuration. In addition, the EGS2 performs encapsulation/decapsulation, virtual
concatenation, and SDH mapping/demapping for data. The EGS2 can be interconnected with
the bandwidth access equipment and the data communication equipment at the same time, thus
to provide a network-level solution.
NOTE
When the service converging FE services into GE services is configured, the GE switching board can be
set only to the 1000M full-duplex mode, the VLAN of the convergence service is variable, and the binding
granularity can be at the VC-3 or VC-12 level.
Figure 11-34 Networking and application of the EGS2
NE1
NE2 NE4
NE3
User A2
User B2
User B1
User A1
NMS
PORT 1
VLAN 100
PORT 2
VLAN 100
PORT 2
VLAN 100
PORT 1 VLAN 100
Service flow
Line board
Cross-connect and
timing board
Data board
MSP ring

11.7.3 Functions and Features
The EGS2 supports the Layer 2 switching, MPLS, and broadcast functions.
Table 11-62 provides the functions and features of the EGS2.
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Table 11-62 Functions and features of the EGS2
Function and
Feature
EGS2
Basic functions Processes 2xGE services.
Functions when
being used with
the interface board
Accesses 2xGE signals by providing interfaces on the front panel.
Specifications of
the optical
interface
l Supports the 1000BASE-SX/LX/ZX/VX Ethernet optical interfaces.
The optical interfaces support the auto-negotiation function in
compliance with IEEE 802.3z. The optical interfaces use the SFP
optical module and support hot swapping. When the multi-mode
optical fiber is used, the maximum transmission distance is 550 m.
When the single-mode optical fiber is used, the maximum
transmission distance is 10 km. The optical modules that can meet
different requirements for the transmission distance such as 40 km
and 80 km can also be used.
l The N3EGS2 also supports the 1000BASE-T RJ-45 Ethernet
electrical interface. The electrical interface supports the auto-
negotiation function. The negotiated rate can be 10 Mbit/s, 100 Mbit/
s, or 1000 Mbit/s. The N3EGS2 uses the SFP electrical interface and
supports hot swapping. The maximum transmission distance is 100
m.
Format of service
frames
l Supports Ethernet II, IEEE 802.3, and IEEE 802.1q/p formats.
l Supports the frame with a length ranging from 64 bytes to 9600 bytes.
l Supports the Jumbo frame with a length less than 9600 bytes.
Maximum uplink
bandwidth
The maximum uplink bandwidth is 2.5 Gbit/s. The EGS2 can adapt to
the bandwidth of the slot.
VCTRUNKs Number of supported VCTRUNKs: 48
Configuration principles are as follows:
l VCTRUNK 1VCTRUNK 12 can be bound with VC-4s numbered
14 only. VCTRUNK13VCTRUNK 24 can be bound with VC-4s
numbered 58 only. VCTRUNK 25VCTRUNK 36 can be bound
with VC-4s numbered 912 only. VCTRUNK 37VCTRUNK 48 can
be bound with VC-4s numbered 1316 only.
l VC-4s numbered 4, 8, 12, and 16 support the binding of VC-3 and
VC-12 paths. The other VC-4s support the binding of VC-3 paths
only.
l A VC-4 cannot be bound with VC-3 and VC-12 paths at the same
time.
Mapping
granularities
Supports VC-12, VC-3, VC12-Xv (X63), and VC3-Xv (X12)
granularities.
Encapsulation
format
Supports the GFP-F protocol.
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Function and
Feature
EGS2
EPL services Supports the PORT-based transparent transmission.
EVPL services Supports PORT+VLAN-based EVPL services that use the frame
encapsulation formats of MartinioE and stack VLAN.
EPLAN services l Supports the P2MP converging service that is based on Layer 2.
l Supports the Layer 2 forwarding function.
l Supports switching on the client and SDH sides.
l Supports the self-learning of the source MAC address. The capacity
of the MAC address table is 16K. The aging time of the MAC address
can be set and queried.
l Supports the configuration of the static MAC route.
l Supports the creation, deletion, and query of the VB. The maximum
number of supported VBs is 2. The maximum number of logical ports
for each VB is 30.
l Supports the EPLAN services that are based on the IEEE 802.1d MAC
bridge.
EVPLAN services l Supports EVPLAN virtual bridges.
l Supports data isolation based on VB+VLAN.
l Supports the setting of a maximum of 4096 VLAN services.
l Supports the EVPLAN services that are based on the IEEE 802.1q
virtual bridge.
MTU Supports the setting of the packet length, which ranges from 1518 bytes
to 9600 bytes. After the setting becomes valid, the length of the packets
that exit the IP ports is restricted by the pre-set MTU.
MPLS Supports the MPLS.
VLAN Supports 4k VLANs. The VLAN technology complies with IEEE
802.1q/p.
RSTP Supports the broadcast packet suppression function and RSTP that
comply with IEEE 802.1w.
Link aggregation
function
Supports manual link aggregation.
Multicast function
(IGMP snooping)
Supports the multicast function.
ETH-OAM
function
l The N2EGS2 does not support the ETH-OAM function.
l The N3EGS2 supports CC for the multicast service, LB test for the
unicast service, LT test, LD, auto-negotiation, fault diagnosis, and
link performance detection. The ETH-OAM function complies with
IEEE 802.1ag and IEEE 802.3ah.
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Function and
Feature
EGS2
QoS function l Supports the CAR. The granularity is 64 kbit/s.
l Supports the flow classification based on PORT, PORT+VLAN ID,
or PORT+VLAN ID+VLAN PRI.
LCAS function Dynamically increases or decreases the bandwidth and protects the
bandwidth in compliance with ITU-T G.7042.
LPT function l The N2EGS2 supports the P2P LPT.
l The N3EGS2 supports the P2P LPT and P2MP LPT.
Flow control
function
Supports the port-based flow control function that complies with IEEE
802.3x.
High-precision
time (IEEE 1588
V2)
Does not support the high-precision time.
Test frames Receives and transmits Ethernet test frames.
Port mirroring The N3EGS2 supports ingress mirroring.
Loopback
function
l Supports inloops on Ethernet ports (at the PHY layer or MAC layer).
l The N2EGS2 supports inloops and outloops at the VC-3 level, but the
N3EGS2 does not support inloops and outloops at the VC-3 level.
Protection
schemes
Supports the following protection schemes at the Ethernet network level:
l STP/RSTP
l LCAS
l LPT
l LAG
Ethernet
performance
monitoring
Supports Ethernet performance monitoring at the port level.
Alarms and
performance
events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.

11.7.4 Working Principle and Signal Flow
The EGS2 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
Figure 11-35 shows the functional block diagram of the EGS2 by describing how to process
1xGE signals.
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Figure 11-35 Functional block diagram of the EGS2
Interface
converting
module
Ethernet
access
module
GE
Mapping module
Network processor module
Control
Data
Reference clock and frame header
Communication
Switch
fabric
Network
processor
Logic and
control module
Clock module
50
MHz
SCC unit
+3.3 V backup power
+3.3 V
Power
module
Fuse
Fuse
-48 V/-60 V
Cross-connect unit
Power
module
D
E
N
C
P
V
C
P
E
N
C
P
LOS
Laser
shutdown
77
MHz
125
MHz
155
MHz
Backplane
-48 V/-60 V
Cross-connect unit
SCC unit
ENCP: data encapsulation module DENCP: decapsulation module
VCP: virtual concatenation processing module

Ethernet Access Module
In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
Network Processor Module
The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The following formats are supported:
l MPLS
l L2 MPLS VPN
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l Ethernet/VLAN
In the receive direction, services are mapped and forwarded after the Tunnel and VC tags are
added according to the service configuration. In the transmit direction, the Tunnel or VC tag is
extracted based on the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module supports the following functions:
l Flow sense and flow classification
l Unicast, multicast, and broadcast of the flow
l Setting of data priorities
l WFQ
l Four CoSs
Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS or GFP format.
The concatenation is performed. Then, the Ethernet signals are converted into SDH signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.
Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l Manages and configures other modules of the board.
l Implements inter-board communication through the internal Ethernet interface.
The control module also contains basic logic units. This module performs the following
functions:
l Writes and reads the register.
l Provides interfaces for the CPU.
l Checks and selects the clock.
l Performs phase discrimination and frequency division on the clock.
l Checks the in-service state of the cross-connect, SCC, and line boards.
l Controls the shutting down of the optical module.
l Implements communication.
l Controls indicators.
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Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
11.7.5 Front Panel
The front panel of the EGS2 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 11-36 shows the appearance of the front panel of the N2EGS2/N3EGS2 that is installed
with the GE optical interface.
Figure 11-36 Front panel of the N2EGS2/N3EGS2 that is installed with the GE optical interface
EGS2
EGS2
ACT
PROG
SRV
STAT
O
U
T
1
I
N
1
CLASS 1
LASER
PRODUCT
O
U
T
2
I
N
2
LINK1
ACT1
LINK2
ACT2
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The N3EGS2 can also be installed with the GE electrical interface. Figure 11-37 shows the
appearance of the front panel of the N3EGS2 that is installed with the GE electrical interface.
Figure 11-37 Front panel of the N3EGS2 that is installed with the GE electrical interface
EGS2
EGS2
ACT
PROG
SRV
STAT
LINK1
ACT1
LINK2
ACT2
O
U
T
1
I
N
1
O
U
T
2
I
N
2

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Connection status indicator (LINK) one color (green)
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l Data receiving and transmission indicator (ACT) one color (orange)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the N2EGS2/N3EGS2 has two GE optical interfaces. Table 11-63 describes
the types and usage of the optical interfaces of the N2EGS2/N3EGS2.
Table 11-63 Optical interfaces of the N2EGS2/N3EGS2
Interface Type of
Interface
Usage
OUT1/IN1 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.
OUT2/IN2 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.

When the N3EGS2 is installed with the electrical interfaces, the two GE electrical interfaces are
of the same type and have the same usage. Table 11-64 describes the types and usage of the
electrical interfaces of the N3EGS2.
Table 11-64 Electrical interfaces of the N3EGS2
Interface Type of
Interface
Usage
GE RJ-45 (swappable) Transmits and receives 1000BASE-T signals.

Table 11-65 provides the pin assignments of the RJ-45 interface of the N3EGS2.
Table 11-65 Pin assignments of the RJ-45 interface of the N3EGS2
Pin Description
1 BI_DA+
2 BI_DA
3 BI_DB+
4 BI_DC+
5 BI_DC
6 BI_DB
7 BI_DD+
8 BI_DD
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11.7.6 Jumpers and DIP Switches
The EGS2 does not have any jumpers or DIP switches that are used for board settings.
11.7.7 Valid Slots
The EGS2 must be installed in a valid slot in the subrack. Otherwise, the EGS2 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the EGS2 and the bandwidth of the EGS2 vary with the cross-connect capacity
of the subrack and the version of the board. The slots valid for the EGS2 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the slots valid for the EGS2 are as follows:
The N2EGS2 can be installed in slots 18 and 1116. When the N2EGS2 is installed
in slots 14, 15, and 16, the bandwidth is 1.25 Gbit/s. When the N2EGS2 is installed in
slots 58 and 1114, the bandwidth is 2.5 Gbit/s.
The N3EGS2 can be installed in slots 18 and 1116. In this case, the bandwidth is 2.5
Gbit/s.
11.7.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGS2 indicates the type of interface.
Table 11-66 provides the relationship between the feature code of the EGS2 and the type of
interface.
Table 11-66 Relationship between the feature code of the EGS2 and the type of interface
Board Feature Code Type of Interface
SSN2EGS210 and
SSN2EGS310
10 1000BASE-SX (0.5 km)
SSN2EGS211 and
SSN2EGS311
11 1000BASE-LX (10 km)
SSN2EGS212 and
SSN2EGS312
12 1000BASE-VX (40 km)
SSN2EGS213 and
SSN2EGS213
13 1000BASE-ZX (80 km)
SSN3EGS214 14 1000BASE-T (100 m)

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11.7.9 Parameter Settings
You can set parameters for the EGS2 by using the T2000.
You can set the following main parameters for the EGS2 by using the T2000:
l Working mode
l LCAS
l Maximum frame length
l Mapping protocol
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
11.7.10 Technical Specifications
The technical specifications of the EGS2 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.
Parameter Specified for Optical Interfaces
NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EGS2 board of the N2 version.
Table 11-67 lists the parameters specified for the optical interfaces of the EGS2.
Table 11-67 Parameters specified for the optical interfaces of the EGS2
Parameter Value
Type of optical
interface
1000BASE-ZX
(80 km)
1000BASE-
VX (40 km)
1000BASE-
LX (10 km)
1000BASE-SX
(0.5 km)
Type of fiber Single-mode LC Single-mode
LC
Single-mode
LC
Multi-mode LC
Launched optical
power range
(dBm)
-2 to 5 -5 to 0 -11 to -3 -9.5 to 0
Operating
wavelength range
(nm)
1500 to 1580 1275 to 1350 1270 to 1355 770 to 860
Minimum
overload (dBm)
-3 -3 -3 0
Receiver
sensitivity (dBm)
-23 -22 -19 -17
Minimum
extinction ratio
(dB)
9 9 9 9
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Ethernet Electrical Interfaces
Table 11-68 lists the parameters specified for the electrical interfaces of the EGS2.
Table 11-68 Parameters specified for the electrical interfaces of the EGS2
Type of Interface Code Type
1000Base-T, RJ-45 4D-PAM5

WARNING
Only the EGS2 boards of the N3 version supports the GE electrical interfaces.
Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Ethernet Performance Specifications
NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EGS2 board of the N2 version.
Figure 11-38 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, latency specifications, and back-to-back specifications of the
N2EGS2.
Figure 11-38 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications of the N2EGS2
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer

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Table 11-69 lists the throughput specifications of the N2EGS2. Table 11-70 lists the packet loss
ratio in the case of overloading of the N2EGS2. Table 11-71 lists the latency specifications of
the N2EGS2. Table 11-72 lists the back-to-back specifications of the N2EGS2.
NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured and five VC-12s are bound on the GE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-69 lists the throughput specifications of the N2EGS2. The values are obtained when
the SmartApplication is set as follows:
l Test duration (sec): 10
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 1.00
l Maximum rate (%): 2.00
l Resolution rate (%): 0.01
l Mode: bidirectional
Table 11-69 Throughput specifications of the N2EGS2
Frame Size
(Byte)
Passed Rate
(%)
(01,01,01) to
(01,01,02) (pks/
sec)
(01,01,02) to
(01,01,01) (pks/
sec)
Total (pks/
sec)
64 1.15 17086 17086 34172
128 1.12 9501 9501 19002
256 1.12 5094 5094 10188
512 1.13 2660 2660 5320
1024 1.12 1346 1346 2692
1280 1.13 1088 1088 2176
1518 1.14 925 925 1850

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Table 11-70 lists the packet loss ratio in the case of overloading of the N2EGS2. The values are
obtained when the SmartApplication is set as follows:
l Test duration (sec): 10
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 11-70 Packet loss ratio in the case of overloading of the N2EGS2
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) (%)
(01,01,02) to
(01,01,01) (%)
Average (%)
64 100.00 98.846 98.846 98.846
128 100.00 98.869 98.868 98.868
256 100.00 98.874 98.875 98.874
512 100.00 98.866 98.863 98.865
1024 100.00 98.870 98.870 98.870
1280 100.00 98.863 98.861 98.862
1518 100.00 98.855 98.855 98.855

Table 11-71 lists the latency specifications of the N2EGS2. The values are obtained when the
SmartApplication is set as follows:
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
l CT: cut through or FIFO; S&F: store forward or LIFO
l Measure on one receiving card only. Mode: SmartMetrics Comp. Mode
l Test duration (sec): 10
l Minimum frame size (byte): 64
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l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 1.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 11-71 Latency specifications of the N2EGS2
Frame
Size
(Byte)
Rate
Tested
(%)
(01,01,01) to
(01,01,02) (us)-
CT (us)
Average
(CT) (us)
(01,01,01) to
(01,01,02)
(us)-S&F (us)
Average
(S&F) (us)
64 1.00 555.8 555.8 555.3 555.3
128 1.00 615.2 615.2 614.2 614.2
256 1.00 734.6 734.6 732.6 732.6
512 1.00 914.0 914.0 909.9 909.9
1024 1.00 1313.7 1313.7 1305.6 1305.6
1280 1.00 1523.1 1523.1 1512.9 1512.9
1518 1.00 1706.6 1706.6 1694.4 1694.4

Table 11-72 lists the back-to-back specifications of the N2EGS2. The values are obtained when
the SmartApplication is set as follows:
l Test duration (sec): 10
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
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Table 11-72 Back-to-back specifications of the N2EGS2
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,01,02) Burst
Size (Number of
Frames)
(01,01,02) to
(01,01,01)
(Number of
Frames)
Total
(Number of
Frames)
64 100.00 1236 1236 2472
128 100.00 1321 1323 2644
256 100.00 1070 1070 2140
512 100.00 934 934 1868
1024 100.00 468 468 936
1280 100.00 458 458 916
1518 100.00 450 453 903

NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EGS2 board of the N3 version.
Figure 11-39 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, latency specifications, and back-to-back specifications of the
N3EGS2.
Figure 11-39 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications of the N3EGS2
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer

Table 11-73 lists the throughput specifications of the N3EGS2. Table 11-74 lists the packet loss
ratio in the case of overloading of the N3EGS2. Table 11-75 lists the latency specifications of
the N3EGS2. Table 11-76 lists the back-to-back specifications of the N3EGS2.
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NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured and 12 VC-3s are bound on the GE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-73 lists the throughput specifications of the N3EGS2. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The permitted packet loss ratio is set to 0% and the resolution rate is set to 1%.
l The test duration is set to 10 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 58
l Maximum rate (%): 65
l Mode: Uni-directional
Table 11-73 Throughput specifications of the N3EGS2
Frame Size
(byte)
Passed Rate (%) (01,04,01) to (01,04,02)
(pks/sec)
Total (pks/sec)
64 60.00 892857 892857
128 58.73 496032 496032
256 57.98 262605 262605
512 58.08 136463 136463
1024 58.00 69444 69444
1280 58.04 55804 55804
1518 58.04 47170 47170

Table 11-74 lists the packet loss ratio in the case of overloading of the N3EGS2. The values are
obtained when the SmartApplication is set as follows:
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l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The tested traffic starts from the throughput and increases to 100% in 10% steps.
l The test duration is set to 10 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): None
l Mode: Uni-directional
Table 11-74 Packet loss ratio in the case of overloading of the N3EGS2
Frame Size
(byte)
Rate Tested (%) (01,04,01) to (01,04,02)
(%)
Average (%)
64 100.00 39.033 39.033
128 100.00 40.323 40.323
256 100.00 41.081 41.081
512 100.00 41.492 41.492
1024 100.00 41.703 41.703
1280 100.00 41.744 41.744
1518 100.00 41.769 41.769

Table 11-75 lists the latency specifications of the N3EGS2. The values are obtained when the
SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The test duration is set to 10 seconds.
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
l CT: Cut Through (or FIFO),S&F: Store & Forward (or LIFO)
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l Measure on one receiving card only, Mode: SmartMetrics Comp. Mode
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 1.00
l Maximum rate (%): 60.00
l Step rate (%): 10.00
l Resolution rate (%): None
l Mode: Uni-directional
Table 11-75 Latency specifications of the N3EGS2
Frame
Size
(byte)
Rate
Tested
(%)
(01,04,01) to
(01,04,02) (us)-
CT (us)
Average
(CT) (us)
(01,04,01) to
(01,04,02)
(us)-S&F (us)
Average
(S&F) (us)
64 60.00 89.9 89.9 89.4 89.4
128 58.73 94.8 94.8 93.8 93.8
256 57.98 97.4 97.4 95.3 95.3
512 58.08 108.9 108.9 104.9 104.9
1024 58.00 123.4 123.4 115.3 115.3
1280 58.04 129.2 129.2 119.0 119.0
1518 58.04 138.0 138.0 125.8 125.8

Table 11-76 lists the back-to-back specifications of the N3EGS2. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 2 seconds, and the number of repetitions is set to
a value more than 1 on the SmartApplication.
l The tested traffic is set to the wire speed.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 60.00
l Maximum rate (%): 10.00
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l Resolution rate (%): None
l Mode: Uni-directional
Table 11-76 Back-to-back specifications of the N3EGS2
Frame Size
(byte)
Rate Tested (%) (01,04,01) to (01,04,02)
Burst Size (frames)
Total (frames)
64 60.00 1785714 1785714
128 58.73 992064 992064
256 57.98 525210 525210
512 58.08 272926 272926
1024 58.00 138888 138888
1280 58.04 111608 111608
1518 58.04 94340 94340

Mechanical Specifications
The mechanical specifications of the EGS2 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight of the N2EGS2 (kg): 1.0
l Weight of the N3EGS2 (kg): 0.6
Power Consumption
The maximum power consumption of the N2EGS2 at room temperature (25C) is 43 W.
The maximum power consumption of the N3EGS2 at room temperature (25C) is 25 W.
11.8 EMS2
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EMS2 (2xGE and 16xFE switching and processing board). This
topic also describes how to configure and commission the EMS2.
11.8.1 Version Description
The EMS2 is available in one functional version, namely, N1.
11.8.2 Application
The EMS2 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
11.8.3 Functions and Features
The EMS2 supports the Layer 2 switching, link convergence, and multicast functions.
11.8.4 Working Principle and Signal Flow
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The EMS2 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
11.8.5 Front Panel
The front panel of the EMS2 has indicators, interfaces, a bar code, and a laser safety class label.
11.8.6 Jumpers and DIP Switches
The EMS2 does not have any jumpers or DIP switches that are used for board settings.
11.8.7 Valid Slots
The EMS2 must be installed in a valid slot in the subrack. Otherwise, the EMS2 cannot work
normally.
11.8.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EMS2 indicates the type of interface.
11.8.9 Parameter Settings
You can set parameters for the EMS2 by using the T2000.
11.8.10 Technical Specifications
The technical specifications of the EMS2 include the parameters specified for optical interfaces,
laser safety class, dimensions, weight, and power consumption.
11.8.1 Version Description
The EMS2 is available in one functional version, namely, N1.
11.8.2 Application
The EMS2 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
Figure 11-40 shows the typical networking and application of the EMS2. The EMS2 accesses
and converges Ethernet services, and provides the Ethernet data with the following data features:
Layer 2 switching, port isolation, flow classification, traffic control, VLAN management, and
priority configuration. In addition, the EMS2 performs encapsulation/decapsulation, virtual
concatenation, and SDH mapping/demapping for data. The EMS2 can be interconnected with
the bandwidth access equipment and the data communication equipment at the same time, thus
to provide a network-level solution.
NOTE
When the service converging FE services into GE services is configured, the GE switching board can be
set only to the 1000M full-duplex mode, the VLAN of the convergence service is variable, and the binding
granularity can be at the VC-3 or VC-12 level.
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Figure 11-40 Networking and application of the EMS2
NE1
NE2 NE4
NE3
User A2
User B2
User B1
User A1
NMS
PORT 1
VLAN 100
PORT 2
VLAN 100
PORT 2
VLAN 100
PORT 1 VLAN 100
Service flow
Line board
Cross-connect and
timing board
Data board
MSP ring

11.8.3 Functions and Features
The EMS2 supports the Layer 2 switching, link convergence, and multicast functions.
Table 11-77 provides the functions and features of the EMS2.
Table 11-77 Functions and features of the EMS2
Function and
Feature
EMS2
Basic functions Accesses and processes 2xGE services.
Processes 16xFE services.
Support point-to-multipoint convergence services.
Functions when being
used with the interface
board
l Accesses 16xFE signals through the electrical interface when the
EMS2 is used with the ETF8.
l Accesses 16xFE signals through the optical interface when the
EMS2 is used with the EFF8.
l Accesses 8xFE signals through the electrical interface and 8xFE
signals through the optical interface when the EMS2 is used with
the ETF8 and EFF8.
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Function and
Feature
EMS2
Specifications of the
optical interface
l Supports the 1000BASE-SX/LX/ZX/VX Ethernet optical
interfaces. The optical interfaces support the auto-negotiation
function in compliance with IEEE 802.3z. The optical interfaces
use the SFP optical module and support hot swapping. When the
multi-mode optical fiber is used, the maximum transmission
distance is 550 m. When the single-mode optical fiber is used, the
maximum transmission distance is 10 km. The optical modules
that can meet different requirements for the transmission distance
such as 40 km and 80 km can also be used.
l Supports the 1000BASE-T RJ-45 Ethernet electrical interface.
The electrical interface supports the auto-negotiation function.
The negotiated rate can be 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/
s. The board uses the SFP electrical interface and supports hot
swapping. The maximum transmission distance is 100 m.
l Supports 10BASE-T/100BASE-TX signals when the EMS2 is
used with the ETF8 and supports 100BASE-FX signals when the
EMS2 is used with the EFF8.
l The optical interfaces comply with IEEE 802.3u.
Format of service
frames
l Supports Ethernet II, IEEE 802.3, IEEE 802.1q/p formats.
l Supports the frame with a length ranging from 64 bytes to 9600
bytes.
l Supports the Jumbo frame with a length less than 9600 bytes.
Maximum uplink
bandwidth
2.5 Gbit/s
VCTRUNKs Number of supported VCTRUNKs: 48
Configuration principles are as follows:
l VCTRUNK 1VCTRUNK 12 can be bound with VC-4s
numbered 14 only. VCTRUNK13VCTRUNK 24 can be bound
with VC-4s numbered 58 only. VCTRUNK 25VCTRUNK 36
can be bound with VC-4s numbered 912 only. VCTRUNK 37
VCTRUNK 48 can be bound with VC-4s numbered 1316 only.
l VC-4s numbered 4, 8, 12, and 16 support the binding of VC-3 and
VC-12 paths. The other VC-4s support the binding of VC-3 paths
only.
l A VC-4 cannot be bound with VC-3 and VC-12 paths at the same
time.
Mapping granularities Supports the following virtual concatenation granularities: VC-12,
VC-3, VC-4, VC12-Xv (X63), VC3-Xv (X12), and VC-4-Xv
(X8).
Encapsulation format Supports the GFP-F protocol.
EPL services Supports PORT-based transparent transmission.
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Function and
Feature
EMS2
EVPL services The services that are based on the IEEE 802.1d MAC bridge are
referred to as EPLAN service.
l Supports EVPL services based on PORT+VLAN.
Supports a maximum of 4000 services that are accessed
through IP ports.
Supports a maximum of 4000 services that are accessed
through VCTRUNKs.
Supports a maximum of 8000 links.
l Supports QinQ-based EVPL services.
l Supports PORT-based service forwarding.
EPLAN l Supports the Layer 2 forwarding function.
l Supports switching on the client and SDH sides.
l Supports the blacklist that can contain 2K records and also the
static MAC address table that can contain 2K records. The sum
of the number of records in the blacklist and the number of
addresses in the static MAC address table must not exceed 2K.
l Supports the self-learning of the source MAC address. The
capacity of the MAC address table is 16K. The aging time of the
MAC address can be set and queried.
l Supports the configuration of the static MAC route.
l Supports the creation, deletion, and query of the VB. The
maximum number of supported VBs is 2.
l Supports the EPLAN services that are based on the IEEE 802.1d
MAC bridge, IEEE 802.1q, and IEEE 802.1ad.
EVPLAN l Support EVPLAN virtual bridges.
l Supports data isolation based on VB+VLAN.
l Supports the configuration of up to 4096 VLAN services.
l Supports the EVPLAN services that are based on the IEEE 802.1q
virtual bridge.
MTU Supports the setting of the packet length, which ranges from 1518
bytes to 9600 bytes. After the setting becomes valid, the length of
the packets that enter or exit the IP ports is restricted by the pre-set
MTU.
MPLS Support the MPLS.
VLAN l Supports VLAN and QinQ, and supports the addition, deletion,
and exchanging of VLAN tags. The function complies with IEEE
802.1q/p.
l Supports 4096 S-VLANs (04095) and 4096 C-VLANs (04095)
in the case of QinQ services.
l Supports 4095 VLANs (14095) in the case of EVPL services.
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Function and
Feature
EMS2
RSTP Supports the RSTP, which complies with IEEE 802.1w.
Link aggregation
function
Supports manual link aggregation.
Multicast function
(IGMP snooping)
Supports the multicast function.
ETH-OAM function Supports CC for the multicast service, LB test for the unicast service,
LT test, LD, auto-negotiation, fault diagnosis, and link performance
detection. The ETH-OAM function complies with IEEE 802.1ag and
IEEE 802.3ah.
QoS function l Supports the CAR. The granularity is 64 kbit/s.
l Supports the flow classification based on PORT, PORT+VLAN,
PORT+SVLAN, and PORT+VLAN+PRI.
LCAS function Dynamically increases or decreases the bandwidth and protects the
bandwidth in compliance with ITU-T G.7042.
LPT function Supports the P2P LPT and P2MP LPT.
Flow control function Supports the port-based flow control function that complies with
IEEE 802.3x.
High-precision time
(IEEE 1588 V2)
Does not support the high-precision time.
Test frames Supports test frames.
Port mirroring Supports ingress mirroring.
Loopback function Supports inloops on Ethernet ports (on the PHY layer).
Protection schemes Supports the following protection schemes at the Ethernet network
level:
l STP/RSTP
l LCAS
l LPT
l LAG
Ethernet performance
monitoring
Supports RMON of the Ethernet performance at the PORT level and
the VCTRUNK level.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.

11.8.4 Working Principle and Signal Flow
The EMS2 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
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Figure 11-41 shows the functional block diagram of the EMS2 by describing how to process
1xGE/FE signals.
Figure 11-41 Functional block diagram of the EMS2
Interface
converting
module
Ethernet
access
module
GE/FE
Mapping module
Network processor module
Control
Data
Reference clock and frame header
Communication
Switch
fabric
Network
processor
Logic and
control module
Clock module
50
MHz
SCC unit
+3.3 V
Power
module
Fuse
-48 V/-60 V
Cross-connect unit
Power
module
D
E
N
C
P
V
C
P
E
N
C
P
LOS
Laser
shutdown
77
MHz
125
MHz
155
MHz
Backplane
-48 V/-60 V
Cross-connect unit
SCC unit
ENCP: data encapsulation module DENCP: decapsulation module
VCP: virtual concatenation processing module

Ethernet Access Module
In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
Network Processor Module
The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The Ethernet/VLAN format is supported.
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The network processor module supports the following functions:
l Flow sense and flow classification
l Unicast, multicast, and broadcast of the flow
l Setting of data priorities
l WFQ
l Four CoSs
Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, GFP-F, or
HDLC format. The concatenation is performed. The LCAS function is supported. Then, the
Ethernet signals are converted into SDH signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.
Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l Manages and configures other modules of the board.
l Implements inter-board communication through the internal Ethernet interface.
The control module also contains basic logic units. This module performs the following
functions:
l Writes and reads the register.
l Provides interfaces for the CPU.
l Checks and selects the clock.
l Performs phase discrimination and frequency division on the clock.
l Checks the in-service state of the cross-connect, SCC, and line boards.
l Controls the shutting down of the optical module.
l Implements communication.
l Controls indicators.
Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.
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Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
11.8.5 Front Panel
The front panel of the EMS2 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 11-42 shows the appearance of the front panel of the EMS2 that is installed with the GE
optical interface.
Figure 11-42 Front panel of the EMS2 that is installed with the GE optical interface
EMS2
EMS2
ACT
PROG
SRV
STAT
O
U
T
1
I
N
1
CLASS 1
LASER
PRODUCT
O
U
T
2
I
N
2
LINK1
ACT1
LINK2
ACT2

Figure 11-43 shows the appearance of the front panel of the EMS2 that is installed with the GE
electrical interface.
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Figure 11-43 Front panel of the EMS2 that is installed with the GE electrical interface
EMS2
EMS2
ACT
PROG
SRV
STAT
LINK1
ACT1
LINK2
ACT2
O
U
T
1
I
N
1
O
U
T
2
I
N
2

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Connection status indicator (LINK) one color (green)
l Data receiving and transmission indicator (ACT) one color (orange)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the EMS2 has two interfaces. Table 11-78 describes the types and usage of
the interfaces of the EMS2 when the EMS2 is installed with the optical interfaces. When the
EMS2 is installed with the electrical interfaces, the two GE electrical interfaces are of the same
type and have the same usage. Table 11-79 describes the types and usage of the electrical
interfaces of the EMS2.
Table 11-78 Optical interfaces of the EMS2
Interface Type of
Interface
Usage
OUT1/IN1 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.
OUT2/IN2 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.

Table 11-79 Electrical interfaces of the EMS2
Interface Type of
Interface
Usage
GE RJ-45
(swappable)
Transmits and receives 1000BASE-T signals.

Table 11-80 provides the pin assignments of the RJ-45 interface of the EMS2.
Table 11-80 Pin assignments of the RJ-45 interface of the EMS2
Pin Description
1 BI_DA+
2 BI_DA
3 BI_DB+
4 BI_DC+
5 BI_DC
6 BI_DB
7 BI_DD+
8 BI_DD

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11.8.6 Jumpers and DIP Switches
The EMS2 does not have any jumpers or DIP switches that are used for board settings.
11.8.7 Valid Slots
The EMS2 must be installed in a valid slot in the subrack. Otherwise, the EMS2 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The EMS2 can be used with the ETF8 and EFF8.
The EMS2 can be installed in slots 16 and 1316 in the subrack. The slots valid for the EMS2
vary with the bandwidth and the cross-connect capacity of the subrack.
l When the cross-connect capacity is 200 Gbit/s, the EMS2 can be installed in slots 16 and
1316. In this case, the bandwidth is 2.5 Gbit/s.
Table 11-81 lists the slots valid for the EMS2 and the corresponding slots for the ETF8 and
EFF8.
Table 11-81 Slots valid for the EMS2 and the corresponding slots for the ETF8 and EFF8
Slot Valid for the EMS2 Corresponding Slots for the ETF8
and EFF8
Slot 1 Without an interface board
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 6 Without an interface board
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

11.8.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EMS2 indicates the type of interface.
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Table 11-82 provides the relationship between the feature code of the EMS2 and the type of
interface.
Table 11-82 Relationship between the feature code of the EMS2 and the type of interface
Board Feature Code Type of Interface
SSN1EMS210 10 1000BASE-ZX (80 km)
SSN1EMS211 11 1000BASE-SX (0.5 km)
SSN1EMS212 12 1000BASE-LX (10 km)
SSN1EMS213 13 1000BASE-VX (40 km)
SSN1EMS214 14 1000BASE-T (100 m)

11.8.9 Parameter Settings
You can set parameters for the EMS2 by using the T2000.
You can use set the following main parameters for the EMS2 by using the T2000:
l Working mode
l LCAS
l Maximum frame length
l Mapping protocol
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
11.8.10 Technical Specifications
The technical specifications of the EMS2 include the parameters specified for optical interfaces,
laser safety class, dimensions, weight, and power consumption.
Parameters Specified for Optical Interfaces
Table 11-83 lists the parameters specified for the optical interfaces of the EMS2.
Table 11-83 Parameters specified for the optical interfaces of the EMS2
Parameter Value
Type of optical
interface
1000BASE-ZX
(80 km)
1000BASE-
VX (40 km)
1000BASE-
LX (10 km)
1000BASE-SX
(0.5 km)
Type of fiber Single-mode LC Single-mode
LC
Single-mode
LC
Multi-mode LC
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Parameter Value
Launched optical
power range
(dBm)
-2 to 5 -5 to 0 -11 to -3 -9.5 to 0
Operating
wavelength range
(nm)
1500 to 1580 1275 to 1350 1270 to 1355 770 to 860
Minimum
overload (dBm)
-3 -3 -3 0
Receiver
sensitivity (dBm)
-23 -22 -19 -17
Minimum
extinction ratio
(dB)
9 9 9 9

Ethernet Performance Specifications
NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EMS2 board of the N1 version.
Figure 11-44 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, latency specifications, and back-to-back specifications of the EMS2.
Figure 11-44 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer

Table 11-84 and Table 11-85 list the throughput specifications of the EMS2. Table 11-86 and
Table 11-87 list the packet loss ratio in the case of overloading of the EMS2. Table 11-88 and
Table 11-89 list the latency specifications of the EMS2. Table 11-90 and Table 11-91 list the
back-to-back specifications of the EMS2.
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NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured and three VC-3s is bound on the FE port, or EPL services are configured and 48 VC-12s
are bound on the GE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-84 lists the throughput specifications of the EMS2 (three VC-3s is bound on the FE
port). The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.
l The test duration is set to 5 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): none
l Mode: Uni-directional
Table 11-84 Throughput specifications of the EMS2 (three VC-3s is bound on the FE port)
Frame Size
(byte)
Passed Rate (%) (01,09,01) to (01,09,02)
(pks/sec)
Total (pks/sec)
64 100.00 148810 148810
128 100.00 84459 84459
256 100.00 45290 45290
512 100.00 23496 23496
1024 100.00 11973 11973
1280 100.00 9615 9615
1518 100.00 8127 8127

Table 11-85 lists the throughput specifications of the EMS2 (48 VC-12s are bound on the GE
port). The values are obtained when the SmartApplication is set as follows:
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l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.
l The test duration is set to 60 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 100.00
l Resolution rate (%): 1.00
l Mode: Uni-directional
Table 11-85 Throughput specifications of the EMS2 (48 VC-12s are bound on the GE port)
Frame Size
(byte)
Passed Rate (%) (01,05,01) to (01,05,02)
(pks/sec)
Total (pks/sec)
64 11.41 169837 339674
128 10.82 91374 182748
256 10.19 46160 92320
512 10.20 23965 47930
1024 10.20 12212 24424
1280 10.20 9809 19618
1518 10.20 8288 16576

Table 11-86 lists the packet loss ratio in the case of overloading of the EMS2 (three VC-3s is
bound on the FE port). The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The tested traffic starts from the throughput and increases to 100% in 10% steps.
l The test duration is set to 5 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
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l Mode: Uni-directional
Table 11-86 Packet loss ratio in the case of overloading of the EMS2 (three VC-3s is bound on
the FE port)
Frame Size
(byte)
Rate Tested (%) (01,09,01) to (01,09,02)
(%)
Average (%)
64 100.00 0.000 0.000
128 100.00 0.000 0.000
256 100.00 0.000 0.000
512 100.00 0.000 0.000
1024 100.00 0.000 0.000
1280 100.00 0.000 0.000
1518 100.00 0.000 0.000

Table 11-87 lists the packet loss ratio in the case of overloading of the EMS2 (48 VC-12s are
bound on the GE port). The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The tested traffic starts from the throughput and increases to 100% in 10% steps.
l The test duration is set to 60 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 11.41
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: Uni-directional
Table 11-87 Packet loss ratio in the case of overloading of the EMS2 (48 VC-12s are bound on
the GE port)
Frame Size
(byte)
Rate Tested (%) (01,05,01) to (01,05,02)
(%)
Average (%)
64 11.41 0.000 0.000
128 10.82 0.000 0.000
256 10.19 0.000 0.000
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Frame Size
(byte)
Rate Tested (%) (01,05,01) to (01,05,02)
(%)
Average (%)
512 10.20 0.000 0.000
1024 10.20 0.000 0.000
1280 10.20 0.000 0.000
1518 10.20 0.000 0.000

Table 11-88 lists the latency specifications of the EMS2 (three VC-3s is bound on the FE port).
The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The test duration is set to 10 seconds.
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
l CT: cut through or FIFO; S&F: store forward or LIFO
l Measure on one receiving card only. Mode: SmartMetrics Comp. Mode
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: Uni-directional
Table 11-88 Latency specifications of the EMS2 (three VC-3s is bound on the FE port)
Frame
Size
(byte)
Rate
Tested
(%)
(01,09,01) to
(01,09,02) (us)-
CT (us)
Average
(CT) (us)
(01,09,01) to
(01,09,02)
(us)-S&F (us)
Average
(S&F) (us)
64 100.00 127.1 127.1 121.9 121.9
128 100.00 144.1 144.1 133.9 133.9
256 100.00 172.2 172.2 151.8 151.8
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Frame
Size
(byte)
Rate
Tested
(%)
(01,09,01) to
(01,09,02) (us)-
CT (us)
Average
(CT) (us)
(01,09,01) to
(01,09,02)
(us)-S&F (us)
Average
(S&F) (us)
512 100.00 215.3 215.3 174.4 174.4
1024 100.00 299.8 299.8 217.8 217.8
1280 100.00 341.7 341.7 239.3 239.3
1518 100.00 377.1 377.1 255.7 255.7

Table 11-89 lists the latency specifications of the EMS2 (48 VC-12s are bound on the GE port).
The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The test duration is set to 100 seconds.
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
l CT: cut through or FIFO; S&F: store forward or LIFO
l Measure on one receiving card only. Mode: SmartMetrics Comp. Mode
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 11.41
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: Uni-directional
Table 11-89 Latency specifications of the EMS2 (48 VC-12s are bound on the GE port)
Frame
Size
(byte)
Rate
Tested
(%)
(01,03,01) to
(01,03,02) (us)-
CT (us)
Average
(CT) (us)
(01,03,01) to
(01,03,02)
(us)-S&F (us)
Average
(S&F) (us)
64 11.41 657.9 657.9 657.4 657.4
128 10.82 663.9 663.9 662.8 662.8
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Frame
Size
(byte)
Rate
Tested
(%)
(01,03,01) to
(01,03,02) (us)-
CT (us)
Average
(CT) (us)
(01,03,01) to
(01,03,02)
(us)-S&F (us)
Average
(S&F) (us)
256 10.19 683.6 683.6 681.6 681.6
512 10.20 717.3 717.3 713.3 713.3
1024 10.20 789.6 789.6 781.5 781.5
1280 10.20 822.1 822.1 811.9 811.9
1518 10.20 846.9 846.9 834.8 834.8

Table 11-90 lists the back-to-back specifications of the EMS2 (three VC-3s is bound on the FE
port). The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 2 seconds, and the number of repetitions is set to
a value more than 1 on the Smart Application.
l The tested traffic is set to the wire speed.
l The test duration is set to 2 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: Uni-directional
Table 11-90 Back-to-back specifications of the EMS2 (three VC-3s is bound on the FE port)
Frame Size
(byte)
Rate Tested (%) (01,01,03) to (01,01,06)
Burst Size (frames)
Total (frames)
64 100.00 297620 297620
128 100.00 168918 168918
256 100.00 90580 90580
512 100.00 46992 46992
1024 100.00 23946 23946
1280 100.00 19230 19230
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Frame Size
(byte)
Rate Tested (%) (01,01,03) to (01,01,06)
Burst Size (frames)
Total (frames)
1518 100.00 16254 16254

Table 11-91 lists the back-to-back specifications of the EMS2 (48 VC-12s are bound on the GE
port). The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 2 seconds, and the number of repetitions is set to
a value more than 1 on the Smart Application.
l The tested traffic is set to the wire speed.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 11.41
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: Uni-directional
Table 11-91 Back-to-back specifications of the EMS2 (48 VC-12s are bound on the GE port)
Frame Size
(byte)
Rate Tested (%) (01,03,01) to (01,03,02)
Burst Size (frames)
Total (frames)
64 11.41 339674 679348
128 10.82 182748 365496
256 10.19 92320 184640
512 10.20 47930 95860
1024 10.20 24424 48848
1280 10.20 19610 39220
1518 10.20 16576 33152

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
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Mechanical Specifications
The mechanical specifications of the EMS2 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.8
Power Consumption
The maximum power consumption of the EMS2 at room temperature (25C) is 40 W.
11.9 EMS4
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EMS4 (4xGE and 16xFE switching and processing board). This
topic also describes how to configure and commission the EMS4.
11.9.1 Version Description
The EMS4 is available in one functional version, namely, N1.
11.9.2 Application
The EMS4 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
11.9.3 Functions and Features
The EMS4 supports the Layer 2 switching, link convergence, and multicast functions.
11.9.4 Working Principle and Signal Flow
The EMS4 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
11.9.5 Front Panel
The front panel of the EMS4 has indicators, interfaces, a bar code, and a laser safety class label.
11.9.6 Jumpers and DIP Switches
The EMS4 does not have any jumpers or DIP switches that are used for board settings.
11.9.7 Valid Slots
The EMS4 must be installed in a valid slot in the subrack. Otherwise, the EMS4 cannot work
normally.
11.9.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EMS4 indicates the type of interface.
11.9.9 Board Protection
The EMS4 supports the BPS, PPS, and distributed link aggregation group (DLAG) protection.
11.9.10 Parameter Settings
You can set parameters for the EMS4 by using the T2000.
11.9.11 Technical Specifications
The technical specifications of the EMS4 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.
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11.9.1 Version Description
The EMS4 is available in one functional version, namely, N1.
11.9.2 Application
The EMS4 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
Figure 11-45 shows the typical networking and application of the EMS4. The EMS4 accesses
and converges Ethernet services, and provides the Ethernet data with the following data features:
Layer 2 switching, port isolation, flow classification, traffic control, VLAN management, and
priority configuration. In addition, the EMS4 performs encapsulation/decapsulation, virtual
concatenation, and SDH mapping/demapping for data. The EMS4 can be interconnected with
the bandwidth access equipment and the data communication equipment at the same time, thus
to provide a network-level solution.
NOTE
When the service converging FE services into GE services is configured, the GE switching board can be
set only to the 1000M full-duplex mode, the VLAN of the convergence service is variable, and the binding
granularity can be at the VC-3 or VC-12 level.
Figure 11-45 Networking and application of the EMS4
NE1
NE2 NE4
NE3
User A2
User B2
User B1
User A1
NMS
PORT 1
VLAN 100
PORT 2
VLAN 100
PORT 2
VLAN 100
PORT 1 VLAN 100
Service flow
Line board
Cross-connect and
timing board
Data board
MSP ring

11.9.3 Functions and Features
The EMS4 supports the Layer 2 switching, link convergence, and multicast functions.
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Table 11-92 provides the functions and features of the EMS4.
Table 11-92 Functions and features of the EMS4
Function and Feature EMS4
Basic functions Accesses and processes 4xGE services
Processes 16xFE services.
Supports point-to-multipoint convergence services.
Functions when being
used with the interface
board
l Accesses 16xFE signals through the electrical interface when
the EMS4 is used with the ETF8.
l Accesses 16xFE signals through the optical interface when the
EMS4 is used with the EFF8.
l Accesses 8xFE signals through the electrical interface and
8xFE signals through the optical interface when the EMS4 is
used with the ETF8 and EFF8.
Specifications of the
optical interface
l Supports the 1000BASE-SX/LX/ZX/VX Ethernet optical
interfaces. The optical interfaces support the auto-negotiation
function in compliance with IEEE 802.3z. The optical
interfaces use the SFP optical module and support hot
swapping. When the multi-mode optical fiber is used, the
maximum transmission distance is 550 m. When the single-
mode optical fiber is used, the maximum transmission distance
is 10 km. The optical modules that can meet different
requirements for the transmission distance such as 40 km and
80 km can also be used.
l Supports the 1000BASE-T RJ-45 Ethernet electrical interface.
The electrical interface supports the auto-negotiation function.
The negotiated rate can be 10 Mbit/s, 100 Mbit/s, or. 1000 Mbit/
s. The EMS4 uses the SFP electrical interface and supports hot
swapping. The maximum transmission distance is 100 m.
l Supports 10BASE-T/100BASE-TX signals when the EMS4 is
used with the ETF8 and supports 100BASE-FX signals when
the EMS4 is used with the EFF8.
l The optical interfaces comply with IEEE 802.3u.
Format of service frames l Supports Ethernet II, IEEE 802.3, IEEE 802.1q/p formats.
l Supports the frame with a length ranging from 64 bytes to 9216
bytes.
l Supports the Jumbo frame with a length less than 9216 bytes.
Maximum uplink
bandwidth
2.5 Gbit/s.
Number of supported
VCTRUNKs
64
Mapping granularities Supports the following virtual concatenation granularities:
VC-12, VC-3, VC-4, VC12-Xv (X64), VC3-Xv (X24), and
VC4-Xv (X8).
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Function and Feature EMS4
Encapsulation format Supports the GFP-F, LAPS, and HDLG protocols.
EPL services Supports PORT-based transparent transmission.
Supports 4000 bidirectional services.
EVPL services l Supports EVPL services based on PORT+VLAN.
Supports a maximum of 4000 services that are accessed
through IP ports.
Supports a maximum of 4000 services that are accessed
through VCTRUNKs.
Supports a maximum of 8000 links.
l Supports QinQ-based EVPL services.
l Supports PORT-based service forwarding.
EPLAN services l Supports the Layer 2 forwarding function.
l Supports switching on the client and SDH sides.
l Supports the blacklist that can contain 512 records and also the
static MAC address table that can contain 512 records.
l Supports the self-learning of the source MAC address. The
capacity of the MAC address table is 128K. The aging time of
the MAC address can be set and queried.
l Supports the configuration of the static MAC route.
l Supports the creation, deletion, and query of the VB. The
maximum number of supported VBs is 2.
l Supports the EPLAN services that are based on the IEEE
802.1d MAC bridge.
EVPLAN services l Supports data isolation based on VB+VLAN.
l Supports the setting of a maximum of 4000 VLAN services.
l Supports the EVPLAN services that are based on the IEEE
802.1q virtual bridge and IEEE 802.1ad provider bridge.
MTU Supports the setting of the packet length, which ranges from 1518
bytes to 9216 bytes. After the setting becomes valid, the length of
the packets that enter the IP ports is restricted by the pre-set MTU.
MPLS Does not support the MPLS.
VLAN l Supports VLAN and QinQ, and supports the addition, deletion,
and exchanging of VLAN tags. The function complies with
IEEE 802.1q/p.
l Supports 4096 S-VLANs (04095) and 4096 C-VLANs (0
4095) in the case of QinQ services.
l Supports 4095 VLANs (14095) in the case of EVPL services.
RSTP Supports the RSTP, which complies with IEEE 802.1w.
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Function and Feature EMS4
Multiple Spanning Tree
Protocol (MSTP)
Supports the MSTP.
Link aggregation
function
Supports manual link aggregation and static link aggregation.
Inter-board link
aggregation
Supports inter-board link aggregation.
Multicast function
(IGMP snooping)
Supports the multicast function.
ETH-OAM function Supports CC for the multicast service, LB test for the unicast
service, remote loopback, auto-negotiation, LD, fault diagnosis,
and link performance detection. The ETH-OAM function
complies with IEEE 802.1ag and IEEE 802.3ah.
QoS function l Supports the CAR. The granularity is 64 kbit/s.
l Supports the flow classification based on PORT, PORT
+VLAN, or PORT+SVLAN.
LCAS function Dynamically increases or decreases the bandwidth and protects
the bandwidth in compliance with ITU-T G.7042.
LPT function l Supports the P2P LPT and P2MP LPT.
l Supports the setting of the LPT revertive mode. Based on the
revertive mode, the RNC shutdown mode can be set.
Flow control function Supports the port-based flow control function that complies with
IEEE 802.3x.
High-precision time
(IEEE 1588 V2)
Does not support the high-precision time.
Test frames Supports test frames.
Port mirroring Does not support the port mirroring function.
Loopback function Supports inloops on Ethernet ports (at the PHY layer).
Protection schemes Supports the following protection schemes at the Ethernet
network level:
l BPS/PPS/DLAG
l STP/RSTP
l LCAS
l LPT
l LAG
Ethernet performance
monitoring
Supports RMON of the Ethernet performance at the PORT level
and the VCTRUNK level.
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Function and Feature EMS4
Alarms and performance
events
Reports various alarms and performance events, which facilitates
management and maintenance of the equipment.

11.9.4 Working Principle and Signal Flow
The EMS4 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
Figure 11-46 shows the functional block diagram of the EMS4 by describing how to process
1xGE/FE signals.
Figure 11-46 Functional block diagram of the EMS4
Interface
converting
module
Ethernet
access
module
GE/FE
Mapping module
Network processor module
Control
Data
Reference clock and frame header
Communication
Switch
fabric
Network
processor
Logic and
control module
Clock module
50
MHz
SCC unit
+3.3 V
Power
module
Fuse
-48 V/-60 V
Cross-connect unit
Power
module
D
E
N
C
P
V
C
P
E
N
C
P
LOS
Laser
shutdown
77
MHz
125
MHz
155
MHz
Backplane
-48 V/-60 V
Cross-connect unit
SCC unit
ENCP: data encapsulation module DENCP: decapsulation module
VCP: virtual concatenation processing module

Ethernet Access Module
In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
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In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
Network Processor Module
The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The Ethernet/VLAN format is supported.
The network processor module supports the following functions:
l Flow sense and flow classification
l Unicast, multicast, and broadcast of the flow
l Setting of data priorities
l WFQ
l Four CoSs
Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, GFP-F, or
HDLC format. The concatenation is performed. The LCAS function is supported. Then, the
Ethernet signals are converted into SDH signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.
Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l Manages and configures other modules of the board.
l Implements inter-board communication through the internal Ethernet interface.
The control module also contains basic logic units. This module performs the following
functions:
l Writes and reads the register.
l Provides interfaces for the CPU.
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l Checks and selects the clock.
l Performs phase discrimination and frequency division on the clock.
l Checks the in-service state of the cross-connect, SCC, and line boards.
l Controls the shutting down of the optical module.
l Implements communication.
l Controls indicators.
Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
11.9.5 Front Panel
The front panel of the EMS4 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 11-47 shows the appearance of the front panel of the EMS4 that is installed with the GE
optical interface.
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Figure 11-47 Front panel of the EMS4 that is installed with the GE optical interface
EMS4
EMS4
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4
1
LINK
2
3
4
ACT

Figure 11-48 shows the appearance of the front panel of the EMS4 that is installed with the GE
electrical interface.
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Figure 11-48 Front panel of the EMS4 that is installed with the GE electrical interface
EMS4
EMS4
ACT
PROG
STAT
SRV
1
LINK
2
3
4
ACT
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Connection status indicator (LINK) one color (green)
l Data receiving and transmission indicator (ACT) one color (orange)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the EMS4 has four interfaces. Table 11-93 describes the types and usage of
the optical interfaces of the EMS4. When the EMS4 is installed with the electrical interfaces,
the four GE electrical interfaces are of the same type and have the same usage. Table 11-94
describes the types and usage of the electrical interfaces of the EMS4.
Table 11-93 Optical interfaces of the EMS4
Interface Type of
Interface
Usage
OUT1/IN1 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.
OUT2/IN2 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.
OUT3/IN3 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.
OUT4/IN4 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.

Table 11-94 Electrical interfaces of the EMS4
Interface Type of
Interface
Usage
GE RJ-45
(swappable)
Transmits and receives 1000BASE-T signals.

Table 11-95 provides the pin assignments of the RJ-45 interface of the EMS4.
Table 11-95 Pin assignments of the RJ-45 interface of the EMS4
Pin Description
1 BI_DA+
2 BI_DA
3 BI_DB+
4 BI_DC+
5 BI_DC
6 BI_DB
7 BI_DD+
8 BI_DD
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11.9.6 Jumpers and DIP Switches
The EMS4 does not have any jumpers or DIP switches that are used for board settings.
11.9.7 Valid Slots
The EMS4 must be installed in a valid slot in the subrack. Otherwise, the EMS4 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The EMS4 can be used with the ETF8 and EFF8.
The EMS4 can be installed in slots 16 and 1316 in the subrack. The slots valid for the EMS4
vary with the bandwidth and cross-connect capacity of the subrack.
l When the cross-connect capacity is 200 Gbit/s, the EMS4 can be installed in slots 16 and
1316. When the EMS4 is installed in slots 14, 15, and 16, the bandwidth is 1.25 Gbit/s.
When the EMS4 is installed in slots 5, 6, 13, and 14, the bandwidth is 2.5 Gbit/s.
Table 11-96 lists the slots valid for the EMS4 and the corresponding slots for the ETF8 and
EFF8.
Table 11-96 Slots valid for the EMS4 and the corresponding slots for the ETF8 and EFF8
Slot Valid for the EMS4 Corresponding Slots for the ETF8
and EFF8
Slot 1 Without an interface board
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 6 Without an interface board
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

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11.9.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EMS4 indicates the type of interface.
Table 11-97 provides the relationship between the feature code of the EMS4 and the type of
interface.
Table 11-97 Relationship between the feature code of the EMS4 and the type of interface
Board Feature Code Type of Interface
SSN1EMS410 10 1000BASE-LX (0.5 km)
SSN1EMS411 11 1000BASE-SX (10 km)
SSN1EMS412 12 1000BASE-VX (40 km)
SSN1EMS413 13 1000BASE-ZX (80 km)
SSN1EMS414 14 1000BASE-T (100 m)

11.9.9 Board Protection
The EMS4 supports the BPS, PPS, and distributed link aggregation group (DLAG) protection.
Protection Principle
When the BPS protection is provided for the EMS4, the GE and FE ports are protected by using
the single-fed and selective-receiving scheme. The EMS4 has four GE ports and 16 FE ports
and hence may be connected to many sets of communication equipment. Normally, the active
board is working and services are transmitted in two directions of the active link. On the standby
link, the EMS4 disables the transmission of all ports. In this case, the ports of the opposite board
are in the link-down state. In addition, the opposite board enables the transmission but does not
transmit services. In this manner, the receive ports of the standby EMS4 are not in the link-down
state. The solid lines in Figure 11-49 show how the EMS4 normally works.
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Figure 11-49 Normal working of the EMS4
EMS4
Active
EMS4
Standby
XCS
No.1
No.2
No.3
No.1
No.2
No.3
Active
communication
equipment
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment
A
B
C

l BPS Protection
When the BPS protection is provided, if the active board detects the link-down state of any link,
any fault in the board, or the offline state of any board, the cross-connect board switches all the
services to the standby board. In this manner, services are protected. The solid lines in Figure
11-50 show how the BPS protection functions. The services numbered 1, 2 and 3 are all switched
to the standby EMS4 and the corresponding communication equipment.
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Figure 11-50 Principle of the BPS protection for the EMS4
EMS4
Active
EMS4
Standby
XCS
No.1
No.2
No.3
No.1
No.2
No.3
Active
communication
equipment
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment
A
B
C

l PPS Protection
When the PPS protection is provided, if the active board detects the link-down state of any link,
the cross-connect board switches all the services to the standby board. In this manner, services
are protected. The solid lines in Figure 11-51 show how the PPS protection functions. Only the
service numbered 1 is switched to the standby EMS4 and the standby communication equipment.
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Figure 11-51 Principle of the PPS protection for the EMS4
EMS4
Active
EMS4
Standby
XCS
No.1
No.2
No.3
No.1
No.2
No.3
Active
communication
equipment
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment
A
B
C

NOTE
In the case of the PPS, when a link failure occurs on a port, only the link services on the port are switched
generally. If the services of two ports are associated, for example, the services of port IP1 and port IP2 are
converged into the same VCTRUNK, port IP1 and port IP2 are defined as associated ports. When one port
of the associated ports is faulty, the services of the entire associated port group are switched.
l DLAG Protection
The DLAG is a group where the two mapping ports on two identical boards are aggregated to
from a protection group, thus providing 1+1 protection for the ports. By default, the port on the
active board is working, and the port on the standby board is protecting the working port.
When the DLAG is configured, the cross-connect board switches all services from the active
board to the standby board if the active board detects a link failure on a port, a board offline
event, or a board hardware failure. As shown in Figure 11-52, the services carried on port 1 are
switched to port 1 of the standby EMS4 and the associated equipment.
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Figure 11-52 Principle of the DLAG protection for the EMS4
EMS4
1#
A
B
C
XCS
PORT1
PORT2
PORT3
PORT1
PORT2
PORT3
VCG
VCG
2#
3#
1#
2#
3#
EMS4
Active
communication
equipment
Active
Standby
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment

WARNING
When the board-level protection is performed, the FE ports support only the 100M full-duplex
mode and the GE optical ports support the auto-negotiation and 1000M full-duplex mode.
Board Configuration
Two EMS4 boards should be configured on an NE to provide the board-level protection. One
EMS4 is the active board and the other is the standby board. When you configure the EMS4
board protection, ensure that the access capacity of the slot that houses the standby board must
not be less than the access capacity of the slot that houses the active board.
11.9.10 Parameter Settings
You can set parameters for the EMS4 by using the T2000.
You can set the following main parameters for the EMS4 by using the T2000:
l Working mode
l LCAS
l Maximum frame length
l Mapping protocol
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
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11.9.11 Technical Specifications
The technical specifications of the EMS4 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.
Parameters Specified for Optical Interfaces
Table 11-98 lists the parameters specified for the optical interfaces of the EMS4.
Table 11-98 Parameters specified for the optical interfaces of the EMS4
Parameter Value
Type of optical
interface
1000BASE-ZX
(80 km)
1000BASE-
VX (40 km)
1000BASE-
LX (10 km)
1000BASE-SX
(0.5 km)
Type of fiber Single-mode LC Single-mode
LC
Single-mode
LC
Multi-mode LC
Launched optical
power range
(dBm)
-2 to 5 -5 to 0 -11 to -3 -9.5 to 0
Operating
wavelength range
(nm)
1500 to 1580 1275 to 1350 1270 to 1355 770 to 860
Minimum
overload (dBm)
-3 -3 -3 0
Receiver
sensitivity (dBm)
-23 -22 -19 -17
Minimum
extinction ratio
(dB)
9 9 9 9

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Ethernet Performance Specifications
NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EMS4 board of the N1 version.
Figure 11-53 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, latency specifications, and back-to-back specifications of the EMS4.
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Figure 11-53 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer

Table 11-99 and Table 11-100 list the throughput specifications of the EMS4. Table 11-101
and Table 11-102 list the packet loss ratio in the case of overloading of the EMS4. Table
11-103 and Table 11-104 list the latency specifications of the EMS4. Table 11-105 and Table
11-106 list the back-to-back specifications of the EMS4.
NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured and one VC-4 is bound on the FE port, or EPL services are configured and 24 VC-3s are
bound on the GE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-99 lists the throughput specifications of the EMS4 (one VC-4 is bound on the FE port).
The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.
l The test duration is set to 60 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): none
l Mode: Uni-directional
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Table 11-99 Throughput specifications of the EMS4 (one VC-4 is bound on the FE port)
Frame Size
(Byte)
Passed Rate (%) (01,01,03) to (01,01,06)
(pks/sec)
Total (pks/sec)
64 100.00 148810 148810
128 100.00 84459 84459
256 100.00 45290 45290
512 100.00 23496 23496
1024 100.00 11973 11973
1280 100.00 9615 9615
1518 100.00 8127 8127

Table 11-100 lists the throughput specifications of the EMS4 (24 VC-3s are bound on the GE
port). The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.
l The test duration is set to 60 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 100.00
l Resolution rate (%): 1.00
l Mode: Uni-directional
Table 11-100 Throughput specifications of the EMS4 (24 VC-3s are bound on the GE port)
Frame Size
(Byte)
Passed Rate (%) (01,03,01) to (01,03,02)
(pks/sec)
Total (pks/sec)
64 100.00 1488095 1488095
128 100.00 844595 844595
256 100.00 452899 452899
512 100.00 234962 234962
1024 100.00 119732 119732
1280 100.00 96154 96154
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Frame Size
(Byte)
Passed Rate (%) (01,03,01) to (01,03,02)
(pks/sec)
Total (pks/sec)
1518 100.00 81274 81274

Table 11-101 lists the packet loss ratio in the case of overloading of the EMS4 (one VC-4 is
bound on the FE port). The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The tested traffic starts from the throughput and increases to 100% in 10% steps.
l The test duration is set to 60 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: Uni-directional
Table 11-101 Packet loss ratio in the case of overloading of the EMS4 (one VC-4 is bound on
the FE port)
Frame Size
(Byte)
Rate Tested (%) (01,01,03) to (01,01,06)
(%)
Average (%)
64 100.00 0.000 0.000
128 100.00 0.000 0.000
256 100.00 0.000 0.000
512 100.00 0.000 0.000
1024 100.00 0.000 0.000
1280 100.00 0.000 0.000
1518 100.00 0.000 0.000

Table 11-102 lists the packet loss ratio in the case of overloading of the EMS4 (24 VC-3s are
bound on the GE port). The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The tested traffic starts from the throughput and increases to 100% in 10% steps.
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l The test duration is set to 60 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: Uni-directional
Table 11-102 Packet loss ratio in the case of overloading of the EMS4 (24 VC-3s are bound on
the GE port)
Frame Size
(Byte)
Rate Tested (%) (01,03,01) to (01,03,02)
(%)
Average (%)
64 100.00 0.000 0.000
128 100.00 0.000 0.000
256 100.00 0.000 0.000
512 100.00 0.000 0.000
1024 100.00 0.000 0.000
1280 100.00 0.000 0.000
1518 100.00 0.000 0.000

Table 11-103 lists the latency specifications of the EMS4 (one VC-4 is bound on the FE port).
The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The test duration is set to 60 seconds.
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
l CT: cut through or FIFO; S&F: store forward or LIFO
l Measure on one receiving card only. Mode: SmartMetrics Comp. Mode
l Minimum frame size (byte): 64
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l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: Uni-directional
Table 11-103 Latency specifications of the EMS4 (one VC-4 is bound on the FE port)
Frame
Size
(Byte)
Rate
Tested
(%)
(01,01,03) to
(01,01,06) (us)-
CT (us)
Average
(CT) (us)
(01,01,03) to
(01,01,06)
(us)-S&F (us)
Average
(S&F) (us)
64 100.00 110.6 110.6 105.5 105.5
128 100.00 123.8 123.8 113.6 113.6
256 100.00 149.2 149.2 128.8 128.8
512 100.00 195.5 195.5 154.6 154.6
1024 100.00 285.6 285.6 203.7 203.7
1280 100.00 344.6 344.6 240.5 240.5
1518 100.00 373.1 373.1 251.7 251.7

Table 11-104 lists the latency specifications of the EMS4 (24 VC-3s are bound on the GE port).
The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The test duration is set to 60 seconds.
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
l CT: cut through or FIFO; S&F: store forward or LIFO
l Measure on one receiving card only. Mode: SmartMetrics Comp. Mode
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
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l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: Uni-directional
Table 11-104 Latency specifications of the EMS4 (24 VC-3s are bound on the GE port)
Frame
Size
(Byte)
Rate
Tested
(%)
(01,03,01) to
(01,03,02) (us)-
CT (us)
Average
(CT) (us)
(01,03,01) to
(01,03,02)
(us)-S&F (us)
Average
(S&F) (us)
64 100.00 80.9 80.9 80.4 80.4
128 100.00 83.0 83.0 82.0 82.0
256 100.00 86.9 86.9 84.9 84.9
512 100.00 94.9 94.9 90.9 90.9
1024 100.00 108.8 108.8 100.7 100.7
1280 100.00 115.2 115.2 105.0 105.0
1518 100.00 120.7 120.7 108.6 108.6

Table 11-105 lists the back-to-back specifications of the EMS4 (one VC-4 is bound on the FE
port). The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 2 seconds, and the number of repetitions is set to
a value more than 50 on the Smart Application.
l The tested traffic is set to the wire speed.
l The test duration is set to 10 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: Uni-directional
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Table 11-105 Back-to-back specifications of the EMS4 (one VC-4 is bound on the FE port)
Frame Size
(Byte)
Rate Tested (%) (01,01,03) to (01,01,06)
Burst Size (Number of
Frames)
Total (Number of
Frames)
64 100.00 1488100 1488100
128 100.00 844590 844590
256 100.00 452900 452900
512 100.00 234960 234960
1024 100.00 119730 119730
1280 100.00 96150 96150
1518 100.00 81270 81270

Table 11-106 lists the back-to-back specifications of the EMS4 (24 VC-3s are bound on the GE
port). The values are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 2 seconds, and the number of repetitions is set to
a value more than 50 on the Smart Application.
l The tested traffic is set to the wire speed.
l The test duration is set to 10 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: Uni-directional
Table 11-106 Back-to-back specifications of the EMS4 (24 VC-3s are bound on the GE port)
Frame Size
(Byte)
Rate Tested (%) (01,03,01) to (01,03,02)
Burst Size (Number of
Frames)
Total (Number of
Frames)
64 100.00 2976190 2976190
128 100.00 1689190 1689190
256 100.00 905798 905798
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Frame Size
(Byte)
Rate Tested (%) (01,03,01) to (01,03,02)
Burst Size (Number of
Frames)
Total (Number of
Frames)
512 100.00 469924 469924
1024 100.00 239464 239464
1280 100.00 192308 192308
1518 100.00 162548 162548

Mechanical Specifications
The mechanical specifications of the EMS4 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.1
Power Consumption
The maximum power consumption of the EMS4 at room temperature (25C) is 65 W.
11.10 EGS4
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EGS4 (4xGE switching and processing board). This topic also
describes how to configure and commission the EGS4.
11.10.1 Version Description
The EGS4 is available in three functional versions, namely, N1, N3 and N4. The N1EGS4 is
discontinued.
11.10.2 Application
The EGS4 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
11.10.3 Functions and Features
The EGS4 supports the Layer 2 switching, link aggregation, and multicast functions.
11.10.4 Working Principle and Signal Flow
The EGS4 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
11.10.5 Front Panel
The front panel of the EGS4 has indicators, interfaces, a bar code, and a laser safety class label.
11.10.6 Jumpers and DIP Switches
The EGS4 does not have any jumpers or DIP switches that are used for board settings.
11.10.7 Valid Slots
The EGS4 must be installed in a valid slot in the subrack. Otherwise, the EGS4 cannot work
normally.
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11.10.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGS4 indicates the type of interface.
11.10.9 Board Protection
The EGS4 supports the BPS, PPS, and DLAG protection.
11.10.10 Parameter Settings
You can set parameters for the EGS4 by using the T2000.
11.10.11 Technical Specifications
The technical specifications of the EGS4 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.
11.10.1 Version Description
The EGS4 is available in three functional versions, namely, N1, N3 and N4. The N1EGS4 is
discontinued.
Table 11-107 describes the versions of the EGS4.
Table 11-107 Versions of the EGS4
Item Description
Functional versions The EGS4 is available in three functional versions, namely, N1, N3
and N4.
Differences The N1EGS4 supports the binding of a maximum of 1008 VC-12s.
The N3EGS4 and N4EGS4 support the binding of a maximum of 504
VC-12s. The restrictions that exist in the case of the VC-4/VC-3
binding and VC-12 binding are as follows:
l VC-4/VC-3 binding: VC-4s are divided into two areas, namely,
VC-4-1 to VC-4-8 and VC-4-9 to VC-4-16. The VC-4s/VC-3s in
these two areas cannot be bound at one time.
l VC-12 binding: VC-4s are divided into two areas, namely, VC-4-1
to VC-4-4 and VC-4-9 to VC-4-12. The VC-12s in these two areas
cannot be bound at one time.
Substitution l The N1EGS4 can substitute for the N3EGS4.
l The N4EGS4 can substitute for the N3EGS4.

11.10.2 Application
The EGS4 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
Figure 11-54 shows the typical networking and application of the EGS4. The EGS4 accesses
and converges Ethernet services, and provides the Ethernet data with the following data features:
Layer 2 switching, port isolation, flow classification, traffic control, VLAN management, and
priority configuration. In addition, the EGS4 performs encapsulation/decapsulation, virtual
concatenation, and SDH mapping/demapping for data. The EGS4 can be interconnected with
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the bandwidth access equipment and the data communication equipment at the same time, thus
to provide a network-level solution.
NOTE
When the service converging FE services into GE services is configured, the GE switching board can be
set only to the 1000M full-duplex mode, the VLAN of the convergence service is variable, and the binding
granularity can be at the VC-3 or VC-12 level.
Figure 11-54 Networking and application of the EGS4
NE1
NE2 NE4
NE3
User A2
User B2
User B1
User A1
NMS
PORT 1
VLAN 100
PORT 2
VLAN 100
PORT 2
VLAN 100
PORT 1 VLAN 100
Service flow
Line board
Cross-connect and
timing board
Data board
MSP ring

11.10.3 Functions and Features
The EGS4 supports the Layer 2 switching, link aggregation, and multicast functions.
Table 11-108 provides the functions and features of the EGS4.
Table 11-108 Functions and features of the EGS4
Function and
Feature
EGS4
Basic functions Accesses and processes 4xGE services.
Supports point-to-multipoint convergence services.
Functions when
being used with the
interface board
Accesses 4xGE signals by providing interfaces on the front panel.
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Function and
Feature
EGS4
Specifications of the
optical interface
l Supports the 1000BASE-SX/LX/ZX/VX Ethernet optical
interfaces. The optical interfaces support the auto-negotiation
function in compliance with IEEE 802.3z. The optical interfaces
use the SFP optical module and support hot swapping. When the
multi-mode optical fiber is used, the maximum transmission
distance is 550 m. When the single-mode optical fiber is used, the
maximum transmission distance is 10 km. The optical modules that
can meet different requirements for the transmission distance such
as 40 km and 80 km can also be used.
l The N1EGS4 and N4EGS4 also support the 1000BASE-T RJ-45
Ethernet electrical interface. The electrical interface supports the
auto-negotiation function. The N1EGS4 supports the negotiated
rate of 1000 Mbit/s and the N4EGS4 supports the negotiated rate
of 10 Mbit/s, 100 Mbit/s, or 1000 Mbit/s. The N1EGS4 and
N4EGS4 use the SFP electrical interface and support hot swapping.
The maximum transmission distance is 100 m.
Format of service
frames
l Supports Ethernet II, IEEE 802.3, and IEEE 802.1q/p formats.
l Supports the frame with a length ranging from 64 bytes to 9216
bytes.
l Supports the Jumbo frame with a length less than 9216 bytes.
Maximum uplink
bandwidth
2.5 Gbit/s
Number of supported
VCTRUNKs
64
Mapping
granularities
Supports the following virtual concatenation granularities: VC-12,
VC-3, VC-4, VC12-Xv (X64), VC3-Xv (X24), and VC4-Xv
(X8).
Encapsulation format Supports the GFP-F, LAPS, and HDLG protocols.
EPL services Supports PORT-based transparent transmission.
EVPL services l Supports EVPL services based on PORT+VLAN.
Supports a maximum of 4000 services that are accessed through
IP ports.
Supports a maximum of 4000 services that are accessed through
VCTRUNKs.
Supports a maximum of 8000 links.
l Supports QinQ-based EVPL services.
l Supports PORT-based service forwarding.
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Function and
Feature
EGS4
EPLAN services l Supports the Layer 2 forwarding function.
l Supports switching on the client and SDH sides.
l Supports the self-learning of the source MAC address. The
capacity of the MAC address table is 128K. The aging time of the
MAC address can be set and queried.
l Supports the configuration of the static MAC route.
l Supports the creation, deletion, and query of the VB. The EGS4
supports a maximum of two VBs.
EVPLAN services l Supports data isolation based on VB+VLAN.
l Supports the setting of a maximum of 4000 VLAN services.
l Supports the EVPLAN services that are based on the IEEE 802.1q
virtual bridge and IEEE 802.1ad provider bridge.
MTU Supports the setting of the packet length, which ranges from 1518
bytes to 9216 bytes. After the setting becomes valid, the length of the
packets that enter the IP ports of the N1EGS4/N3EGS4 is restricted
by the pre-set MTU, and the length of the packets that enter or exit
the IP ports of the N4EGS4 is also restricted by the pre-set MTU.
MPLS Does not support the MPLS.
VLAN l Supports VLAN and QinQ, and supports the addition, deletion, and
exchanging of VLAN tags. The function complies with IEEE
802.1q/p.
l Supports 4096 S-VLANs (04095) and 4096 C-VLANs (04095)
in the case of QinQ services.
l Supports 4095 VLANs (14095) in the case of EVPL services.
RSTP Supports the RSTP, which complies with IEEE 802.1w.
MSTP The N1EGS4 Supports the MSTP.
Link aggregation
function
Supports manual link aggregation and static link aggregation.
Inter-board link
aggregation
Supports inter-board link aggregation.
Multicast function
(IGMP snooping)
Supports the multicast function.
ETH-OAM function l Supports CC for the multicast service, LB test for the unicast
service, and LD.
l Supports the initiation of remote loopbacks, auto-negotiation,
status query in the case of a severe fault in the board, and link
performance detection functions, which comply with IEEE
802.3ah.
l The N4EGS4 supports the LT test function.
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Function and
Feature
EGS4
QoS function l Supports the CAR. The granularity is 64 kbit/s. The N1EGS4
supports 512 rate modes, and the N3EGS4 and N4EGS4 support
60 rate modes.
l The N3EGS4/N4EGS4 supports the flow classification based on
PORT, PORT+VLAN, or PORT+SVLAN.
LCAS function Dynamically increases or decreases the bandwidth and protects the
bandwidth in compliance with ITU-T G.7042.
LPT function Supports the P2P LPT and the P2MP LPT.
Flow control
function
Supports the port-based flow control function that complies with
IEEE 802.3x.
High-precision time
(IEEE 1588 V2)
Does not support the high-precision time.
Test frames Supports test frames.
Port mirroring The N4EGS4 supports ingress mirroring.
Loopback function Supports inloops on Ethernet ports (at the PHY layer).
Protection schemes Supports the following protection schemes at the Ethernet equipment
level and network level:
l BPS/PPS/DLAG
l STP/RSTP
l LCAS
l LPT
l LAG
Ethernet
performance
monitoring
Supports RMON of the Ethernet performance at the port level and the
VCTRUNK level.
Alarms and
performance events
Reports various alarms and performance events, which facilitates
management and maintenance of the equipment.

11.10.4 Working Principle and Signal Flow
The EGS4 consists of the Ethernet access module, network processor module, mapping module,
interface converting module, logic and control module, clock module, and power module.
Figure 11-55 shows the functional block diagram of the EGS4 by describing how to process
1xGE signals.
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Figure 11-55 Functional block diagram of the EGS4
Interface
converting
module
Ethernet
access
module
GE
Mapping module
Network processor module
Control
Data
Reference clock and frame header
Communication
Switch
fabric
Network
processor
Logic and
control module
Clock module
50
MHz
SCC unit
+3.3 V
Power
module
Fuse
-48 V/-60 V
Cross-connect unit
Power
module
D
E
N
C
P
V
C
P
E
N
C
P
LOS
Laser
shutdown
77
MHz
125
MHz
155
MHz
Backplane
-48 V/-60 V
Cross-connect unit
SCC unit

Ethernet Access Module
In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
Network Processor Module
The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The Ethernet/VLAN format is supported.
The network processor module supports the following functions:
l Flow sense and flow classification
l Unicast, multicast, and broadcast of the flow
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l Setting of data priorities
l WFQ
l Three CoSs
Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, this module first encapsulates Ethernet signals in LAPS, GFP-F, or
HDLC format. The concatenation is processed. The LCAS function is supported. Then, the
Ethernet signals are converted into SDH signals.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the network processor module in packets.
Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l Manages and configures other modules of the board.
l Implements inter-board communication through the internal Ethernet interface.
The control module also contains basic logic units. This module has the following functions:
l Writes and reads the register.
l Provides interfaces for the CPU.
l Checks and selects the clock.
l Performs phase discrimination and frequency division on the clock.
l Checks the in-service state of the cross-connect, SCC, and line boards.
l Controls the shutting down of the optical module.
l Implements communication.
l Controls indicators.
Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 155 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
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11.10.5 Front Panel
The front panel of the EGS4 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 11-56 shows the appearance of the front panel of the N1EGS4/N3EGS4/N4EGS4 that
is installed with the optical interface.
Figure 11-56 Front panel of the N1EGS4/N3EGS4/N4EGS4 that is installed with the optical
interface
EGS4
EGS4
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4
1
LINK
2
3
4
ACT

The N1EGS4/N4EGS4 can also be installed with the GE electrical interface. Figure 11-57 shows
the appearance of the front panel of the N1EGS4/N4EGS4 that is installed with the GE electrical
interface.
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Figure 11-57 front panel of the N1EGS4/N4EGS4 that is installed with the GE electrical
interface
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4
EGS4
EGS4
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
1
LINK
2
3
4
ACT

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Connection status indicator (LINK) one color (green)
l Data receiving and transmission indicator (ACT) one color (orange)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the N1EGS4/N3EGS4/N4EGS4 has four GE optical interfaces. Table
11-109 describes the types and usage of the optical interfaces of the N1EGS4/N3EGS4/N4EGS4.
Table 11-109 Optical interfaces of the N1EGS4/N3EGS4/N4EGS4
Interface Type of
Interface
Usage
OUT1/IN1 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.
OUT2/IN2 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.
OUT3/IN3 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.
OUT4/IN4 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.

The four GE electrical interfaces of the N1EGS4/N4EGS4 are of the same type and have the
same usage. Table 11-110 describes the types and usage of the electrical interfaces of the
N1EGS4/N4EGS4.
Table 11-110 Electrical interfaces of the N1EGS4/N4EGS4
Interface Type of
Interface
Usage
GE RJ-45
(swappable)
Transmits and receives 1000BASE-T signals.

Table 11-111 provides the pin assignments of the RJ-45 interface of the N1EGS4/N4EGS4.
Table 11-111 Pin assignments of the RJ-45 interface of the N1EGS4/N4EGS4
Pin Description
1 BI_DA+
2 BI_DA
3 BI_DB+
4 BI_DC+
5 BI_DC
6 BI_DB
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Pin Description
7 BI_DD+
8 BI_DD

11.10.6 Jumpers and DIP Switches
The EGS4 does not have any jumpers or DIP switches that are used for board settings.
11.10.7 Valid Slots
The EGS4 must be installed in a valid slot in the subrack. Otherwise, the EGS4 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The EGS4 can be installed in slots 18 and 1116 in the subrack. The relation between the slots
valid for the EGS4 and the bandwidth is as follows:
l When the cross-connect capacity is 200 Gbit/s, the EGS4 can be installed in slots 18 and
1116. When the EGS4 is installed in slots 14, 15, and 16, the bandwidth is 1.25 Gbit/s.
When the EGS4 is installed in slots 58 and 1114, the bandwidth is 2.5 Gbit/s.
11.10.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGS4 indicates the type of interface.
Table 11-112 provides the relationship between the feature code of the EGS4 and the type of
interface.
Table 11-112 Relationship between the feature code of the EGS4 and the type of interface
Board Feature Code Type of Interface
SSN1EGS410,
SSN3EGS410, and
SSN4EGS10
10 1000BASE-SX (0.5 km)
SSN1EGS411,
SSN3EGS411, and
SSN4EGS411
11 1000BASE-LX (10 km)
SSN1EGS412,
SSN3EGS412, and
SSN4EGS412
12 1000BASE-VX (40 km)
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Board Feature Code Type of Interface
SSN1EGS413,
SSN3EGS413, and
SSN4EGS413
13 1000BASE-ZX (80 km)
SSN1EGS414 and
SSN4EGS414
14 1000BASE-T (100 m)

11.10.9 Board Protection
The EGS4 supports the BPS, PPS, and DLAG protection.
Protection Principle
When the BPS protection is provided for the EGS4, the GE and FE ports are protected by using
the single-fed and selective-receiving scheme. The EGS4 may be connected to many sets of
communication equipment. Normally, the active board is working and services are transmitted
in two directions of the active link. On the standby link, the EGS4 disables the transmission of
all ports. In this case, the ports of the opposite board are in the link-down state. In addition, the
opposite board enables the transmission but does not transmit services. In this manner, the
receive ports of the standby EGS4 are not in the link-down state. The solid lines in Figure
11-58 show how the EGS4 normally works.
Figure 11-58 Normal working of the EGS4
EGS4
Active
EGS4
Standby
XCS
No.1
No.2
No.3
No.1
No.2
No.3
Active
communication
equipment
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment
A
B
C
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l BPS Protection
When the BPS protection is provided, if the active board detects the link-down state of any link,
any fault in the board, or the offline state of any board, the cross-connect board switches all the
services to the standby board. In this manner, services are protected. The solid lines in Figure
11-59 show how the BPS protection functions. The services numbered 1, 2 and 3 are all switched
to the standby EGS4 and the corresponding communication equipment.
Figure 11-59 Principle of the BPS protection for the EGS4
EGS4
Active
EGS4
Standby
XCS
No.1
No.2
No.3
No.1
No.2
No.3
Active
communication
equipment
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment
A
B
C

l PPS Protection
When the PPS protection is provided, if the active board detects the link-down state of any link,
the cross-connect board switches all the services to the standby board. In this manner, services
are protected. The solid lines in Figure 11-60 show how the PPS protection functions. Only the
service numbered 1 is switched to the standby EGS4 and the standby communication equipment.
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Figure 11-60 Principle of the PPS protection for the EGS4
EGS4
Active
EGS4
Standby
XCS
No.1
No.2
No.3
No.1
No.2
No.3
Active
communication
equipment
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment
A
B
C

NOTE
In the case of the PPS, when a link failure occurs on a port, only the link services on the port are switched
generally. If the services of two ports are associated, for example, the services of port IP1 and port IP2 are
converged into the same VCTRUNK, port IP1 and port IP2 are defined as associated ports. When one port
of the associated ports is faulty, the services of the entire associated port group are switched.
l DLAG Protection
The DLAG is a group where the two mapping ports on two identical boards are aggregated to
from a protection group, thus providing 1+1 protection for the ports. By default, the port on the
active board is working, and the port on the standby board is protecting the working port.
When the DLAG is configured, the cross-connect board switches all services from the active
board to the standby board if the active board detects a link failure on a port, a board offline
event, or a board hardware failure. As shown in Figure 11-61, the services carried on port 1 are
switched to port 1 of the standby EGS4 and the associated equipment.
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Figure 11-61 Principle of the DLAG protection for the EGS4
EGS4
1#
A
B
C
XCH
PORT1
PORT2
PORT3
PORT1
PORT2
PORT3
VCG
VCG
2#
3#
1#
2#
3#
EGS4
Active
communication
equipment
Active
Standby
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment
Active
communication
equipment
Standby
communication
equipment

WARNING
When the board-level protection is performed, the GE optical ports support the auto-negotiation
and 1000M full-duplex mode.
Board Configuration
Two EGS4 boards should be configured on an NE to provide the board-level protection. One
EGS4 is the active board and the other is the standby board. When you configure the EGS4 board
protection, ensure that the access capacity of the slot that houses the standby board must not be
less than the access capacity of the slot that houses the active board.
11.10.10 Parameter Settings
You can set parameters for the EGS4 by using the T2000.
You can set the following main parameters for the EGS4 by using the T2000:
l Working mode
l LCAS
l Maximum frame length
l Mapping protocol
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
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11.10.11 Technical Specifications
The technical specifications of the EGS4 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.
Parameters Specified for Optical Interfaces
Table 11-113 lists the parameters specified for the optical interfaces of the EGS4.
Table 11-113 Parameters specified for the optical interfaces of the EGS4
Parameter Value
Type of optical
interface
1000BASE-ZX
(80 km)
1000BASE-
VX (40 km)
1000BASE-
LX (10 km)
1000BASE-SX
(0.5 km)
Type of fiber Single-mode LC Single-mode
LC
Single-mode
LC
Multi-mode LC
Launched optical
power range
(dBm)
-2 to 5 -5 to 0 -11 to -3 -9.5 to 0
Operating
wavelength range
(nm)
1500 to 1580 1275 to 1350 1270 to 1355 770 to 860
Minimum
overload (dBm)
-3 -3 -3 0
Receiver
sensitivity (dBm)
-23 -22 -19 -17
Minimum
extinction ratio
(dB)
9 9 9 9

Parameters Specified for Electrical Interfaces
Table 11-114 lists the parameters specified for the electrical interfaces of the EGS4.
Table 11-114 Parameters specified for the electrical interfaces of the EGS4
Type of Electrical
Interface
Code Pattern
1000Base-T, RJ-45 4D-PAM5

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WARNING
Only the EGS4 boards of the N1 and N4 versions support the GE electrical interfaces.
Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Ethernet Performance Specifications
NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EGS4 board of the N1 version.
Figure 11-62 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, latency specifications, and back-to-back specifications of the
N1EGS4.
Figure 11-62 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications of the N1EGS4
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer

Table 11-115 lists the throughput specifications of the N1EGS4. Table 11-116 lists the packet
loss ratio in the case of overloading of the N1EGS4. Table 11-117 lists the latency specifications
of the N1EGS4. Table 11-118 lists the back-to-back specifications of the N1EGS4.
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NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured 24 VC-3s are bound on the GE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-115 lists the throughput specifications of the N1EGS4. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The permitted packet loss ratio is set to 0% and the resolution rate is set to 0.1%.
l The test duration is set to 60 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 100.00
l Resolution rate (%): 1.00
l Mode: Uni-directional
Table 11-115 Throughput specifications of the N1EGS4
Frame Size
(Byte)
Passed Rate (%) (01,03,01) to (01,03,02)
(pks/sec)
Total (pks/sec)
64 100.00 1488095 1488095
128 100.00 844595 844595
256 100.00 452899 452899
512 100.00 234962 234962
1024 100.00 119732 119732
1280 100.00 96154 96154
1518 100.00 81274 81274

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Table 11-116 lists the packet loss ratio in the case of overloading of the N1EGS4. The values
are obtained when the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The tested traffic starts from the throughput and increases to 100% in 10% steps.
l The test duration is set to 60 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: Uni-directional
Table 11-116 Packet loss ratio in the case of overloading of the N1EGS4
Frame Size
(Byte)
Rate Tested (%) (01,03,01) to (01,03,02)
(%)
Average (%)
64 100.00 0.000 0.000
128 100.00 0.000 0.000
256 100.00 0.000 0.000
512 100.00 0.000 0.000
1024 100.00 0.000 0.000
1280 100.00 0.000 0.000
1518 100.00 0.000 0.000

Table 11-117 lists the latency specifications of the N1EGS4. The values are obtained when the
SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The test duration is set to 60 seconds.
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
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equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
l CT: cut through or FIFO; S&F: store forward or LIFO
l Measure on one receiving card only. Mode: SmartMetrics Comp. Mode
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: Uni-directional
Table 11-117 Latency specifications of the N1EGS4
Frame
Size
(Byte)
Rate
Tested
(%)
(01,03,01) to
(01,03,02) (us)-
CT (us)
Average
(CT) (us)
(01,03,01) to
(01,03,02)
(us)-S&F (us)
Average
(S&F) (us)
64 100.00 80.9 80.9 80.4 80.4
128 100.00 83.0 83.0 82.0 82.0
256 100.00 86.9 86.9 84.9 84.9
512 100.00 94.9 94.9 90.9 90.9
1024 100.00 108.8 108.8 100.7 100.7
1280 100.00 115.2 115.2 105.0 105.0
1518 100.00 120.7 120.7 108.6 108.6

Table 11-118 lists the back-to-back specifications of the N1EGS4. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 2 seconds, and the number of repetitions is set to
a value more than 50 on the SmartApplication.
l The tested traffic is set to the wire speed.
l The test duration is set to 10 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
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l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: Uni-directional
Table 11-118 Back-to-back specifications of the N1EGS4
Frame Size
(Byte)
Rate Tested (%) (01,03,01) to (01,03,02)
Burst Size (Number of
Frames)
Total (Number of
Frames)
64 100.00 2976190 2976190
128 100.00 1689190 1689190
256 100.00 905798 905798
512 100.00 469924 469924
1024 100.00 239464 239464
1280 100.00 192308 192308
1518 100.00 162548 162548

NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EGS4 board of the N4 version.
Figure 11-63 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, latency specifications, and back-to-back specifications of the
N4EGS4.
Figure 11-63 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications of the N4EGS4
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer

Table 11-119 lists the throughput specifications of the N4EGS4. Table 11-120 lists the packet
loss ratio in the case of overloading of the N4EGS4. Table 11-121 lists the latency specifications
of the N4EGS4. Table 11-122 lists the back-to-back specifications of the N4EGS4.
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NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured and one VC-4 are bound on the GE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-119 lists the throughput specifications of the N4EGS4. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The permitted packet loss ratio is set to 0% and the resolution rate is set to 1%.
l The test duration is set to 30 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 16.54
l Maximum rate (%): 16.54
l Mode: Uni-directional
Table 11-119 Throughput specifications of the N4EGS4
Frame Size
(byte)
Passed Rate (%) (01,01,02) to (01,01,01)
(pks/sec)
Total (pks/sec)
64 16.54 246063 492126
128 15.81 133547 267094
256 15.40 69754 139508
512 15.20 35714 71428
1024 15.10 18074 36148
1280 15.07 14488 28976
1518 15.06 12238 24476

Table 11-120 lists the packet loss ratio in the case of overloading of the N4EGS4. The values
are obtained when the SmartApplication is set as follows:
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l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The tested traffic starts from the throughput and increases to 100% in 10% steps.
l The test duration is set to 30 seconds.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 16.54
l Maximum rate (%): 10.00
l Resolution rate (%): None
l Mode: Uni-directional
Table 11-120 Packet loss ratio in the case of overloading of the N4EGS4
Frame Size
(byte)
Rate Tested (%) (01,01,02) to (01,01,01)
(%)
Average (%)
64 16.54 0.000 0.000
128 15.81 0.000 0.000
256 15.40 0.000 0.000
512 15.20 0.000 0.000
1024 15.10 0.000 0.000
1280 15.07 0.000 0.000
1518 15.06 0.000 0.000

Table 11-121 lists the latency specifications of the N4EGS4. The values are obtained when the
SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The test duration is set to 30 seconds.
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the first bit of the transmitted frame reaches the input port of the tested
equipment. In store forward mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the tested equipment
and the time when the last bit of the transmitted frame reaches the input port of the tested
equipment. In the table, the CT values are obtained in cut through mode and the S&F values
are obtained in store forward mode.
l CT: Cut Through (or FIFO),S&F: Store & Forward (or LIFO)
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l Measure on one receiving card only, Mode: SmartMetrics Comp. Mode
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 16.54
l Maximum rate (%): 10.00
l Resolution rate (%): None
l Mode: Uni-directional
Table 11-121 Latency specifications of the N4EGS4
Frame
Size
(byte)
Rate
Tested
(%)
(01,01,02) to
(01,01,01) (us)-
CT (us)
Average
(CT) (us)
(01,01,02) to
(01,01,01)
(us)-S&F (us)
Average
(S&F) (us)
64 16.54 103.3 103.3 102.8 102.8
128 15.81 115.2 115.2 114.2 114.2
256 15.40 126.7 126.7 124.7 124.7
512 15.20 154.4 154.4 150.4 150.4
1024 15.10 3721.4 3721.4 3713.3 3713.3
1280 15.07 223.9 223.9 213.7 213.7
1518 15.06 3447.5 3447.5 3435.4 3435.4

Table 11-122 lists the back-to-back specifications of the N4EGS4. The values are obtained when
the SmartApplication is set as follows:
l The specifications in the table are obtained in the scenario wherein point-to-point
transparent transmission services are configured and the flow control function is disabled.
l The frame size is set to the range from 64 bytes to 1518 bytes, the packet transmission rate
is set to 100%, the test duration is set to 30 seconds, and the number of repetitions is set to
a value more than 1 on the SmartApplication.
l The tested traffic is set to the wire speed.
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): Custom
l Number of pairs: 1
l Initial rate (%): 16.54
l Maximum rate (%): 10.00
l Resolution rate (%): None
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l Mode: Uni-directional
Table 11-122 Back-to-back specifications of the N4EGS4
Frame Size
(byte)
Rate Tested (%) (01,01,02) to (01,01,01)
Burst Size (frames)
Total (frames)
64 16.54 7381890 14763780
128 15.81 4006410 8012820
256 15.40 2092620 4185240
512 15.20 1071420 2142840
1024 15.10 542220 1084440
1280 15.07 434640 869280
1518 15.06 367140 734280

Mechanical Specifications
The mechanical specifications of the EGS4 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight of the N1EGS4 or N3EGS4 (kg): 1.1
l Weight of the N4EGS4 (kg): 0.7
Power Consumption
The maximum power consumption of the N1EGS4 and N3EGS4 at room temperature (25C) is
70 W.
The maximum power consumption of the N4EGS4 at room temperature (25C) is 34 W.
11.11 EAS2
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EAS2 (2-port 10xGE Layer 2 switching and processing board).
This topic also describes how to configure and commission the EAS2.
11.11.1 Version Description
The EAS2 is available in one functional version, namely, N1.
11.11.2 Application
The EAS2 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
11.11.3 Functions and Features
The EAS2 supports the access of 10 GE Ethernet services, LCAS, and test frame functions.
11.11.4 Working Principle and Signal Flow
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The EAS2 consists of the interface processing module, mapping module, interface converting
module, logic and control module, clock module, and power module.
11.11.5 Front Panel
The front panel of the EAS2 has indicators, interfaces, a bar code, and a laser safety class label.
11.11.6 Jumpers and DIP Switches
The EAS2 does not have any jumpers or DIP switches that are used for board settings.
11.11.7 Valid Slots
The slots valid for the EAS2 vary with the cross-connect capacity of the subrack.
11.11.8 Feature Code
The EAS2 does not have the feature code.
11.11.9 Parameter Settings
You can set parameters for the EAS2 by using the T2000.
11.11.10 Technical Specifications
The technical specifications of the EAS2 include the parameters specified for optical interfaces,
dimensions, weight, and power consumption.
11.11.1 Version Description
The EAS2 is available in one functional version, namely, N1.
11.11.2 Application
The EAS2 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
Figure 11-64 shows the typical networking and application of the EAS2. The EAS2 accesses
and converges Ethernet services, and provides the Ethernet data with the following data features:
Layer 2 switching, port isolation, flow classification, traffic control, VLAN management, and
priority configuration. In addition, the EAS2 performs encapsulation/decapsulation, virtual
concatenation, and SDH mapping/demapping for data. The EAS2 can be interconnected with
the bandwidth access equipment and the data communication equipment at the same time, thus
to provide a network-level solution.
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Figure 11-64 Networking and application of the EAS2
NE1
NE2 NE4
NE3
User A2
User B2
User B1
User A1
NMS
PORT 1
VLAN 100
PORT 2
VLAN 100
PORT 2
VLAN 100
PORT 1 VLAN 100
Service flow
Line board
Cross-connect and
timing board
Data board
MSP ring

11.11.3 Functions and Features
The EAS2 supports the access of 10 GE Ethernet services, LCAS, and test frame functions.
Table 11-123 provides the functions and features of the EAS2.
Table 11-123 Functions and features of the EAS2 board
Function and
Feature
EAS2
Basic functions Accesses 2x10 GE Ethernet services.
Supports point-to-multipoint convergence services.
Functions when
being used with the
interface board
Provides interfaces on the front panel.
Specifications of the
optical interface
The optical interfaces are 10GBASE-LR and 10GBASE-LW Ethernet
optical interfaces, which comply with IEEE 802.3ae.
Format of service
frames
l Supports Ethernet II, IEEE 802.3, and IEEE 802.1qTAG formats.
l Supports the frame with a length ranging from 64 bytes to 9600
bytes.
l Supports the Jumbo frame with a length less than 9600 bytes.
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Function and
Feature
EAS2
Maximum uplink
bandwidth
10 Gbit/s
The EAS2 can adapt to the bandwidth of the slot.
Number of
supported
VCTRUNKs
24
Mapping
granularities
Supports the following adjacent concatenation granularities: VC4-Xv
(X8), VC3-Xv (X24), and VC4-4c.
Encapsulation
format
Supports the GFP-F protocol, which meets ITU-T G.7041.
EPL services Supports the PORT-based transparent transmission.
EVPL services l Supports EVPL services based on PORT+VLAN.
l Supports EVPL services based on VCTRUNK+VLAN.
l Supports QinQ-based EVPL services.
l Supports a maximum of 2048 links.
EPLAN services l Supports the creation, deletion, and query of the VB. The maximum
number of supported VBs is 1.
l Supports the setting and query of the aging time of the MAC address
l Supports the configuration of static MAC routes.
EVPLAN services l Supports EVPLAN services that use the stack VLAN
encapsulation.
l Supports data isolation based on VB+VLAN.
MTU Supports the setting of the packet length, which ranges from 1518
bytes to 9600 bytes. After the setting becomes valid, the length of the
packets that enter the IP ports is restricted by the pre-set MTU.
MPLS Does not support the MPLS.
VLAN Supports VLAN and QinQ, which comply with IEEE 802.1q/p.
LPT function Supports the P2P LPT and P2MP LPT.
QoS function Supports the CAR.
The granularity is 64kbit/s.
Flow control
function
Supports the port-based flow control function that complies with IEEE
802.3x.
LCAS function Dynamically increases or decreases the bandwidth and protects the
bandwidth in compliance with ITU-T G.7042.
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Function and
Feature
EAS2
Multicast function
(IGMP snooping)
l Supports the enabling of the IGMP snooping protocol. Supports a
maximum of 512 multicast groups.
l Supports the query of the enabling status of the IGMP snooping
protocol.
l Supports the setting and query of the IGMP snooping protocol
parameters.
l Supports a maximum of 512 static multicast groups.
RSTP Supports the broadcast packet suppression and RSTP, which comply
with IEEE 802.1w.
ETH-OAM function Supports CC for the multicast service, LB test for the unicast service,
and LT test. The ETH-OAM function complies with IEEE 802.1ag.
Link aggregation Supports manual link aggregation and static link aggregation for
Ethernet links and VCTRUNKs.
Inter-board link
aggregation
Supports inter-board link aggregation.
Test frames Supports test frames in ETH and GFP bearer modes.
Loopback function Supports inloops on Ethernet ports (at the PHY or MAC layer).
Protection schemes Supports the following protection schemes at the Ethernet service
layer:
l STP/RSTP
l LCAS
l LPT
l LAG
l DLAG
Ethernet
performance
monitoring
(RMON)
l Supports the Ethernet performance monitoring at the port level.
l Supports the query of the rate of a port.
Alarms and
performance events
Provides various alarm and performance events, which facilitates the
management and maintenance of the equipment.

11.11.4 Working Principle and Signal Flow
The EAS2 consists of the interface processing module, mapping module, interface converting
module, logic and control module, clock module, and power module.
Figure 11-65 shows the functional block diagram of the EAS2 by describing how to process
1x10 GE signals.
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Figure 11-65 Functional block diagram of the EAS2
Interface
processing
module
Logic and
control module
SCC unit
10GE
Communication
Cross-connect unit
Clock reference and frame delimitation
Clock module
LOS
Interface
converting
module Digital encap-
sulation module
Mapping module
Virtual
concatenation
processing
module
Laser
shutdown
+3.3 V
-48 V/-60 V Power
module
Fuse
Power
module
Backplane
Service
processing
module
Encapsulation
module
-48 V/-60 V
Cross-connect unit
SCC unit

In the Transmit Direction
The encapsulation or conversion module demaps and decapsulates the signals received from the
cross-connect unit. Then, the interface converting module performs the interface converting
operations and transmits the signals to the service processing module. The service processing
module implements the functions of the Layer 2 switching and private line service. After the
interface processing module converts parallel signals to serial signals and encodes the serial
signals, the Ethernet interface module transmits the serial signals.
In the Receive Direction
The XFP optical module performs O/E conversion on the 10 GE Ethernet signals, and then
transmits the signals to the Ethernet interface module. The Ethernet interface module transmits
the parallel signals to the service processing module to realize the functions of the Layer 2
switching and private line service. The encapsulation module encapsulates and maps the Ethernet
GFP-F frames, and then transmits the signals to the cross-connect unit.
Logic and Control Module
The logic and control module provides the communication, control, and service configuration
functions of the board.
Clock Module
The clock module traces the system reference clock, and generates the required clock signals
when the board is working.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
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11.11.5 Front Panel
The front panel of the EAS2 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 11-66 shows the appearance of the front panel of the EAS2.
Figure 11-66 Front panel of the EAS2
EAS2
EAS2
ACT
PROG
SRV
STAT
CLASS 1
LASER
PRODUCT
LINK1
ACT1
LINK2
ACT2
OUT1
IN1
OUT2
IN2

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
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l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Connection status indicator (LINK) one color (green)
l Data receiving and transmission indicator (ACT) one color (orange)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the EAS2 has two 10 GE interfaces. Table 11-124 describes the types and
usage of the interfaces of the EAS2.
Table 11-124 Interfaces of the EAS2
Interface Type of Interface Usage
IN1IN2 LC Receives 10 GE signals.
OUT1OUT2 LC Transmits 10 GE signals.

11.11.6 Jumpers and DIP Switches
The EAS2 does not have any jumpers or DIP switches that are used for board settings.
11.11.7 Valid Slots
The slots valid for the EAS2 vary with the cross-connect capacity of the subrack.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the EAS2 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the EAS2 can be installed in slots 58 and
1114.
11.11.8 Feature Code
The EAS2 does not have the feature code.
11.11.9 Parameter Settings
You can set parameters for the EAS2 by using the T2000.
You can set the following main parameters for the EAS2 by using the T2000:
l Working mode
l LCAS
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l Maximum frame length
l Mapping protocol
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
11.11.10 Technical Specifications
The technical specifications of the EAS2 include the parameters specified for optical interfaces,
dimensions, weight, and power consumption.
Parameters Specified for Optical Interfaces
Table 11-125 lists the parameters specified for the optical interfaces of the EAS2.
Table 11-125 Parameters specified for the optical interfaces of the EAS2
Parameter Value
Transmission rate 10.3125 Gbit/s or 9.953 Gbit/s
Processing capability 2x10GE signals
Type of optical interface 10GBASE-LR/LX
Type of fiber Single-mode LC
Operating wavelength
range (nm)
1290 to 1330
Transmission distance (km) 10
Maximum mean launched
power (dBm)
-1
Minimum mean launched
power (dBm)
-6
Receiver sensitivity (dBm) -11
Minimum extinction ratio
(dB)
6
Connector type LC

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Ethernet Performance Specifications
NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EAS2 board of the N1 version.
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Figure 11-67 shows the connection for testing the throughput specifications, packet loss ratio
in the case of overloading, latency specifications, and back-to-back specifications of the EAS2.
Figure 11-67 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading and latency specifications
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer

Table 11-126 lists the throughput specifications of the EAS2. Table 11-127 lists the packet loss
ratio in the case of overloading of the EAS2. Table 11-128 lists the latency specifications of the
EAS2.
NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EPL services are
configured and 64 VC-4s are bound on the 10xGE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 11-126 Throughput specifications of the EAS2
Frame Size
(Byte)
Passed Rate
(%)
Number of Tx
Frames (pks/sec)
Number of Rx
Frames (pks/sec)
Total (%)
64 100.00000 148809440 148613326 99.29688
128 100.00000 84459360 84457314 99.29688
256 99.29687 44974080 44719807 98.59375
512 97.89062 23001600 22892340 97.1875
1024 96.48437 11552000 11552000 96.48438
1280 96.48437 9277280 9277280 96.48438
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Frame Size
(Byte)
Passed Rate
(%)
Number of Tx
Frames (pks/sec)
Number of Rx
Frames (pks/sec)
Total (%)
1518 96.48437 7841440 7831693 95.78125

Table 11-127 Packet loss ratio in the case of overloading of the EAS2
Frame Size
(Byte)
Rate Tested
(%)
Number of Tx
Frames (pks/sec)
Number of Rx
Frames (pks/sec)
Total (%)
64 100.00000 148809440 148614523 0.13
128 100.00000 84459360 84457396 0.00
256 100.00000 45289760 44709723 1.28
512 100.00000 23496160 22868728 2.67
1024 100.00000 11973120 11566750 3.39
1280 100.00000 9615360 9274900 3.54
1518 100.00000 8127360 7832064 3.63

Table 11-128 Latency specifications of the EAS2
Frame
Size
(Byte)
Rate
Tested
(%)
Number
of Tx
Frames
(pks/sec)
Number of
Rx Frames
(pks/sec)
Minimum
Latency
(ms)
Average
Latency
(ms)
Maximu
m
Latency
(ms)
64 100.0000
0
14880950 14880950 59.7 90.798 98.2
128 100.0000
0
8445940 8445940 55.9 92.201 99.5
256 100.0000
0
4528980 4528980 61 96.178 103.7
512 100.0000
0
2349620 2349620 72.7 102.403 109.9
1024 100.0000
0
1197310 1197310 81.8 116.101 123.7
1280 100.0000
0
961530 961530 88.2 122.479 130.2
1518 100.0000
0
812740 812740 99.1 128.928 136.3

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Mechanical Specifications
The mechanical specifications of the EAS2 board are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.2
Power Consumption
The maximum power consumption of the EAS2 at room temperature (25C) is 70 W.
11.12 EFF8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EFF8 (8x100M Ethernet optical interface board).
11.12.1 Version Description
The EFF8 is available in one functional version, namely, N1.
11.12.2 Application
The EFF8 is an Ethernet optical interface board. The EFF8 can be used on the OptiX OSN
equipment series to transmit and receive 100M Ethernet optical signals for the data board.
11.12.3 Functions and Features
The EFF8 receives and transmits 8x100M Ethernet optical signals. The EFF8 must work with
the Ethernet processing board.
11.12.4 Working Principle and Signal Flow
The EFF8 consists of the interface module and power module.
11.12.5 Front Panel
The front panel of the EFF8 has indicators, interfaces, a bar code, and a laser safety class label.
11.12.6 Valid Slots
The EFF8 can be installed in slots 19, 21, 23, 25, 29, 31, 33,and 35 in the subrack and works as
the interface board of the EFT8, EFS0, EMR0 or EFP0. The EFF8 can be installed in slots 19
26 and 2936 in the subrack and works as the interface board of the EMS4.
11.12.7 Technical Specifications
The technical specifications of the EFF8 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
11.12.1 Version Description
The EFF8 is available in one functional version, namely, N1.
11.12.2 Application
The EFF8 is an Ethernet optical interface board. The EFF8 can be used on the OptiX OSN
equipment series to transmit and receive 100M Ethernet optical signals for the data board.
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11.12.3 Functions and Features
The EFF8 receives and transmits 8x100M Ethernet optical signals. The EFF8 must work with
the Ethernet processing board.
11.12.4 Working Principle and Signal Flow
The EFF8 consists of the interface module and power module.
Figure 11-68 shows the functional block diagram of the EFF8 by describing how to process
1x100 Mbit/s Ethernet signals.
Figure 11-68 Functional block diagram of the EFF8
Backplane
+3.3 V backup power
+3.3 V Fuse
EFT8/EFS0/EMS4/EMR0
100 Mbit/s
Ethernet signal
module
Interface
Power
module
100 Mbit/s
Ethernet signal
EFT8/EFS0/EMS4/EMR0

Interface Module
In the receive direction, the interface module performs O/E conversion for the Ethernet signals
and transmits the signals to the EFT8, EFS0, EMS4, or EMR0.
In the transmit direction, the interface module performs E/O conversion for the Ethernet signals
and transmits the signals to the optical interface.
Power Module
The power module provides all the modules of the EFF8 with the required DC voltages.
11.12.5 Front Panel
The front panel of the EFF8 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 11-69 shows the appearance of the front panel of the EFF8.
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Figure 11-69 Front panel of the EFF8
EFF8
EFF8
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4
O
U
T
5
I
N
5
O
U
T
6
I
N
6
O
U
T
7
I
N
7
O
U
T
8
I
N
8
CLASS 1
LASER
PRODUCT
1
2
3
4
5
6
7
8
LINK ACT

Indicators
The front panel of the board has the following indicators:
l Eight connection status indicators (LINK) one color (green)
l Eight data receiving and transmission indicators (ACT) one color (orange)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the EFF8 has eight optical interfaces.
Table 11-129 describes the types and usage of the interfaces of the EFF8.
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Table 11-129 Interfaces of the EFF8
Interface Type of
Interface
Usage
IN1IN8 LC Receives the 1st to the 8th channels of Ethernet
optical signals.
OUT1OUT8 LC Transmits the 1st to the 8th channels of Ethernet
optical signals.

11.12.6 Valid Slots
The EFF8 can be installed in slots 19, 21, 23, 25, 29, 31, 33,and 35 in the subrack and works as
the interface board of the EFT8, EFS0, EMR0 or EFP0. The EFF8 can be installed in slots 19
26 and 2936 in the subrack and works as the interface board of the EMS4.
Table 11-130 lists the slots valid for the EFT8/EFS0/EMR0/EFP0 and the corresponding slots
for the EFF8.
Table 11-130 Slots valid for the EFT8/EFS0/EMR0/EFP0 and the corresponding slots for the
EFF8
Slot Valid for the EFT8/EFS0/
EMR0/EFP0
Corresponding Slot for the EFF8
Slot 2 Slots 19
Slot 3 Slots 21
Slot 4 Slots 23
Slot 5 Slots 25
Slot 13 Slots 29
Slot 14 Slots 31
Slot 15 Slots 33
Slot 16 Slots 35

Table 11-131 lists the slots valid for the EMS4 and the corresponding slots for the EFF8.
Table 11-131 Slots valid for the EMS4 and the corresponding slots for the EFF8
Slot Valid for the EMS4 Corresponding Slot for the EFF8
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
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Slot Valid for the EMS4 Corresponding Slot for the EFF8
Slot 5 Slots 25 and 26
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

11.12.7 Technical Specifications
The technical specifications of the EFF8 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 11-132 lists the parameters specified for the optical interfaces of the EFF8.
Table 11-132 Parameters specified for the optical interfaces of the EFF8
Parameter Value
Nominal bit rate 10 Mbit/s or 100 Mbit/s
Line code pattern Manchester encoding signal (10M) or MLT-3 encoding signal
(100M)
Type of optical
interface
100BASE-FX
Operating
wavelength range
(nm)
100BASE-FX (15 km): 1261 to 1360
100BASE-FX (2 km): 1270 to 1380
Type of fiber Single-mode LC (15 km), Multi-mode LC (2 km)
Mean launched
optical power (dBm)
100BASE-FX (15 km): -15 to -8
100BASE-FX (2 km): -19 to -14
Receiver sensitivity
(dBm)
100BASE-FX (15 km): -28
100BASE-FX (2 km): -30
Minimum overload
(dBm)
100BASE-FX (15 km): -7
100BASE-FX (2 km): -14
Minimum extinction
ratio (dB)
10

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Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the EFF8 are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
The maximum power consumption of the EFF8 at room temperature (25C) is 6 W.
11.13 EFF8A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the EFF8A (8x100M Ethernet optical interface board).
11.13.1 Version Description
The EFF8A is available in one functional version, namely, N1.
11.13.2 Application
The EFF8A is an Ethernet optical interface board. The EFF8A can be used on the OptiX OSN
equipment series to transmit and receive 100M Ethernet optical signals for the data board.
11.13.3 Functions and Features
The EFF8A receives and transmits 8x100M Ethernet optical signals. The EFF8A must work
with the N5EFS0.
11.13.4 Working Principle and Signal Flow
The EFF8A consists of the interface module and power module.
11.13.5 Front Panel
The front panel of the EFF8A has indicators, interfaces, a bar code, and a laser safety class label.
11.13.6 Valid Slots
The EFF8A can be installed in slots 1926 and 2936 in the subrack and works as the interface
board of the N5EFS0.
11.13.7 Technical Specifications
The technical specifications of the EFF8A include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.
11.13.1 Version Description
The EFF8A is available in one functional version, namely, N1.
11.13.2 Application
The EFF8A is an Ethernet optical interface board. The EFF8A can be used on the OptiX OSN
equipment series to transmit and receive 100M Ethernet optical signals for the data board.
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11.13.3 Functions and Features
The EFF8A receives and transmits 8x100M Ethernet optical signals. The EFF8A must work
with the N5EFS0.
11.13.4 Working Principle and Signal Flow
The EFF8A consists of the interface module and power module.
Figure 11-70 shows the functional block diagram of the EFF8A by describing how to process
1x100 Mbit/s Ethernet signals.
Figure 11-70 Functional block diagram of the EFF8A
N5EFS0
Backplane
+3.3 V backup power
+3.3 V Fuse
100 Mbit/s
Ethernet signal
module
Interface
Power
module
N5EFS0
100 Mbit/s
Ethernet signal

Interface Module
In the receive direction, the interface module performs O/E conversion for the Ethernet signals
and transmits the signals to the N5EFS0.
In the transmit direction, the interface module performs E/O conversion for the Ethernet signals
and transmits the signals to the optical interface.
Power Module
The power module provides all the modules of the EFF8A with the required DC voltages.
11.13.5 Front Panel
The front panel of the EFF8A has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 11-71 shows the appearance of the front panel of the EFF8A.
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Figure 11-71 Front panel of the EFF8A
EFF8
EFF8
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4
O
U
T
5
I
N
5
O
U
T
6
I
N
6
O
U
T
7
I
N
7
O
U
T
8
I
N
8
CLASS 1
LASER
PRODUCT
1
2
3
4
5
6
7
8
LINK ACT

Indicators
The front panel of the board has the following indicators:
l Eight connection status indicators (LINK) one color (green)
l Eight data receiving and transmission indicators (ACT) one color (orange)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the EFF8A has eight optical interfaces.
Table 11-133 describes the types and usage of the interfaces of the EFF8A.
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Table 11-133 Interfaces of the EFF8A
Interface Type of
Interface
Usage
IN1IN8 LC Receives the 1st to the 8th channels of Ethernet
optical signals.
OUT1OUT8 LC Transmits the 1st to the 8th channels of Ethernet
optical signals.

11.13.6 Valid Slots
The EFF8A can be installed in slots 1926 and 2936 in the subrack and works as the interface
board of the N5EFS0.
Table 11-134 lists the slots valid for the N5EFS0 and the corresponding slots for the EFF8A.
Table 11-134 Slots valid for the N5EFS0 and the corresponding slots for the EFF8A
Slot Valid for the N5EFS0 Corresponding Slot for the EFF8A
Slot 2 Slot 19
Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33
Slot 16 Slot 35

11.13.7 Technical Specifications
The technical specifications of the EFF8A include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 11-135 lists the parameters specified for the optical interfaces of the EFF8A.
Table 11-135 Parameters specified for the optical interfaces of the EFF8A
Parameter Value
Nominal bit rate 10 Mbit/s or 100 Mbit/s
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Parameter Value
Line code pattern Manchester encoding signal (10M) or MLT-3 encoding signal
(100M)
Type of optical
interface
100BASE-FX
Operating
wavelength range
(nm)
100BASE-FX (15 km): 1261 to 1360
100BASE-FX (2 km): 1270 to 1380
Type of fiber Single-mode LC (15 km), Multi-mode LC (2 km)
Mean launched
optical power (dBm)
100BASE-FX (15 km): -15 to -8
100BASE-FX (2 km): -19 to -14
Receiver sensitivity
(dBm)
100BASE-FX (15 km): -28
100BASE-FX (2 km): -30
Minimum overload
(dBm)
100BASE-FX (15 km): -7
100BASE-FX (2 km): -14
Minimum extinction
ratio (dB)
10

Mechanical Specifications
The mechanical specifications of the EFF8A are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
The maximum power consumption of the EFF8A at room temperature (25C) is 15 W.
11.14 ETF8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ETF8 (8x100M Ethernet twisted pair interface board).
11.14.1 Version Description
The ETF8 is available in one functional version, namely, N1.
11.14.2 Application
The ETF8 is an Ethernet electrical interface board. The ETF8 can be used on the OptiX OSN
equipment series to transmit and receive 100M Ethernet electrical signals for the data board.
11.14.3 Functions and Features
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The ETF8 receives and transmits 8x100M Ethernet electrical signals. The ETF8 must work with
the EFT8.
11.14.4 Working Principle and Signal Flow
The ETF8 consists of the interface module and power module.
11.14.5 Front Panel
The front panel of the ETF8 has interfaces and a bar code.
11.14.6 Valid Slots
The ETF8 can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the subrack and works
as the interface board of the EFT8, EFS0, EMR0 or EFP0. The ETF8 can be installed in slots
1926 and 2936 in the subrack and works as the interface board of the EMS4.
11.14.7 Technical Specifications
The technical specifications of the ETF8 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
11.14.1 Version Description
The ETF8 is available in one functional version, namely, N1.
11.14.2 Application
The ETF8 is an Ethernet electrical interface board. The ETF8 can be used on the OptiX OSN
equipment series to transmit and receive 100M Ethernet electrical signals for the data board.
11.14.3 Functions and Features
The ETF8 receives and transmits 8x100M Ethernet electrical signals. The ETF8 must work with
the EFT8.
11.14.4 Working Principle and Signal Flow
The ETF8 consists of the interface module and power module.
Figure 11-72 shows the functional block diagram of the ETF8 by describing how to process
1x100 Mbit/s Ethernet signals.
Figure 11-72 Functional block diagram of the ETF8
Backplane
+3.3 V backup power
+3.3 V Fuse
EFT8/EFS0/EMS4/EMR0
100 Mbit/s
Ethernet signal
module
Interface
Power
module
100 Mbit/s
Ethernet signal
EFT8/EFS0/EMS4/EMR0
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Interface Module
In the receive direction, the interface module performs O/E conversion for the Ethernet signals
and transmits the signals to the EFT8, EFS0, EMS4, or EMR0.
In the transmit direction, the interface module performs E/O conversion for the Ethernet signals
and transmits the signals to the optical interface.
Power Module
The power module provides all the modules of the ETF8 with the required DC voltages.
11.14.5 Front Panel
The front panel of the ETF8 has interfaces and a bar code.
Diagram of the Front Panel
Figure 11-73 shows the appearance of the front panel of the ETF8.
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Figure 11-73 Front panel of the ETF8
ETF8
ETF8
F
E
1
F
E
2
F
E
3
F
E
4
F
E
5
F
E
6
F
E
7
F
E
8

Interfaces
The front panel of the ETF8 has eight electrical interfaces.
Table 11-136 describes the types and usage of the interfaces of the ETF8.
Table 11-136 Interfaces of the ETF8
Interface Type of
Interface
Usage
FE1FE8 RJ-45 Receives the 1st to the 8th channels of Ethernet
electrical signals.

Table 11-137 provides the pin assignments of the RJ-45 connector of the ETF8.
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Table 11-137 Pin assignments of the RJ-45 connector of the ETF8
Front View Pin Description
8 7 6 5 4 3 2 1
1 Transmitting (+)
2 Transmitting ()
3 Receiving (+)
4 Grounding
5 Grounding
6 Receiving ()
7 Grounding
8 Grounding

11.14.6 Valid Slots
The ETF8 can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the subrack and works
as the interface board of the EFT8, EFS0, EMR0 or EFP0. The ETF8 can be installed in slots
1926 and 2936 in the subrack and works as the interface board of the EMS4.
Table 11-138 lists the slots valid for the EFT8/EFS0/EMR0/EFP0 and the corresponding slots
for the ETF8.
Table 11-138 Slots valid for the EFT8/EFS0/EMR0/EFP0 and the corresponding slots for the
ETF8
Slot Valid for the EFT8/EFS0/
EMR0/EFP0
Corresponding Slot for the ETF8
Slot 2 Slots 19
Slot 3 Slots 21
Slot 4 Slots 23
Slot 5 Slots 25
Slot 13 Slots 29
Slot 14 Slots 31
Slot 15 Slots 33
Slot 16 Slots 35

Table 11-139 lists the slots valid for the EMS4 and the corresponding slots for the ETF8.
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Table 11-139 Slots valid for the EMS4 and the corresponding slots for the ETF8
Slot Valid for the EMS4 Corresponding Slot for the ETF8
Slot 2 Slots 19 and 20
Slot 3 Slots 21 and 22
Slot 4 Slots 23 and 24
Slot 5 Slots 25 and 26
Slot 13 Slots 29 and 30
Slot 14 Slots 31 and 32
Slot 15 Slots 33 and 34
Slot 16 Slots 35 and 36

11.14.7 Technical Specifications
The technical specifications of the ETF8 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
Table 11-140 lists the parameters specified for the electrical interfaces of the ETF8.
Table 11-140 Parameters specified for the optical interfaces of the ETF8
Parameter Value
Nominal bit rate 10 Mbit/s or 100 Mbit/s
Line code pattern Manchester encoding signal (10M) or MLT-3
encoding signal (100M)
Specifications of the
interface
Complies with IEEE 802.3u.

Mechanical Specifications
The mechanical specifications of the ETF8 are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
The maximum power consumption of the ETF8 at room temperature (25C) is 2 W.
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11.15 ETF8A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ETF8A (8x100M Ethernet twisted pair interface board).
11.15.1 Version Description
The ETF8A is available in one functional version, namely, N1.
11.15.2 Application
The ETF8A is an Ethernet electrical interface board. The ETF8A can be used on the OptiX OSN
equipment series to transmit and receive 100M Ethernet electrical signals for the data board.
11.15.3 Functions and Features
The ETF8A receives and transmits 8x100M Ethernet electrical signals. The ETF8A must work
with the N5EFS0.
11.15.4 Working Principle and Signal Flow
The ETF8A consists of the interface module and power module.
11.15.5 Front Panel
The front panel of the ETF8A has interfaces and a bar code.
11.15.6 Valid Slots
The ETF8A can be installed in slots 1926 and 2936 in the subrack and works as the interface
board of the N5EFS0.
11.15.7 Technical Specifications
The technical specifications of the ETF8A include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
11.15.1 Version Description
The ETF8A is available in one functional version, namely, N1.
11.15.2 Application
The ETF8A is an Ethernet electrical interface board. The ETF8A can be used on the OptiX OSN
equipment series to transmit and receive 100M Ethernet electrical signals for the data board.
11.15.3 Functions and Features
The ETF8A receives and transmits 8x100M Ethernet electrical signals. The ETF8A must work
with the N5EFS0.
11.15.4 Working Principle and Signal Flow
The ETF8A consists of the interface module and power module.
Figure 11-74 shows the functional block diagram of the ETF8A by describing how to process
1x100 Mbit/s Ethernet signals.
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Figure 11-74 Functional block diagram of the ETF8A
N5EFS0
Backplane
+3.3 V backup power
+3.3 V Fuse
100 Mbit/s
Ethernet signal
module
Interface
Power
module
N5EFS0
100 Mbit/s
Ethernet signal

Interface Module
In the receive direction, the interface module performs O/E conversion for the Ethernet signals
and transmits the signals to the N5EFS0.
In the transmit direction, the interface module performs E/O conversion for the Ethernet signals
and transmits the signals to the optical interface.
Power Module
The power module provides all the modules of the ETF8A with the required DC voltages.
11.15.5 Front Panel
The front panel of the ETF8A has interfaces and a bar code.
Diagram of the Front Panel
Figure 11-75 shows the appearance of the front panel of the ETF8A.
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Figure 11-75 Front panel of the ETF8A
ETF8A
ETF8A
F
E
1
F
E
2
F
E
3
F
E
4
F
E
5
F
E
6
F
E
7
F
E
8

Interfaces
The front panel of the ETF8A has eight electrical interfaces.
Table 11-141 describes the types and usage of the interfaces of the ETF8A.
Table 11-141 Interfaces of the ETF8A
Interface Type of
Interface
Usage
FE1FE8 RJ-45 Receives the 1st to the 8th channels of Ethernet
electrical signals.

Table 11-142 provides the pin assignments of the RJ-45 connector of the ETF8A.
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Table 11-142 Pin assignments of the RJ-45 connector of the ETF8A
Front View Pin Description
8 7 6 5 4 3 2 1
1 Transmitting (+)
2 Transmitting ()
3 Receiving (+)
4 Grounding
5 Grounding
6 Receiving ()
7 Grounding
8 Grounding

11.15.6 Valid Slots
The ETF8A can be installed in slots 1926 and 2936 in the subrack and works as the interface
board of the N5EFS0.
Table 11-143 lists the slots valid for the N5EFS0 and the corresponding slots for the ETF8A.
Table 11-143 Slots valid for the N5EFS0 and the corresponding slots for the ETF8A
Slot Valid for the N5EFS0 Corresponding Slot for the ETF8A
Slot 2 Slot 19
Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33
Slot 16 Slot 35

11.15.7 Technical Specifications
The technical specifications of the ETF8A include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
Table 11-144 lists the parameters specified for the electrical interfaces of the ETF8A.
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Table 11-144 Parameters specified for the optical interfaces of the ETF8A
Parameter Value
Nominal bit rate 10 Mbit/s or 100 Mbit/s
Line code pattern Manchester encoding signal (10M) or MLT-3
encoding signal (100M)
Specifications of the
interface
Complies with IEEE 802.3u.

Mechanical Specifications
The mechanical specifications of the ETF8A are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
The maximum power consumption of the ETF8A at room temperature (25C) is 11 W.
11.16 ETS8
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the ETS8 (8x10/100M Ethernet twisted pair interface switching
board).
11.16.1 Version Description
The ETS8 is available in one functional version, namely, N1.
11.16.2 Application
The ETS8 is an Ethernet electrical interface protection switching board. The ETS8 can be used
on the OptiX OSN equipment series to realize the TPS protection on the data board.
11.16.3 Functions and Features
The ETS8 is used to provide the TPS protection for 8xFE signals at the electrical interface. The
ETS8 must work with the EFS0 or EFS0A.
11.16.4 Working Principle and Signal Flow
The ETS8 consists of the interface module, switch matrix module, and power module.
11.16.5 Front Panel
The front panel of the ETS8 has interfaces and a bar code.
11.16.6 Valid Slots
The ETS8 can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the subrack and works
as the interface board of the EFS0. The ETS8 can be installed in slots 19, 21, 22, 23, 25, 29, 31,
33, 34, and 35 in the subrack and works as the interface board of the EFS0A.
11.16.7 Technical Specifications
The technical specifications of the ETS8 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
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11.16.1 Version Description
The ETS8 is available in one functional version, namely, N1.
11.16.2 Application
The ETS8 is an Ethernet electrical interface protection switching board. The ETS8 can be used
on the OptiX OSN equipment series to realize the TPS protection on the data board.
11.16.3 Functions and Features
The ETS8 is used to provide the TPS protection for 8xFE signals at the electrical interface. The
ETS8 must work with the EFS0 or EFS0A.
11.16.4 Working Principle and Signal Flow
The ETS8 consists of the interface module, switch matrix module, and power module.
Figure 11-76 shows the functional block diagram of the ETS8 by describing how to process
1x100 Mbit/s Ethernet signals.
Figure 11-76 Functional block diagram of the ETS8
+3.3 V backup power
+3.3 V
TSB8 Interface
module
Cross-connect board
Backplane
Power
module
Switch
matrix
module
100 Mbit/s
Ethernet signal
EFS0
TSB8
Fuse
EFS0
100 Mbit/s
Ethernet signal

Interface Module
The interface module receives and transmits the Ethernet optical signals.
Switch Matrix Module
In the receive direction, the switch matrix module receives the signal sent from the interface
module and selects the output direction of the signal according to the TPS protection control
signal sent from the cross-connect board. When the TPS is not performed, the switch matrix
module transmits the signal to the EFS0. When the TPS is performed, the switch matrix module
transmits the signal to the TSB8 for bridging.
In the transmit direction, the switch matrix module performs the reverse process.
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Power Module
The power module provides all the modules of the ETS8 with the required DC voltages.
11.16.5 Front Panel
The front panel of the ETS8 has interfaces and a bar code.
Diagram of the Front Panel
Figure 11-77 shows the appearance of the front panel of the ETS8.
Figure 11-77 Front panel of the ETS8
ETS8
ETS8
F
E
1
F
E
2
F
E
3
F
E
4
F
E
5
F
E
6
F
E
7
F
E
8

Interfaces
The front panel of the ETS8 has eight electrical interfaces.
Table 11-145 describes the types and usage of the interfaces of the ETS8.
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Table 11-145 Interfaces of the ETS8
Interface Type of
Interface
Usage
FE1FE8 RJ-45 Receives the 1st to the 8th channels of Ethernet
electrical signals.

Table 11-146 provides the pin assignments of the RJ-45 connector of the ETS8.
Table 11-146 Pin assignments of the RJ-45 connector of the ETS8
Front View Pin Description
8 7 6 5 4 3 2 1

1 Transmitting (+)
2 Transmitting ()
3 Receiving (+)
4 Grounding
5 Grounding
6 Receiving ()
7 Grounding
8 Grounding

11.16.6 Valid Slots
The ETS8 can be installed in slots 19, 21, 23, 25, 29, 31, 33, and 35 in the subrack and works
as the interface board of the EFS0. The ETS8 can be installed in slots 19, 21, 22, 23, 25, 29, 31,
33, 34, and 35 in the subrack and works as the interface board of the EFS0A.
Table 11-147 lists the slots valid for the EFS0 and the corresponding slots for the ETS8.
Table 11-147 Slots valid for the EFS0 and the corresponding slots for the ETS8
Slot Valid for the EFS0 Corresponding Slot for the ETS8
Slot 2 Slot 19
Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 13 Slot 29
Slot 14 Slot 31
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Slot Valid for the EFS0 Corresponding Slot for the ETS8
Slot 15 Slot 33
Slot 16 Slot 35

Table 11-148 lists the slots valid for the EFS0A and the corresponding slots for the ETS8.
Table 11-148 Slots valid for the EFS0A and the corresponding slots for the ETS8
Slot Valid for the EFS0A Corresponding Slot for the ETS8
Slot 2 Slot 19
Slot 3 Slot 21 and 22
Slot 4 Slot 23
Slot 5 Slot 25
Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33 and 34
Slot 16 Slot 35

11.16.7 Technical Specifications
The technical specifications of the ETS8 include the parameters specified for electrical
interfaces, mechanical specifications, and power consumption.
Parameters Specified for Electrical Interfaces
Table 11-149 lists the parameters specified for the electrical interfaces of the ETS8.
Table 11-149 Parameters specified for the optical interfaces of the ETS8
Parameter Value
Nominal bit rate 10 Mbit/s or 100 Mbit/s
Line code pattern Manchester encoding signal (10M) or MLT-3
encoding signal (100M)
Specifications of the
interface
Complies with IEEE 802.3u.

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Mechanical Specifications
The mechanical specifications of the ETS8 are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
At room temperature (25C), the maximum power consumption of the ETS8 is 0 W.
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12 ATM Boards
About This Chapter
The ATM boards include STM-1 and STM-4 ATM service processing boards.
12.1 ADL4
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the ADL4 (1xSTM-4 ATM service processing board). This topic also
describes how to configure and commission the ADL4.
12.2 ADQ1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the ADQ1 (4xSTM-1 ATM service processing board). This topic also
describes how to configure and commission the ADQ1.
12.3 IDL4
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the IDL4 (1xSTM-4 ATM service processing board). This topic also
describes how to configure and commission the IDL4.
12.4 IDQ1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the IDQ1 (4xSTM-1 ATM service processing board). This topic also
describes how to configure and commission the IDQ1.
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12-1
12.1 ADL4
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the ADL4 (1xSTM-4 ATM service processing board). This topic also
describes how to configure and commission the ADL4.
12.1.1 Version Description
The ADL4 is available in one functional version, namely, N1.
12.1.2 Application
The ATM board is used in the network that is based on ATM switching and transmission. The
ATM board can carry various types of ATM services.
12.1.3 Functions and Features
The ADL4 supports the ATM switching and ATM protection.
12.1.4 Working Principle and Signal Flow
The ADL4 consists of the O/E converting module, physical layer module, ATM module, E3
module, mapping module, logic and control module, clock module, and power module.
12.1.5 Front Panel
The front panel of the ADL4 has indicators, interfaces, a bar code, and a laser safety class label.
12.1.6 Jumpers and DIP Switches
The ADL4 does not have any jumpers or DIP switches that are used for board settings.
12.1.7 Valid Slots
The ADL4 must be installed in a valid slot in the subrack. Otherwise, the ADL4 cannot work
normally.
12.1.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the ADL4 indicates the type of optical interface.
12.1.9 Parameter Settings
You can set parameters for the ADL4 by using the T2000.
12.1.10 Technical Specifications
The technical specifications of the ADL4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
12.1.1 Version Description
The ADL4 is available in one functional version, namely, N1.
12.1.2 Application
The ATM board is used in the network that is based on ATM switching and transmission. The
ATM board can carry various types of ATM services.
The ADL4 provides one standard STM-4 optical interface and can be interconnected with the
switch or DSLAM to transmit the ATM services. In addition, the ADL4 can switch cell headers
to converge and multiplex bandwidths so that the bandwidths are not wasted. The ADL4 supports
the following types of application of the ATM services:
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l Application of the ATM services that occupy bandwidths exclusively
l Application of the ATM services that share bandwidths
Application of the ATM Services That Occupy Bandwidths Exclusively
When the ATM services do not share bandwidths, only the ATM service processing boards on
the source NE and sink NE perform ATM layer processing for the ATM services. The
intermediate NEs that the ATM services traverse do not perform ATM layer processing and only
pass through the ATM services on the SDH timeslots. In this case, each ATM service occupies
the VC-3 or VC-4 channel exclusively. The ATM services can be converged at the central node
and then transmitted on the STM-4 optical interface. Figure 12-1 shows the networking and
application of the ATM services that occupy bandwidths exclusively.
Figure 12-1 Networking and application of the ATM services that occupy bandwidths
exclusively
2.5 Gbit/s
SDH ring
NE2 NE4
NE1
NE3
34 Mbit/s
ATM traffic
622 Mbit/s
ATM traffic
Service
convergence
DSLAM
DSLAM
Router DSLAM
155 Mbit/s
ATM traffic
34 Mbit/s
ATM traffic

Application of the ATM Services That Share Bandwidths
The VP-ring and VC-ring realize bandwidth sharing and statistical multiplexing for the ATM
services. The ATM services on each NE share one VC (VC-3, VC-4, or VC-4-Xv) channel. In
this case, each NE performs ATM layer processing for the ATM services. Figure 12-2 shows
the networking and application of the ATM services that share bandwidths.
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Figure 12-2 Networking and application of the ATM services that share bandwidths
VC4-Xv
VP/VC-ring
NE2
NE4
NE1
NE3
34 Mbit/s
ATM traffic
DSLAM
DSLAM
Router
DSLAM
622 Mbit/s
ATM traffic
34 Mbit/s
ATM traffic
155 Mbit/s
ATM traffic
The ATM services on NE1 are
dropped on NE2, then converged
with the other ATM services, and
finally sent to the VP/VC-ring.

12.1.3 Functions and Features
The ADL4 supports the ATM switching and ATM protection.
Table 12-1 provides the functions and features of the ADL4.
Table 12-1 Functions and features of the ADL4
Function and
Feature
ADL4
Basic functions Accesses and processes 1xSTM-4 ATM services.
Type of optical
interface
Supports the following types of optical interfaces: S-4.1, L-4.1,
L-4.2 and Ve-4.2.
Connector type LC
Type of optical module SFP
E3 ATM interface Supports 12xE3 signals, which are accessed through the PD3, PL3,
or N1PL3A.
IMA function Does not support the IMA function.
Maximum uplink
bandwidth
Supports a bandwidth of 8xVC-4s, or a bandwidth of 12xVC-3s
and 4xVC-4s.
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Function and
Feature
ADL4
ATM switching
capability
1.2 Gbit/s
Mapping granularities Supports VC-3, VC-4, and VC4-Xv (X = 14) granularities.
Service types Supports the CBR, rt-VBR, nrt-VBR, and UBR.
Number of supported
ATM connections
2048
Statistical multiplexing Supports the statistical multiplexing.
Flow types and QoS Complies with IETF RFC2514 and ATM forum TM4.0.
ATM multicast
connection
Supports the spatial multicast and logical multicast.
ATM protection (ITU-
T I.630)
Supports the unidirectional/bidirectional 1+1, unidirectional/
bidirectional 1:1, VP-Ring, and VC-Ring protection schemes.
OAM functions (ITU-T
I.610)
Supports the AIS, RDI, LB , and CC.
Maintenance features Supports inloops at the ATM layer and on optical interfaces.
Supports outloops at the ATM layer.
These features can be used to locate faults quickly.
Alarms and
performance events
Reports various alarms and performance events, which can be used
to locate faults and maintain the equipment.

12.1.4 Working Principle and Signal Flow
The ADL4 consists of the O/E converting module, physical layer module, ATM module, E3
module, mapping module, logic and control module, clock module, and power module.
Figure 12-3 shows the functional block diagram of the ADL4 by describing how to process
1xSTM-4 signals.
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Figure 12-3 Functional block diagram of the ADL4
E/O
O/E
Physical
layer
module
ATM
module
Mapping
module
E3
module
High-speed
bus
Logic and
control module
LOS
Laser shutdown
Reference clock and frame header
Communication
SCC unit
Clock
module
50 MHz
77 MHz
100 MHz
+3.3 V backup power
+3.3 V
Fuse
Fuse
-48 V/-60 V Power
module
622
Mbit/s
622
Mbit/s
Cross-connect unit
Power
module
O/E converting
module
Backplane
-48 V/-60 V
Cross-connect unit
Cross-connect unit
High-speed
bus
622
Mbit/s
622
Mbit/s

O/E Converting Module
In the receive direction, optical signals are converted into electrical signals. In the transmit
direction, electrical signals are converted into optical signals.
Physical Layer Module
The physical layer module mainly performs the following functions:
l Maps ATM cells into SDH frames.
l Demaps SDH frames to ATM cells.
l Implements the following functions at the ATM service physical layer: cell delimitation,
and test and generation of header error control (HEC) sequence.
ATM Module
The ATM module mainly performs the following ATM layer functions that are specified in
ATM protocols:
l Flow control
l Extraction and generation of cell headers
l ATM switching
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E3 Module
The E3 module mainly processes ATM services at the E3 rate. This module performs the
following functions:
l Maps the ATM cells into E3 containers.
l Demaps E3 containers to ATM cells.
l Implements functions at the ATM physical layer for ATM services at the E3 rate.
Mapping Module
The mapping module performs the following functions:
l Maps ATM cells into SDH frame payloads.
l Demaps SDH frame payloads to ATM cells.
l Implements functions at the ATM physical layer.
l Implements the VC4-Xv (X4) virtual concatenation.
Logic and Control Module
The logic and control module performs the following functions:
l Controls writing and reading of each chip.
l Communicates with the NE.
l Issues configured services.
l Reports alarms of each functional module.
l Detects R_LOS alarms of optical modules.
l Controls the shutting down of the laser.
Clock Module
This module mainly generates the required working clock for each chip. The frequency of the
clock can be 50 MHz, 77 MHz, or 100 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
12.1.5 Front Panel
The front panel of the ADL4 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 12-4 shows the appearance of the front panel of the ADL4.
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Figure 12-4 Front panel of the ADL4
ADL4
ADL4
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the ADL4 has one optical interface. Table 12-2 describes the type and usage
of the optical interface of the ADL4.
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Table 12-2 Optical interface of the ADL4
Interface Type of
Interface
Usage
OUT1/IN1 LC
(swappable)
Transmits and receives STM-4 optical signals.

12.1.6 Jumpers and DIP Switches
The ADL4 does not have any jumpers or DIP switches that are used for board settings.
12.1.7 Valid Slots
The ADL4 must be installed in a valid slot in the subrack. Otherwise, the ADL4 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the ADL4 vary with the cross-connect capacity of the subrack. The slots valid
for the ADL4 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the ADL4 can be installed in slots 18 and
1117. In this case, the bandwidth is 1.25 Gbit/s.
12.1.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the ADL4 indicates the type of optical interface.
Table 12-3 provides the relationship between the feature code of the ADL4 and the type of
optical interface.
Table 12-3 Relationship between the feature code of the ADL4 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1ADL410 10 S-4.1
SSN1ADL411 11 L-4.1
SSN1ADL412 12 L-4.2
SSN1ADL413 13 Ve-4.2

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12.1.9 Parameter Settings
You can set parameters for the ADL4 by using the T2000.
You can set the following main parameters for the ADL4 by using the T2000:
l Port type
l Flow type
l Service type
l Peak cell rate (PCR)
l Sustainable cell rate (SCR)
l Maximum cell burst size
l Cell delay variation tolerance (CDVT)
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
12.1.10 Technical Specifications
The technical specifications of the ADL4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 12-4 lists the parameters specified for the optical interfaces of the ADL4.
Table 12-4 Parameters specified for the optical interfaces of the ADL4
Parameter Value
Type of optical
interface
S-4.1 L-4.1 L-4.2 Ve-4.2
Type of fiber Single-mode LC Single-mode
LC
Single-mode
LC
Single-mode
LC
Operating
wavelength range
(nm)
1274 to 1356 1280 to 1335 1480 to 1580 1480 to 1580
Launched optical
power range
(dBm)
-15 to -8 -3 to +2 -3 to +2 -3 to +2
Minimum
overload (dBm)
-8 -8 -8 -13
Receiver
sensitivity (dBm)
-28 -28 -28 -34
Minimum
extinction ratio
(dB)
8.2 10 10 10.5
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Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the ADL4 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.9
Power Consumption
The maximum power consumption of the ADL4 at room temperature (25C) is 41 W.
12.2 ADQ1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the ADQ1 (4xSTM-1 ATM service processing board). This topic also
describes how to configure and commission the ADQ1.
12.2.1 Version Description
The ADQ1 is available in one functional version, namely, N1.
12.2.2 Application
The ATM board is used in the network that is based on ATM switching and transmission. The
ATM board can carry various types of ATM services.
12.2.3 Functions and Features
The ADQ1 supports the ATM switching and ATM protection.
12.2.4 Working Principle and Signal Flow
The ADQ1 consists of the O/E converting module, physical layer module, ATM module, E3
module, mapping module, logic and control module, clock module, and power module.
12.2.5 Front Panel
The front panel of the ADQ1 has indicators, interfaces, a bar code, and a laser safety class label.
12.2.6 Jumpers and DIP Switches
The ADQ1 does not have any jumpers or DIP switches that are used for board settings.
12.2.7 Valid Slots
The ADQ1 must be installed in a valid slot in the subrack. Otherwise, the ADQ1 cannot work
normally.
12.2.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the ADQ1 indicates the type of optical interface.
12.2.9 Parameter Settings
You can set parameters for the ADQ1 by using the T2000.
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12.2.10 Technical Specifications
The technical specifications of the ADQ1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
12.2.1 Version Description
The ADQ1 is available in one functional version, namely, N1.
12.2.2 Application
The ATM board is used in the network that is based on ATM switching and transmission. The
ATM board can carry various types of ATM services.
The ADQ1 provides four standard STM-1 optical interfaces and can be interconnected with the
switch or DSLAM to transmit the ATM services. In addition, the ADQ1 can switch cell headers
to converge and multiplex bandwidths so that the bandwidths are not wasted. The ADQ1 supports
the following types of application of the ATM services:
l Application of the ATM Services That Occupy Bandwidths Exclusively
l Application of the ATM Services That Share Bandwidths
Application of the ATM Services That Occupy Bandwidths Exclusively
When the ATM services do not share bandwidths, only the ATM service processing boards on
the source NE and sink NE perform ATM layer processing for the ATM services. The
intermediate NEs that the ATM services traverse do not perform ATM layer processing and only
pass through the ATM services on the SDH timeslots. In this case, each ATM service occupies
the VC-3 or VC-4 channel exclusively. The ATM services can be converged at the central node
and then transmitted on the STM-1 optical interface. Figure 12-5 shows the networking and
application of the ATM services that occupy bandwidths exclusively.
Figure 12-5 Networking and application of the ATM services that occupy bandwidths
exclusively
2.5 Gbit/s
SDH ring
NE2 NE4
NE1
NE3
34 Mbit/s
ATM traffic
622 Mbit/s
ATM traffic
Service
convergence
DSLAM
DSLAM
Router DSLAM
155 Mbit/s
ATM traffic
34 Mbit/s
ATM traffic
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Application of the ATM Services That Share Bandwidths
The VP-ring and VC-ring realize bandwidth sharing and statistical multiplexing for the ATM
services. The ATM services on each NE share one VC (VC-3, VC-4, or VC-4-Xv) channel. In
this case, each NE performs ATM layer processing for the ATM services. Figure 12-6 shows
the networking and application of the ATM services that share bandwidths.
Figure 12-6 Networking and application of the ATM services that share bandwidths
VC4-Xv
VP/VC-ring
NE2
NE4
NE1
NE3
34 Mbit/s
ATM traffic
DSLAM
DSLAM
Router
DSLAM
622 Mbit/s
ATM traffic
34 Mbit/s
ATM traffic
155 Mbit/s
ATM traffic
The ATM services on NE1 are
dropped on NE2, then converged
with the other ATM services, and
finally sent to the VP/VC-ring.

12.2.3 Functions and Features
The ADQ1 supports the ATM switching and ATM protection.
Table 12-5 provides the functions and features of the ADQ1.
Table 12-5 Functions and features of the ADQ1
Function and
Feature
ADQ1
Basic functions Accesses and processes 4xSTM-1 ATM services.
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Function and
Feature
ADQ1
Type of optical
interface
Supports different types of standard optical interfaces, namely, the
Ie-1, S-1.1, L-1.1, L-1.2, and Ve-1.2. The characteristics of the
optical interfaces of the I-1, S-1.1, L-1.1, and L-1.2 types comply
with ITU-T G.957. The characteristics of the optical interfaces of
the Ie-1 and Ve-1.2 types comply with the standards defined by
Huawei.
Connector type LC
Optical module type SFP
E3 ATM interface Supports 12xE3 signals, which are accessed through the PD3, PL3,
or N1PL3A.
IMA function Does not support the IMA function.
Maximum uplink
bandwidth
Supports a bandwidth of 8xVC-4s, or a bandwidth of 12xVC-3s and
4xVC-4s.
ATM switching
capability
1.2 Gbit/s
Mapping granularities Supports VC-3, VC-4, and VC4-Xv (X = 14) granularities.
Service types Supports the CBR, rt-VBR, nrt-VBR and UBR.
Number of supported
ATM connections
2048
Statistical
multiplexing
Supports the statistical multiplexing.
Flow types and QoS Complies with IETF RFC2514 and ATM forum TM4.0.
ATM multicast
connection
Supports the spatial multicast and logical multicast.
ATM protection (ITU-
T I.630)
Supports the unidirectional/bidirectional 1+1, unidirectional/
bidirectional 1:1, VP-Ring, and VC-Ring protection schemes.
OAM functions (ITU-
T I.610)
Supports the AIS, RDI, LB , and CC.
Maintenance features Supports inloops at the ATM layer and on optical interfaces.
Supports outloops at the ATM layer.
These features can be used to locate faults quickly.
Alarms and
performance events
Reports various alarms and performance events, which can be used
to locate faults and maintain the equipment.

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12.2.4 Working Principle and Signal Flow
The ADQ1 consists of the O/E converting module, physical layer module, ATM module, E3
module, mapping module, logic and control module, clock module, and power module.
Figure 12-7 shows the functional block diagram of the ADQ1.
Figure 12-7 Functional block diagram of the ADQ1
E/O
O/E
Physical
layer
module
ATM
module
Mapping
module
E3
module
High-speed
bus
Logic and
control module
LOS
Laser shutdown
Reference clock and frame header
Communication
SCC unit
Clock
module
50 MHz
77 MHz
100 MHz
+3.3 V backup power
+3.3 V
Fuse
Fuse
-48 V/-60 V Power
module
4x155
Mbit/s
Cross-connect unit
Power
module
O/E converting
module
Backplane
-48 V/-60 V
Cross-connect unit
Cross-connect unit
High-speed
bus
4x155
Mbit/s
4x155
Mbit/s
4x155
Mbit/s

O/E Converting Module
In the receive direction, optical signals are converted into electrical signals. In the transmit
direction, electrical signals are converted into optical signals.
Physical Layer Module
The physical layer module mainly performs the following functions:
l Maps ATM cells into SDH frames.
l Demaps SDH frames to ATM cells.
l Implements the following functions at the ATM service physical layer: cell delimitation,
and test and generation of HEC sequence.
ATM Module
The ATM module mainly performs the following ATM layer functions that are specified in
ATM protocols:
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l Flow control
l Extraction and generation of cell headers
l ATM switching
E3 Module
The E3 module mainly processes ATM services at the E3 rate. This module performs the
following functions:
l Maps the ATM cells into E3 containers.
l Demaps E3 containers to ATM cells.
l Implements functions at the ATM physical layer for ATM services at the E3 rate.
Mapping Module
The mapping module performs the following functions:
l Maps ATM cells into SDH frame payloads.
l Demaps SDH frame payloads to ATM cells.
l Implements functions at the ATM physical layer.
l Implements the VC4-Xv (X4) virtual concatenation.
Logic and Control Module
The logic and control module performs the following functions:
l Controls writing and reading of each chip.
l Communicates with the NE.
l Issues configured services.
l Reports alarms of each functional module.
l Detects R_LOS alarms of optical modules.
l Controls the shutting down of the laser.
Clock Module
This module mainly generates the required working clock for each chip. The frequency of the
clock can be 50 MHz, 77 MHz, or 100 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
12.2.5 Front Panel
The front panel of the ADQ1 has indicators, interfaces, a bar code, and a laser safety class label.
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Diagram of the Front Panel
Figure 12-8 shows the appearance of the front panel of the ADQ1.
Figure 12-8 Front panel of the ADQ1
ADQ1
ADQ1
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the ADQ1 has four optical interfaces. Table 12-6 describes the types and
usage of the optical interfaces of the ADQ1.
Table 12-6 Optical interfaces of the ADQ1
Interface Type of
Interface
Usage
OUT1/IN1 LC (swappable) Transmits and receives STM-1 optical signals.
OUT2/IN2 LC (swappable) Transmits and receives STM-1 optical signals.
OUT3/IN3 LC (swappable) Transmits and receives STM-1 optical signals.
OUT4/IN4 LC (swappable) Transmits and receives STM-1 optical signals.

12.2.6 Jumpers and DIP Switches
The ADQ1 does not have any jumpers or DIP switches that are used for board settings.
12.2.7 Valid Slots
The ADQ1 must be installed in a valid slot in the subrack. Otherwise, the ADQ1 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the ADQ1 vary with the cross-connect capacity of the subrack. The slots valid
for the ADQ1 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the ADQ1 can be installed in slots 18 and
1117. In this case, the bandwidth is 1.25 Gbit/s.
12.2.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the ADQ1 indicates the type of optical interface.
Table 12-7 provides the relationship between the feature code of the ADQ1 and the type of
optical interface.
Table 12-7 Relationship between the feature code of the ADQ1 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1ADQ110 10 S-1.1
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Board Feature Code Type of Optical Interface
SSN1ADQ111 11 L-1.1
SSN1ADQ112 12 L-1.2
SSN1ADQ113 13 Ve-1.2
SSN1ADQ114 14 Ie-1

12.2.9 Parameter Settings
You can set parameters for the ADQ1 by using the T2000.
You can set the following main parameters for the ADQ1 by using the T2000:
l Port type
l Flow type
l Service type
l PCR
l SCR
l Maximum cell burst size
l CDVT
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
12.2.10 Technical Specifications
The technical specifications of the ADQ1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 12-8 lists the parameters specified for the optical interfaces of the ADQ1.
Table 12-8 Parameters specified for the optical interfaces of the ADQ1
Parameter Value
Type of optical
interface
Ie-1 S-1.1 L-1.1 L-1.2 Ve-1.2
Type of fiber Multi-
mode LC
Single-mode
LC
Single-mode
LC
Single-
mode LC
Single-mode
LC
Operating
wavelength
range (nm)
1270 to
1380
1261 to 1360 1263 to 1360 1480 to
1580
1480 to 1580
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Parameter Value
Transmission
distance (km)
0 to 0.5 2 to 15 15 to 40 40 to 80 80 to 100
Launched
optical power
range (dBm)
-19 to -14 -15 to -8 -5 to 0 -5 to 0 -3 to 0
Receive optical
power (dBm)
-30 -28 -34 -34 -34
Minimum
overload (dBm)
-14 -8 -10 -10 -10
Minimum
extinction ratio
(dB)
10 8.2 10 10 10

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the ADQ1 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the ADQ1 at room temperature (25C) is 41 W.
12.3 IDL4
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the IDL4 (1xSTM-4 ATM service processing board). This topic also
describes how to configure and commission the IDL4.
12.3.1 Version Description
The IDL4 is available in one functional version, namely, N1.
12.3.2 Application
The IMA technology demultiplexes the assembled ATM cell flow into multiple low-speed links,
and multiplexed the multiple low-speed links on the remote end to restore the original assembled
cell flow. The IMA technology realizes the interconnection between high-speed links and low-
speed links.
12.3.3 Functions and Features
The IDL4 supports the ATM switching, IMA, and ATM protection.
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12.3.4 Working Principle and Signal Flow
The IDL4 consists of the O/E converting module, physical layer module, ATM module, IMA
module, mapping module, logic and control module, clock module, and power module.
12.3.5 Front Panel
The front panel of the IDL4 has indicators, interfaces, a bar code, and a laser safety class label.
12.3.6 Jumpers and DIP Switches
The IDL4 does not have any jumpers or DIP switches that are used for board settings.
12.3.7 Valid Slots
The IDL4 must be installed in a valid slot in the subrack. Otherwise, the IDL4 cannot work
normally.
12.3.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL1 indicates the type of optical interface.
12.3.9 Board Protection
The IDL4 supports the 1+1 board-level protection. The working IDL4 and protection IDL4
should be installed in paired slots.
12.3.10 Parameter Settings
You can set parameters for the IDL4 by using the T2000.
12.3.11 Technical Specifications
The technical specifications of the IDL4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
12.3.1 Version Description
The IDL4 is available in one functional version, namely, N1.
12.3.2 Application
The IMA technology demultiplexes the assembled ATM cell flow into multiple low-speed links,
and multiplexed the multiple low-speed links on the remote end to restore the original assembled
cell flow. The IMA technology realizes the interconnection between high-speed links and low-
speed links.
The IMA board is applicable to the transmission of the ATM cells on the E1 interface or
interfaces at the other rates. The IMA board only provides a channel and does not process the
service type or ATM cells. That is, the IMA board transparently transmits the ATM layer signals
and higher-layer signals. Figure 12-9 shows the networking and application of the IMA services.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 12 ATM Boards
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
12-21
Figure 12-9 Networking and application of the IMA services
Two-fiber bidirectional
MSP ring
NMS
NE1
NE2
NE3
NE4
25 km
35 km
30 km
40 km
RNC
NodeB 1
NodeB 3
NodeB 2
NodeB 4

12.3.3 Functions and Features
The IDL4 supports the ATM switching, IMA, and ATM protection.
Table 12-9 provides the functions and features of the IDL4.
Table 12-9 Functions and features of the IDL4
Function and
Feature
IDL4
Basic functions Accesses and processes 1xSTM-4 ATM services.
Type of optical
interface
Supports the following types of optical interfaces: S-4.1, L-4.1, L-4.2
and Ve-4.2.
Connector type LC
Optical module type SFP
E3 ATM interface Does not support the E3 ATM interface.
IMA functions
(ATM Forum IMA
1.1)
l Accesses and processes IMA services when the IDL4 is used with
the E1 service processing board N1PQ1 or N1PQM.
l Supports a maximum of 63 IMA E1 services.
l Supports the mapping between ATM ports and a maximum of 16
IMA groups. Each IMA group supports 132 E1 signals.
l Supports the mapping between ATM ports and a maximum of 16
E1 links that belong to non-IMA groups.
l Supports the maximum IMA multichannel delay of 226 ms.
12 ATM Boards
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Function and
Feature
IDL4
Maximum uplink
bandwidth
Supports a bandwidth of 8xVC-4s, or a bandwidth of 63xVC-12s and
7xVC-4s.
ATM switching
capability
1.0 Gbit/s
The IDL4 can adapt to the bandwidth of the slot.
Mapping
granularities
Supports VC-12, VC-4, VC4-Xc (X = 14), and VC12-Xv (X = 1
32) granularities.
Service types Supports the CBR, rt-VBR, nrt-VBR and UBR.
Number of supported
ATM connections
2048
Statistical
multiplexing
Supports the statistical multiplexing.
Flow types and QoS Complies with IETF RFC2514 and ATM forum TM4.0.
ATM multicast
connection
Supports the spatial multicast and logical multicast.
ATM protection
(ITU-T I.630)
Supports the unidirectional/bidirectional 1+1, unidirectional/
bidirectional 1:1, VP-Ring, and VC-Ring protection schemes.
Board-level 1+1
protection
Supports the board-level 1+1 protection.
OAM functions
(ITU-T I.610)
Supports the AIS, RDI, LB , and CC.
Maintenance
features
Supports inloops at the ATM layer and on optical interfaces.
Supports outloops at the ATM layer.
These features can be used to locate faults quickly.
Alarms and
performance events
Reports various alarms and performance events, which can be used
to locate faults and maintain the equipment.
Note: The IMA function can encapsulate ATM cells into E1 signals. The IMA group can
coexist with a single E1 signal. The IMA group can dynamically increase or decrease the
bandwidth to improve the bandwidth utilization. The IMA group can also be used to converge
2 Mbit/s services and to interconnect with other IMA equipment.

12.3.4 Working Principle and Signal Flow
The IDL4 consists of the O/E converting module, physical layer module, ATM module, IMA
module, mapping module, logic and control module, clock module, and power module.
Figure 12-10 shows the functional block diagram of the IDL4 by describing how to process
1xSTM-4 signals.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 12 ATM Boards
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Copyright Huawei Technologies Co., Ltd.
12-23
Figure 12-10 Functional block diagram of the IDL4
E/O
O/E
Physical
layer
module
ATM
module
Mapping
module
IMA
module
High-speed
bus
Logic and
control module
LOS
Laser shutdown
Reference clock and frame header
Communication
SCC unit
Clock
module
50 MHz
77 MHz
100 MHz
+3.3 V backup power
+3.3 V
Fuse
Fuse
-48 V/-60 V Power
module
Cross-connect unit A
Power
module
O/E converting
module
Backplane
-48 V/-60 V
Cross-connect unit B
Cross-connect unit
High-speed
bus
622
Mbit/s
622
Mbit/s
622
Mbit/s
622
Mbit/s

O/E Converting Module
In the receive direction, optical signals are converted into electrical signals. In the transmit
direction, electrical signals are converted into optical signals.
Physical Layer Module
The physical layer module mainly performs the following functions:
l Maps ATM cells into SDH frames.
l Demaps SDH frames to ATM cells.
l Implements the following functions at the ATM service physical layer: cell delimitation,
and test and generation of HEC sequence.
ATM Module
The ATM module mainly performs the following ATM layer functions that are specified in
ATM protocols:
l Flow control
l Extraction and generation of cell headers
l ATM switching
12 ATM Boards
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IMA Module
This module mainly performs the following functions that are specified in IMA protocols:
l Separation and re-creation of ATM cells
l Frame synchronization
l Insertion and extraction of IMA control protocol (ICP) cells
l Management of IMA groups
Mapping Module
The mapping module performs the following functions:
l Maps ATM cells into SDH frame payloads.
l Demaps SDH frame payloads to ATM cells.
l Implements functions at the ATM physical layer.
l Implements the VC4-Xv (X4) virtual concatenation.
Logic and Control Module
The logic and control module performs the following functions:
l Controls writing and reading of each chip.
l Communicates with the NE.
l Issues configured services.
l Reports alarms of each functional module.
l Detects R_LOS alarms of optical modules.
l Controls the shutting down of the laser.
Clock Module
This module mainly generates the required working clock for each chip. The frequency of the
clock can be 50 MHz, 77 MHz, or 100 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
12.3.5 Front Panel
The front panel of the IDL4 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 12-11 shows the appearance of the front panel of the IDL4.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 12 ATM Boards
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Copyright Huawei Technologies Co., Ltd.
12-25
Figure 12-11 Front panel of the IDL4
IDL4
IDL4
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the IDL4 has one optical interface. Table 12-10 describes the type and usage
of the optical interface of the IDL4.
12 ATM Boards
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Table 12-10 Optical interface of the IDL4
Interface Type of
Interface
Usage
OUT1/IN1 LC
(swappable)
Transmits and receives STM-4 optical signals.

12.3.6 Jumpers and DIP Switches
The IDL4 does not have any jumpers or DIP switches that are used for board settings.
12.3.7 Valid Slots
The IDL4 must be installed in a valid slot in the subrack. Otherwise, the IDL4 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the IDL4 vary with the cross-connect capacity of the subrack. The slots valid
for the IDL4 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the IDL4 can be installed in slots 18 and
1117. In this case, the bandwidth is 1.25 Gbit/s.
12.3.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the SL1 indicates the type of optical interface.
Table 12-11 provides the relationship between the feature code of the IDL4 and the type of
optical interface.
Table 12-11 Relationship between the feature code of the IDL4 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1IDL410 10 S-4.1
SSN1IDL411 11 L-4.1
SSN1IDL412 12 L-4.2
SSN1IDL413 13 Ve-4.2

OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 12 ATM Boards
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Copyright Huawei Technologies Co., Ltd.
12-27
12.3.9 Board Protection
The IDL4 supports the 1+1 board-level protection. The working IDL4 and protection IDL4
should be installed in paired slots.
The paired slots valid for the IDL4 vary with the cross-connect capacity.
l When the cross-connect capacity is 200 Gbit/s: (slot 8, slot 11), (slot 7, slot 12), (slot 6,
slot 13), (slot 5, slot 14), (slot 4, slot 15), (slot 3, slot 16), and (slot 2, slot 17)
12.3.10 Parameter Settings
You can set parameters for the IDL4 by using the T2000.
You can set the following main parameters for the IDL4 by using the T2000:
l Port type
l Flow type
l Service type
l PCR
l SCR
l Maximum cell burst size
l CDVT
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
12.3.11 Technical Specifications
The technical specifications of the IDL4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 12-12 lists the parameters specified for the optical interfaces of the IDL4.
Table 12-12 Parameters specified for the optical interfaces of the IDL4
Parameter Value
Type of optical
interface
S-4.1 L-4.1 L-4.2 Ve-4.2
Type of fiber Single-mode
LC
Single-mode
LC
Single-mode
LC
Single-mode
LC
Operating
wavelength range
(nm)
1274 to 1356 1280 to 1335 1480 to 1580 1480 to 1580
Launched optical
power range (dBm)
-15 to -8 -3 to +2 -3 to +2 -3 to +2
12 ATM Boards
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Parameter Value
Receiver sensitivity
(dBm)
-28 -28 -28 -34
Minimum overload
(dBm)
-8 -8 -8 -13
Minimum extinction
ratio (dB)
8.2 10 10 10.5

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the IDL4 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the IDL4 at room temperature (25C) is 41 W.
12.4 IDQ1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the IDQ1 (4xSTM-1 ATM service processing board). This topic also
describes how to configure and commission the IDQ1.
12.4.1 Version Description
The IDQ1 is available in one functional version, namely, N1.
12.4.2 Application
The IMA technology demultiplexes the assembled ATM cell flow into multiple low-speed links,
and multiplexed the multiple low-speed links on the remote end to restore the original assembled
cell flow. The IMA technology realizes the interconnection between high-speed links and low-
speed links.
12.4.3 Functions and Features
The IDQ1 supports the ATM switching, IMA, and ATM protection.
12.4.4 Working Principle and Signal Flow
The IDQ1 consists of the O/E converting module, physical layer module, ATM module, IMA
module, mapping module, logic and control module, clock module, and power module.
12.4.5 Front Panel
The front panel of the IDQ1 has indicators, interfaces, a bar code, and a laser safety class label.
12.4.6 Jumpers and DIP Switches
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 12 ATM Boards
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12-29
The IDQ1 does not have any jumpers or DIP switches that are used for board settings.
12.4.7 Valid Slots
The IDQ1 must be installed in a valid slot in the subrack. Otherwise, the IDQ1 cannot work
normally.
12.4.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the IDQ1 indicates the type of optical interface.
12.4.9 Board Protection
The IDQ1 supports the 1+1 board-level protection. The active and standby IDQ1 should be
housed in paired slots.
12.4.10 Parameter Settings
You can set parameters for the IDQ1 by using the T2000.
12.4.11 Technical Specifications
The technical specifications of the IDQ1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
12.4.1 Version Description
The IDQ1 is available in one functional version, namely, N1.
12.4.2 Application
The IMA technology demultiplexes the assembled ATM cell flow into multiple low-speed links,
and multiplexed the multiple low-speed links on the remote end to restore the original assembled
cell flow. The IMA technology realizes the interconnection between high-speed links and low-
speed links.
The IMA board is applicable to the transmission of the ATM cells on the E1 interface or
interfaces at the other rates. The IMA board only provides a channel and does not process the
service type or ATM cells. That is, the IMA board transparently transmits the ATM layer signals
and higher-layer signals. Figure 12-12 shows the networking and application of the IMA
services.
Figure 12-12 Networking and application of the IMA services
Two-fiber bidirectional
MSP ring
NMS
NE1
NE2
NE3
NE4
25 km
35 km
30 km
40 km
RNC
NodeB 1
NodeB 3
NodeB 2
NodeB 4
12 ATM Boards
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Hardware Description
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Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)

12.4.3 Functions and Features
The IDQ1 supports the ATM switching, IMA, and ATM protection.
Table 12-13 provides the functions and features of the IDQ1.
Table 12-13 Functions and features of the IDQ1
Function and
Feature
IDQ1
Basic functions Accesses and processes 4xSTM-1 ATM services.
Type of optical
interface
Supports different types of standard optical interfaces, namely, the Ie-1,
S-1.1, L-1.1, L-1.2, and Ve-1.2. The characteristics of the optical
interfaces of the I-1, S-1.1, L-1.1, and L-1.2 types comply with ITU-T
G.957. The characteristics of the optical interfaces of the Ie-1 and
Ve-1.2 types comply with the standards defined by Huawei.
Connector type LC
Optical module
type
SFP
E3 ATM interface Does not support the E3 ATM interface.
IMA functions
(ATM Forum
IMA 1.1)
l Accesses and processes IMA services when the IDQ1 is used with
the E1 service processing board N1PQ1 or N1PQM.
l Supports a maximum of 63 IMA E1 services.
l Supports the mapping between ATM ports and a maximum of 93
IMA groups. Each IMA group supports 132 E1 signals.
l Supports the mapping between ATM ports and a maximum of 16 E1
links that belong to non-IMA groups.
l Supports the maximum IMA multichannel delay of 226 ms.
Maximum uplink
bandwidth
Supports a bandwidth of 8xVC-4s, or a bandwidth of 63xVC-12s and
7xVC-4s.
The IDQ1 can adapt to the bandwidth of the slot.
ATM switching
capability
1.0 Gbit/s
Mapping
granularities
Supports VC-12, VC-4, VC4-Xc (X = 14), and VC12-Xv (X = 132)
granularities.
Service types Supports the CBR, rt-VBR, nrt-VBR, and UBR.
Number of
supported ATM
connections
2048
Statistical
multiplexing
Supports the statistical multiplexing.
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Function and
Feature
IDQ1
Flow types and
QoS
Complies with IETF RFC2514 and ATM forum TM4.0.
ATM multicast
connection
Supports the spatial multicast and logical multicast.
ATM protection
(ITU-T I.630)
Supports unidirectional/bidirectional 1+1, unidirectional/bidirectional
1:1, VP-Ring, and VC-Ring protection schemes.
Board-level 1+1
protection
Supports the board-level 1+1 protection.
OAM functions
(ITU-T I.610)
Supports the AIS, RDI, LB , and CC.
Maintenance
features
Supports inloops at the ATM layer and on optical interfaces.
Supports outloops at the ATM layer.
These features can be used to locate faults quickly.
Alarm and
performance event
Reports various alarms and performance events, which can be used to
locate faults and maintain the equipment.
Note: The IMA function can encapsulate ATM cells into E1 signals. The IMA group can
coexist with a single E1 signal. The IMA group can dynamically increase or decrease the
bandwidth to improve the bandwidth utilization. The IMA group can also be used to converge
2 Mbit/s services and to interconnect with other IMA equipment.

12.4.4 Working Principle and Signal Flow
The IDQ1 consists of the O/E converting module, physical layer module, ATM module, IMA
module, mapping module, logic and control module, clock module, and power module.
Figure 12-13 shows the functional block diagram of the IDQ1.
12 ATM Boards
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Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Figure 12-13 Functional block diagram of the IDQ1
E/O
O/E
Physical
layer
module
ATM
module
Mapping
module
IMA
module
High-speed
bus
Logic and
control module
LOS
Laser shutdown
Reference clock and frame header
Communication
SCC unit
Clock
module
50 MHz
77 MHz
100 MHz
+3.3 V backup power
+3.3 V
Fuse
Fuse
-48 V/-60 V Power
module
Cross-connect unit A
Power
module
O/E converting
module
Backplane
-48 V/-60 V
Cross-connect unit B
Cross-connect unit
High-speed
bus
4x155
Mbit/s
4x155
Mbit/s
4x155
Mbit/s
4x155
Mbit/s

O/E Converting Module
In the receive direction, optical signals are converted into electrical signals. In the transmit
direction, electrical signals are converted into optical signals.
Physical Layer Module
The physical layer module mainly performs the following functions:
l Maps ATM cells into SDH frames.
l Demaps SDH frames to ATM cells.
l Implements the following functions at the ATM service physical layer: cell delimitation,
and test and generation of HEC sequence.
ATM Module
The ATM module mainly performs the following ATM layer functions that are specified in
ATM protocols:
l Flow control
l Extraction and generation of cell headers
l ATM switching
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IMA Module
This module mainly performs the following functions that are specified in IMA protocols:
l Separation and re-creation of ATM cells
l Frame synchronization
l Insertion and extraction of IMA control protocol (ICP) cells
l Management of IMA groups
Mapping Module
The mapping module performs the following functions:
l Maps ATM cells into SDH frame payloads.
l Demaps SDH frame payloads to ATM cells.
l Implements functions at the ATM physical layer.
l Implements the VC4-Xv (X4) virtual concatenation.
Logic and Control Module
The logic and control module performs the following functions:
l Controls writing and reading of each chip.
l Communicates with the NE.
l Issues configured services.
l Reports alarms of each functional module.
l Detects R_LOS alarms of optical modules.
l Controls the shutting down of the laser.
Clock Module
This module mainly generates the required working clock for each chip. The frequency of the
clock can be 50 MHz, 77 MHz, or 100 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
12.4.5 Front Panel
The front panel of the IDQ1 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 12-14 shows the appearance of the front panel of the IDQ1.
12 ATM Boards
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Figure 12-14 Front panel of the IDQ1
IDQ1
IDQ1
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the IDQ1 has four optical interfaces. Table 12-14 describes the types and
usage of the optical interfaces of the IDQ1.
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Table 12-14 Optical interfaces of the IDQ1
Interface Type of
Interface
Usage
OUT1/IN1 LC (swappable) Transmits and receives STM-1 optical signals.
OUT2/IN2 LC (swappable) Transmits and receives STM-1 optical signals.
OUT3/IN3 LC (swappable) Transmits and receives STM-1 optical signals.
OUT4/IN4 LC (swappable) Transmits and receives STM-1 optical signals.

12.4.6 Jumpers and DIP Switches
The IDQ1 does not have any jumpers or DIP switches that are used for board settings.
12.4.7 Valid Slots
The IDQ1 must be installed in a valid slot in the subrack. Otherwise, the IDQ1 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the IDQ1 vary with the cross-connect capacity of the subrack. The slots valid
for the IDQ1 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the IDQ1 can be installed in slots 18 and
1117. In this case, the bandwidth is 1.25 Gbit/s.
12.4.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the IDQ1 indicates the type of optical interface.
Table 12-15 provides the relationship between the feature code of the IDQ1 and the type of
optical interface.
Table 12-15 Relationship between the feature code of the IDQ1 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN1IDQ110 10 S-1.1
SSN1IDQ111 11 L-1.1
SSN1IDQ112 12 L-1.2
SSN1IDQ113 13 Ve-1.2
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Board Feature Code Type of Optical Interface
SSN1IDQ114 14 Ie-1

12.4.9 Board Protection
The IDQ1 supports the 1+1 board-level protection. The active and standby IDQ1 should be
housed in paired slots.
The valid paired slots for the IDQ1 vary with the cross-connect capacity.
l When the cross-connect capacity is 200 Gbit/s: (slot 8, slot 11), (slot 7, slot 12), (slot 6,
slot 13), (slot 5, slot 14), (slot 4, slot 15), (slot 3, slot 16), (slot 2, slot 17)
12.4.10 Parameter Settings
You can set parameters for the IDQ1 by using the T2000.
You can set the following main parameters for the IDQ1 by using the T2000:
l Port type
l Flow type
l Service type
l PCR
l SCR
l Maximum cell burst size
l CDVT
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
12.4.11 Technical Specifications
The technical specifications of the IDQ1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 12-16 lists the parameters specified for the optical interfaces of the IDQ1.
Table 12-16 Parameters specified for the optical interfaces of the IDQ1
Parameter Value
Type of optical
interface
Ie-1 S-1.1 L-1.2 Ve-1.2 L-1.1
Type of fiber Multi-
mode LC
Single-
mode LC
Single-
mode LC
Single-mode
LC
Single-mode
LC
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Parameter Value
Operating
wavelength
range (nm)
1270 to
1380
1261 to
1360
1480 to
1580
1480 to 1580 1263 to 1360
Transmission
distance (km)
0 to 0.5 2 to 15 40 to 80 80 to 100 15 to 40
Launched optical
power range
(dBm)
-19 to -14 -15 to -8 -5 to 0 -3 to 0 -5 to 0
Receiver
sensitivity
(dBm)
-30 -28 -34 -34 -34
Minimum
overload (dBm)
-14 -8 -10 -10 -10
Minimum
extinction ratio
(dB)
10 8.2 10 10 10

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the IDQ1 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the IDQ1 at room temperature (25C) is 41 W.
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13 RPR Boards
About This Chapter
The RPR boards include FE/GE Ethernet ring processing boards.
13.1 EGR2
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EGR2 (2xGE ring processing board). This topic also describes
how to configure and commission the EGR2.
13.2 EMR0
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EMR0 (12xFE and 1xGE ring processing board). This topic also
describes how to configure and commission the EMR0.
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13.1 EGR2
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EGR2 (2xGE ring processing board). This topic also describes
how to configure and commission the EGR2.
13.1.1 Version Description
The EGR2 is available in one functional version, namely, N2.
13.1.2 Application
The EGR2 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
13.1.3 Functions and Features
The EGR2 supports the Layer 2 switching, port aggregation, and RPR functions.
13.1.4 Working Principle and Signal Flow
The EGR2 consists of the Ethernet access module, network processor module, RPR protocol
processing module, mapping module, interface converting module, logic and control module,
clock module, and power module.
13.1.5 Front Panel
The front panel of the EGR2 has indicators, interfaces, a bar code, and a laser safety class label.
13.1.6 Jumpers and DIP Switches
The EGR2 does not have any jumpers or DIP switches that are used for board settings.
13.1.7 Valid Slots
The EGR2 must be installed in a valid slot in the subrack. Otherwise, the EGR2 cannot work
normally.
13.1.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGR2 indicates the type of optical interface.
13.1.9 Parameter Settings
You can set parameters for the EGR2 by using the T2000.
13.1.10 Technical Specifications
The technical specifications of the EGR2 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.
13.1.1 Version Description
The EGR2 is available in one functional version, namely, N2.
13.1.2 Application
The EGR2 is used to access Ethernet services, manage bandwidths, and realize Layer 2 switching
of Ethernet services.
Figure 13-1 shows the typical networking and application of the EGR2. The EGR2 accesses
and converges Ethernet services, and provides the Ethernet data with the following data features:
Layer 2 switching, port isolation, flow classification, traffic control, VLAN management, and
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priority configuration. In addition, the EGR2 performs encapsulation/decapsulation, virtual
concatenation, and SDH mapping/demapping for data. The EGR2 can be interconnected with
the bandwidth access equipment and the data communication equipment at the same time, thus
to provide a network-level solution.
NOTE
When the service converging FE services into GE services is configured, the GE switching board can be
set only to the 1000M full-duplex mode, the VLAN of the convergence service is variable, and the binding
granularity can be at the VC-3 or VC-12 level.
Figure 13-1 Networking and application of the EGR2
NE1
NE2 NE4
NE3
User A2
User B2
User B1
User A1
NMS
PORT 1
VLAN 100
PORT 2
VLAN 100
PORT 2
VLAN 100
PORT 1 VLAN 100
Service flow
Line board
Cross-connect and
timing board
Data board
MSP ring

13.1.3 Functions and Features
The EGR2 supports the Layer 2 switching, port aggregation, and RPR functions.
Table 13-1 provides the functions and features of the EGR2.
Table 13-1 Functions and features of the EGR2
Function and
Feature
EGR2
Basic functions Accesses and processes 2xGE services.
Supports the RPR feature.
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Function and
Feature
EGR2
Functions when
being used with the
interface board
Accesses 2xGE signals by providing interfaces on the front panel.
Specifications of the
optical interface
l The optical interfaces are 1000BASE-SX/LX/ZX/VX Ethernet
optical interfaces.
l The optical interfaces support the auto-negotiation function in
compliance with IEEE 802.3z.
l The optical interfaces use the SFP optical module and support hot
swapping.
When the multi-mode optical fiber is used, the maximum
transmission distance is 550 m.
When the single-mode optical fiber is used, the maximum
transmission distance is 10 km.
The optical modules that can meet different requirements for the
transmission distance such as 40 km and 80 km can also be used.
Format of service
frames
l Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG formats.
l Supports the frame with a length ranging from 64 bytes to 9600
bytes.
l Supports the Jumbo frame with a length less than 9600 bytes.
Maximum uplink
bandwidth
2.5 Gbit/s
The EGR2 can adapt to the bandwidth of the slot.
Mapping
granularities
Supports VC-3, VC3-2v, VC-4, and VC4-Xv (X8) granularities.
Encapsulation
format
Supports the GFP-F and LAPS protocols.
EVPL services l Supports EVPL services. The frame format can be Ethernet II,
IEEE 802.3, IEEE 802.1q TAG, or MPLS Martini.
l Supports the MPLS encapsulation and forwarding based on PORT
or PORT+VLAN.
l Supports five types of LSPs, including ingress LSP, egress LSP,
transit LSP, RPR ingress LSP, and RPR transit LSP.
l Supports a maximum of 512 LSPs.
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Function and
Feature
EGR2
EVPLAN services l Supports EVPLAN services that use the stack VLAN
encapsulation.
l Supports the self-learning of the source MAC address. The capacity
of the MAC address table in the N2 functional version is 64K. The
aging time of the MAC address can be set and queried.
l Supports the configuration of the static MAC routes. A maximum
of 4K static MAC routes can be configured.
l Supports data isolation based on VB+VLAN.
l Supports the creation, deletion, and query of the VB. The maximum
number of supported VBs is 16. The maximum number of logical
ports for each VB is 32.
MTU Supports the setting of the packet length, which ranges from 1518
bytes to 9600 bytes. After the setting becomes valid, the length of the
packets that enter the IP ports is restricted by the pre-set MTU.
MPLS Supports MartinioE.
Stack VLAN Supports the stack VLAN.
VLAN l Supports 4096 VLAN tags, and the addition, deletion, and
exchanging of VLAN tags in compliance with IEEE 802.1q/p.
l Supports the replacement of VLAN tags in Ethernet signal frames.
Link aggregation
function
Supports the aggregation of the links of two GE ports.
RPR l Supports the RPR feature that complies with IEEE 802.17.
l Supports a maximum of 255 nodes on the ring network, and
supports stripping at the destination node and weighted fairness
algorithm.
l Supports five priority levels, including A0, A1, B_EIR, B_CIR,
and C, and supports automatic discovery of topologies, which can
display the network status in real time.
l Supports three protection modes, including Steering, Wrapping,
and Wrapping+Steering. Hence, the signal failure time is less than
50 ms.
l Supports the manual configuration of routes for the services on the
RPR ring network.
l Supports the self-learning of routes on the ring, that is, supports the
learning of mapping relationship between MAC addresses and
node numbers.
RSTP Supports the broadcast packet suppression and RSTP, which comply
with IEEE 802.1w.
Multicast function
(IGMP snooping)
Supports the multicast function.
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Function and
Feature
EGR2
QoS l Supports the CAR. The granularity is 64 kbit/s.
l Supports the flow classification based on PORT, PORT+VLAN
ID, or PORT+VLAN ID+VLAN PRI.
LCAS function Dynamically increases or decreases the bandwidth and protects the
bandwidth in compliance with ITU-T G.7042.
LPT function Supports the P2MP LPT.
Flow control
function
Supports the port-based flow control function that complies with
IEEE 802.3x.
High-precision time
(IEEE 1588 V2)
Does not support the high-precision time.
Echo test frames Supports the echo function specified in the RPR OAM function, which
is used to test the connectivity of the link.
Port mirroring Does not support port mirroring.
Loopback function Supports inloops on Ethernet ports (at the PHY layer or MAC layer).
Protection schemes Supports the following protection schemes at the Ethernet network
level:
l STP/RSTP
l LCAS
l LPT
l LAG
Ethernet
performance
monitoring
Supports Ethernet performance monitoring at the port level.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Weighted fairness
algorithm
Supports the weighted fairness algorithm.
Automatic discovery
of topologies
Supports the automatic discovery of topologies.
Maximum number of
supported nodes
255
Service priority
levels
Supports A0, A1, B_CIR, B_EIR, and C.

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13.1.4 Working Principle and Signal Flow
The EGR2 consists of the Ethernet access module, network processor module, RPR protocol
processing module, mapping module, interface converting module, logic and control module,
clock module, and power module.
Figure 13-2 shows the functional block diagram of the EGR2 by describing how to process
1xGE/FE signals.
Figure 13-2 Functional block diagram of the EGR2
RPR protocol
processing module
RPR
MAC
(west)
Clock module
77 MHz
50 MHz
125 MHz
100 MHz
LOS
Laser shutdown
SCC unit
+3.3 V backup power
+3.3 V
Power
module
Fuse
Fuse
Power
module
Ethernet
access
module
GE/FE
Mapping module
Network processor module
Control
signal
Data
Switch
fabric
Network
processor
D
E
N
C
P
V
C
P
E
N
C
P
-48 V/-60 V
-48 V/-60 V
Logic and
control module
Communication
Reference clock and frame header
Cross-connect unit
Cross-connect unit
Cross-connect unit
Backplane
Interface
converting
module
RPR
MAC
(east)
RPR: resilient package ring

Ethernet Access Module
In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
Network Processor Module
The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The following formats are supported:
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l MPLS
l L2 MPLS VPN
l Ethernet/VLAN
In the receive direction, services are mapped and forwarded after the Tunnel and VC tags are
added according to the service configuration. In the transmit direction, the Tunnel or VC tag is
extracted based on the level (P or PE) of the equipment. Services are then routed or forwarded.
The network processor module supports the following functions:
l Flow sense and flow classification
l Unicast, multicast, and broadcast of the flow
l Setting of data priorities
l WFQ
l Four CoSs
RPR Protocol Processing Module
The RPR implements the weighted fairness algorithm and statistical multiplexing for the ring
bandwidth. In addition, the RPR provides protection switching schemes. By using the RPR
protocol and RPR weighted fairness algorithm, the RPR protocol processing module controls
the bandwidth of each node accessed by the ring network. In addition, the RPR ring has the
features of spatial reuse and statistical multiplexing. Hence, the bandwidth utilization is
improved.
Topology auto-discovery ensures the plug-and-play feature of the RPR. The protocol for
topology auto-discovery provides correct and reliable ways of discovering topologies of all
nodes and changes occurring on these topologies.
RPR unicast frames are striped at the destination node and thus the bandwidth on the ring is
reused spatially.
The RPR ring supports a maximum of 255 nodes.
Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, virtual concatenation services support the LCAS function. The
encapsulation formats are LAPS and GFP-F.
In the downstream direction, SDH signals are demapped. The delay of virtual concatenation is
compensated. After aligning, packets are decapsulated according to the encapsulation format.
The decapsulated data is finally transmitted to the RPR protocol processing module in packets.
Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
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Logic and Control Module
The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l Manages and configures other modules of the board.
l Implements inter-board communication through the internal Ethernet interface.
The control module also contains basic logic units. This module performs the following
functions:
l Writes and reads the register.
l Provides interfaces for the CPU.
l Checks and selects the clock.
l Performs phase discrimination and frequency division on the clock.
l Checks the in-service state of the cross-connect, SCC, and line boards.
l Controls the shutting down of the optical module.
l Implements communication.
l Controls indicators.
Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 100 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
13.1.5 Front Panel
The front panel of the EGR2 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 13-3 shows the appearance of the front panel of the EGR2.
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Figure 13-3 Front panel of the EGR2
EGR2
EGR2
ACT
PROG
SRV
STAT
O
U
T
1
I
N
1
CLASS 1
LASER
PRODUCT
O
U
T
2
I
N
2
LINK1
ACT1
LINK2
ACT2

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Connection status indicator (LINK) one color (green)
l Data receiving and transmission indicator (ACT) one color (orange)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the EGR2 has two optical interfaces. Table 13-2 describes the types and usage
of the optical interfaces of the EGR2.
Table 13-2 Optical interfaces of the EGR2
Interface Type of Interface Usage
OUT1/IN1 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.
OUT2/IN2 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.

13.1.6 Jumpers and DIP Switches
The EGR2 does not have any jumpers or DIP switches that are used for board settings.
13.1.7 Valid Slots
The EGR2 must be installed in a valid slot in the subrack. Otherwise, the EGR2 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The EGR2 can be installed in slots 18 and 1116 in the subrack. The relation between the slots
valid for the EGR2 and the bandwidth is as follows:
l When the cross-connect capacity is 200 Gbit/s, the EGR2 can be installed in slots 18 and
1116. When the EGR2 is installed in slots 14, 15, and 16, the bandwidth is 1.25 Gbit/s.
When the EGR2 is installed in slots 58 and 1114, the bandwidth is 2.5 Gbit/s.
13.1.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EGR2 indicates the type of optical interface.
Table 13-3 provides the relationship between the feature code of the EGR2 and the type of
optical interface.
Table 13-3 Relationship between the feature code of the EGR2 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN2EGR210 10 1000BASE-SX (0.5 km)
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Board Feature Code Type of Optical Interface
SSN2EGR211 11 1000BASE-LX (10 km)
SSN2EGR212 12 1000BASE-VX (40 km)
SSN2EGR213 13 1000BASE-ZX (80 km)

13.1.9 Parameter Settings
You can set parameters for the EGR2 by using the T2000.
You can set the following main parameters for the EGR2 by using the T2000:
l Working mode
l LCAS
l Maximum frame length
l Mapping protocol
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
13.1.10 Technical Specifications
The technical specifications of the EGR2 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.
Parameters Specified for Optical Interfaces
Table 13-4 lists the parameters specified for the optical interfaces of the EGR2.
Table 13-4 Parameters specified for the optical interfaces of the EGR2
Parameter Value
Type of optical
interface
1000BASE-ZX
(80 km)
1000BASE-
VX (40 km)
1000BASE-
LX (10 km)
1000BASE-SX
(0.5 km)
Type of fiber Single-mode LC Single-mode
LC
Single-mode
LC
Multi-mode LC
Launched optical
power range
(dBm)
-2 to 5 -5 to 0 -11 to -3 -9.5 to 0
Operating
wavelength range
(nm)
1500 to 1580 1275 to 1350 1270 to 1355 770 to 860
Minimum
overload (dBm)
-3 -3 -3 0
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Parameter Value
Receiver
sensitivity (dBm)
-23 -22 -19 -17
Minimum
extinction ratio
(dB)
9 9 9 9

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Ethernet Performance Specifications
NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EGR2 board of the N2 version.
Figure 13-4 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, latency specifications, and back-to-back specifications of the EGR2.
Figure 13-4 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer

Table 13-5 lists the throughput specifications of the EGR2. Table 13-6 lists the packet loss ratio
in the case of overloading of the EGR2. Table 13-7 lists the latency specifications of the EGR2.
Table 13-8 lists the back-to-back specifications of the EGR2.
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NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EVPL bidirectional
unicast services are configured and eight VC-4s are bound on the GE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 13-5 lists the throughput specifications of the EGR2. The values are obtained when the
SmartApplication is set as follows:
l Test duration (sec): 3
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 90.00
l Maximum rate (%): 100.00
l Resolution rate (%): 1.00
l Mode: bidirectional
Table 13-5 Throughput specifications of the EGR2
Frame Size
(Byte)
Passed Rate
(%)
(01,08,01) to
(01,08,02) (pks/
sec)
(01,08,02) to
(01,08,01) (pks/
sec)
Total (pks/
sec)
64 80.77 1201923 1201923 2403846
128 94.87 801282 801282 1602564
256 100.00 452899 452899 905798
512 100.00 234962 234962 469924
1024 100.00 119732 119732 239464
1280 100.00 196154 96154 192308
1518 100.00 81274 81274 162548

Table 13-6 lists the packet loss ratio in the case of overloading of the EGR2. The values are
obtained when the SmartApplication is set as follows:
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l Test duration (sec): 4
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 13-6 Packet loss ratio in the case of overloading of the EGR2
Frame Size
(Byte)
Rate Tested
(%)
(01,08,01) to
(01,08,02) (%)
(01,08,02) to
(01,08,01) (%)
Average (%)
64 100.00 16.719 16.720 16.719
128 100.00 4.315 4.328 4.321
256 100.00 0.000 0.000 0.000
512 100.00 0.000 0.000 0.000
1024 100.00 0.000 0.000 0.000
1280 100.00 0.000 0.000 0.000
1518 100.00 0.000 0.000 0.000

Table 13-7 lists the latency specifications of the EGR2. The values are obtained when the
SmartApplication is set as follows:
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the equipment and the
time when the first bit of the transmitted frame reaches the input port of the equipment. In
store forward mode, the analyzer calculates the difference between the time when the first
bit of the transmitted frame reaches the output port of the equipment and the time when the
last bit of the transmitted frame reaches the input port of the equipment. In the table, the
CT values are obtained in cut through mode and the S&F values are obtained in store
forward mode.
l CT: cut through or FIFO; S&F: store forward or LIFO
l Measure on one receiving card only. Mode: SmartMetrics Comp. Mode
l Test duration (sec): 4
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
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l Number of pairs: 1
l Initial rate (%): 80.77
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 13-7 Latency specifications of the EGR2
Frame
Size
(Byte)
Rate
Tested
(%)
(01,08,01) to
(01,08,02) (us)-
CT (us)
Average
(CT) (us)
(01,08,01) to
(01,08,02)
(us)-S&F (us)
Average
(S&F) (us)
64 80.77 117.8 117.8 117.3 117.3
128 94.87 121.2 121.2 120.2 120.2
256 100.00 126.6 126.6 124.6 124.6
512 100.00 137.7 137.7 133.7 133.7
1024 100.00 159.9 159.9 151.8 151.8
1280 100.00 170.2 170.2 160.0 160.0
1518 100.00 182.9 182.9 170.8 170.8

Table 13-8 lists the back-to-back specifications of the EGR2. The values are obtained when the
SmartApplication is set as follows:
l Test duration (sec): 2
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 13-8 Back-to-back specifications of the EGR2
Frame Size
(Byte)
Rate Tested
(%)
(01,08,01) to
(01,08,02) Burst
Size (Number of
Frames)
(01,08,02) to
(01,08,01)
(Number of
Frames)
Total
(Number of
Frames)
64 100.00 298 300 598
128 100.00 650 650 1300
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Frame Size
(Byte)
Rate Tested
(%)
(01,08,01) to
(01,08,02) Burst
Size (Number of
Frames)
(01,08,02) to
(01,08,01)
(Number of
Frames)
Total
(Number of
Frames)
256 100.00 905798 905798 1811596
512 100.00 469924 469924 939848
1024 100.00 239464 239464 478928
1280 100.00 192308 192308 384616
1518 100.00 162548 162548 325096

Mechanical Specifications
The mechanical specifications of the EGR2 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.1
Power Consumption
The maximum power consumption of the EGR2 at room temperature (25C) is 40 W.
13.2 EMR0
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the EMR0 (12xFE and 1xGE ring processing board). This topic also
describes how to configure and commission the EMR0.
13.2.1 Version Description
The EMR0 is available in one functional version, namely, N2.
13.2.2 Application
The EMR0 is used to access Ethernet services, manage bandwidths, and realize Layer 2
switching of Ethernet services.
13.2.3 Functions and Features
The EMR0 supports the Layer 2 switching, port aggregation, and RPR functions.
13.2.4 Working Principle and Signal Flow
The EMR0 consists of the Ethernet access module, network processor module, RPR protocol
processing module, mapping module, interface converting module, logic and control module,
clock module, and power module.
13.2.5 Front Panel
The front panel of the EMR0 has indicators, interfaces, a bar code, and a laser safety class label.
13.2.6 Jumpers and DIP Switches
The EMR0 does not have any jumpers or DIP switches that are used for board settings.
13.2.7 Valid Slots
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The EMR0 must be installed in a valid slot in the subrack. Otherwise, the EMR0 cannot work
normally.
13.2.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EMR0 indicates the type of optical interface.
13.2.9 Parameter Settings
You can set parameters for the EMR0 by using the T2000.
13.2.10 Technical Specifications
The technical specifications of the EMR0 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.
13.2.1 Version Description
The EMR0 is available in one functional version, namely, N2.
13.2.2 Application
The EMR0 is used to access Ethernet services, manage bandwidths, and realize Layer 2
switching of Ethernet services.
Figure 13-5 shows the typical networking and application of the EMR0. The EMR0 accesses
and converges Ethernet services, and provides the Ethernet data with the following data features:
Layer 2 switching, port isolation, flow classification, traffic control, VLAN management, and
priority configuration. In addition, the EMR0 performs encapsulation/decapsulation, virtual
concatenation, and SDH mapping/demapping for data. The EMR0 can be interconnected with
the bandwidth access equipment and the data communication equipment at the same time, thus
to provide a network-level solution.
NOTE
When the service converging FE services into GE services is configured, the GE switching board can be
set only to the 1000M full-duplex mode, the VLAN of the convergence service is variable, and the binding
granularity can be at the VC-3 or VC-12 level.
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Figure 13-5 Networking and application of the EMR0
NE1
NE2 NE4
NE3
User A2
User B2
User B1
User A1
NMS
PORT 1
VLAN 100
PORT 2
VLAN 100
PORT 2
VLAN 100
PORT 1 VLAN 100
Service flow
Line board
Cross-connect and
timing board
Data board
MSP ring

13.2.3 Functions and Features
The EMR0 supports the Layer 2 switching, port aggregation, and RPR functions.
Table 13-9 provides the functions and features of the EMR0.
Table 13-9 Functions and features of the EMR0
Function and
Feature
EMR0
Basic functions Accesses and processes 12xFE services and 1xGE services.
Supports the RPR feature.
Functions when
being used with the
interface board
l Supports four FE ports and one GE ports.
l Accesses 12xFE signals through the electrical interface when the
EMR0 is used with the ETF8.
l Accesses 8xFE signals through the optical interface when the
EMR0 is used with the EFF8.
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Function and
Feature
EMR0
Specifications of the
optical interface
l Supports 10BASE-T/100BASE-TX signals when the EMR0 is
used with the ETF8. The maximum transmission distance is 100
m.
l Supports 100BASE-FX signals in compliance with IEEE 802.3u
when the EMR0 is used with the EFF8.
Format of service
frames
l Supports Ethernet II, IEEE 802.3, and IEEE 802.1q TAG formats.
l Supports the frame with a length ranging from 64 bytes to 9600
bytes.
l Supports the Jumbo frame with a length less than 9600 bytes.
Maximum uplink
bandwidth
2.5 Gbit/s
The EMR0 can adapt to the bandwidth of the slot.
Mapping
granularities
Supports VC-3, VC3-2v, VC-4, and VC4-Xv (X8) granularities.
Encapsulation format Supports the GFP-F and LAPS protocols.
EVPL services l Supports EVPL services. The frame format can be Ethernet II,
IEEE 802.3, IEEE 802.1q TAG, or MPLS Martini.
l Supports the MPLS encapsulation and forwarding based on PORT
or PORT+VLAN.
l Supports five types of LSPs, including ingress LSP, egress LSP,
transit LSP, RPR ingress LSP, and RPR transit LSP.
l Supports a maximum of 512 LSPs.
EVPLAN services l Supports EVPLAN services that use the stack VLAN
encapsulation.
l Supports the self-learning of the source MAC address. The
capacity of the MAC address table in the N2 functional version is
64K. The capacity of the MAC address table in the N1 functional
version is 16K. The aging time of the MAC address can be set and
queried.
l Supports the configuration of the static MAC routes. A maximum
of 4K static MAC routes can be configured.
l Supports data isolation based on VB+VLAN.
l Supports the creation, deletion, and query of the VB. The
maximum number of VBs supported by the N2EMR0 is 16. The
maximum number of logical ports for each VB is 32.
MTU Supports the setting of the packet length, which ranges from 1518
bytes to 9600 bytes. After the setting becomes valid, the length of the
packets that exit the IP ports is restricted by the pre-set MTU.
MPLS Supports MartinioE.
Stack VLAN Supports the stack VLAN.
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Function and
Feature
EMR0
VLAN l Supports 4096 VLAN tags, and the addition, deletion, and
exchanging of VLAN tags in compliance with IEEE 802.1q/p.
l Supports the replacement of VLAN tags in Ethernet signal frames.
Link aggregation
function
Supports the aggregation of the links of a maximum of eight FE ports.
RPR l Supports the RPR feature that complies with IEEE 802.17.
l Supports a maximum of 255 nodes on the ring network, and
supports stripping at the destination node and weighted fairness
algorithm.
l Supports five priority levels, including A0, A1, B_EIR, B_CIR,
and C, and supports automatic discovery of topologies, which can
display the network status in real time.
l Supports three protection modes, including Steering, Wrapping,
and Wrapping+Steering. Hence, the signal failure time is less than
50 ms.
l Supports the self-learning of routes on the ring, that is, supports
the learning of mapping relationship between MAC addresses and
node numbers.
l The N2EMR0 supports the manual configuration of routes for the
services on the RPR ring network.
RSTP Supports the broadcast packet suppression and RSTP, which comply
with IEEE 802.1w.
Multicast function
(IGMP snooping)
Supports the multicast function.
QoS function l Supports the CAR. The granularity is 64 kbit/s.
l The N2EMR0 supports the flow classification based on PORT,
PORT+VLAN ID, or PORT+VLAN ID+VLAN PRI.
LCAS function Dynamically increases or decreases the bandwidth and protects the
bandwidth in compliance with ITU-T G.7042.
Flow control function Supports the port-based flow control function that complies with
IEEE 802.3x.
Echo test frames Supports the echo function specified in the RPR OAM function,
which is used to test the connectivity of the link.
Loopback function Supports inloops on Ethernet ports (at the PHY layer or MAC layer).
Protection schemes Supports the following protection schemes at the Ethernet network
level:
l STP/RSTP
l LCAS
l LAG
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Function and
Feature
EMR0
Ethernet
performance
monitoring
Supports Ethernet performance monitoring at the port level.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Weighted fairness
algorithm
Supports the weighted fairness algorithm.
Automatic discovery
of topologies
Supports the automatic discovery of topologies.
Maximum number of
supported nodes
255
Service priority
levels
Supports A0, A1, B_CIR, B_EIR, and C.

13.2.4 Working Principle and Signal Flow
The EMR0 consists of the Ethernet access module, network processor module, RPR protocol
processing module, mapping module, interface converting module, logic and control module,
clock module, and power module.
Figure 13-6 shows the functional block diagram of the EMR0 by describing how to process
1xGE/FE signals.
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Figure 13-6 Functional block diagram of the EMR0
RPR protocol
processing module
RPR
MAC
(west)
Clock module
77 MHz
50 MHz
125 MHz
100 MHz
LOS
Laser shutdown
SCC unit
+3.3 V backup power
+3.3 V
Power
module
Fuse
Fuse
Power
module
Ethernet
access
module
GE/FE
Mapping module
Network processor module
Control
signal
Data
Switch
fabric
Network
processor
D
E
N
C
P
V
C
P
E
N
C
P
-48 V/-60 V
-48 V/-60 V
Logic and
control module
Communication
Reference clock and frame header
Cross-connect unit
Cross-connect unit
Cross-connect unit
Backplane
Interface
converting
module
RPR
MAC
(east)
RPR: resilient package ring

Ethernet Access Module
In the receive direction, the optical signals from Ethernet equipment such as switches or routers
are converted into electrical signals. If the signals are accessed through electrical interfaces, O/
E conversion is not required. At the PHY layer, the electrical signals are decoded and the
ETH_LOS alarm is detected. The electrical signals are converted from serial signals into parallel
signals and then sent to the network processor module.
In the transmit direction, the parallel signals are converted into serial signals. At the PHY layer,
signals are encoded and converted from electrical signals to optical signals.
Network Processor Module
The network processor module consists of the network processor and switch fabric. The network
processor first performs MAC functions, which include code conversion, framing of Ethernet
packets, CRC check, and Ethernet performance statistics.
After the striped Ethernet frames enter the core of network processor, the flow is classified
according to the service type and configuration requirement. The frames are encapsulated or
decapsulated. The following formats are supported:
l MPLS
l L2 MPLS VPN
l Ethernet/VLAN
In the receive direction, services are mapped and forwarded after the Tunnel and VC tags are
added according to the service configuration. In the transmit direction, the Tunnel or VC tag is
extracted based on the level (P or PE) of the equipment. Services are then routed or forwarded.
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The network processor module supports the following functions:
l Flow sense and flow classification
l Unicast, multicast, and broadcast of the flow
l Setting of data priorities
l WFQ
l Three CoSs
RPR Protocol Processing Module
The RPR implements the weighted fairness algorithm and statistical multiplexing for the ring
bandwidth. In addition, the RPR provides protection switching schemes. By using the RPR
protocol and RPR weighted fairness algorithm, the RPR protocol processing module controls
the bandwidth of each node accessed by the ring network. In addition, the RPR ring has the
features of spatial reuse and statistical multiplexing. Hence, the bandwidth utilization is
improved.
Topology auto-discovery ensures the plug-and-play feature of the RPR. The protocol for
topology auto-discovery provides correct and reliable ways of discovering topologies of all
nodes and changes occurring on these topologies.
RPR unicast frames are striped at the destination node and thus the bandwidth on the ring is
reused spatially.
The RPR ring supports a maximum of 255 nodes.
Mapping Module
The mapping module performs encapsulation and mapping functions.
In the upstream direction, virtual concatenation services support the LCAS function. The
encapsulation formats are LAPS and GFP-F.
In the downstream direction, virtual concatenation services are received. The delay of virtual
concatenation is compensated. After aligning, packets are decapsulated according to the
encapsulation format. The decapsulated data is finally transmitted to the RPR protocol
processing module in packets.
Interface Converting Module
The interface converting module converts the 622 Mbit/s LVDS bus of the SDH system into the
parallel bus. The high-rate backplane interface is connected to the low-rate interface chip of the
transmit system through the interface converting module.
Logic and Control Module
The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through the bus. The logic and control
module performs the following functions:
l Manages and configures other modules of the board.
l Implements inter-board communication through the internal Ethernet interface.
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The control module also contains basic logic units. This module performs the following
functions:
l Writes and reads the register.
l Provides interfaces for the CPU.
l Checks and selects the clock.
l Performs phase discrimination and frequency division on the clock.
l Checks the in-service state of the cross-connect, SCC, and line boards.
l Controls the shutting down of the optical module.
l Implements communication.
l Controls indicators.
Clock Module
The clock module traces the system reference clock and generates the required working clock
for each chip. The frequency of the clock can be 50 MHz, 77 MHz, 125 MHz, or 100 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
13.2.5 Front Panel
The front panel of the EMR0 has indicators, interfaces, a bar code, and a laser safety class label.
Diagram of the Front Panel
Figure 13-7 shows the appearance of the front panel of the EMR0.
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Figure 13-7 Front panel of the EMR0
EMR0
EMR0
ACT
PROG
SRV
STAT
O
U
T
1
I
N
1
CLASS 1
LASER
PRODUCT
LINK
ACT
FE1
FE2
FE3
FE4

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Connection status indicator (LINK) one color (green)
l Data receiving and transmission indicator (ACT) one color (orange)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the EMR0 has five interfaces. Table 13-10 describes the types and usage of
the interfaces of EMR0.
Table 13-10 Interfaces of the EMR0
Interface Type of
Interface
Usage
OUT1/IN1 LC (swappable) Transmits and receives 1000BASE-SX/LX/ZX
signals.
FE1 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE2 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE3 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.
FE4 RJ-45 Transmits and receives 10BASE-T/100BASE-TX
signals.

13.2.6 Jumpers and DIP Switches
The EMR0 does not have any jumpers or DIP switches that are used for board settings.
13.2.7 Valid Slots
The EMR0 must be installed in a valid slot in the subrack. Otherwise, the EMR0 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The EMR0 can be used with the ETF8 and EFF8.
The slots valid for the EMR0 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the EMR0 can be installed in slots 16 and
1316. When the EMR0 is installed in slots 14, 15, and 16, the bandwidth is 1.25 Gbit/s.
When the EMR0 is installed in slots 5, 6, 13, and 14, the bandwidth is 2.5 Gbit/s.
Table 13-11 lists the slots valid for the EMR0 and the corresponding slots for the ETF8 and
EFF8.
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Table 13-11 Slots valid for the EMR0 and the corresponding slots for the ETF8 and EFF8
Slot Valid for the EMR0 Corresponding Slot for the ETF8 and
EFF8
Slot 1 Without an interface board
Slot 2 Slot 19
Slot 3 Slot 21
Slot 4 Slot 23
Slot 5 Slot 25
Slot 6 Without an interface board
Slot 13 Slot 29
Slot 14 Slot 31
Slot 15 Slot 33
Slot 16 Slot 35

13.2.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the EMR0 indicates the type of optical interface.
Table 13-12 provides the relationship between the feature code of the EMR0 and the type of
optical interface.
Table 13-12 Relationship between the feature code of the EMR0 and the type of optical interface
Board Feature Code Type of Optical Interface
SSN2EMR010 10 1000BASE-SX (0.5 km)
SSN2EMR011 11 1000BASE-LX (10 km)
SSN2EMR012 12 1000BASE-VX (40 km)
SSN2EMR013 13 1000BASE-ZX (80 km)

13.2.9 Parameter Settings
You can set parameters for the EMR0 by using the T2000.
You can set the following main parameters for the EMR0 by using the T2000:
l Working mode
l LCAS
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l Maximum frame length
l Mapping protocol
For information about more parameters and the description of each parameter, see 25 Parameter
Settings.
13.2.10 Technical Specifications
The technical specifications of the EMR0 include the parameters specified for optical interfaces,
laser safety class, Ethernet performance specifications, mechanical specifications, and power
consumption.
Parameters Specified for Optical Interfaces
Table 13-13 lists the parameters specified for the optical interfaces of the EMR0.
Table 13-13 Parameters specified for the optical interfaces of the EMR0
Parameter Value
Type of optical
interface
1000BASE-ZX
(80 km)
1000BASE-VX
(40 km)
1000BASE-
LX (10 km)
1000BASE-SX
(0.5 km)
Type of fiber Single-mode
LC
Single-mode LC Single-mode
LC
Multi-mode LC
Launched optical
power range
(dBm)
-2 to 5 -5 to 0 -11 to -3 -9.5 to 0
Operating
wavelength
range (nm)
1500 to 1580 1275 to 1350 1270 to 1355 770 to 860
Minimum
overload (dBm)
-3 -3 -3 0
Receiver
sensitivity (dBm)
-23 -22 -19 -17
Minimum
extinction ratio
(dB)
9 9 9 9

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Ethernet Performance Specifications
NOTE
The following part lists the throughput specifications, packet loss ratio in the case of overloading, delay
specifications, and back-to-back specifications of the EMR0 board of the N2 version.
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Figure 13-8 shows the connection for testing the throughput specifications, packet loss ratio in
the case of overloading, latency specifications, and back-to-back specifications of the EMR0.
Figure 13-8 Connection for testing the throughput specifications, packet loss ratio in the case
of overloading, latency specifications, and back-to-back specifications
Port 1 Port 2
Tested
equipment 1
Tested
equipment 2
Data network
performance
analyzer

Table 13-14 and Table 13-15 list the throughput specifications of the EMR0. Table 13-16 and
Table 13-17 list the packet loss ratio in the case of overloading of the EMR0. Table 13-18 and
Table 13-19 list the latency specifications of the EMR0. Table 13-20 and Table 13-21 list the
back-to-back specifications of the EMR0.
NOTE
l The specifications vary according to the configuration and networking of the test environment and
the VC services bound on the VCG side. The specifications that are obtained in the actual environment
are used.
l The specifications in the following tables are obtained in the following scenario: EVPL bidirectional
unicast services are configured and eight VC-4s are bound on the FE port, or EVPL bidirectional
unicast services are configured and eight VC-4s are bound on the GE port.
l The data network performance is measured by using the SmartBits. The specification values in the
following tables are obtained by using the SmartApplication software of the SmartBits analyzer.
l The specific test results depend on the settings on the SmartApplication. The values listed in the
following tables are the values displayed on the SmartBits analyzer.
l In the following tables, the value such as (01,01,01) indicates the equipment No., slot No., and port
No. "(01,01,01) to (01,01,02)" and "(01,01,02) to (01,01,01)", however, indicate the forward and
reverse tests values, respectively. For details about the parameters, see SmartApplications Help.
Table 13-14 lists the throughput specifications of the EMR0 (eight VC-4s are bound on the FE
port). The values are obtained when the SmartApplication is set as follows:
l Test duration (sec): 5
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 100.00
l Resolution rate (%): 1.00
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l Mode: bidirectional
Table 13-14 Throughput specifications of the EMR0 (eight VC-4s are bound on the FE port)
Frame Size
(Byte)
Passed Rate
(%)
(01,06,05) to
(01,06,06) (pks/
sec)
(01,06,06) to
(01,06,05) (pks/
sec)
Total (pks/
sec)
64 100.00 148810 148810 297620
128 100.00 84459 84459 168918
256 100.00 45290 45290 90580
512 100.00 23496 23496 46992
1024 100.00 11973 11973 23946
1280 100.00 9615 9615 19230
1518 100.00 8127 8127 16254

Table 13-15 lists the throughput specifications of the EMR0 (eight VC-4s are bound on the GE
port). The values are obtained when the SmartApplication is set as follows:
l Test duration (sec): 20
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Maximum rate (%): 100.00
l Resolution rate (%): 1.00
l Mode: bidirectional
Table 13-15 Throughput specifications of the EMR0 (eight VC-4s are bound on the GE port)
Frame Size
(Byte)
Passed Rate
(%)
(01,01,01) to
(01,04,01) (pks/
sec)
(01,04,01) to
(01,01,01) (pks/
sec)
Total (pks/
sec)
64 72.41 1077586 1077586 2155172
128 94.87 801282 801282 1602564
256 100.00 452899 452899 905798
512 100.00 234962 234962 469924
1024 100.00 119732 119732 239464
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Frame Size
(Byte)
Passed Rate
(%)
(01,01,01) to
(01,04,01) (pks/
sec)
(01,04,01) to
(01,01,01) (pks/
sec)
Total (pks/
sec)
1280 100.00 96154 96154 192308
1518 100.00 81274 81274 162548

Table 13-16 lists the packet loss ratio in the case of overloading of the EMR0 (eight VC-4s are
bound on the FE port). The values are obtained when the SmartApplication is set as follows:
l Test duration (sec): 5
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Step rate: 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 13-16 Packet loss ratio in the case of overloading of the EMR0 (eight VC-4s are bound
on the FE port)
Frame Size
(Byte)
Rate Tested
(%)
(01,06,05) to
(01,06,06) (%)
(01,06,06) to
(01,06,05) (%)
Average (%)
64 100.00 0.000 0.000 0.000
128 100.00 0.000 0.000 0.000
256 100.00 0.000 0.000 0.000
512 100.00 0.000 0.000 0.000
1024 100.00 0.000 0.000 0.000
1280 100.00 0.000 0.000 0.000
1518 100.00 0.000 0.000 0.000

Table 13-17 lists the packet loss ratio in the case of overloading of the EMR0 (eight VC-4s are
bound on the GE port). The values are obtained when the SmartApplication is set as follows:
l Test duration (sec): 5
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
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l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Step rate: 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 13-17 Packet loss ratio in the case of overloading of the EMR0 (eight VC-4s are bound
on the GE port)
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,04,01) (%)
(01,04,01) to
(01,01,01) (%)
Average (%)
64 100.00 29.833 29.827 29.830
128 100.00 4.306 4.309 4.307
256 100.00 0.000 0.000 0.000
512 100.00 0.000 0.000 0.000
1024 100.00 0.000 0.000 0.000
1280 100.00 0.000 0.000 0.000
1518 100.00 0.000 0.000 0.000

Table 13-18 lists the latency specifications of the EMR0 (eight VC-4s are bound on the FE port).
The values are obtained when the SmartApplication is set as follows:
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the equipment and the
time when the first bit of the transmitted frame reaches the input port of the equipment. In
store forward mode, the analyzer calculates the difference between the time when the first
bit of the transmitted frame reaches the output port of the equipment and the time when the
last bit of the transmitted frame reaches the input port of the equipment. In the table, the
CT values are obtained in cut through mode and the S&F values are obtained in store
forward mode.
l Test duration (sec): 5
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Step rate: 10.00
l Resolution rate (%): none
l Mode: bidirectional
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Table 13-18 Latency specifications of the EMR0 (eight VC-4s are bound on the FE port)
Frame
Size
(Byte)
Rate
Tested
(%)
(01,06,05) to
(01,06,06) (us)-
CT (us)
Average
(CT) (us)
(01,06,05) to
(01,06,06)
(us)-S&F (us)
Average
(S&F) (us)
64 100.00 126.1 126.1 121.0 121.0
128 100.00 131.0 131.0 120.8 120.8
256 100.00 149.2 149.2 128.8 128.8
512 100.00 176.9 176.9 136.0 136.0
1024 100.00 237.0 237.0 155.1 155.1
1280 100.00 266.7 266.7 164.3 164.3
1518 100.00 289.3 289.3 167.9 167.9

Table 13-19 lists the latency specifications of the EMR0 (eight VC-4s are bound on the GE
port). The values are obtained when the SmartApplication is set as follows:
l The latency modes are classified into two modes, namely, cut through mode and store
forward mode. In cut through mode, the analyzer calculates the difference between the time
when the first bit of the transmitted frame reaches the output port of the equipment and the
time when the first bit of the transmitted frame reaches the input port of the equipment. In
store forward mode, the analyzer calculates the difference between the time when the first
bit of the transmitted frame reaches the output port of the equipment and the time when the
last bit of the transmitted frame reaches the input port of the equipment. In the table, the
CT values are obtained in cut through mode and the S&F values are obtained in store
forward mode.
l Test duration (sec): 20
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 72.41
l Step rate: 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 13-19 Latency specifications of the EMR0 (eight VC-4s are bound on the GE port)
Frame
Size
(Byte)
Rate
Tested
(%)
(01,01,01) to
(01,04,01) (us)-
CT (us)
Average
(CT) (us)
(01,01,01) to
(01,04,01)
(us)-S&F (us)
Average
(S&F) (us)
64 72.41 130.1 130.1 129.6 129.6
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Frame
Size
(Byte)
Rate
Tested
(%)
(01,01,01) to
(01,04,01) (us)-
CT (us)
Average
(CT) (us)
(01,01,01) to
(01,04,01)
(us)-S&F (us)
Average
(S&F) (us)
128 94.87 143.1 143.1 142.1 142.1
256 100.00 123.4 123.4 121.4 121.4
512 100.00 130.7 130.7 126.7 126.7
1024 100.00 154.4 154.4 146.3 146.3
1280 100.00 164.6 164.6 154.4 154.4
1518 100.00 174.4 174.4 162.3 162.3

Table 13-20 lists the back-to-back specifications of the EMR0 (eight VC-4s are bound on the
FE port). The values are obtained when the SmartApplication is set as follows:
l Test duration (sec): 2
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Step rate: 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 13-20 Back-to-back specifications of the EMR0 (eight VC-4s are bound on the FE port)
Frame Size
(Byte)
Rate Tested
(%)
(01,06,05) to
(01,06,06) Burst
Size (Number of
Frames)
(01,06,06) to
(01,06,05)
(Number of
Frames)
Total
(Number of
Frames)
64 100.00 297620 297620 595240
128 100.00 168918 168918 337836
256 100.00 90580 90580 181160
512 100.00 46992 46992 93984
1024 100.00 23946 23946 47892
1280 100.00 19230 19230 38460
1518 100.00 16254 16254 32508

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Table 13-21 lists the back-to-back specifications of the EMR0 (eight VC-4s are bound on the
GE port). The values are obtained when the SmartApplication is set as follows:
l Test duration (sec): 2
l Minimum frame size (byte): 64
l Maximum frame size (byte): 1518
l Step frame size (byte): custom
l Number of pairs: 1
l Initial rate (%): 100.00
l Step rate: 10.00
l Resolution rate (%): none
l Mode: bidirectional
Table 13-21 Back-to-back specifications of the EMR0 (eight VC-4s are bound on the GE port)
Frame Size
(Byte)
Rate Tested
(%)
(01,01,01) to
(01,04,01) Burst
Size (Number of
Frames)
(01,04,01) to
(01,01,01)
(Number of
Frames)
Total
(Number of
Frames)
64 100.00 3410 3410 6820
128 100.00 29054 29054 58108
256 100.00 905798 905798 1811596
512 100.00 469924 469924 939848
1024 100.00 239464 239464 478928
1280 100.00 192308 192308 384616
1518 100.00 162548 162548 325096

Mechanical Specifications
The mechanical specifications of the EMR0 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.2
Power Consumption
The maximum power consumption of the EMR0 at room temperature (25C) is 50 W.
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14 SAN Boards
About This Chapter
The SAN boards are multi-service transparent transmission processing boards.
14.1 MST4
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the MST4 (4-port multi-service transparent transmission board). This
topic also describes how to configure and commission the MST4.
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14.1 MST4
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the MST4 (4-port multi-service transparent transmission board). This
topic also describes how to configure and commission the MST4.
14.1.1 Version Description
The MST4 is available in one functional version, namely, N1.
14.1.2 Application
The MST4 is a multi-service transparent transmission board. The MST4 is used in remote
disaster recovery, remote backup and data centralization, and integration of storage resources.
14.1.3 Functions and Features
The MST4 supports the access of multiple services, alarms, and other maintenance functions.
14.1.4 Working Principle and Signal Flow
The MST4 consists of the client-side access module, FC protocol processing module,
encapsulation and mapping module, logic and control module, clock module, and power module.
14.1.5 Front Panel
The front panel of the MST4 has indicators, interfaces, and a bar code.
14.1.6 Jumpers and DIP Switches
The MST4 does not have any jumpers or DIP switches that are used for board settings.
14.1.7 Valid Slots
The MST4 must be installed in a valid slot in the subrack. Otherwise, the MST4 cannot work
normally.
14.1.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the MST4 indicates the type of supported services, type of optical interface,
and transmission distance.
14.1.9 Parameter Settings
You can set parameters for the MST4 by using the T2000.
14.1.10 Technical Specifications
The specifications of the MST4 include the parameters specified for optical interfaces, laser
safety class, dimensions, weight, and power consumption.
14.1.1 Version Description
The MST4 is available in one functional version, namely, N1.
14.1.2 Application
The MST4 is a multi-service transparent transmission board. The MST4 is used in remote
disaster recovery, remote backup and data centralization, and integration of storage resources.
The MST4 is used in the fields of the SAN services and video services. The MST4 can access
the FC100/FICON, FC200, ESCON, and DVB-ASI services, and provides the FC100 and FC200
services with the distance extension function. Hence, the MST4 is applicable to the long-distance
transmission of the FC services on the SDH network. In addition, the MST4 meets the
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transmission requirements of the storage network and extends the types of services supported
by the equipment. Figure 14-1 shows the networking and application of the SAN services.
Figure 14-1 Networking and application of the SAN services
FC switch FC switch
NE1 NE2

14.1.3 Functions and Features
The MST4 supports the access of multiple services, alarms, and other maintenance functions.
Table 14-1 provides the functions and features of the MST4.
Table 14-1 Functions and features of the MST4
Function and
Feature
MST4
Basic functions Provides four independent ports to access multiple services.
Supports the transparent transmission of the SAN and Video services.
Connector type LC
Optical module
type
SFP
Service types l Supports FC100/FICON, FC200, ESCON, and DVB-ASI services.
Table 14-2 describes types and rates of the services.
l Accesses four-channel FC services (FC100/FICON and FC200) at the
same time, and the total bandwidth is less than 2.5 Gbit/s.
l Supports the full-rate transmission of FC services (one-channel FC200
services or two-channel FC100 services).
l Accesses four-channel ESCON or DVB-ASI services, and the total
bandwidth is less than 2.5 Gbit/s.
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Function and
Feature
MST4
Distance
extension
The first and second ports support the distance extension function on the
SDH side.
l FC100 services: 3000 km
l FC200 services: 1500 km
Maximum
uplink
bandwidth
2.5 Gbit/s
The backplane provides four 622 Mbit/s buses that are directly connected
to the cross-connect unit.
The MST4 can adapt to the bandwidth of the slot.
Mapping
granularity
Supports the VC4-Xc (X = 4, 8, or 16) granularity.
ESCON
services
Accesses four-channel ESCON services, and the total bandwidth is less
than 2.5 Gbit/s.
DVB-ASI
services
Accesses four-channel DVB-ASI services, and the total bandwidth is less
than 2.5 Gbit/s.
Encapsulation
format
Supports the GFP-T protocol, which complies with ITU-T G.7041.
Maintenance
features
Supports inloops and outloops on ports on the customer side, which can
be used to locate faults quickly.
Alarms and
performance
events
Reports various alarms and performance events, which can be used to
locate faults and maintain the equipment.

Table 14-2 Service types service rates supported by the MST4
Service Type Rate Remarks
FC100/FICON 1062.5 Mbit/s SAN service
FC200 2125 Mbit/s SAN service
ESCON 200 Mbit/s SAN service
DVB-ASI 270 Mbit/s Video service

14.1.4 Working Principle and Signal Flow
The MST4 consists of the client-side access module, FC protocol processing module,
encapsulation and mapping module, logic and control module, clock module, and power module.
Figure 14-2 shows the functional block diagram of the MST4 by describing how to process
1xFC100 signals, 1xFC200 signals, 1xFICON signals, 1xDVB-ASI signals, or 1xESCON
signals.
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Figure 14-2 Functional block diagram of the MST4
Client-
side
access
module
FC100
FC200
FICON
DVB-ASI
Reference clock and frame header
SCC unit
Communication
processing module
FC1_
SND
Decap-
sulation
FC1_
SND
Logic and control module
Clock
module
135 MHz
125 MHz
100 MHz
212.5 MHz
622 MHz
ESCON
Encapsulation and
+3.3 V backup power
+3.3 V
Power
module
Fuse
Fuse
-48 V/-60 V
Cross-connect unit A/B
Power
module
FC2
FC1_
RCV
FC1_
RCV
FC2
Mapping
Interface
converting
module
Backplane
-48 V/-60 V
Cross-connect unit A/B
Cross-connect unit
Encap-
sulation
FC protocol
mapping module

Client-Side Access Module
The client-side access module accesses FC100, FC200, FICON, DVB-ASI, and ESCON
services. The client-side interface unit performs O/E conversion for services and monitors the
optical signals on the client side.
In the upstream direction, the client-side data interface (CDI) receives serial data signals accessed
through the SFP optical module. The serial data signals are then transmitted to the PCS functional
module for physical layer and 8B/10B line performance monitoring.
In the downstream direction, 8B/ 10B conversion is performed for the signals from FC. The
signals are then adapted into client reference clocks by inserting or discarding idle packets. After
being converted from parallel signals into serial signals, the signals are transmitted through the
CDI interface to the optical module on the client side.
FC Protocol Processing Module
The FC protocol processing unit mainly extends the distance of FC service transmission. This
module supports the maximum transmission distance of 3000 km for 2xFC100 services or the
maximum transmission distance of 1500 km for 1xFC200 services.
The FC protocol processing unit performs FC1 layer and FC2 layer functions. The FC1 layer
functions include the following:
l 8B/10B conversion
l Synchronous processing
l Extraction of primitive signal and primitive sequence
The FC2 layer functions include the following:
l Check and counting of all special frames
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l Modification of values of certain special frames (FLOG1, PLOG1, and ELP)
l CRC check
Encapsulation and Mapping Module
The encapsulation and mapping module mainly performs the following functions:
l Encapsulates and maps data.
l Decapsulates and demaps data.
According to the direction of the signal flow, the functional modules inside the chip can be
classified into modules in the ingress direction and modules in the egress direction. In the ingress
direction, signals from the client side to the line side are processed. In the egress direction, signals
from the line side to the client side are processed.
Ingress direction
Through GFP encapsulation, 64B/65B conversion is performed for data bytes after decoding.
The data bytes are then mapped in compliance with the GFP protocol.
Egress direction
SDH data frames are received from the line-side interface module. After overheads are
processed, GFP data frames are extracted from SDH concatenated channels and are then
transmitted to the decapsulation module for decapsulation.
Logic and Control Module
The logic and control module consists of the CPU, register, oscillator, Ethernet port, and HDLC
controller. This module is connected to external circuits through buses. The logic and control
module manages and configures other modules of the board. This module contains basic logic
units and performs the following functions:
l Writes and reads the register.
l Provides interfaces for the CPU.
l Checks and selects the clock.
l Performs phase discrimination and frequency division on the clock.
l Checks the in-service state of the cross-connect, SCC, and line boards.
l Controls the shutting down of the optical module.
l Implements communication.
l Controls indicators.
Clock Module
This module provides required reference clocks for boards. The clock frequency can be 100
MHz or 125 MHz.
Power Module
It converts the 48 V/60 V power supply into the DC voltages that the modules of the board
require.
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14.1.5 Front Panel
The front panel of the MST4 has indicators, interfaces, and a bar code.
Diagram of the Front Panel
Figure 14-3 shows the appearance of the front panel of the MST4.
Figure 14-3 Front panel of the MST4
MST4
MST4
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
O
U
T
1
I
N
1
O
U
T
2
I
N
2
O
U
T
3
I
N
3
O
U
T
4
I
N
4

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
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l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the MST4 has four pair of optical interfaces. Table 14-3 describes the types
and usage of the optical interfaces of the MST4.
Table 14-3 Optical interfaces of the MST4
Interface Type of
Interface
Usage
IN1IN4 LC Receives multi-service optical signals.
OUT1OUT4 LC Transmits multi-service optical signals.

14.1.6 Jumpers and DIP Switches
The MST4 does not have any jumpers or DIP switches that are used for board settings.
14.1.7 Valid Slots
The MST4 must be installed in a valid slot in the subrack. Otherwise, the MST4 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The MST4 can be installed in slots 18 and 1116 in the subrack.
l When the cross-connect capacity is 200 Gbit/s, the MST4 can be installed in slots 18 and
1116. When the MST4 is installed in slots 14, 15, and 16, the bandwidth is 1.25 Gbit/s.
When the MST4 is installed in slots 58 and 1114, the bandwidth is 2.5 Gbit/s.
14.1.8 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the MST4 indicates the type of supported services, type of optical interface,
and transmission distance.
Table 14-4 provides the relationship between the feature code of the MST4, the type of supported
services, type of optical interface, and transmission distance.
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Table 14-4 Relationship between the feature code of the MST4, the type of supported services,
type of optical interface, and transmission distance
Board Feature
Code
Type of Supported Services
(Type of Optical Interface)
Transmission
Distance
SSN1MST410 10 2xFC (SM) 2 km
SSN1MST411 11 2xFC (SM) 15 km
SSN1MST412 12 2xFC (MM) 0.5 km
SSN1MST413 13 4xESCON/DVB-ASI (SM) 15 km
SSN1MST414 14 4xESCON/DVB-ASI (MM) 2 km
SSN1MST415 15 1xFC2 (MM) -
ESCON/DVB-ASI (MM)
SSN1MST416 16 1xFC2 (MM) -
ESCON/DVB-ASI (SM)
SSN1MST417 17 1xFC (SM) 2 km
2xESCON/DVB-ASI (SM) -
SSN1MST418 18 1xFC (SM) 2 km
2xESCON/DVB-ASI (MM) -

14.1.9 Parameter Settings
You can set parameters for the MST4 by using the T2000.
You can set the following parameters for the MST4 by using the T2000:
l J1 byte
l C2 byte
For the description of each parameter, see 25 Parameter Settings.
14.1.10 Technical Specifications
The specifications of the MST4 include the parameters specified for optical interfaces, laser
safety class, dimensions, weight, and power consumption.
Parameters Specified for Optical Interfaces
The optical interfaces of the MST4 can use several types of optical modules. Table 14-5 lists
the parameters specified for the optical interfaces of the MST4.
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Table 14-5 Parameters specified for the optical interfaces of the MST4
Parameter Value
Type of optical
interface
X3.296/(DVB-ASI )
EN50083-9
200-M5-SN-I 200-SM-LC-I
Part number of
optical module
34060277 34060287 34060325 34060288 34060278
Type of
supported
services
ESCON/DVB FC200, FC100
Service rate STM-4 STM-1 2.125 Gbit/s STM-16
Type of fiber Single-
mode LC
Multi-mode
LC
Multi-mode
LC
Single-
mode LC
Single-
mode LC
Operating
wavelength
range (nm)
1310 850 1310
Transmission
distance (km)
15 2 0.5 2 15
Launched
optical power
range (dBm)
-15 to -8 -19 to -14 -9.5 to -2.5 -10 to -3 -5 to -3
Receiver
sensitivity
(dBm)
-31 -30 -17 -21
Minimum
overload (dBm)
-8 -14 0 -3 0

Mechanical Specifications
The mechanical specifications of the MST4 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.9
Power Consumption
The maximum power consumption of the MST4 at room temperature (25C) is 26 W.
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15 Microwave Boards
About This Chapter
The microwave boards include the microwave intermediate frequency (IF) board IFSD1 and
microwave power board RPWR.
15.1 IFSD1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the IFSD1 (dual-port IF board). This topic also describes how to
configure and commission the IFSD1.
15.2 RPWR
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the RPWR (6-channel ODU power board). This topic also describes
how to configure and commission the RPWR.
15.3 ODU
When the microwave board is used, it needs to work with the microwave outdoor unit (ODU).
The ODU types supported by the equipment are standard power (SP) and high power (HP).
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15.1 IFSD1
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the IFSD1 (dual-port IF board). This topic also describes how to
configure and commission the IFSD1.
15.1.1 Version Description
The IFSD1 is available in one functional version, namely, N1.
15.1.2 Application
Working as the microwave module on the OptiX OSN equipment, the IFSD1 can receive and
transmit two IF signals and work with the OptiX RTN 600 to transmit microwave signals.
15.1.3 Functions and Features
The IFSD1 transmits and receives two IF signals, provides the management channel to the ODU,
and supplies the 48 V power to the ODU.
15.1.4 Working Principle and Signal Flow
The IFSD1 consists of the combiner interface module, IF processing module, MODEM module,
FPGA module, rate converting module, and communication and control module.
15.1.5 Front Panel
The front panel of the IFSD1 has indicators, interfaces, power switches, and labels.
15.1.6 Jumpers and DIP Switches
The IFSD1 does not have any jumpers or DIP switches that are used for board settings.
15.1.7 Valid Slots
The IFSD1 must be installed in a valid slot in the subrack. Otherwise, the IFSD1 cannot work
normally.
15.1.8 Feature Code
The IFSD1 does not have the feature code.
15.1.9 Board Protection
The IFSD1 supports the 1+1 HSB/FD/SD protection and N+1 protection.
15.1.10 Parameter Settings
You can set parameters for the IFSD1 by using the T2000 LCT and T2000.
15.1.11 Technical Specifications
The technical specifications of the IFSD1 include the IF performance, baseband signal
processing performance, board mechanical specifications, and power consumption.
15.1.1 Version Description
The IFSD1 is available in one functional version, namely, N1.
15.1.2 Application
Working as the microwave module on the OptiX OSN equipment, the IFSD1 can receive and
transmit two IF signals and work with the OptiX RTN 600 to transmit microwave signals.
The OptiX OSN equipment can be configured with multiple IFSD1 boards according to the
service configuration so that the microwave services in multiple directions can be connected.
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Figure 15-1 shows the position of the OptiX OSN equipment that is configured with the IFSD1
in the network.
Figure 15-1 Position of the OptiX OSN equipment that is configured with the IFSD1 in the
network
SDH/PDH
SDH/PDH
STM-64/STM-16/STM-4 ring
OptiX optical
transmission product
OptiX RTN 600
SDH/PDH
OptiX OSN
equipment
IFSD1: 11-13

15.1.3 Functions and Features
The IFSD1 transmits and receives two IF signals, provides the management channel to the ODU,
and supplies the 48 V power to the ODU.
Table 15-1 provides the functions and features of the IFSD1.
Table 15-1 Functions and features of the IFSD1
Function and
Feature
IFSD1
Basic functions Supports 2xSTM-1 SDH or PDH IF signals and management control
signals between the IDU and ODU, and supplies power to the ODU.
IF processing l Maps PDH signals and SDH signals into IF signals.
l Codes and decodes IF signals.
l Modulates and demodulates IF signals.
l Modulates and demodulates ODU control signals.
l Combines and splits service signals, ODU control signals, and 48
V power supplies.
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Function and
Feature
IFSD1
Microwave features l Supports the software programmable radio (SPR) function. That
is, you can set the microwave capacity and modulation scheme by
using the software.
l Supports the microwave frame that is based on the tributary and
STM-1, and hence supports the interconnection with the OptiX
OSN products or the OptiX RTN 600 products that support this
type of microwave frame through the air interface.
l Supports the automatic transmit power control (ATPC) function.
Service processing Supports the configuration of VC-12, VC-3, and VC-4 services.
Overhead processing l Processes the section overheads of the STM-1 IF signals.
l Supports the transparent transmission and termination of the path
overheads of the STM-1 IF signals.
l Supports the setting and query of the J1 and C2 bytes.
Pointer processing l Processes AU pointers of SDH IF signals.
l Processes TU pointers of PDH IF signals.
Alarms and
performance events
Reports various alarms and performance events, which facilitates the
management and maintenance of the equipment.
Protection schemes Supports the following protection schemes:
l 1+1 HSB
l 1+1 FD
l 1+1 SD
l N+1 Protection
l Microwave lower order SNCP
Maintenance
features
l Supports loopbacks on VC-4 paths.
l Supports loopbacks on IF ports.
l Supports the detection of the board temperature.
l Supports warm resets and cold resets. The warm reset does not
affect the services.
l Supports the query of the manufacturing information of the board.
l Supports the query of the version information of the board.
l Supports the in-service loading of the FPGA.
l Supports the detection of the hardware fault.
l Supports the PRBS function.

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15.1.4 Working Principle and Signal Flow
The IFSD1 consists of the combiner interface module, IF processing module, MODEM module,
FPGA module, rate converting module, and communication and control module.
This topic considers the processing of one IF signal that is sent from the ODU as an example to
describe the working principle and signal flow of the IFSD1.
Figure 15-2 shows the functional block diagram of the IFSD1.
Figure 15-2 Functional block diagram of the IFSD1
Backplane
IF
SCC
Service bus
Overhead bus Control bus
IF signal ODU control signal
Board in the paired slot
FPGA module
M
U
X/
D
E
M
U
X
ODU
Cross-connect
unit
-48 V power supply
-48 V
Communication bus
R
a
t
e
c
o
n
v
e
r
t
i
n
g
IF
processing
module
Combiner
interface
module
Clock
module
Power
module
Communication and
control module
Overhead
processing
Overhead
s related
to HSM
SCC
SCC
SMOD
EM
MODEM
module

Signal Processing Flow in the Transmit Direction
After the service signals are processed by the rate converting module, the signals from the cross-
connect unit are sent to the MUX/DEMUX module of the FPGA module where the signals are
scrambled and the overhead byte and pointer are set. Then, the signals are sent to the MODEM
module for FEC coding and digital modulation and to the IF processing module for D/A
converting and analog modulation. The ODU control signals sent from the logic and control
module are sent to the combiner interface module after being modulated by the SMODEM
module. Finally, the IF signals, ODU control signals, and 48 V power supplies are combined
at the combiner interface module and then sent to the ODU over IF cables.
Signal Processing Flow in the Receive Direction
The combiner interface module divides the ODU control signals and IF signals from the received
IF signals. The ODU control signals are sent to the SMODEM module for demodulation and
then to the logic and control module. The IF signals are sent to the IF processing module for
filtering and A/D converting and then to the FPGA module for demultiplexing and overhead
processing. Then, the signals are sent to the rate converting module. Finally, the signals are sent
to the cross-connect unit.
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15-5
Auxiliary Modules
The auxiliary modules include the logic and control module, clock module, and power module.
The functions of these modules are as follows:
l Logic and control module
This module realizes the alarm display, performance monitoring, and communication with the
system control and communication board and the other boards through the Ethernet interface.
In addition, this module provides two pairs of RS485 data buses and can provide quick response
in real time. This module supports the in-service loading of programs.
l Clock module
Extracts the clock from the received signal and sends the 8 KHz clock to the clock unit.
Supports the 38 MHz system clock in the transmit direction.
l Power module
Provides two 48 V power input interfaces and supports the DC power supply whose
input voltage ranges from 38.4 V to 72 V.
Provides DC power supplies for all the modules on the IFSD1.
Monitors all the power supplies for the IFSD1 and reports alarms in the case of a board
voltage abnormality.
Provides one 48 V DC power supply for the ODU.
15.1.5 Front Panel
The front panel of the IFSD1 has indicators, interfaces, power switches, and labels.
Diagram of the Front Panel
Figure 15-3 shows the appearance of the front panel of the IFSD1.
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Figure 15-3 Front panel of the IFSD1
IFSD1
IFSD1
IF1
ODU-PWR1
STAT
PROG
SRV
ODU1
LINK2
LINK1
ACT2
ODU2
ACT1
ODU-PWR2
I
IF2
W
A
R
N
IN
G
-
4
8
V
O
U
T
P
U
T
T
U
R
N
O
F
F
P
O
W
E
R
B
E
F
O
R
E
D
IS
C
O
N
N
E
C
T
IN
G
IF
C
A
B
L
E
!
PWR1
PWR2
O
I
O

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Board software status indicator (PROG) two colors (red and green)
l Active/Standby state indicator (ACT1) one color (green)
l Active/Standby state indicator (ACT2) one color (green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
l Connection status indicator 1 (LINK1) two colors (red and green)
l Connection status indicator 2 (LINK2) two colors (red and green)
l Working indicator of ODU 1 (ODU1) two colors (red and green)
l Working indicator of ODU 2 (ODU2) two colors (red and green)
For the meanings of the status of the indicators, see 22 Indicators.
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15-7
Interfaces
Table 15-2 Interfaces of the IFSD1
Interface Description Usage
IF1 IF port 1 IF port 1 refers to the IF interface between the
IDU and the ODU. This port transmits the
signal that combines the IF service signal,
ODU control signal, and 48 V power supply
required by the ODU. A single type-N IF
cable is used for connection.
IF2 IF port 2 IF port 2 refers to the IF interface between the
IDU and the ODU. This port transmits the
signal that combines the IF service signal,
ODU control signal, and 48 V power supply
required by the ODU. A single N-Type IF
cable is used for connection.
PWR1 Power interface 1 The power supply provided by the RPWR is
transferred by the combiner unit of the IF
board to supply power to the ODU. The IF
board can provide a maximum through-
current of 1.76 A for the ODU. The PWR1
interface must be connected to the dedicated
power cable that is delivered with the
equipment.
PWR2 Power interface 2 The power supply provided by the RPWR is
transferred by the combiner unit of the IF
board to supply power to the ODU. The IF
board can provide a maximum through-
current of 1.76 A for the ODU. The PWR2
interface must be connected to the dedicated
power cable that is delivered with the
equipment.
ODU-PWR1
a
ODU power switch 1 Turns on or turns off the 48 V DC power
supply for the ODU.
ODU-PWR2
a
ODU power switch 2 Turns on or turns off the 48 V DC power
supply for the ODU.

CAUTION
a: The ODU-PWR1 and ODU-PWR2 switches are equipped with lockup devices. To move the
switch, you need to pull the switch lever partially. When the switch is set to "O", it indicates that
the circuit is open. When the switch is set to "I", it indicates that the circuit is closed.
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Labels
The front label has a high temperature warning label and an operation warning label.
The high temperature warning label indicates that the board surface temperature may exceed
70C when the ambient temperature is higher than 55C. In this case, you need to wear protective
gloves before touching the board.
The operation warning label indicates that the ODU power switch must be turned off before the
IF cable is removed.
15.1.6 Jumpers and DIP Switches
The IFSD1 does not have any jumpers or DIP switches that are used for board settings.
15.1.7 Valid Slots
The IFSD1 must be installed in a valid slot in the subrack. Otherwise, the IFSD1 cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the IFSD1 are as follows:
l When the cross-connect capacity is 200 Gbit/s, the IFSD1 can be installed in slots 18 and
1117.
15.1.8 Feature Code
The IFSD1 does not have the feature code.
15.1.9 Board Protection
The IFSD1 supports the 1+1 HSB/FD/SD protection and N+1 protection.
15.1.10 Parameter Settings
You can set parameters for the IFSD1 by using the T2000 LCT and T2000.
You can set the following parameters for the IFSD1 by using the network management system:
l Radio work mode
l Radio link ID
l ATPC attributes
l J1 byte
The J1 byte is applicable to SDH microwave only. The other parameters are applicable to both
PDH and SDH microwaves.
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15-9
Radio Work Mode
Table 15-3 Radio work modes
Service Capacity Modulation Scheme Channel Spacing (MHz)
4xE1 QPSK 7
4xE1 16QAM 3.5
8xE1 QPSK 14 (13.75)
8xE1 16QAM 7
16xE1 QPSK 28 (27.5)
16xE1 16QAM 14 (13.75)
22xE1 32QAM 14 (13.75)
26xE1 64QAM 14 (13.75)
35xE1 16QAM 28 (27.5)
44xE1 32QAM 28 (27.5)
53xE1 64QAM 28 (27.5)
STM-1 128QAM 28 (27.5)

NOTE
l The channel spacings 13.75 MHz and 27.5 MHz are applied to the 18 GHz frequency band.
l The channel spacings provided in the table are the minimum channel spacings supported by the OptiX OSN
equipment series. The channel spacings equal to or larger than the values are also supported.
Radio Link ID
The radio link ID is an identification of the radio link. The transmit end sends the radio link ID
byte continuously so that the receive end can learn that the transmit end is in a constant
connection state. If the receive end detects a mismatch of the radio link ID, the receive end inserts
the all "1"s signal and the corresponding IF port reports the MW_LIM alarm.
ATPC Attributes
The ATPC is a technology that automatically adjusts the transmit power of the transmitter
according to the attenuation of the received signal level (RSL) at the receive end. The ATPC
attributes include the following parameters:
l ATPC enable status
This parameter specifies whether the NE enables the ATPC function to control the transmit
power of the transmitter. By default, the ATPC function is disabled.
l ATPC upper threshold
When the RSL at the receive end is higher than the set value of this parameter, the receive
end notifies the transmit end to reduce the transmit power by using the ATPC overhead in
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the microwave frame. The decrement depends on the value of the ATPC adjustment
parameter.
l ATPC lower threshold
When the RSL at the receive end is lower than the set value of this parameter, the receive
end notifies the transmit end to increase the transmit power by using the ATPC overhead
in the microwave frame. The increment depends on the value of the ATPC adjustment
parameter.
l ATPC adjustment
This parameter specifies the decrement/increment of an ATPC adjustment.
NOTE
The ATPC adjustment cannot exceed the range of the ODU transmit power.
J1 Byte
The IFSD1 board supports four byte modes, which are as follows:
l Single-byte mode
l 16-byte mode with CRC
l 16-byte mode without CRC
l 64-byte mode
By default, the IFSD1 board does not monitor the received J1 byte. That is, the J1 byte to be
received is set to the disabled mode. The J1 byte to be sent is a 16-byte string with CRC. The
first byte is created automatically and the following 15 bytes are the ASCII codes "HuaWei SBS
". The last five characters of the string are blank spaces.
15.1.11 Technical Specifications
The technical specifications of the IFSD1 include the IF performance, baseband signal
processing performance, board mechanical specifications, and power consumption.
Microwave Capacity
One IFSD1 board can access microwave signals in both directions. The capacity of microwave
signals in each direction depends on the radio work mode of these microwave signals. For details
about the radio work modes, see 15.1.10 Parameter Settings.
IF Performance
Table 15-4 IF performance
Item Performance
IF signal
Transmit frequency of the IF
board (MHz)
350
Receive frequency of the IF
board (MHz)
140
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Item Performance
Impedance (ohm) 50
ODU O&M signal
Modulation scheme ASK
Transmit frequency of the IF
board (MHz)
5.5
Receive frequency of the IF
board (MHz)
10

Baseband Signal Processing Performance of the Modem
Table 15-5 Baseband signal processing performance of the modem
Item Performance
Coding mode l Uses Reed-Solomon (RS) coding for PDH signals.
l Uses Trellis-Coded Modulation (TCM) and RS two-level coding
for SDH signals.
Adaptive time-
domain equalizer for
baseband signals
Consists of the feed forward equalizer filter and decision feedback
equalizer.

Mechanical Specification
The mechanical specifications of the IFSD1 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 245.1 (H)
l Weight (kg): 1.1
Power Consumption
The maximum power consumption of the IFSD1 at room temperature (25C) is 24 W.
15.2 RPWR
This topic describes the version, application, functions, working principle, front panel, and
technical specifications of the RPWR (6-channel ODU power board). This topic also describes
how to configure and commission the RPWR.
15.2.1 Version Description
The RPWR is available in one functional version, namely, N1.
15.2.2 Application
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The RPWR is a power access board and is not related to the service features. The RPWR,
however, must be configured if the product needs to provide the IF feature. The RPWR accesses
two 38.4 V to 72 V DC power supplies, provides the IFSD1 with six independent 48 V power
supplies, and finally feeds power to the ODU after the IFSD1 processes the six 48 V power
supplies.
15.2.3 Functions and Features
The RPWR accesses two 48 V/60 V DC power supplies and supplies the 48 V power to six
ODUs.
15.2.4 Working Principle and Signal Flow
The RPWR consists of the combiner module, protection module, filtering module, DC/DC power
module (that is, power module), and status detection module.
15.2.5 Front Panel
The front panel of the RPWR has indicators, power input interfaces, and power output interfaces.
15.2.6 Valid Slots
The RPWR must be installed in a valid slot in the subrack. Otherwise, the RPWR cannot work
normally.
15.2.7 Feature Code
The RPWR does not have the feature code.
15.2.8 Technical Specifications
The technical specifications of the RPWR include the mechanical specifications, power
consumption, input voltage, and specifications of the fuse.
15.2.1 Version Description
The RPWR is available in one functional version, namely, N1.
15.2.2 Application
The RPWR is a power access board and is not related to the service features. The RPWR,
however, must be configured if the product needs to provide the IF feature. The RPWR accesses
two 38.4 V to 72 V DC power supplies, provides the IFSD1 with six independent 48 V power
supplies, and finally feeds power to the ODU after the IFSD1 processes the six 48 V power
supplies.
Figure 15-4 shows the position of the OptiX OSN equipment that is configured with the RPWR
in the network.
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15-13
Figure 15-4 Position of the OptiX OSN equipment that is configured with the RPWR in the
network
SDH/PDH
SDH/PDH
STM-64/STM-16/STM-4 ring
OptiX optical
transmission product
OptiX RTN 600
SDH/PDH
OptiX OSN
equipment
RPWR: 11-13

15.2.3 Functions and Features
The RPWR accesses two 48 V/60 V DC power supplies and supplies the 48 V power to six
ODUs.
Table 15-6 provides the functions and features of the RPWR.
Table 15-6 Functions and features of the RPWR
Function and
Feature
RPWR
Input power l Provides the 48 V power supply after converting the 48 V DC
power supply, which is realized through the internal power module.
l Accesses the 48 V/60 V DC power system. The voltage of the
two input DC power supplies ranges from 38.4 V to 72 V.
Combiner function Combines the power supplies.
Protection against
lightning, surge,
and short-circuit
Provides protection against lightning, surge, and short-circuit.
Protection
function
In the case of the DC power interface, the differential-mode voltage
must be more than 2 kV and the common-mode voltage must be more
than 4 kV.
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Function and
Feature
RPWR
Filtering function Provides the filtering for the power interface and has the structural
shielding that improves the electromagnetic compatibility.
Power output Provides six 48 V power supplies for the ODU. The maximum power
consumption of each power supply is 60 W.
Alarm and
indication
Provides one board operation indicator.
l When the indicator turns red, it indicates that one or more power
modules are faulty.
l When the indicator is on and green, it indicates that the board works
normally and no alarms are reported.
Power supply
backup
The input of the power board supports the 1+1 hot backup. The output
of the power module has no backup.

15.2.4 Working Principle and Signal Flow
The RPWR consists of the combiner module, protection module, filtering module, DC/DC power
module (that is, power module), and status detection module.
Figure 15-5 shows the functional block diagram of the RPWR.
Figure 15-5 Functional block diagram of the RPWR
-48V_1
-48V_2
Fuse 2
Fuse 1
Fuse 3
Fuse 4
Fuse 5
Fuse 6
Six channels
IF port 1
IF port 2
IF port 3
IF port 4
IF port 5
IF port 6
Power
module 6
Power
module 4
Power
module 5
Power
module 3
Power
module 2
Power
module 1
Combiner
module
Protection
module
Filtering
module
Soft start
module
Status
detection
module
Optical
coupling
isolation
Board operation
indicator

Signal Flow
The two 48 V power supplies pass through the combiner, protection, filtering, soft start, and
power modules after they are accessed to the power board. The voltage converting operation is
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15-15
performed on the two 48 V power supplies at the power module (using the DC_I and DC_C
grounding mode). Then, six isolated ODU power supplies are sent to the IF board for processing
and finally are used to supply power to ODUs.
Status Detection Module
The status detection module checks whether the output power supply exists and reports the real
condition so that the STAT indicator indicates the condition. When the STAT indicator turns
red, it indicates that one ore more power modules are faulty. When the STAT indicator is on and
green, it indicates that the power supply works normally.
Power Module
The two 48 V power supplies enter the DC/DC power converting module after they traverse
the protection, filtering, and soft start modules. The power supplies are isolated by the internal
transformer of the power module so that six independent stable power supplies can be sent to
the status detection module and finally to the IF board.
15.2.5 Front Panel
The front panel of the RPWR has indicators, power input interfaces, and power output interfaces.
Diagram of the Front Panel
Figure 15-6 shows the appearance of the front panel of the RPWR.
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Figure 15-6 Front panel of the RPWR
P
O
W
E
R
4
P
O
W
E
R
4
N
E
G
(
-
)
R
T
N
(
+
)
RPWR
RPWR
P
O
W
E
R
2
P
O
W
E
R
1
P
O
W
E
R
3
P
O
W
E
R
4
STAT
N
E
G
(
-
)
R
T
N
(
+
)

Indicators
The front panel of the board has one indicator as follows: board hardware status indicator (STAT)
two colors (red and green)
For the meanings of the status of the indicator, see 22 Indicators.
Interfaces
The front panel of the RPWR has two power input interfaces and six power output interfaces.
Table 15-7 describes the types and usage of the interfaces of the RPWR.
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15-17
Table 15-7 Interfaces of the RPWR
Interface Type of Interface Usage
PWR1 48 V power input interface Accesses the 48 V power supply.
PWR2 48 V power input interface Accesses the 48 V power supply.
POWER1
POWER6
48 V power output interface Supplies the 48 V power to the IF
board for processing. Then, the IF
board supplies the power to the ODU.

15.2.6 Valid Slots
The RPWR must be installed in a valid slot in the subrack. Otherwise, the RPWR cannot work
normally.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the RPWR are as follows:
l When the cross-connect capacity is 200 Gbit/s, the RPWR can be installed in slots 18 and
1117.
15.2.7 Feature Code
The RPWR does not have the feature code.
15.2.8 Technical Specifications
The technical specifications of the RPWR include the mechanical specifications, power
consumption, input voltage, and specifications of the fuse.
Mechanical Specifications
The mechanical specifications of the RPWR are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 245.1 (H)
l Weight (kg): 1.4
Power Consumption
The maximum power consumption of the RPWR at room temperature (25C) is 45 W.
Input Voltage
The input voltage range of the RPWR is as follows:
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l If the standard voltage of the accessed power supply is -48 V, the voltage of the power
supply ranges from -38.4 V to -57.6 V.
l If the standard voltage of the accessed power supply is -60 V, the voltage of the power
supply ranges from -48 V to -72 V.
Specifications of the Fuses
Two types of fuses are available for the main circuit and power modules of the RPWR.
l Specifications of the fuse for the main circuit are as follows: fast blow fuse, 250 V, 20 A,
UL certificated, 0.00355 ohms, 631 A x A x second, UL/CSA/METI
l Specifications of the fuse for the power modules of the RPWR are as follows: slow blow
fuse, surface-mounted fuse, 125 V, 4 A, UL certificated, 0.023 ohms, 23 A x A x second,
UL.
15.3 ODU
When the microwave board is used, it needs to work with the microwave outdoor unit (ODU).
The ODU types supported by the equipment are standard power (SP) and high power (HP).
For more information on the ODU, see the ODU Hardware Description.
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15-19
16 WDM Boards
About This Chapter
The WDM boards include the CMR2, CMR4, MR2, MR2A, MR2C, MR4, LWX, and FIB.
16.1 CMR2
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11CMR2 (2-channel optical add/drop multiplexing board).
16.2 CMR4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11CMR4 (4-channel optical add/drop multiplexing board).
16.3 MR2
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11MR2 (2-channel optical add/drop multiplexing board).
16.4 MR2A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the MR2A (2-channel optical add/drop multiplexing board).
16.5 MR2C
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the MR2C (2-channel optical add/drop multiplexing board).
16.6 MR4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11MR4 (4-channel optical add/drop multiplexing board).
16.7 LWX
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the LWX (arbitrary bit rate wavelength conversion board).
16.8 FIB
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the FIB (filter isolating board).
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16.1 CMR2
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11CMR2 (2-channel optical add/drop multiplexing board).
16.1.1 Version Description
The CMR2 is available in one functional version, namely, TN11.
16.1.2 Application
The CMR2 is mainly used to add/drop and multiplex two channels of wavelength signals to/
from the multiplexed signals.
16.1.3 Functions and Features
The CMR2 is applied to the coarse wavelength division multiplexing (CWDM) system. The
channel spacing is 20 nm. The CMR2 supports the add/drop multiplexing function and channel
expansion function.
16.1.4 Working Principle and Signal Flow
The CMR2 consists of the OADM module, communication and control module, and power
module.
16.1.5 Front Panel
The front panel of the CMR2 has indicators, interfaces, and a laser safety class label.
16.1.6 Valid Slots
16.1.7 Feature Code
The feature code of the CMR2 contains eight characters, which indicate the wavelengths of the
two channels of optical signals processed by the CMR2.
16.1.8 Technical Specifications
The technical specifications of the CMR2 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
16.1.1 Version Description
The CMR2 is available in one functional version, namely, TN11.
16.1.2 Application
The CMR2 is mainly used to add/drop and multiplex two channels of wavelength signals to/
from the multiplexed signals.
Figure 16-1 shows the application of the CMR2 in the CWDM system.
Figure 16-1 Application of the CMR2 in the CWDM system
CMR2 CMR2
Remarks: The line board in this figure supports CWDM wavelength signals.
Line
board
Line
board
Line
board
Optical transmission
network
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16.1.3 Functions and Features
The CMR2 is applied to the coarse wavelength division multiplexing (CWDM) system. The
channel spacing is 20 nm. The CMR2 supports the add/drop multiplexing function and channel
expansion function.
Table 16-1 provides the functions and features of the CMR2.
Table 16-1 Functions and features of the CMR2
Function and
Feature
CMR2
Basic functions Adds/Drops and multiplexes two signals to/from the multiplexed
signals.
Channel expansion Provides the interface to cascade another optical add/drop
multiplexing board to realize the expansion of the add/drop channel.

16.1.4 Working Principle and Signal Flow
The CMR2 consists of the OADM module, communication and control module, and power
module.
Figure 16-2 shows the functional block diagram of the CMR2.
Figure 16-2 Functional block diagram of the CMR2
OADM optical
module
IN
D1 D2 A1 A2
Drop optical
module
Add optical
module
OUT
MO MI
SCC
CPU Memory
Control
Communication
Control and communication module
Backplane
(controlled by SCC)
Power supply
module
DC power supply
from a backplane
Required
voltage
Fuse
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The CMR2 contains the OADM module that adds, drops, and multiplexes two channels of
signals. In addition, the CMR2 provides the interface to cascade another optical add/drop
multiplexing board to increase the add/drop capability. The CMR2 is a passive board and does
not have an interface with the backplane.
OADM Module
The board receives one multiplexed optical signal that is sent by the upstream station on the IN
interface. Then, the drop optical module drops two wavelengths from the signal through optical
interfaces D01 and D02. The two dropped wavelengths are transmitted through the MO optical
interface.
The board receives one multiplexed signal that travels over the main optical path on the MI
optical interface. Then, the add optical module adds two wavelengths through optical interfaces
A01 and A02 and multiplexes them with the signal on the main optical path into one signal. This
multiplexed signal is transmitted through the OUT interface.
Communication and Control Module
l Controls the operations of the entire board.
l Collects the following information of each functional module of the board: alarms,
performance events, working status, and voltage detection.
l Communicates data with the SCC.
DC/DC Converter
It converts 48 V DC or 60 V DC into a voltage required by each module of the board.
16.1.5 Front Panel
The front panel of the CMR2 has indicators, interfaces, and a laser safety class label.
Diagram of the Front Panel
Figure 16-3 shows the appearance of the front panel of the CMR2.
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Figure 16-3 Front panel of the CMR2
CMR2
CMR2
STAT
LASER
RADIATION
DONOT VIEWDIRECTLY
WITHOPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
O
U
T
I
N
M
O
M
I
D
1
A
1
D
2
A
2

Indicator
The front panel of the CMR2 has one indicator as follows: board hardware status indicator
(STAT) two colors (red and green)
For the meanings of the status of the indicator, see 22 Indicators.
Interfaces
The front panel of the CMR2 has eight optical interfaces. Table 16-2 describes the types and
usage of the optical interfaces of the CMR2.
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Table 16-2 Optical interfaces of the CMR2
Interface Type of
Interface
Usage
A1A2 LC Receives the signals sent from the optical wavelength
converting board or centralized client-side equipment.
D1D2 LC Transmits signals to the optical wavelength converting board
or centralized client-side equipment.
IN LC Receives the multiplexed signals.
OUT LC Transmits the multiplexed signals.
MO LC Works as a cascading output optical interface and is connected
to the input optical interface of an OADM board.
MI LC Works as a cascading input optical interface and is connected
to the output optical interface of an OADM board.

16.1.6 Valid Slots
16.1.7 Feature Code
The feature code of the CMR2 contains eight characters, which indicate the wavelengths of the
two channels of optical signals processed by the CMR2.
Table 16-3 describes the feature code of the CMR2.
Table 16-3 Feature code of the CMR2
Feature Code Indication Description
First four characters Wavelength of optical
signals
Indicates the wavelength of
the first channel of optical
signals processed by the
CMR2.
Last four characters Wavelength of optical
signals
Indicates the wavelength of
the second channel of optical
signals processed by the
CMR2.

Consider the TN11CMR2 whose feature code is "14711571" as an example. The meaning of
the feature code of the TN11CMR2 is as follows:
l "1471" indicates that the wavelength of the first channel of optical signals is 1471 nm.
l "1571" indicates that the wavelength of the second channel of optical signals is 1571 nm.
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16.1.8 Technical Specifications
The technical specifications of the CMR2 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 16-4 lists the parameters specified for the optical interfaces of the CMR2.
Table 16-4 Parameters specified for the optical interfaces of the CMR2
Optical
Interface
Parameter Value
- Operating wavelength range
(nm)
1271 to 1611
- Channel spacing (nm) 20
IN-D1
IN-D2
0.5 dB passband bandwidth
(nm)
6.5
Insertion loss (dB) on the
drop channel
1.5
Adjacent channel isolation
(dB)
> 25
Non-adjacent channel
isolation (dB)
> 35
A1-OUT
A2-OUT
0.5 dB passband bandwidth
(nm)
6.5
Insertion loss (dB) on the add
channel
1.5
IN-MO
MI-OUT
Insertion loss (dB) 1.0
Isolation (dB) > 13
- Return loss (dB) > 40

Laser Safety Class
The safety class of the laser on the board is Class 1M. The maximum launched optical power of
the optical interfaces is within the range from 10 dBm (10 mW) to 22.15 dBm (164 mW).
Mechanical Specifications
The mechanical specifications of the CMR2 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.8
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Power Consumption
The power consumption of the CMR2 at room temperature (25C) is 0 W.
16.2 CMR4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11CMR4 (4-channel optical add/drop multiplexing board).
16.2.1 Version Description
The CMR4 is available in one functional version, namely, TN11.
16.2.2 Application
The CMR4 is mainly used to add/drop and multiplex four channels of wavelength signals to/
from the multiplexed signals.
16.2.3 Functions and Features
The CMR4 is applied to the CWDM system. The channel spacing is 20 nm. The CMR4 supports
the add/drop multiplexing function and channel expansion function.
16.2.4 Working Principle and Signal Flow
The CMR4 consists of the OADM module, communication and control module, and power
module.
16.2.5 Front Panel
The front panel of the CMR4 has indicators, interfaces, and a laser safety class label.
16.2.6 Valid Slots
16.2.7 Feature Code
The feature code of the CMR4 contains eight characters, which indicate the wavelengths of the
four channels of optical signals processed by the CMR4.
16.2.8 Technical Specifications
The technical specifications of the CMR4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
16.2.1 Version Description
The CMR4 is available in one functional version, namely, TN11.
16.2.2 Application
The CMR4 is mainly used to add/drop and multiplex four channels of wavelength signals to/
from the multiplexed signals.
Figure 16-4 shows the application of the CMR4 in the CWDM system.
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Figure 16-4 Application of the CMR4 in the CWDM system
CMR4 CMR4
Line
board
Line
board
Line
board
Line
board
Optical transmission
network
Remarks: The line board in this figure supports CWDM wavelength signals.

16.2.3 Functions and Features
The CMR4 is applied to the CWDM system. The channel spacing is 20 nm. The CMR4 supports
the add/drop multiplexing function and channel expansion function.
Table 16-5 provides the functions and features of the CMR4.
Table 16-5 Functions and features of the CMR4
Function and
Feature
CMR4
Basic functions Adds/Drops and multiplexes four signals to/from the multiplexed
signals.
Channel expansion Provides the interface to cascade another optical add/drop
multiplexing board to realize the expansion of the add/drop channel.

16.2.4 Working Principle and Signal Flow
The CMR4 consists of the OADM module, communication and control module, and power
module.
Figure 16-5 shows the functional block diagram of the CMR4.
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Figure 16-5 Functional block diagram of the CMR4
Communication and control module
OADM module
IN
D01 D03 A01 A04
Drop Add OUT
MO MI
SCC
DC/DC
converter
Power module
Delayed
startup
-48 V/-60 V
Fuse
-48 V/-60 V SCC
Backplane
D02 D04 A02 A03

OADM Module
The board receives one multiplexed optical signal that is sent by the upstream station on the IN
interface. Then, the drop optical module drops four wavelengths from the signal through optical
interfaces D01D04. The four dropped wavelengths are transmitted through the MO optical
interface.
The board receives one multiplexed signal that travels over the main optical path on the MI
optical interface. Then, the add optical module adds four wavelengths through optical interfaces
A01A04 and multiplexes them with the signal on the main optical path into one signal. This
multiplexed signal is transmitted through the OUT interface.
Communication and Control Module
l Controls the operations of the entire board.
l Collects the following information of each functional module of the board: alarms,
performance events, working status, and voltage detection.
l Communicates data with the SCC.
DC/DC Converter
It converts 48 V DC or 60 V DC into a voltage required by each module of the board.
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16.2.5 Front Panel
The front panel of the CMR4 has indicators, interfaces, and a laser safety class label.
Diagram of the Front Panel
Figure 16-6 shows the appearance of the front panel of the CMR4.
Figure 16-6 Front panel of the CMR4
CMR4
CMR4
STAT
LASER
RADIATION
DONOT VIEWDIRECTLY
WITHOPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
O
U
T
I
N
M
O
M
I
D
1
A
1
D
2
A
2
D
3
A
3
D
4
A
4

Indicators
The front panel of the CMR4 has one indicator as follows: board hardware status indicator
(STAT) two colors (red and green)
For the meanings of the status of the indicator, see 22 Indicators.
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Interfaces
The front panel of the CMR4 has 12 optical interfaces. Table 16-6 describes the types and usage
of the optical interfaces of the CMR4.
Table 16-6 Optical interfaces of the CMR4
Interface Type of
Interface
Usage
A1A4 LC Receives the signals sent from the optical wavelength
converting board or centralized client-side equipment.
D1D4 LC Transmits signals to the optical wavelength converting
board or centralized client-side equipment.
IN LC Receives the multiplexed signals.
OUT LC Transmits the multiplexed signals.
MO LC Works as a cascading output optical interface and is
connected to the input optical interface of an OADM
board.
MI LC Works as a cascading input optical interface and is
connected to the output optical interface of an OADM
board.

16.2.6 Valid Slots
16.2.7 Feature Code
The feature code of the CMR4 contains eight characters, which indicate the wavelengths of the
four channels of optical signals processed by the CMR4.
Table 16-7 describes the feature code of the CMR4.
Table 16-7 Feature code of the CMR4
Feature Code Indication Description
1st and 2nd characters Wavelength of optical
signals
The two characters are the
two middle characters of the
figure that indicates the
wavelength of the first
channel of optical signals
processed by the CMR4.
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Feature Code Indication Description
3rd and 4th characters Wavelength of optical
signals
The two characters are the
two middle characters of the
figure that indicates the
wavelength of the second
channel of optical signals
processed by the CMR4.
5th and 6th characters Wavelength of optical
signals
The two characters are the
two middle characters of the
figure that indicates the
wavelength of the third
channel of optical signals
processed by the CMR4.
7th and 8th characters Wavelength of optical
signals
The two characters are the
two middle characters of the
figure that indicates the
wavelength of the fourth
channel of optical signals
processed by the CMR4.

Consider the TN11CMR4 whose feature code is "47495961" as an example. The meaning of
the feature code of the TN11CMR4 is as follows:
l "47" indicates that the wavelength of the first channel of optical signals is 1471 nm.
l "49" indicates that the wavelength of the second channel of optical signals is 1491 nm.
l "59" indicates that the wavelength of the third channel of optical signals is 1591 nm.
l "61" indicates that the wavelength of the fourth channel of optical signals is 1611 nm.
16.2.8 Technical Specifications
The technical specifications of the CMR4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 16-8 lists the parameters specified for the optical interfaces of the CMR4.
Table 16-8 Parameters specified for the optical interfaces of the CMR4
Optical
Interface
Parameter Value
- Operating wavelength range
(nm)
1291 to 1611 (1371 nm excluded)
- Channel spacing (nm) 20
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Optical
Interface
Parameter Value
IN-D1
IN-D2
IN-D3
IN-D4
0.5 dB passband bandwidth
(nm)
6.5
Insertion loss (dB) on the
drop channel
2
Adjacent channel isolation
(dB)
> 25
Non-adjacent channel
isolation (dB)
> 35
A1-OUT
A2-OUT
A3-OUT
A4-OUT
0.5 dB passband bandwidth
(nm)
6.5
Insertion loss (dB) on the add
channel
2
IN-MO
MI-OUT
Insertion loss (dB) 1.5
Isolation (dB) > 13
- Return loss (dB) > 40

Laser Safety Class
The safety class of the laser on the board is Class 1M. The maximum launched optical power of
the optical interfaces is within the range from 10 dBm (10 mW) to 22.15 dBm (164 mW).
Mechanical Specifications
The mechanical specifications of the CMR4 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.9
Power Consumption
The power consumption of the CMR4 at room temperature (25C) is 0 W.
16.3 MR2
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11MR2 (2-channel optical add/drop multiplexing board).
16.3.1 Version Description
The MR2 is available in one functional version, namely, TN11.
16.3.2 Application
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The MR2 is mainly used to add/drop and multiplex two channels of wavelength signals to/from
the multiplexed signals.
16.3.3 Functions and Features
The MR2 is applied to the dense wavelength division multiplexing (DWDM) system. The
channel spacing is 0.8 nm. The MR2 supports the add/drop multiplexing function and channel
expansion function.
16.3.4 Working Principle and Signal Flow
The MR2 consists of the OADM module, communication and control module, and power
module.
16.3.5 Front Panel
The front panel of the MR2 has indicators, interfaces, and a laser safety class label.
16.3.6 Valid Slots
16.3.7 Feature Code
The feature code of the MR2 contains eight characters, which indicate the frequencies of the
two channels of optical signals processed by the MR2.
16.3.8 Technical Specifications
The technical specifications of the MR2 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
16.3.1 Version Description
The MR2 is available in one functional version, namely, TN11.
16.3.2 Application
The MR2 is mainly used to add/drop and multiplex two channels of wavelength signals to/from
the multiplexed signals.
Figure 16-7 shows the application of the MR2 in the DWDM system.
Figure 16-7 Application of the MR2 in the DWDM system
MR2 MR2
Remarks: The line board in this figure supports DWDM wavelength signals.
Line
board
Line
board
Line
board
Line
board
Optical transmission
network

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16.3.3 Functions and Features
The MR2 is applied to the dense wavelength division multiplexing (DWDM) system. The
channel spacing is 0.8 nm. The MR2 supports the add/drop multiplexing function and channel
expansion function.
Table 16-9 provides the functions and features of the MR2.
Table 16-9 Functions and features of the MR2
Function and
Feature
MR2
Basic functions Adds/Drops and multiplexes any two signals to/from the multiplexed
signals.
Channel expansion Provides the interface to cascade another optical add/drop
multiplexing board to realize the expansion of the add/drop channel.

16.3.4 Working Principle and Signal Flow
The MR2 consists of the OADM module, communication and control module, and power
module.
Figure 16-8 shows the functional block diagram of the MR2.
Figure 16-8 Functional block diagram of the MR2
OADM optical
module
IN
D1 D2 A1 A2
Drop optical
module
Add optical
module
OUT
MO MI
SCC
CPU Memory
Control
Communication
Control and communication module
Backplane
(controlled by SCC)
Power supply
module
DC power supply
from a backplane
Required
voltage
Fuse
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OADM Module
The board receives one multiplexed optical signal that is sent by the upstream station on the IN
interface. Then, the drop optical module drops two wavelengths from the signal through optical
interfaces D01 and D02. The two dropped wavelengths are transmitted through the MO optical
interface.
The board receives one multiplexed signal that travels over the main optical path on the MI
optical interface. Then, the add optical module adds two wavelengths through optical interfaces
A01 and A02 and multiplexes them with the signal on the main optical path into one signal. This
multiplexed signal is transmitted through the OUT interface.
Communication and Control Module
l Controls the operations of the entire board.
l Collects the following information of each functional module of the board: alarms,
performance events, working status, and voltage detection.
l Communicates data with the SCC.
DC/DC Converter
It converts 48 V DC or 60 V DC into a voltage required by each module of the board.
16.3.5 Front Panel
The front panel of the MR2 has indicators, interfaces, and a laser safety class label.
Diagram of the Front Panel
Figure 16-9 shows the appearance of the front panel of the MR2.
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16-17
Figure 16-9 Front panel of the MR2
MR2
MR2
STAT
O
U
T
I
N
LASER
RADIATION
DONOT VIEWDIRECTLY
WITHOPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
M
O
M
I
D
1
A
1
D
2
A
2

Indicators
The front panel of the MR2 has one indicator as follows: board hardware status indicator (STAT)
two colors (red and green)
For the meanings of the status of the indicator, see 22 Indicators.
Interfaces
The front panel of the MR2 has eight optical interfaces. Table 16-10 describes the types and
usage of the optical interfaces of the MR2.
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Table 16-10 Optical interfaces of the MR2
Interface Type of
Interface
Usage
A1A2 LC Receives the signals sent from the optical wavelength
converting board or centralized client-side equipment.
D1D2 LC Transmits signals to the optical wavelength converting
board or centralized client-side equipment.
IN LC Receives the multiplexed signals.
OUT LC Transmits the multiplexed signals.
MO LC Works as a cascading output optical interface and is
connected to the input optical interface of an OADM
board.
MI LC Works as a cascading input optical interface and is
connected to the output optical interface of an OADM
board.

16.3.6 Valid Slots
16.3.7 Feature Code
The feature code of the MR2 contains eight characters, which indicate the frequencies of the
two channels of optical signals processed by the MR2.
Table 16-11 describes the feature code of the MR2.
Table 16-11 Feature code of the MR2
Feature Code Indication Description
First four (14) characters Frequency of optical signals The four characters are the
last four characters of the
figure that indicates the
frequency of the first channel
of optical signals processed
by the MR2.
Last four (58) characters Frequency of optical signals The four characters are the
last four characters of the
figure that indicates the
frequency of the second
channel of optical signals
processed by the MR2.

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Consider the TN11MR2 whose feature code is "93609370" as an example. The meaning of the
feature code of the TN11MR2 is as follows:
l "9360" indicates that the frequency of the first channel of optical signals is 193.60 THz.
l "9370" indicates that the frequency of the second channel of optical signals is 193.70 THz.
16.3.8 Technical Specifications
The technical specifications of the MR2 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 16-12 lists the parameters specified for the optical interfaces of the MR2.
Table 16-12 Parameters specified for the optical interfaces of the MR2
Optical
Interface
Parameter Value
- Operating wavelength range
(nm)
1529 to 1561
- Channel spacing (GHz) 100
IN-D1
IN-D2
0.5 dB passband bandwidth
(nm)
0.11
Insertion loss (dB) on the
drop channel
1.5
Adjacent channel isolation
(dB)
> 25
Non-adjacent channel
isolation (dB)
> 35
A1-OUT
A2-OUT
0.5 dB passband bandwidth
(nm)
0.11
Insertion loss (dB) on the add
channel
1.5
IN-MO
MI-OUT
Insertion loss (dB) 1.0
Isolation (dB) > 13
- Return loss (dB) > 40

Laser Safety Class
The safety class of the laser on the board is Class 1M. The maximum launched optical power of
the optical interfaces is within the range from 10 dBm (10 mW) to 22.15 dBm (164 mW).
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Mechanical Specifications
The mechanical specifications of the MR2 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.9
Power Consumption
The power consumption of the MR2 at room temperature (25C) is 0 W.
16.4 MR2A
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the MR2A (2-channel optical add/drop multiplexing board).
16.4.1 Version Description
The MR2A is available in one functional version, namely, N1.
16.4.2 Application
The MR2A is mainly used to add/drop and multiplex two channels of wavelength signals to/
from the multiplexed signals.
16.4.3 Functions and Features
The MR2A is applied to the DWDM system. The channel spacing is 0.8 nm. The MR2A supports
the add/drop multiplexing function between any two adjacent wavelengths.
16.4.4 Working Principle and Signal Flow
The MR2A consists of the OADM module.
16.4.5 Front Panel
The front panel of the MR2A has interfaces and a laser safety class label.
16.4.6 Valid Slots
The slots valid for the MR2A vary with the cross-connect capacity and subrack of the equipment.
16.4.7 Technical Specifications
The technical specifications of the MR2A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
16.4.1 Version Description
The MR2A is available in one functional version, namely, N1.
16.4.2 Application
The MR2A is mainly used to add/drop and multiplex two channels of wavelength signals to/
from the multiplexed signals.
Figure 16-10 shows the application of the MR2A in the DWDM system.
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Figure 16-10 Application of the MR2A in the DWDM system
MR2A MR2A
Remarks: The line board in this figure supports DWDM wavelength signals.
Line
board
Line
board
Line
board
Line
board
Optical transmission
network

16.4.3 Functions and Features
The MR2A is applied to the DWDM system. The channel spacing is 0.8 nm. The MR2A supports
the add/drop multiplexing function between any two adjacent wavelengths.
Table 16-13 provides the functions and features of the MR2A.
Table 16-13 Functions and features of the MR2A
Function and
Feature
MR2A
Basic functions Adds/Drops any two adjacent standard wavelengths defined in ITU-
T G.692 (DWDM). The signals are transparently transmitted and the
operating wavelength ranges from 1535.82 nm to 1560.61 nm.
OTM function One MR2A board can work as a two-channel add/drop OTM station,
as shown in Figure 16-11. Two MR2A boards can be cascaded to
work as a four-channel add/drop OTM station, as shown in Figure
16-12.
OADM function Works as a two-channel add/drop OADM station when working with
the LWX. For details, see Figure 16-13.
Central wavelength Supports the standard wavelengths defined in ITU-T
Recommendations. The channel spacing is 100 GHz.

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Figure 16-11 One MR2A board working as a two-channel add/drop OTM station
MR2A
IN
OUT
MO
MI
D1 D2
A1 A2
Add
Drop

Figure 16-12 Two MR2A boards being cascaded to work as a four-channel add/drop OTM
station
MR2A
IN
OUT
MO
MI
D1 D2
A1 A2
Add
Drop
MR2A
IN
OUT
MO
MI
D1 D2
A1 A2
Add
Drop

Figure 16-13 MR2A and LWX working as a two-channel add/drop OADM station
In
Out
MI
MO
D1 A1
A2 D2
MR2A
LWX
LWX

16.4.4 Working Principle and Signal Flow
The MR2A consists of the OADM module.
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Figure 16-14 shows the functional block diagram of the MR2A.
Figure 16-14 Functional block diagram of the MR2A
OADM
module
IN
D01 D02 A01 A02
Drop Add OUT
MO MI

The MR2A contains the OADM module that adds, drops, and multiplexes two channels of
signals. In addition, the MR2A provides the interface to cascade another optical add/drop
multiplexing board to increase the add/drop capability. The MR2A is a passive board and does
not have an interface with the backplane.
OADM Module
The board receives one multiplexed optical signal that is sent by the upstream station on the IN
interface. Then, the drop optical module drops two wavelengths from the signal through optical
interfaces D01 and D02. The two dropped wavelengths are transmitted through the MO optical
interface.
The board receives one multiplexed signal that travels over the main optical path on the MI
optical interface. Then, the add optical module adds two wavelengths through optical interfaces
A01 and A02 and multiplexes them with the signal on the main optical path into one signal. This
multiplexed signal is transmitted through the OUT interface.
16.4.5 Front Panel
The front panel of the MR2A has interfaces and a laser safety class label.
Diagram of the Front Panel
Figure 16-15 shows the appearance of the front panel of the MR2A.
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Figure 16-15 Front panel of the MR2A
MR2A
MR2A
O
U
T
I
N
M
O
M
I
D
1
A
1
D
2
A
2
CLASS 1
LASER
PRODUCT

Interfaces
The front panel of the MR2A has four LC optical interfaces. Table 16-14 describes the types
and usage of the optical interfaces of the MR2A.
Table 16-14 Optical interfaces of the MR2A
Interface Type of
Interface
Usage
A01A02 LC Adds two wavelengths of signals from the local equipment.
D01D02 LC Drops two wavelengths of signals to the local equipment.
IN LC Receives the multiplexed signals of two wavelengths.
OUT LC Transmits the multiplexed signals of two wavelengths.
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Interface Type of
Interface
Usage
MO/MI LC Works as a cascading interface and cascades several MR2A
boards.

16.4.6 Valid Slots
The slots valid for the MR2A vary with the cross-connect capacity and subrack of the equipment.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the MR2A are as follows:
l When the cross-connect capacity is 200 Gbit/s, the MR2A can be installed in slots 18 and
1117 in the subrack.
16.4.7 Technical Specifications
The technical specifications of the MR2A include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 16-15 lists the parameters specified for the optical interfaces of the MR2A.
Table 16-15 Parameters specified for the optical interfaces of the MR2A
Parameter Value
Operating wavelength
range (nm)
The operating wavelength range is from 1535.82 nm to 1560.61
nm. The working wavelengths can be any two adjacent standard
wavelengths defined in ITU-T G.692 (DWDM).
Line code pattern NRZ
Channel spacing (GHz) 100
Insertion loss on the add
channel or drop channel
(dB)
< 2
Adjacent channel isolation
(dB)
> 25
Non-adjacent channel
isolation (dB)
> 35
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Parameter Value
-0.5 dB channel bandwidth
(nm)
< 0.11

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the MR2A are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the MR2A at room temperature (25C) is 0 W.
16.5 MR2C
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the MR2C (2-channel optical add/drop multiplexing board).
16.5.1 Version Description
The MR2C is available in one functional version, namely, N1.
16.5.2 Application
The MR2C is mainly used to add/drop and multiplex two channels of wavelength signals to/
from the multiplexed signals.
16.5.3 Functions and Features
The MR2C is applied to the DWDM system. The channel spacing is 0.8 nm. The MR2C supports
the add/drop multiplexing function between any two adjacent wavelengths.
16.5.4 Working Principle and Signal Flow
The MR2C consists of the OADM module.
16.5.5 Front Panel
The front panel of the MR2C has interfaces and a laser safety class label.
16.5.6 Valid Slots
The slots valid for the MR2C vary with the cross-connect capacity and subrack of the equipment.
16.5.7 Technical Specifications
The technical specifications of the MR2C include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
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16.5.1 Version Description
The MR2C is available in one functional version, namely, N1.
16.5.2 Application
The MR2C is mainly used to add/drop and multiplex two channels of wavelength signals to/
from the multiplexed signals.
Figure 16-16 shows the application of the MR2C in the DWDM system.
Figure 16-16 Application of the MR2C in the DWDM system
MR2C
Optical transmission
network MR2C
Remarks: The line board in this figure supports DWDM wavelength signals.
Line
board
Line
board
Line
board
Line
board

16.5.3 Functions and Features
The MR2C is applied to the DWDM system. The channel spacing is 0.8 nm. The MR2C supports
the add/drop multiplexing function between any two adjacent wavelengths.
Table 16-16 provides the functions and features of the MR2C.
Table 16-16 Functions and features of the MR2C
Function and
Feature
MR2C
Basic functions Adds/Drops any two adjacent standard wavelengths defined in
ITU-T G.692 (DWDM). The signals are transparently
transmitted and the operating wavelength ranges from 1535.82
nm to 1560.61 nm.
OTM function One MR2C board can work as a two-channel add/drop OTM
station, as shown in Figure 16-17. Two MR2C boards can be
cascaded to work as a four-channel add/drop OTM station, as
shown in Figure 16-18.
OADM function Works as a two-channel add/drop OADM station when working
with the LWX. For details, see Figure 16-19.
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Function and
Feature
MR2C
Central wavelength Supports the standard wavelengths defined in ITU-T
Recommendations. The channel spacing is 100 GHz.

Figure 16-17 One MR2C board working as a two-channel add/drop OTM station
MR2C
IN
OUT
MO
MI
D1 D2
A1 A2
Add
Drop

Figure 16-18 Two MR2C boards being cascaded to work as a four-channel add/drop OTM
station
MR2C
IN
OUT
MO
MI
D1 D2
A1 A2
Add
Drop
MR2C
IN
OUT
MO
MI
D1 D2
A1 A2
Add
Drop

Figure 16-19 MR2C and LWX working as a two-channel add/drop OADM station
In
Out
MI
MO
D1 A1
A2 D2
MR2C
LWX
LWX
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16-29

16.5.4 Working Principle and Signal Flow
The MR2C consists of the OADM module.
Figure 16-20 shows the functional block diagram of the MR2C.
Figure 16-20 Functional block diagram of the MR2C
OADM
module
IN
D01 D02 A01 A02
Drop Add OUT
MO MI

The MR2C contains the OADM module that adds, drops, and multiplexes two channels of
signals. In addition, the MR2C provides the interface to cascade another optical add/drop
multiplexing board to increase the add/drop capability. The MR2C is a passive board and does
not have an interface with the backplane.
OADM Module
The board receives one multiplexed optical signal that is sent by the upstream station on the IN
interface. Then, the drop optical module drops two wavelengths from the signal through optical
interfaces D01 and D02. The two dropped wavelengths are transmitted through the MO optical
interface.
The board receives one multiplexed signal that travels over the main optical path on the MI
optical interface. Then, the add optical module adds two wavelengths through optical interfaces
A01 and A02 and multiplexes them with the signal on the main optical path into one signal. This
multiplexed signal is transmitted through the OUT interface.
16.5.5 Front Panel
The front panel of the MR2C has interfaces and a laser safety class label.
Diagram of the Front Panel
Figure 16-21 shows the appearance of the front panel of the MR2C.
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Figure 16-21 Front panel of the MR2C
MR2C
MR2C
O
U
T
A
O
1
CLASS 1
LASER
PRODUCT
A
O
2
M
I
M
O
D
O
2
D
O
1
I
N

Interfaces
The front panel of the MR2C has four pairs of LC optical interfaces. Table 16-17 describes the
types and usage of the optical interfaces of the MR2C.
Table 16-17 Optical interfaces of the MR2C
Interface Type of
Interface
Usage
A01A02 LC Adds two wavelengths of signals from the local equipment.
D01D02 LC Drops two wavelengths of signals to the local equipment.
IN LC Receives the multiplexed signals of two wavelengths.
OUT LC Transmits the multiplexed signals of two wavelengths.
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16-31
Interface Type of
Interface
Usage
MO/MI LC Works as a cascading interface and cascades several MR2C
boards.

16.5.6 Valid Slots
The slots valid for the MR2C vary with the cross-connect capacity and subrack of the equipment.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the MR2C are as follows:
l When the cross-connect capacity is 200 Gbit/s, the MR2C can be installed in slots 1926
and 2936 in the subrack.
16.5.7 Technical Specifications
The technical specifications of the MR2C include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 16-18 lists the parameters specified for the optical interfaces of the MR2C.
Table 16-18 Parameters specified for the optical interfaces of the MR2C
Parameter Value
Operating wavelength
range (nm)
The operating wavelength range is from 1535.82 nm to 1560.61
nm. The working wavelengths can be any two adjacent standard
wavelengths defined in ITU-T G.692 (DWDM).
Line code pattern NRZ
Channel spacing (GHz) 100
Insertion loss on the add
channel or drop channel
(dB)
< 2
Adjacent channel isolation
(dB)
> 25
Non-adjacent channel
isolation (dB)
> 35
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Parameter Value
-0.5 dB channel bandwidth
(nm)
< 0.11

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the MR2C are as follows:
l Dimensions (mm): 22 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the MR2C at room temperature (25C) is 0 W.
16.6 MR4
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11MR4 (4-channel optical add/drop multiplexing board).
16.6.1 Version Description
The MR4 is available in one functional version, namely, TN11.
16.6.2 Application
The MR4 is mainly used to add/drop and multiplex four channels of wavelength signals to/from
the multiplexed signals.
16.6.3 Functions and Features
The MR4 is applied to the DWDM system. The channel spacing is 0.8 nm. The MR4 supports
the add/drop multiplexing function and channel expansion function.
16.6.4 Working Principle and Signal Flow
The MR4 consists of the OADM module, communication and control module, and power
module.
16.6.5 Front Panel
The front panel of the MR4 has indicators, interfaces, and a laser safety class label.
16.6.6 Valid Slots
16.6.7 Feature Code
The feature code of the MR4 contains eight characters, which indicate the frequencies of the
first channel and fourth channel of optical signals processed by the MR4.
16.6.8 Technical Specifications
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The technical specifications of the MR4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
16.6.1 Version Description
The MR4 is available in one functional version, namely, TN11.
16.6.2 Application
The MR4 is mainly used to add/drop and multiplex four channels of wavelength signals to/from
the multiplexed signals.
Figure 16-22 shows the application of the MR4 in the DWDM system.
Figure 16-22 Application of the MR4 in the DWDM system
MR4 MR4
Line
board
Line
board
Line
board
Line
board
Optical transmission
network
Remarks: The line board in this figure supports DWDM wavelength signals.

16.6.3 Functions and Features
The MR4 is applied to the DWDM system. The channel spacing is 0.8 nm. The MR4 supports
the add/drop multiplexing function and channel expansion function.
Table 16-19 provides the functions and features of the MR4.
Table 16-19 Functions and features of the MR4
Function and
Feature
MR4
Basic functions Adds/Drops and multiplexes four continuous signals to/from the
multiplexed signals.
Channel expansion Provides the interface to cascade another optical add/drop
multiplexing board to realize the expansion of the add/drop channel.

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16.6.4 Working Principle and Signal Flow
The MR4 consists of the OADM module, communication and control module, and power
module.
Figure 16-23 shows the functional block diagram of the MR4.
Figure 16-23 Functional block diagram of the MR4
Communication and control module
OADM module
IN
D01 D03 A01 A04
Drop Add OUT
MO MI
SCC
DC/DC
converter
Power module
Delayed
startup
-48 V/-60 V
Fuse
-48 V/-60 V SCC
Backplane
D02 D04 A02 A03

OADM Module
The board receives one multiplexed optical signal that is sent by the upstream station on the IN
interface. Then, the drop optical module drops four wavelengths from the signal through optical
interfaces D01D04. The four dropped wavelengths are transmitted through the MO optical
interface.
The board receives one multiplexed signal that travels over the main optical path on the MI
optical interface. Then, the add optical module adds four wavelengths through optical interfaces
A01A04 and multiplexes them with the signal on the main optical path into one signal. This
multiplexed signal is transmitted through the OUT interface.
Communication and Control Module
l Controls the operations of the entire board.
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l Collects the following information of each functional module of the board: alarms,
performance events, working status, and voltage detection.
l Communicates data with the SCC.
DC/DC Converter
It converts 48 V DC or 60 V DC into a voltage required by each module of the board.
16.6.5 Front Panel
The front panel of the MR4 has indicators, interfaces, and a laser safety class label.
Diagram of the Front Panel
Figure 16-24 shows the appearance of the front panel of the MR4.
Figure 16-24 Front panel of the MR4
MR4
MR4
STAT
O
U
T
I
N
LASER
RADIATION
DONOT VIEWDIRECTLY
WITHOPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
M
O
I
N
D
1
A
1
D
2
A
2
D
3
A
3
D
4
A
4

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Indicators
The front panel of the MR4 has one indicator as follows: board hardware status indicator (STAT)
two colors (red and green)
For the meanings of the status of the indicator, see 22 Indicators.
Interfaces
The front panel of the MR4 has 12 optical interfaces. Table 16-20 describes the types and usage
of the optical interfaces of the MR4.
Table 16-20 Optical interfaces of the MR4
Interface Type of
Interface
Usage
A1A4 LC Receives the signals sent from the optical wavelength
converting board or centralized client-side equipment.
D1D4 LC Transmits signals to the optical wavelength converting
board or centralized client-side equipment.
IN LC Receives the multiplexed signals.
OUT LC Transmits the multiplexed signals.
MO LC Works as a cascading output optical interface and is
connected to the input optical interface of an OADM
board.
MI LC Works as a cascading input optical interface and is
connected to the output optical interface of an OADM
board.

16.6.6 Valid Slots
16.6.7 Feature Code
The feature code of the MR4 contains eight characters, which indicate the frequencies of the
first channel and fourth channel of optical signals processed by the MR4.
Table 16-21 describes the feature code of the MR4.
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Table 16-21 Feature code of the MR4
Feature Code Indication Description
First four (14) characters Frequency of optical signals The four characters are the
last four characters of the
figure that indicates the
frequency of the first channel
of optical signals processed
by the MR4.
Last four (58) characters Frequency of optical signals The four characters are the
last four characters of the
figure that indicates the
frequency of the fourth
channel of optical signals
processed by the MR4.

Consider the TN11MR4 whose feature code is "92109240" as an example. The meaning of the
feature code of the TN11MR4 is as follows:
l "9210" indicates that the frequency of the first channel of optical signals is 192.10 THz.
l "9240" indicates that the frequency of the fourth channel of optical signals is 192.40 THz.
The four channels of optical signals processed by the MR4 are successive. Hence, we can infer
the following:
l The frequency of the second channel of optical signals is 192.20 THz.
l The frequency of the third channel of optical signals is 192.30 THz.
16.6.8 Technical Specifications
The technical specifications of the MR4 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 16-22 lists the parameters specified for the optical interfaces of the MR4.
Table 16-22 Parameters specified for the optical interfaces of the MR4
Optical Interface Parameter Value
- Operating wavelength range (nm) 1529 to 1561
- Channel spacing (GHz) 100
IN-D1
IN-D2
IN-D3
IN-D4
0.5 dB passband bandwidth (nm) 0.11
Insertion loss on the drop channel (dB) 2.2
Adjacent channel isolation (dB) > 25
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Optical Interface Parameter Value
Non-adjacent channel isolation (dB) > 35
A1-OUT
A2-OUT
A3-OUT
A4-OUT
0.5 dB passband bandwidth (nm) 0.11
Insertion loss on the add channel (dB) 2.2
IN-MO
MI-OUT
Insertion loss (dB) 1.5
Isolation (dB) > 13
- Return loss (dB) > 40

Laser Safety Class
The safety class of the laser on the board is Class 1M. The maximum launched optical power of
the optical interfaces is within the range from 10 dBm (10 mW) to 22.15 dBm (164 mW).
Mechanical Specifications
The mechanical specifications of the MR4 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.9
Power Consumption
The power consumption of the MR4 at room temperature (25C) is 0 W.
16.7 LWX
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the LWX (arbitrary bit rate wavelength conversion board).
16.7.1 Version Description
The LWX is available in one functional version, namely, N1.
16.7.2 Application
The LWX is a wavelength conversion board. The LWX converts a wavelength at an arbitrary
rate (10 Mbit/s to 2.7 Gbit/s) into a standard wavelength defined in ITU-T G.692, and performs
the reverse process.
16.7.3 Functions and Features
The LWX converts a wavelength at an arbitrary rate (10 Mbit/s to 2.7 Gbit/s, NRZ code) on the
client side into a standard wavelength defined in ITU-T G.692, and performs the reverse process.
16.7.4 Working Principle and Signal Flow
The LWX consists of the O/E converting module, cross-connect module, CDR module, logic
and control module, DC/DC converter, and other modules.
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16.7.5 Front Panel
The front panel of the LWX has indicators, interfaces, and a laser safety class label.
16.7.6 Valid Slots
The slots valid for the LWX vary with the cross-connect capacity and subrack of the equipment.
16.7.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the LWX indicates the scheme that the optical interfaces use to receive and
transmit signals.
16.7.8 Parameter Settings
You can set the parameters for the LWX by using the T2000.
16.7.9 Technical Specifications
The technical specifications of the LWX include the parameters specified for optical interfaces,
the safety class of the laser, mechanical specifications and power consumption.
16.7.1 Version Description
The LWX is available in one functional version, namely, N1.
16.7.2 Application
The LWX is a wavelength conversion board. The LWX converts a wavelength at an arbitrary
rate (10 Mbit/s to 2.7 Gbit/s) into a standard wavelength defined in ITU-T G.692, and performs
the reverse process.
Figure 16-25 shows the application of the LWX in the DWDM system.
Figure 16-25 Application of the LWX in the DWDM system
Client side WDM side
LWX LWX 10 Mbit/s-2.7 Gbit/s
M
u
l
t
i
p
l
e
x
i
n
g
G.692 G.692
WDM side Client side
D
e
m
u
l
t
i
p
l
e
x
-
i
n
g

16.7.3 Functions and Features
The LWX converts a wavelength at an arbitrary rate (10 Mbit/s to 2.7 Gbit/s, NRZ code) on the
client side into a standard wavelength defined in ITU-T G.692, and performs the reverse process.
The LWX supports the optical wavelength conversion, 3R function, protection, and loopback
function.
Table 16-23 provides the functions and features of the LWX.
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Table 16-23 Functions and features of the LWX
Function
and Feature
LWX
Basic
functions
Converts a wavelength on the client side into a standard wavelength defined
in ITU-T G.692 (DWDM), and performs the reverse process.
Transparently transmits signals.
3R function Provides the 3R function for the signals at a rate ranging from 10 Mbit/s to
2.7 Gbit/s on the client side, restores the clock, and monitors the rate.
Protection
schemes
Single fed and single
receiving
Supports the inter-board protection and 1+1 inter-
board hot standby protection. The protection
switching time is less than 50 ms.
Dual fed and
selective receiving
Supports the intra-board protection. One board can
realize the optical channel protection. The protection
switching time is less than 50 ms.
ALS function Supports the ALS function. When the LWX does not receive light, the LWX
automatically turns off the corresponding optical transmit module.
Loopback
function
Supports inloops and outloops at optical interfaces so that faults can be
located quickly.
Performance
and alarm
monitoring
Reports various alarms and performance events, which facilitates the
maintenance of the equipment.
Central
wavelength
Supports the standard wavelengths defined in ITU-T Recommendations. The
channel spacing is 100 GHz.

16.7.4 Working Principle and Signal Flow
The LWX consists of the O/E converting module, cross-connect module, CDR module, logic
and control module, DC/DC converter, and other modules.
Figure 16-26 shows the functional block diagram of the LWX.
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Figure 16-26 Functional block diagram of the LWX
-48 V/ -60 V
-48 V/ -60 V
LOS
Laser shutdown
SCC unit
Reference
clock
Multi-rate
CDR
Multi-rate
CDR
2x2 cross-
connection
Data
Reference clock
Loopback control
Loopback control
LOS
Laser
shutdown
LOS
Communication
and control
module
WDMside
loopback
Client side
loopback
Clock
Data
Optical module 2
on the WDM side
Optical module 1
Optical
splitter
Optical module on
the client side
O/E
+3.3 V backup
power
+3.3
V
DC/DC
converter
Fuse
Fuse
DC/DC
converter
10 Mbit/s to 2.7
Gbit/s
Communication
Communication
and control
module
10 Mbit/s to 2.7
Gbit/s
10 Mbit/s to 2.7
Gbit/s
2x2 cross-
connection
10 Mbit/s to 2.7
Gbit/s
on the WDM side
10 Mbit/s to 2.7
Gbit/s
E/O
O/E
E/O
O/E

O/E Converting Module
l The optical module on the client side applies SFP encapsulation and can be configured as
different types of optical modules. This module can access the optical signals at a rate
ranging from 10 Mbit/s to 2.7 Gbit/s.
l The optical module on the WDM side can be configured as an optical transceiver module,
or both an optical transceiver module and an optical receiver module. When two modules
are configured on the WDM side, an optical splitter is used to perform dual feeding.
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l In the receive direction, the module converts the received optical signals into electrical
signals.
l In the transmit direction, the module converts the electrical signals into SDH optical signals
and sends the SDH optical signals to fibers for transmission.
l Detects the R_LOS alarm and provides the function of shutting down the laser.
Cross-Connect Module
l Supports the data selection from the client side to the WDM side and the data selection
from the WDM side to the client side.
l Supports the selection of WDM-side optical modules.
l Supports the loopback of client-side signals.
l Supports the loopback of WDM-side signals.
CDR Module
l Restores the data and clock signals from the signals that are at a rate ranging from 10 Mbit/
s to 2.7 Gbit/s.
l Reads the rates of the accessed services.
Logic and Control Module
l Supports Ethernet communication.
l Supports the reference clock of the CDR module.
l Selects and configures the services of the other modules.
l Controls the laser.
l Selects the clock signal from the active and standby cross-connect boards.
l Controls the indicators on the board.
DC/DC Converter
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
16.7.5 Front Panel
The front panel of the LWX has indicators, interfaces, and a laser safety class label.
Diagram of the Front Panel
Figure 16-27 shows the appearance of the front panel of the LWX.
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Figure 16-27 Front panel of the LWX
LWX
LWX
ACT
PROG
STAT
SRV
CLASS 1
LASER
PRODUCT
T
X
R
X
O
U
T
1
I
N
1
O
U
T
2
I
N
2

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the LWX has six optical interfaces. Table 16-24 describes the types and usage
of the optical interfaces of the LWX.
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Table 16-24 Optical interfaces of the LWX
Interface Type of
Interface
Usage
IN1IN2 LC Receives the signals sent from the MR2A.
OUT1OUT2 LC Transmits signals to the MR2A.
TX LC Transmits signals to the client-side equipment.
RX LC Receives the signals sent from the client-side
equipment.

16.7.6 Valid Slots
The slots valid for the LWX vary with the cross-connect capacity and subrack of the equipment.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the LWX are as follows:
l When the cross-connect capacity is 200 Gbit/s, the LWX can be installed in slots 18 and
1117 in the subrack.
16.7.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the LWX indicates the scheme that the optical interfaces use to receive and
transmit signals.
Table 16-25 provides the relationship between the feature code of the LWX and the signal
receive/transmit scheme.
Table 16-25 Relationship between the feature code of the LWX and the signal receive/transmit
scheme
Board Feature Code Signal Receive/Transmit Scheme
SSN1LWX01 01 Single fed and single receiving
SSN1LWX02 02 Dual fed and selective receiving

16.7.8 Parameter Settings
You can set the parameters for the LWX by using the T2000.
You can set the following parameters for the LWX by using the T2000:
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l Path use status
l Optical interface loopback
l Service type
l Client service bearer rate (M)
l Laser status
l Automatic laser shutdown
l Current bearer rate (M)
l Actual wavelength No./wavelength (nm)/frequency (THz)
l Actual band type
l Configure wavelength No./wavelength (nm)/frequency (THz)
l Configure band type
l SD trigger condition
16.7.9 Technical Specifications
The technical specifications of the LWX include the parameters specified for optical interfaces,
the safety class of the laser, mechanical specifications and power consumption.
Parameters Specified for Optical Interfaces
Table 16-26 and Table 16-27 list the parameters specified for the client-side and WDM-side
optical interfaces of the LWX.
Table 16-26 Parameters specified for the client-side optical interfaces of the LWX
Parameter Value
Nominal bit rate 10 Mbit/s to 2.7 Gbit/s
Line code pattern NRZ
Type of fiber Single-mode LC Single-mode LC Single-mode LC
Transmission
distance (km)
15 40 80
Characteristics of the transmitter at point S
Operating
wavelength range
(nm)
1260 to 1360 1260 to 1360 1500 to 1580
Maximum mean
launched power
(dBm)
0 +3 +3
Minimum mean
launched power
(dBm)
-5 -2 -2
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Parameter Value
Minimum extinction
ratio (dB)
+8.2 +8.2 +8.2
Minimum side mode
suppression ratio
(dB)
30 30 30
Eye pattern mask Complies with the
mask defined in ITU-
T G.957.
Complies with the
mask defined in ITU-
T G.957.
Complies with the
mask defined in ITU-
T G.957.
Characteristics of the receiver at point S
Receiver type PIN APD APD
Receiver wavelength
range (nm)
1200 to 1600 1200 to 1600 1200 to 1600
Receiver sensitivity
(dBm)
-18 -27 -28
Minimum overload
(dBm)
0 -9 -9
Maximum
reflectance (dB)
-27 -27 -27

Table 16-27 Parameters specified for the WDM-side optical interfaces of the LWX
Parameter Value
Channel
spacing (GHz)
100
Line code
pattern
NRZ
Characteristics of the transmitter at point Sn
Transmission
distance (km)
640 170 (2 mW) 170 (10 mW) 360
Maximum mean
launched power
(dBm)
+3 +3 +7 +3
Minimum mean
launched power
(dBm)
-2 -2 5 -2
Minimum
extinction ratio
(dB)
+10 +10 +10 +10
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Parameter Value
Nominal central
frequency
(THz)
192.10 to
196.00
192.10 to
196.00
192.10 to
196.00
192.10 to
196.00
Central
frequency
deviation (GHz)
12.5 12.5 12.5 12.5
Maximum -20
dB spectral
width (nm)
0.2 0.4 0.4 0.4
Minimum side
mode
suppression
ratio (dB)
35 35 35 35
Dispersion
compensation
(ps/nm)
12800 3400 3400 7200
Eye pattern
mask
Complies with
the mask
defined in ITU-
T G.957.
Complies with
the mask
defined in ITU-
T G.957.
Complies with
the mask
defined in ITU-
T G.957.
Complies with
the mask
defined in ITU-
T G.957.
Characteristics of the receiver at point Rn
Receiver type APD PIN
Receiver
wavelength
range (nm)
1200 to 1600 1200 to 1600
Receiver
sensitivity
(dBm)
-28 -18
Minimum
overload (dBm)
-9 0
Maximum
reflectance (dB)
-27 -27

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the LWX are as follows:
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l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.1
Power Consumption
The maximum power consumption of the LWX at room temperature (25C) is 30 W.
16.8 FIB
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the FIB (filter isolating board).
16.8.1 Version Description
The FIB is available in one functional version, namely, N1.
16.8.2 Application
The FIB is used in the remote optical pumping amplifier system. The FIB can realize long-
distance optical regeneration transmission when it works with the single-wavelength long-
distance board ROP.
16.8.3 Functions and Features
The FIB filters and isolates 1xSTM-16 optical signals.
16.8.4 Working Principle and Signal Flow
The FIB consists of an isolator and a filter.
16.8.5 Front Panel
The front panel of the FIB has one optical interface.
16.8.6 Valid Slots
The slots valid for the FIB vary with the cross-connect capacity and subrack of the equipment.
16.8.7 Technical Specifications
The technical specifications of the FIB include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.
16.8.1 Version Description
The FIB is available in one functional version, namely, N1.
16.8.2 Application
The FIB is used in the remote optical pumping amplifier system. The FIB can realize long-
distance optical regeneration transmission when it works with the single-wavelength long-
distance board ROP.
Figure 16-28 shows the position of the FIB in an optical transmission system.
Figure 16-28 Position of the FIB in an optical transmission system
G.652 fiber
ROP
Filter
1550.12
a (54 dB)
b (18 dB)
BA17
C (single span)
ISO
->
Optical
transmitter
Optical
receiver
Erbium
doped fiber
FIB
G.652 fiber
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16.8.3 Functions and Features
The FIB filters and isolates 1xSTM-16 optical signals.
Table 16-28 provides the functions and features of the FIB.
Table 16-28 Functions and features of the FIB
Function and
Feature
FIB
Optical isolator The isolator allows optical signals to pass in a single direction. The
operating wavelength ranges from 1529 nm to 1561 nm.
Optical filter The filter filters out the wavelengths other than the 1550.12 nm
wavelength.

16.8.4 Working Principle and Signal Flow
The FIB consists of an isolator and a filter.
Figure 16-29 shows the functional block diagram of the FIB.
Figure 16-29 Functional block diagram of the FIB
Isolator
Filter

Optical signals are heavily attenuated and degraded after they travel for a long distance in fibers.
The degraded signals cannot be normally received by an optical receiver. Hence, an ROP needs
to be used to amplify the gain of the optical signals. To prevent other factors from affecting the
ROP because the ROP has high optical power, the FIB needs to be used to filter wavelengths.
The isolator of the FIB allows the optical signals to pass in a single direction. The filter of the
FIB filters out the wavelengths other than the 1550.12 nm wavelength. As a result, the optical
receiver receives the optical signals normally.
16.8.5 Front Panel
The front panel of the FIB has one optical interface.
Diagram of the Front Panel
Figure 16-30 shows the appearance of the front panel of the FIB.
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Figure 16-30 Front panel of the FIB
FIB
FIB
CLASS 1
LASER
PRODUCT
O
U
T
I
N

Interfaces
The front panel of the FIB has one optical interface. The optical interface is used to receive and
transmit one channel of 2.5 Gbit/s optical signals. Table 16-29 describes the types and usage of
the optical interfaces of the FIB.
Table 16-29 Optical interfaces of the FIB
Interface Type of
Interface
Usage
IN LSH Receives one channel of 2.5 Gbit/s optical signals.
OUT LC Transmits one channel of 2.5 Gbit/s optical
signals.

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16.8.6 Valid Slots
The slots valid for the FIB vary with the cross-connect capacity and subrack of the equipment.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the FIB are as follows:
l When the cross-connect capacity is 200 Gbit/s, the FIB can be installed in slots 18 and
1117 in the main subrack.
16.8.7 Technical Specifications
The technical specifications of the FIB include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 16-30 lists the parameters specified for the optical interfaces of the FIB.
Table 16-30 Parameters specified for the optical interfaces of the FIB
Parameter Value
Nominal bit rate 2488320 kbit/s
Line code pattern NRZ
Central wavelength
(nm)
1550.120.05
-0.5 dB bandwidth
(nm)
> 0.4

Laser Safety Class
The safety class of the laser on the board is Class 1. The maximum launched optical power of
the optical interfaces is less than 10 dBm (10 mW).
Mechanical Specifications
The mechanical specifications of the FIB are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.4
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Power Consumption
The maximum power consumption of the FIB at room temperature (25C) is 0 W.
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17 Auxiliary Boards
About This Chapter
This topic describes the auxiliary boards including the AUX and FAN.
17.1 AUX
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the AUX (system auxiliary interface board).
17.2 FAN
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the FAN (fan board).
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17.1 AUX
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the AUX (system auxiliary interface board).
17.1.1 Version Description
The AUX is available in one functional version, namely, N1.
17.1.2 Application
The AUX is a system auxiliary interface board. The AUX can be used on the OptiX OSN
equipment series to provide various management interfaces and auxiliary interfaces.
17.1.3 Functions and Features
The AUX provides various management and auxiliary interfaces for the system, and provides
the centralized backup for the +3.3 V power supply of the boards in the subrack.
17.1.4 Working Principle and Signal Flow
The AUX consists of the communication module, interface module, and power module.
17.1.5 Jumpers
The jumper J9 is available in the lower right corner of the side panel of the AUX. The jumper
J9 is used to specify the subrack that works as the main subrack or extended subrack.
17.1.6 Front Panel
The front panel of the AUX has indicators and interfaces of various types.
17.1.7 Valid Slots
The AUX can be installed in slot 37 in the subrack.
17.1.8 Technical Specifications
The technical specifications of the AUX include the mechanical specifications and power
consumption.
17.1.1 Version Description
The AUX is available in one functional version, namely, N1.
17.1.2 Application
The AUX is a system auxiliary interface board. The AUX can be used on the OptiX OSN
equipment series to provide various management interfaces and auxiliary interfaces.
17.1.3 Functions and Features
The AUX provides various management and auxiliary interfaces for the system, and provides
the centralized backup for the +3.3 V power supply of the boards in the subrack.
Table 17-1 provides the functions and features of the AUX.
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Table 17-1 Functions and features of the AUX
Item AUX
Management
interface
l Provides the OAM interface, which supports the X.25 protocol.
l Provides the management serial interface F&f.
l Provides the 10M/100M NM interface.
Auxiliary interface l Provides the serial interfaces Serial 1Serial 4, which can function
as four broadcast data interfaces or two pairs of time interfaces.
The two functions of the interfaces are mutually exclusive.
l The two pairs of time interfaces work in full-duplex mode and
support synchronous time input and output of two channels.
l Both the time interface and the broadcast data interface support
the RS-422 level and RS-232 level.
l Provides one F1 interface for the 64 kbit/s codirectional data
channel.
External time
interface
l Supports the input and output of two channels of time signals, with
the external time transmitted in 1pps+TOD mode.
l For details about the external time input and output interfaces, see
Table 17-2 and Table 17-3.
Clock interface l Provides two BITS clock input interfaces and two BITS clock
output interfaces (impedance: 120 ohms).
l Provides two BITS clock input interfaces and two BITS clock
output interfaces (impedance: 75 ohms).
Alarm interface l Provides 16-input and 4-output alarm interfaces.
l Provides 4-output alarm cascading interfaces.
Cabinet alarm
indicator
l Provides four cabinet alarm indicator output interfaces.
l Provides four cabinet alarm indicator input cascading interfaces.
Orderwire interface l Provides two NNI connection signaling interfaces.
l Provides one orderwire phone interface.
l Provides two NNI voice interfaces.
Commissioning
interface
Provides one commissioning interface COM.
Internal
communication
Realizes communication between boards in the subrack.
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Item AUX
Power supply backup
and checking
l Monitors the two independent 48 V power supplies, detects the
overvoltage (72 V) and undervoltage (38.4 V) conditions, and
reports alarms to the SCC unit in the case of overvoltage or
undervoltage occurs.
l Provides the centralized backup for the +3.3 V power supply of
the boards in the subrack, which realizes the 1:N protection for
the secondary power supply of each board.
l Detects the overvoltage (+3.8 V) and undervoltage (+3.1 V)
conditions for the +3.3 V backup power supply.
Audible alarm Supports the audible alarm and the clearing of the audible alarm.
Ethernet port
connection status
checking
Supports the checking of the Ethernet port connection status.
Note: The COM interface is used for internal commissioning only. That is, the COM interface
cannot be used for equipment monitoring. Otherwise, the Ethernet communication between
boards may become abnormal.

Table 17-2 External time input interfaces
External Time Input
TOD-Related Interface
a
1pps-Related Interface
Channel 1 S1 S3 (using the RS422 level)
S1 ALMI4 (using the TTL level)
Channel 2 S2 S4 (using the RS422 level)
S2 ALMI4 (using the TTL level)
a: The TOD-related interfaces can use the RS232 level or RS422 level as required.

Table 17-3 External time input interfaces
External Time Output
TOD-Related Interface
a
1pps-Related Interface
Channel 1 S1 S3 (using the RS422 level)
Channel 2 S2 S4 (using the RS422 level)
a: The TOD-related interfaces can use the RS232 level or RS422 level as required.

17.1.4 Working Principle and Signal Flow
The AUX consists of the communication module, interface module, and power module.
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Figure 17-1 shows the functional block diagram of the AUX.
Figure 17-1 Functional block diagram of the AUX
Communication
module
Other units
ETH interface
SCC A
SCC B
SCC A
COM interface
19x100/10 Mbit/s
Ethernet bus
100/10 Mbit/s
100/10 Mbit/s
100/10 Mbit/s
100/10 Mbit/s
(VLAN A)
(VLAN B)
(VLAN A)
(VLAN A)
(VLAN B)
EXT interface 100/10 Mbit/s
(VLAN B)
Interface
module
F&f
S1~S4
One orderwire phone
interface
Four channels of subrack
indicator interface
Alarm cascading interface
OAM
Cross-connect
unit
SCC B
F1
+3.3 V backup
power supply
-48 V/-60 V
Backplane
Power supply
module
Two NNI voice interfaces
16-input and 4-output alarm interfaces
2-input and 2-output clock
interfaces

Communication Module
This module provides the network management interface for the active and standby GSCC
boards, OAM interface for remote maintenance, and interface for communication between
boards.
Interface Module
This module provides various auxiliary interfaces, including the F&f interface, OAM interface,
F1 interface, and clock input\output interface.
Power Module
This module provides the working power supply for the board and centralized +3.3 V backup
power supply for the other boards.
17.1.5 Jumpers
The jumper J9 is available in the lower right corner of the side panel of the AUX. The jumper
J9 is used to specify the subrack that works as the main subrack or extended subrack.
Figure 17-2 shows the position of the jumper J9 on the AUX.
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Figure 17-2 Position of the jumper J9 on the AUX
Power
Module
J9

Set the jumper J9 as follows:
l To enable the subrack to work as the main subrack, cap the jumper J9.
l To enable the subrack to work as the extended subrack, do not cap the jumper J9.
17.1.6 Front Panel
The front panel of the AUX has indicators and interfaces of various types.
Diagram of the Front Panel
Figure 17-3 shows the appearance of the front panel of the AUX.
17 Auxiliary Boards
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Figure 17-3 Front panel of the AUX
AUX
AUX
STAT
C
L
K
I
1
C
L
K
I
2
C
L
K
O
1
C
L
K
O
2
C
L
K
1
R
E
V
F
&
f
F
1
P
H
O
N
E
V
1
V
2
O
A
M
S
1
S
2
S
3
S
4
C
L
K
2
E
T
H
C
O
M
E
X
T
L
A
M
P
1
L
A
M
P
2
A
L
M
O
1
A
L
M
O
2
A
L
M
I
1
A
L
M
I
2
A
L
M
I
3
A
L
M
I
4

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Connection status indicator (LINK) one color (green)
l Data receiving and transmission indicator (ACT) one color (orange)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the AUX has 28 interfaces. Table 17-4 describes the types and usage of the
interfaces of the AUX.
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Table 17-4 Interfaces of the AUX
Interface Type of
Interface
Usage
CLKO1 SMB 75-ohm clock output interface 1
CLKO2 SMB 75-ohm clock output interface 2
CLK1 RJ-45 120-ohm clock interface 1
REV RJ-45 Reserved
F&f RJ-45 F&f interface
F1 RJ-45 F1 interface
PHONE RJ-45 Orderwire phone interface
V1 RJ-45 NNI voice interface 1
V2 RJ-45 NNI voice interface 2
OAM RJ-45 OAM interface
S1 RJ-45 Serial 1
S2 RJ-45 Serial 2
S3 RJ-45 Serial 3
S4 RJ-45 Serial 4
CLKI1 SMB 75-ohm clock input interface 1
CLKI2 SMB 75-ohm clock input interface 2
CLK2 RJ-45 120-ohm clock interface 2
ETH RJ-45 NM interface
COM RJ-45 Commissioning interface
EXT RJ-45 Interface for connection to the extended subrack
LAMP1 RJ-45 Cabinet alarm indicator output interface
LAMP2 RJ-45 Cabinet alarm indicator cascading input interface
ALMO1 RJ-45 Interface for the 1st to the 4th channels of alarm
outputs
ALMO2 RJ-45 Alarm signal cascading interface
ALMI1 RJ-45 Interface for the 1st to the 4th channels of alarm
inputs
ALMI2 RJ-45 Interface for the 5th to the 8th channels of alarm
inputs
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Interface Type of
Interface
Usage
ALMI3 RJ-45 Interface for the 9th to the 12th channels of alarm
inputs
ALMI4 RJ-45 Interface for the 13th to the 16th channels of alarm
inputs
Note: S1/S3 and S2/S4 form a pair of time input and output interfaces.

Table 17-5 describes the pins of the CLK1 and CLK2 interfaces.
Table 17-5 Pins of the CLK1 and CLK2 interfaces
Front View Pin Usage
8 7 6 5 4 3 2 1
1 Receiving ()
2 Receiving (+)
3 Grounding
4 Transmitting ()
5 Transmitting (+)
6 Grounding
7, 8 Unspecified

Table 17-6 describes the pins of the ETH, COM, EXT, and F1 interfaces.
Table 17-6 Pins of the ETH, COM, EXT, and F1 interfaces
Front View Pin Usage
8 7 6 5 4 3 2 1
1 Transmitting (+)
2 Transmitting ()
3 Receiving (+)
4 Unspecified
5 Unspecified
6 Receiving ()
7, 8 Unspecified

Table 17-7 describes the pins of the F&f interface.
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Table 17-7 Pins of the F&f interface
Front View Pin Usage
8 7 6 5 4 3 2 1
4 Receive end for RS-232 data
5 Grounding
8 Transmit end for RS-232 data
1, 2, 3, 6, 7 Unspecified

Table 17-8 describes the pins of the PHONE, V1, and V2 interfaces.
Table 17-8 Pins of the PHONE, V1, and V2 interfaces
Front View Pin Usage
8 7 6 5 4 3 2 1
4 Signal 1
5 Signal 2
1, 2, 3, 6, 7, 8 Unspecified

Table 17-9 describes the pins of the LAMP1 and LAMP2 interfaces.
Table 17-9 Pins of the LAMP1 and LAMP2 interfaces
Front View Pin Usage
8 7 6 5 4 3 2 1
1 Critical alarm signal (+)
2 Critical alarm signal ()
3 Major alarm signal (+)
4 Power indicator driving signal
(+)
5 Power indicator driving signal
()
6 Major alarm signal ()
7 Minor alarm signal (+)
8 Minor alarm signal ()

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Table 17-10 describes the pins of the ALM01 and ALM02 interfaces.
Table 17-10 Pins of the ALM01 and ALM02 interfaces
Front View Pin Usage
8 7 6 5 4 3 2 1
1 Critical and major alarm signal output
(+)
2 Critical and major alarm signal output
()
3 Minor and warning alarm signal output
(+)
4 Alarm signal output 1 (+)
5 Alarm signal output 1 ()
6 Minor and warning alarm signal output
()
7 Alarm signal output 1 (+)
8 Alarm signal output 1 ()

Table 17-11 describes the pins of the OAM interface.
Table 17-11 Pins of the OAM interface
Front View Pin Usage
8 7 6 5 4 3 2 1
1 Requests for transmission.
2 Transmits the DTE ready signal.
3 Transmits data.
4 Grounding
5 Grounding
6 Receives data.
7 Transmits the DCE ready signal.
8 Ready for receiving signals.

Table 17-12 describes the pins of the S1, S2, S3, and S4 interfaces.
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Table 17-12 Pins of the S1, S2, S3, and S4 interfaces of the AUX
Front View Pin Usage
8 7 6 5 4 3 2 1
1 RS-422 data transmitting (+)
2 RS-422 data transmitting ()
3 RS-422 data receiving (+)
4 Receive end for RS-232 data
5 Grounding
6 RS-422 data receiving ()
7 Unspecified
8 Transmit end for RS-232 data

Table 17-13 describes the pins of the ALMI1 interface.
Table 17-13 Pins of the ALMI1 interface
Front View Pin Usage
8 7 6 5 4 3 2 1
1 Alarm input 1
2 Ground for alarm input 1
3 Alarm input 2
4 Alarm input 3
5 Ground for alarm input 3
6 Ground for alarm input 2
7 Alarm input 4
8 Ground for alarm input 4

Table 17-14 lists the pins of the ALMI2 interface.
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Table 17-14 Pins of the ALMI2 interface
Front View Pin Usage
8 7 6 5 4 3 2 1
1 Alarm input 5
2 Ground for alarm input 5
3 Alarm input 6
4 Alarm input 7
5 Ground for alarm input 7
6 Ground for alarm input 6
7 Alarm input 8
8 Ground for alarm input 8

Table 17-15 describes the pins of the ALMI3 interface.
Table 17-15 Pins of the ALMI3 interface
Front View Pin Usage
8 7 6 5 4 3 2 1
1 Alarm input 9
2 Ground for alarm input 9
3 Alarm input 10
4 Alarm input 11
5 Ground for alarm input 11
6 Ground for alarm input 10
7 Alarm input 12
8 Ground for alarm input 12

Table 17-16 describes the pins of the ALMI4 interface.
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Table 17-16 Pins of the ALMI4 interface
Front View Pin Usage
8 7 6 5 4 3 2 1
1 Alarm input 13
2 Ground for alarm input 13
3 Alarm input 14
4 Alarm input 15
5 Ground for alarm input 15
6 Ground for alarm input 14
7 Alarm input 16
8 Ground for alarm input 16

Connections for Alarm Cascading
l Connections for alarm signal cascading
Figure 17-4 shows the connections when one or multiple cabinets input or output alarm signals.
Connect the alarm output interface to the alarm cascading interface of a lower level. Make the
connections one by one until the alarm output is connected to the centralized alarm system.
Figure 17-4 Connections for alarm input, alarm cascading, and alarm output
ALMO1
ALMO2
ALMI1
ALMO1
ALMO2
ALMI1
Subrack1
Cabinet1 Cabinet2
Centralized
alarm system
ALMO1
ALMO2
ALMI1
ALMO1
ALMO2
ALMI1
Subrack2
Subrack3
Subrack4

l Connections of cabinet alarm indicators
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Figure 17-5 shows the connections of the 4-channel cabinet alarm indicators. Connect LAMP1
of subrack 2 to LAMP2 of subrack 1. Finally, connect LAMP1 of subrack 1 to the indicator
interface at the top of the cabinet.
Figure 17-5 Connections of cabinet alarm indicators
subrack 1
Cabinet indicator
LAMP2
LAMP1
LAMP2
LAMP1
4 cabinet
alarm indicators
subrack 2

17.1.7 Valid Slots
The AUX can be installed in slot 37 in the subrack.
17.1.8 Technical Specifications
The technical specifications of the AUX include the mechanical specifications and power
consumption.
Mechanical Specifications
The mechanical specifications of the AUX are as follows:
l Dimensions (mm): 44 (W) x 110 (D) x 262.05 (H)
l Weight: 1.0 kg
l Dimensions (mm): 25.4 (W) x 220 x (D) x 111.8 (H)
l Weight: 1.0 kg
Power Consumption
At room temperature (25C), the maximum power consumption of the AUX is 19 W.
17.2 FAN
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the FAN (fan board).
17.2.1 Version Description
The FAN is available in one functional version, namely, N1.
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17.2.2 Application
The FAN is a system fan board. The FAN can be used on the OptiX OSN equipment series to
provide the heat dissipation function.
17.2.3 Functions and Features
The FAN adjusts the fan speed, checks the fan status, reports the fault of the fan control board,
and reports the off-position alarm of the fan.
17.2.4 Working Principle and Signal Flow
The FAN consists of the fan control unit and fan power supply unit.
17.2.5 Front Panel
The front panel of the FAN has indicators.
17.2.6 Valid Slots
The FAN can be installed in slots 3840 in the subrack.
17.2.7 Technical Specifications
The technical specifications of the FAN include the mechanical specifications, power
consumption, and working voltages.
17.2.1 Version Description
The FAN is available in one functional version, namely, N1.
The logical board of fan tray assembly XE1FAN is displayed as N1FAN on the T2000. The
XE1FAN is of the two-layer structure. The one-layer fan is no longer manufactured.
17.2.2 Application
The FAN is a system fan board. The FAN can be used on the OptiX OSN equipment series to
provide the heat dissipation function.
17.2.3 Functions and Features
The FAN adjusts the fan speed, checks the fan status, reports the fault of the fan control board,
and reports the off-position alarm of the fan.
Table 17-17 provides the functions and features of the FAN.
Table 17-17 Functions and features of the FAN
Function and
Feature
FAN
Function of
intelligent speed
adjustment
Provides the following functions of intelligent speed adjustment:
l Automatically adjusts the fan speed.
l Ensures that the fan operates at full speed when the speed
adjustment signal is abnormal.
l In normal situations, all the fan tray assemblies operate normally.
When one fan tray assembly reports an alarm, the other fan tray
assemblies adjust the fan speed to operate at full speed.
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Function and
Feature
FAN
Hot swapping
function
Provides the hot swapping function for the fan tray assembly.
Backup function Provides the mutual backup function for the power supplies of the
fans in the fan tray assemblies.
Status checking Supports the checking of the fan status.
Alarm function Reports the fan alarm and in-service information.
Fan backup The two fans in the fan tray assembly function as a backup for each
other. The two fans operate at the same time. When one fan is faulty,
the other fan adjust the speed to operate at full speed.

NOTE
l When one fan tray assembly of the three fan three assemblies fails, the system can work normally
for 96 hours at the ambient temperature ranging from 0C to 45C.
l The fan tray assembly must be replaced when one of the following situations occurs.
l One or more fans in each fan tray assembly of the three fan tray assemblies are faulty.
l Two fans in a fan tray assembly are faulty.
l When a fan tray assembly works normally, the upper fan and lower fan in the fan tray assembly
operate at the same speed.
17.2.4 Working Principle and Signal Flow
The FAN consists of the fan control unit and fan power supply unit.
Figure 17-6 shows the functional block diagram of the XE1FAN.
Figure 17-6 Functional block diagram of the XE1FAN
Fan control
unit
Fan power
supply
unit
Fan
Status signal
Speed adjusting signal
Status signal
Power
External power supply 1
Alarm signal
External power supply 2

Fan Power Supply Unit
This unit provides the driving voltage for the fan to operate.
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Fan Control Unit
The fan control unit controls the operation speed of the fan through the speed adjusting signal.
The fan control unit also detects its faults, faults in the fans, and faults in the fan power supply
unit. When detecting any fault, the fan control unit reports alarm information and the SCC then
issues commands to enable other fans to operate at full speed. The fan control unit also receives
commands from the SCC when the temperature is very low, and stops the fans. The fan control
unit detects the fault in the fan power supply unit, speed adjusting signal, fan state, and in-position
state of the FAN.
17.2.5 Front Panel
The front panel of the FAN has indicators.
Diagram of the Front Panel
The OptiX OSN equipment series use a modular fan platform.
One subrack uses three fan tray assemblies, as shown in Figure 17-7.
Figure 17-7 Modular fan tray assembly

Indicators
The indicator (STATE) on the front panel of the board indicates the running state of the hardware.
This indicator is red, green, or yellow when it is on.
For the meanings of the status of the indicator, see 22 Indicators.
17.2.6 Valid Slots
The FAN can be installed in slots 3840 in the subrack.
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17.2.7 Technical Specifications
The technical specifications of the FAN include the mechanical specifications, power
consumption, and working voltages.
Mechanical Specifications
The mechanical specifications of the FAN are as follows:
l Dimensions (mm): 120 (W) x 120 (D) x 50.8 (H)
l Weight of the XE1FAN: 1.5 kg
l Weight of the XE3FAN:1.2 kg
Power Consumption
At room temperature (25C), the maximum power consumption of each fan assembly of the
XE1FAN is 16 W when the input voltage is -48 V.
At room temperature (25C), the maximum power consumption of each fan assembly of the
XE3FAN is 16 W when the input voltage is -48 V.
Working Voltages
The working voltages of the FAN can be -48 V20% DC or -60 V20% DC.
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18 Optical Amplifier Boards and
Dispersion Compensation Boards
About This Chapter
This topic describes the optical amplifier boards such as the BA2, BPA, COA, OBU1, RPC01,
and RPC02, and the dispersion compensation boards such as the DCU.
18.1 BA2
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the BA2 (optical booster amplifier board).
18.2 BPA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the BPA (optical booster and pre-amplifier board).
18.3 COA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the COA (case-shaped optical amplifier).
18.4 RPC01
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the RPC01 (forward Raman driving board).
18.5 RPC02
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the RPC02 (backward Raman driving board).
18.6 OBU1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11OBU1 (optical booster amplifier board).
18.7 DCU
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the DCU (dispersion compensation board).
OptiX OSN 3500 Intelligent Optical Transmission System
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Boards
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18-1
18.1 BA2
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the BA2 (optical booster amplifier board).
18.1.1 Version Description
The BA2 is available in one functional version, namely, N1.
18.1.2 Application
The BA2 is a two-channel optical power amplifier board. The BA2 amplifies the power of optical
signals and is applicable to the long-distance optical fiber transmission.
18.1.3 Functions and Features
During the long-haul transmission of optical signals, the attenuation of the signals is high. Hence,
the BA is required to ensure that the optical receiver can receive normal optical signals.
18.1.4 Working Principle and Signal Flow
The BA2 consists of the EDFA module, control module, communication module, and DC/DC
converter module.
18.1.5 Front Panel
The front panel of the BA2 has indicators and interfaces.
18.1.6 Valid Slots
The slots valid for the BA2 vary with the cross-connect capacity and subrack of the OptiX OSN
equipment.
18.1.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the BA2 indicates the output optical power of the optical interfaces.
18.1.8 Technical Specifications
The technical specifications of the BA2 include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.
18.1.1 Version Description
The BA2 is available in one functional version, namely, N1.
18.1.2 Application
The BA2 is a two-channel optical power amplifier board. The BA2 amplifies the power of optical
signals and is applicable to the long-distance optical fiber transmission.
Figure 18-1 shows the position of the BA in an optical transmission system.
Figure 18-1 Position of the BA in an optical transmission system
Tx Rx BA

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18.1.3 Functions and Features
During the long-haul transmission of optical signals, the attenuation of the signals is high. Hence,
the BA is required to ensure that the optical receiver can receive normal optical signals.
The BA2 amplifies the power of two-channel optical signals. Table 18-1 provides the functions
and features of the BA2.
Table 18-1 Functions and features of the BA2
Function and
Feature
BA2
Basic functions Increases the launched optical power of the line board to
1315 dBm or 1518 dBm. As a result, when the G.652
optical fiber with a loss of 0.275 dB/km is used, the
transmission distance can be 120 km, 130 km, or above.
Supporting the
EDFA
Supports the automatic control of the laser temperature and
optical power of the EDFA module.
Supports the automatic monitoring of the input and output
optical power of the EDFA module and query of the optical
power of the EDFA module.
Supports the protection function of the EDFA module.
When no optical signals are received, the laser is
automatically turned off. When optical signals are received,
the laser is automatically turned on.
Performance
events and alarms
monitoring
Supports the reporting of the performance parameters of the
laser. Reports various alarms and performance events,
which facilitates the management and maintenance of the
equipment.
Software upgrade Supports the software upgrade and expansion without
interrupting services.

CAUTION
The wavelength of the optical signal transmitted to the BA2 must be within the range from 1530
nm to 1560 nm. Otherwise, the input optical signal cannot be amplified correctly. Hence, make
sure that the output wavelength of the line board that is interconnected with the BA2 is within
the required range.
NOTE
The BA2 provides the intelligent power adjustment (IPA) function. When the IPA function is enabled and
no input signals are detected on the receive side of a line board, the pumping laser is turned off to prevent
high laser power from damaging the eyes.
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18.1.4 Working Principle and Signal Flow
The BA2 consists of the EDFA module, control module, communication module, and DC/DC
converter module.
Figure 18-2 shows the functional block diagram of the BA2.
Figure 18-2 Functional block diagram of the BA2
Fiber
distributor
Input
isolate
Doped
erbium
fiber WDM
coupler
Laser pump
Input
power
monitor
(Pin1)
Output
power
monitor
(Pin2)
Optical
splitter
Temperat
ure
Pump
current
detect
Pump
current
Filter
Pump
temperature
control
Laser
shutdown
Input
power
Output
power
LOS in
Manual
control
SCC unit
Communication
Optical
output
AD/DA
Control&Generation alarms
Optical
input
Output
isolate
Communication
module
EDFA module
Control module
+3.3 V
backup
power
+3.3 V
DC/DC
converter
Fuse
Fuse
DC/DC
converter
-48 V/ -60 V
-48 V/ -60 V
module
module

EDFA Module
The optical amplifier unit consists of two EDFA modules. One module is the BA and the other
module is the PA. When the board is used as a PA, an optical filter with 1550.12 nm as the
central wavelength is added to the optical output end of the module. A BA does not have the
filter. A semi-conductor laser bump with 980 nm as the central wavelength is in the erbium fiber
inside the EDFA module. Bump light and input signal light are coupled into the erbium fiber
through an optical coupler. The input and output optical signals of the module are led out by two
fiber splitters according to a specific coupling ratio. Then, the optical signals are converted into
optical current by two PIN photoelectrical diodes. The input and output power of the EDFA
module is determined according to the optical signals. The module also applies optical isolating
measures at the input and output ends to improve the performance of the module.
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Control Module
The control module performs the following functions:
l Detects and drives bump electricity.
l Controls the temperature of the bump laser.
l Detects the input and output power.
l Reports alarms.
The control module consists of the A/D converting unit, D/A converting unit, and CPU. The A/
D converting unit converts the temperature value of the cooling electricity and the input/output
optical power from analog values into digital values. The converted values are sent to the CPU,
which generates performance reporting events or alarms. The A/D converting unit also converts
bump electricity from analog values into digital values. The converted values are also sent to
the CPU. After the CPU processes the converted values, the D/A converting unit precisely
controls the driving analog circuit of the bump laser of the EDFA optical module. The internal
temperature of the bump laser module remains at 25. The temperature sensor inside the bump
laser outputs temperature change to drive the cooler to keep the internal temperature of the bump
laser module at 25.
Communication Module
The communication module supports Ethernet communication.
DC/DC Converter Module
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
18.1.5 Front Panel
The front panel of the BA2 has indicators and interfaces.
Diagram of the Front Panel
The BA2 is available in two types, namely, one-interface BA2 and two-interface BA2.
Figure 18-3 shows the appearance of the front panel of the one-interface BA2.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
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18-5
Figure 18-3 Front panel of the one-interface BA2
BA2
BA2
ACT
PROG
STAT
SRV
O
U
T
1
I
N
1
LASER
RADIATION
DONOT VIEWDIRECTLY
WITHOPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT

Figure 18-4 shows the appearance of the front panel of the two-interface BA2.
18 Optical Amplifier Boards and Dispersion Compensation
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Figure 18-4 Front panel of the two-interface BA2
BA2
BA2
ACT
PROG
STAT
SRV
O
U
T
1
I
N
1
O
U
T
2
I
N
2
LASER
RADIATION
DONOT VIEWDIRECTLY
WITHOPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT

Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the one-interface BA2 has one optical interface. The optical interface transmits
and receives one channel of optical signals. The one-interface BA2 uses the swappable optical
module, which facilitates the maintenance and upgrading of the optical module.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
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The front panel of the two-interface BA2 has two optical interfaces. The optical interfaces
transmit and receive two channels of optical signals. The two-interface BA2 uses the swappable
optical module, which facilitates the maintenance and upgrading of the optical module.
WARNING
If the front panel of the one-interface BA2 has two LC optical interfaces, only the upper optical
interface (IN1/OUT1) is valid. In the case of the BA2 whose front panel has two LC optical
interfaces, determine whether the BA2 is a one-interface BA2 or a two-interface BA2 according
to 18.1.7 Feature Code.
Table 18-2 describes the type and usage of the optical interface of the one-interface BA2.
Table 18-2 Optical interface of the one-interface BA2
Interface Type of
Interface
Usage
IN LC Receives one channel of optical signals.
OUT LC Transmits one channel of optical signals.

Table 18-3 describes the types and usage of the optical interfaces of the two-interface BA2.
Table 18-3 Optical interfaces of the two-interface BA2
Interface Type of Interface Usage
IN1 LC Receives the first channel of optical signals.
OUT1 LC Transmits the first channel of optical signals.
IN2 LC Receives the second channel of optical signals.
OUT2 LC Transmits the second channel of optical signals.

18.1.6 Valid Slots
The slots valid for the BA2 vary with the cross-connect capacity and subrack of the OptiX OSN
equipment.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the BA2 are as follows:
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l When the cross-connect capacity is 200 Gbit/s, the BA2 can be installed in slots 18 and
1117 in the subrack.
18.1.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the BA2 indicates the output optical power of the optical interfaces.
Table 18-4 provides the relationship between the feature code of the BA2 and the output optical
power.
Table 18-4 Relationship between the feature code of the BA2 and the output optical power
Board Feature Code Output Optical Power
SSN1BA201 01 Dual-channel optical power
amplification: 14 dBm
SSN1BA202 02 Dual-channel optical power
amplification: 17 dBm
SSN1BA203 03 Optical power amplification:
14 dBm
SSN1BA204 04 Optical power amplification:
17 dBm
SSN1BA205 05 Dual-channel optical power
amplification: 14 dBm and 17
dBm

18.1.8 Technical Specifications
The technical specifications of the BA2 include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 18-5 lists the parameters specified for the optical interfaces of the BA2.
Table 18-5 Parameters specified for the optical interfaces of the BA2
Parameter Value
Nominal bit rate 2488320 kbit/s and 9953280 kbit/s
Application code V-16.2, U-16.2, L-64.2, V-64.2, and U-64.2
Line code pattern NRZ
Input wavelength (nm) BA: 1530 to 1565
Input optical power
(dBm)
BA: -6 to +3
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Hardware Description
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Parameter Value
Output optical power
(dBm)
BA: 13 to 15 or 15 to 17
Noise figure (dB) BA: < 6.5

Mechanical Specifications
The mechanical specifications of the BA2 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.0
Power Consumption
The maximum power consumption of the BA2 at room temperature (25C) is 20 W.
18.2 BPA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the BPA (optical booster and pre-amplifier board).
18.2.1 Version Description
The BPA is available in two functional versions, namely, N1 and N2. The N1BPA is no longer
manufactured.
18.2.2 Application
The BPA is an optical booster and pre-amplifier board. The BPA provides a BA and a PA, which
are respectively used at the transmit end and receive end of the OptiX OSN equipment.
18.2.3 Functions and Features
During the long-haul transmission of optical signals, the attenuation of the signals is high. Hence,
the BA and PA are required to ensure that the optical receiver can receive normal optical signals.
18.2.4 Working Principle and Signal Flow
The BPA consists of the optical part, driving and detecting part, and data processing and
communication part.
18.2.5 Front Panel
The front panel of the BPA has indicators, interfaces, and a laser safety class label.
18.2.6 Valid Slots
The slots valid for the BPA vary with the cross-connect capacity and subrack of the OptiX OSN
equipment.
18.2.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the BPA indicates the output optical power of the optical interfaces.
18.2.8 Technical Specifications
The technical specifications of the BPA include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.
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18.2.1 Version Description
The BPA is available in two functional versions, namely, N1 and N2. The N1BPA is no longer
manufactured.
Table 18-6 describes the versions of the BPA.
Table 18-6 Versions of the BPA
Item Description
Functional Versions The BPA is available in two functional versions, namely, N1
and N2.
Differences The N1BPA consists of two EDFA optical modules, whereas
the N2BPA has only one EDFA optical module.
Substitution The two versions can substitute for each other when certain
conditions are met. If the ALS function is required and the
N2BPA is used to substitute for the N1BPA, enable the ALS
function on the N2BPA. If the ALS function is required and the
N1BPA is used to substitute for the N2BPA, enable the ALS
function on the line board. If the ALS function is not required,
this restriction is not applicable.

18.2.2 Application
The BPA is an optical booster and pre-amplifier board. The BPA provides a BA and a PA, which
are respectively used at the transmit end and receive end of the OptiX OSN equipment.
Figure 18-5 shows the position of the BA and PA in an optical transmission system.
Figure 18-5 Position of the BA and PA in an optical transmission system
Tx Rx PA
Tx Rx BA

18.2.3 Functions and Features
During the long-haul transmission of optical signals, the attenuation of the signals is high. Hence,
the BA and PA are required to ensure that the optical receiver can receive normal optical signals.
Table 18-7 provides the functions and features of the BPA.
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Hardware Description
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Table 18-7 Functions and features of the BPA
Function and
Feature
BPA
Basic functions Increases the launched optical power of the line board to 13
15 dBm or 1518 dBm. As a result, when the G.652 optical
fiber with a loss of 0.275 dB/km is used, the transmission
distance can be 120 km, 130 km, or above.
Pre-amplification
function
Provides the PA module to pre-amplify the received optical
signals. Increases the power of the small-volume optical
signals by 2225 dB (N1BPA) or 2233 dB (N2BPA) so that
the sensitivity of the receiver increases to 37 dBm.
Supporting the EDFA l Supports the automatic control of the laser temperature and
optical power of the EDFA module.
l Supports the automatic monitoring of the input and output
optical power of the EDFA module and query of the optical
power of the EDFA module.
l Supports the protection function of the EDFA module.
When no optical signals are received, the laser is
automatically turned off. When optical signals are received,
the laser is automatically turned on.
Performance events
and alarms
monitoring
Supports the reporting of the performance parameters of the
laser. Reports various alarms and performance events, which
facilitates the management and maintenance of the equipment.
Software upgrade Supports the software upgrade and expansion without
interrupting services.

18.2.4 Working Principle and Signal Flow
The BPA consists of the optical part, driving and detecting part, and data processing and
communication part.
Figure 18-6 shows the functional block diagram of the N1BPA.
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Figure 18-6 Functional block diagram of the N1BPA
EDFA optical module 2
A/Dor D/A conversion
Drive
module
Pump
current
check
Control
module
Communication
module
SCC
Data processing and
communication part
EDFA optical module 1
Drive
module
Pump current
check
Module
temperature
control
Input/output
power
check
Module
temperature
control
Input
power
check
Optical output
Optical input Optical input Optical output
Output
power
check
Fixed filter
Optical
part
Driving
and
detecting
part

Figure 18-7 shows the functional block diagram of the N2BPA.
Figure 18-7 Functional block diagram of the N2BPA
A/Dor D/A conversion
Drive
module
Pump
current
check
Control
module
Communication
module
SCC
Data processing and
communication part
EDFA optical module
Drive
module
Pump current
check
Module
temperature
control
Input/output
power
check
Module
temperature
control
Optical output
Optical input Optical input Optical output
Optical
part
Driving
and
detecting
part
Input/output
power
check

Optical Part
The N1BPA consists of two EDFA optical modules, whereas the N2BPA has only one EDFA
optical module. The EDFA optical module magnifies the optical power.
Driving and Detecting Part
The driving and detecting part provides the EDFA optical module with the driving current. It
also checks the working status of each part in the EDFA optical module. In addition, it predicts
and handles possible faults.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
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The driving and detecting part performs the following functions: checking the pump current,
driving the optical module, controlling the temperature of the optical module, and checking the
input and output optical power.
Data Processing and Communication Part
The data processing and communication part consists of the CPU and peripheral chips. The data
processing and communication part analyzes the test result of the tested circuit. Then, it adjusts
the driving circuit based on the analysis result so that the gain or output optical power of the
EDFA optical module remains in the range of the rated value. It also classifies the abnormal
states represented by the measured values and reports the abnormal states to the NMS.
18.2.5 Front Panel
The front panel of the BPA has indicators, interfaces, and a laser safety class label.
Diagram of the Front Panel
Figure 18-8 shows the appearance of the front panel of the BPA.
Figure 18-8 Front panel of the BPA
BPA
BPA
ACT
PROG
STAT
SRV
B
O
U
T
B
I
N
P
O
U
T
P
I
N
LASER
RADIATION
DONOT VIEWDIRECTLY
WITHOPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
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Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the BPA has two LC optical interfaces. Table 18-8 describes the types and
usage of the optical interfaces of the BPA.
Table 18-8 Optical interfaces of the BPA
Interface Type of
Interface
Usage
BIN LC Receives one channel of optical signals for
amplification.
BOUT LC Transmits one channel of amplified optical
signals.
PIN LC Receives one channel of optical signals for pre-
amplification.
POUT LC Transmits one channel of pre-amplified optical
signals.

18.2.6 Valid Slots
The slots valid for the BPA vary with the cross-connect capacity and subrack of the OptiX OSN
equipment.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the BPA are as follows:
l When the cross-connect capacity is 200 Gbit/s, the BPA can be installed in slots 18 and
1117 in the subrack.
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18.2.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the BPA indicates the output optical power of the optical interfaces.
Table 18-9 provides the relationship between the feature code of the BPA and the output optical
power.
Table 18-9 Relationship between the feature code of the BPA and the output optical power
Board Feature Code Description
SSN1BPA01 and
SSN2BPA01
01 The receiver sensitivity of the PA module
is 37 dBm.
The output optical power of the BA
module is 14 dBm.
SSN1BPA02 02 The receiver sensitivity of the PA module
is 37 dBm.
The output optical power of the BA
module is 17 dBm.

18.2.8 Technical Specifications
The technical specifications of the BPA include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 18-10 lists the parameters specified for the optical interfaces of the BPA.
Table 18-10 Parameters specified for the optical interfaces of the BPA
Parameter Value
Nominal bit rate 2488320 kbit/s or 9953280 kbit/s
Application code V-16.2, U-16.2, L-64.2, V-64.2, and U-64.2
Line code pattern NRZ
Input wavelength (nm) BA: 1530 to 1565
PA: 1550.12
Input optical power
(dBm)
BA: -6 to +3
PA: -28 to -10 (when the BPA works with the line board at the rate
of 10 Gbit/s)
PA: -38 to -10 (when the BPA works with the line board at the rate
less than 10 Gbit/s)
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Parameter Value
Output optical power
(dBm)
N1BPA: 13 to 15 or 15 to 17 (BA)
N2BPA: 13 to 15 (BA)
Sensitivity (dBm) PA: -37
Noise figure (dB) BA: < 6.5
PA: < 6

NOTE
When you perform a loopback on the PA module of the BPA, prevent the damage caused by high input
optical power to the optical module.
Mechanical Specifications
The mechanical specifications of the BPA are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight of the N1BPA (kg): 1.0
l Weight of the N2BPA (kg): 1.2
Power Consumption
The maximum power consumption of the N1BPA at room temperature (25C) is 20 W.
The maximum power consumption of the N2BPA at room temperature (25C) is 11 W.
18.3 COA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the COA (case-shaped optical amplifier).
18.3.1 Version Description
The COA is available in three functional versions, namely, 61, 62, and N1.
18.3.2 Application
The COA is a case-shaped optical amplifier that is not installed in a slot of the subrack. The
COA is mainly used to amplify optical signals and is applicable to the long-distance optical fiber
transmission.
18.3.3 Functions and Features
The COA integrates the optical amplifier module, the driving circuit, and the communication
circuit in an aluminium case.
18.3.4 Working Principle and Signal Flow
The 61COA and N1COA consist of the EDFA module, control module, communication module,
and DC/DC converter module.
18.3.5 Front Panel
The front panel of the COA has indicators and interfaces.
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18.3.6 Valid Slots
The COA adopts the case-shape design. Hence, the COA does not require a slot in the subrack.
18.3.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the 61COA indicates the output optical power of the optical interfaces.
18.3.8 Technical Specifications
The technical specifications of the COA include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.
18.3.1 Version Description
The COA is available in three functional versions, namely, 61, 62, and N1.
The working principle of the 62COA is basically the same as the working principle of the 61COA
or N1COA. The difference between the 62COA and the 61COA (N1COA) is with regard to the
used optical amplifier modules. The 62COA uses the Raman optical amplifier module, whereas
the 61COA and N1COA use the EDFA optical amplifier module.
NOTE
The COA that occurs in the following text includes the 61COA, N1COA, and 62COA. The characteristics
of the COA are the common characteristics of the three types of COAs.
Table 18-11 describes the versions of the COA.
Table 18-11 Versions of the COA
Item Description
Functional versions The COA is available in three functional versions, namely, 61, 62,
and N1.
Differences The 61COA is the EDFA optical amplifier in the 1550 nm fiber
communication window.
The N1COA is the EDFA optical amplifier in the 1530 nm to 1560
nm fiber communication window.
The N1COA does not have a filter and is a multi-wavelength
amplifier.
The 62COA uses the Raman optical amplifier module.
Substitution The versions cannot be substituted with each other.

18.3.2 Application
The COA is a case-shaped optical amplifier that is not installed in a slot of the subrack. The
COA is mainly used to amplify optical signals and is applicable to the long-distance optical fiber
transmission.
The application of the COA is the same as that of the BA and PA on the OptiX OSN equipment
series. For details, see Figure 18-5.
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18.3.3 Functions and Features
The COA integrates the optical amplifier module, the driving circuit, and the communication
circuit in an aluminium case.
The COA is an external and independent amplifier and does not occupy a slot in the subrack.
The COA can work independently. The equipment supports a maximum of two 61COAs, two
N1COAs, or one 62COA.
61COA and N1COA
The 61COA/N1COA is equipped with only one EDFA optical module. The 61COA/N1COA
can work as a power amplifier, a pre-amplifier, or a line amplifier. Figure 18-9 shows the
appearance of the 61COA/N1COA.
The optical characteristics of the 61COA/N1COA are the same as the optical characteristics of
the optical amplifier boards such as the BPA and BA2. The difference between the 61COA/
N1COA and the optical amplifier boards is that the 61COA/N1COA is an external optical
amplifier unit, which does not occupy a slot in the subrack. The 61COA/N1COA can be directly
installed in the ETSI cabinet but requires separate power supply.
Figure 18-9 Appearance of the 61COA/N1COA (PA)

The application of the 61COA/N1COA in the optical transmission system is the same as the
application of the BA2 and BPA in the optical transmission system. Table 18-12 provides the
functions and features of the 61COA/N1COA.
Table 18-12 Functions and features of the 61COA/N1COA
Function and
Feature
61COA/N1COA
Power
amplification
function
The 61COA increases the launched optical power of the line
board to 1315 dBm or 1517 dBm. As a result, the valid
transmission distance of optical signals is extended.
Pre-amplification
function
The N1COA provides the pre-amplification function. The
receiver sensitivity is 38 dBm.
ALS function Supports the ALS function.
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Function and
Feature
61COA/N1COA
Communication
through serial ports
Communicates with the GSCC through the RS-232 serial
port, reports the alarms and performance events of the COA
to the NMS, and receives the configuration commands
issued by the NMS.

62COA
The 62COA is a case-shaped Raman optical amplifier and is used at the receive end of the SDH
equipment.
The 62COA transmits counter-propagated pumping optical signals to fibers for distributed
Raman amplification. The gain medium of distributed Raman amplification is the line fiber that
can realize better noise performance. This is different from the 61COA. Hence, the 62COA can
extend the transmission distance, reduce the signal-to-noise ratio, and realize ultra long hop
transmission for a single span.
Figure 18-10 shows the appearance of the 62COA.
Figure 18-10 Appearance of the 62COA
5
1
2
3
4
1. Captive screw 2. Ejector lever 3. COA board
4. ESD jack 5. Power access board

The 62COA is a case-shaped Raman optical amplifier and is used at the receive end of the optical
transmission system. The optical signals are amplified during transmission based on the
stimulated Raman scattering effect of the fiber. The 62COA needs to work with the EDFA to
realize the transmission of optical signals for more than 170 km. For details, see Figure
18-11.
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Figure 18-11 Application of the 62COA
Transmitting end
EDFA
Pump light
Receiving end
Signal light
Laser
EDFA Pump light
Fiber
Raman amplifier
Coupler

The Raman amplifier amplifies optical signals during transmission by transmitting counter-
propagated pumping optical signals to fibers for distributed Raman amplification. As a result,
the phase of optical signals is significantly different from the phase of pump signals. The power
fluctuation of the Raman pumping is offset in the counter-propagation. Hence, the noise caused
by the pump can be effectively suppressed.
Table 18-13 provides the functions and features of the 62COA.
Table 18-13 Functions and features of the 62COA
Function and
Feature
62COA
Basic functions Is configured at the receive end of the SDH system, and
realizes extra long-haul transmission (more than 170 km)
when working with an EDFA whose output power is 17
dBm at the transmit end.
Pre-amplification
function
The 62COA provides the pre-amplification function. The
receiver sensitivity is 39 dBm.
ALS function Supports the ALS function.
Communication
through serial ports
Communicates with the GSCC through the RS-232 serial
port, reports the alarms and performance events of the COA
to the NMS, and receives the configuration commands
issued by the NMS.

18.3.4 Working Principle and Signal Flow
The 61COA and N1COA consist of the EDFA module, control module, communication module,
and DC/DC converter module.
The working principle of the N1COA is similar to the working principle of the 61COA. The
61COA has the filter unit, whereas the N1COA does not have the filter unit.
Figure 18-12 shows the functional block diagram of the 61COA/N1COA.
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Figure 18-12 Functional block diagram of the 61COA/N1COA
Optical part
Driving and
detecting part
EDFA optical
module
A/D or D/A conversion
Drive
module
Pump
power check
Module
temperature
control
Input/Output
Power check
Control
module
Communication
module
Fixed
filter
SCC
Optical input
Optical output
Data processing and
communication part
For pre-amplification

EDFA Module
The optical amplifier unit consists of two EDFA modules. One module is the BA and the other
module is the PA. When the board is used as a PA, an optical filter with 1550.12 nm as the
central wavelength is added to the optical output end of the module. A BA does not have the
filter. A semi-conductor laser bump with 980 nm as the central wavelength is in the erbium fiber
inside the EDFA module. Bump light and input signal light are coupled into the erbium fiber
through an optical coupler. The input and output optical signals of the module are led out by two
fiber splitters according to a specific coupling ratio. Then, the optical signals are converted into
optical current by two PIN photoelectrical diodes. The input and output power of the EDFA
module is determined according to the optical signals. The module also applies optical isolating
measures at the input and output ends to improve the performance of the module.
Control Module
The control module performs the following functions:
l Detects and drives bump electricity.
l Controls the temperature of the bump laser.
l Detects the input and output power.
l Reports alarms.
The control module consists of the A/D converting unit, D/A converting unit, and CPU. The A/
D converting unit converts the temperature value of the cooling electricity and the input/output
optical power from analog values into digital values. The converted values are sent to the CPU,
which generates performance reporting events or alarms. The A/D converting unit also converts
bump electricity from analog values into digital values. The converted values are also sent to
the CPU. After the CPU processes the converted values, the D/A converting unit precisely
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controls the driving analog circuit of the bump laser of the EDFA optical module. The internal
temperature of the bump laser module remains at 25. The temperature sensor inside the bump
laser outputs temperature change to drive the cooler to keep the internal temperature of the bump
laser module at 25.
Communication Module
The communication module supports Ethernet communication.
DC/DC Converter Module
It converts the 48/60 V power supply into the DC voltages that the modules of the board
require.
18.3.5 Front Panel
The front panel of the COA has indicators and interfaces.
Diagram of the Front Panel
Figure 18-13 shows the appearance of the front panel of the 61COA/N1COA.
Figure 18-13 Front panel of the 61COA/N1COA
1 2 3 4 5 6 7
8
9
10
11
1. ID DIP switch 2. Running indicator 3. Alarm indicator
5. RS-232-2 6. MONITOR-1
9. OUT: output optical interface 10. Power switch 11. -48 V power interface
4. RS-232-1
7. MONITOR-2 8. IN: input optical interface

Figure 18-14 shows the appearance of the front panel of the 62COA.
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Figure 18-14 Front panel of the 62COA
1. SC/PC optical interface (OUT) 2. LSH optical interface (IN) 3. Air filter
4. Fan board 5. RJ-45 interface
8. DIP switch (bits 8-5)
10. Power input interface 11. Power switch
6. RS-232-1
7. RS-232-2 9. DIP switch (bits 4-1)

Indicators
The front panel of the board has the following indicators:
l Board running status indicator (RUN) one color (green)
l Fan alarm indicator (ALM) one color (red)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the 61COA/N1COA has one SC/PC optical interface. The optical interface
receives and transmits one channel of optical signals. The input optical interface of the 62COA
is connected to the LSH flange and the output optical interface is connected to the SC flange.
Figure 18-15 shows the SC/PC fiber connector that the SC/PC optical interfaces of the 61COA
and N1COA use.
Figure 18-15 SC/PC fiber connector

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Figure 18-16 shows the flange and fiber connector that the input optical interface of the 62COA
uses.
Figure 18-16 LSH flange and fiber connector

NOTE
The protective cap of the LSH fiber jumper is specially designed. When you connect the LSH fiber jumper
to an LSH flange, do not remove the protective cap but insert the LSH fiber jumper into the LSH flange
directly.
The COA has two RS-232 serial ports, which function as the control and communication ports.
The serial ports communicate with the SCC unit and report alarms and performance events.
Table 18-14 provides the pin assignments of the RS-232 serial port.
Table 18-14 Pin assignments of the RS-232 serial port
Front View Pin of RS-232-1 Pin of RS-232-2 Definition
1
9
2 2 Used to receive
data.
3 3 Used to transmit
data.
5 5 Used for
common
grounding.

TIP
To realize the communication between the COA and the GSCC, use a serial port control line to connect
the RS-232-1 serial port of the COA to the F&f port of the subrack.
The RS-232-2 serial port is used in the scenario where several COAs are used at a single station.
To enable each COA to communicate with the SCC unit, use a serial port line to connect the
RS-232-2 port of COA 1 to the RS-232-1 port of COA 2, and use another serial port line to
connect the RS-232-2 port of COA 2 to the RS-232-1 port of COA 3. Connect the other COAs
similarly. In this case, each COA communicates with the SCC unit through the RS-232-1 serial
port of COA 1.
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NOTE
When you cascade COAs, set the last four digits of the DIP switch on the front panel of each COA to a
unique value. The values are used to identify the COAs. One OptiX OSN 3500 subrack supports a maximum
of two COAs.
The COA has two MONITOR interfaces. When the 61COA is used alone, the MONITOR-1
interface and MONITOR-2 interface are the alarm output interfaces. In this case, the two
MONITOR interfaces have the same functions. Table 18-15 provides the pin assignments of
the MONITOR interfaces.
Table 18-15 Pin assignments of the MONITOR interfaces
Front View Pin of
MONITOR-
1
Pin of
MONITOR-2
Definition
1
9
1 and 6 1 and 6 The input optical power of the
EDFA module is very low.
2 and 7 2 and 7 The working current of the pump
laser of the EDFA module
exceeds the threshold.
3 and 8 3 and 8 The cooling current of the pump
laser of the EDFA module
exceeds the threshold.
4 and 9 4 and 9 The ambient temperature of the
EDFA module exceeds the
threshold.
5 5 Digital ground

The 62COA has one RJ-45 connector, through which the 62COA is connected to the computer
for software loading. Table 18-16 provides the pin assignments of the RJ-45 connector of the
62COA.
Table 18-16 Pin assignments of the RJ-45 connector of the 62COA
Front View Pin Description
8 7 6 5 4 3 2 1
1 Transmitting (+)
2 Transmitting ()
3 Receiving (+)
4 Not defined
5 Not defined
6 Receiving ()
78 Not defined

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The COA has one 48 V power interface. The 48 V power interface accesses the 48 V power
provided by the PIU in the OptiX OSN 3500 subrack or the PDU at the top of the cabinet. The
working voltage under normal working conditions ranges from 38.4 V to 57.6 V (48 V20%).
The COA has one DIP switch.
l The DIP switches of the 61COA/N1COA are in the lower left corner of the front panel.
The DIP switches are used to set the ID of the 61COA/N1COA. When a bit of the DIP
switch is set upwards, the bit is in the OFF position. When the bit is set downwards, the bit
is in the ON position. The SCC identifies a 61COA/N1COA through the ID of the 61COA/
N1COA. The SCC communicates with the 61COAs/N1COAs whose IDs are different in
the master-slave calling mode.
l The DIP switch of the 62COA is used to set the ID of the 62COA and the type of fiber.
The DIP switch has eight bits. The bit on the leftmost side is numbered "8" and the bit on
the rightmost side is numbered "1". When a bit of the DIP switch is set upwards, the bit
indicates "0". When the bit is set downwards, the bit indicates "1". The first four bits (1
4) are used to set the board ID, which ranges from 20 to 35. In actual situations, the first
four bits indicate only the range from 20 to 27. The fifth bit is used to set the type of fiber.
When bit 5 indicates "0", the fiber is of the G.652 type. When bit 5 indicates "1", the fiber
is of the G.655 type.
18.3.6 Valid Slots
The COA adopts the case-shape design. Hence, the COA does not require a slot in the subrack.
In the ETSI cabinet, the 61COA or N1COA is installed on a special bracket, and the 62COA is
installed directly in the cabinet through the mounting ears. On the NMS, the logical slots of the
61COA, N1COA, and 62COA are slots 101 and 102.
Installation Position of the 61COA or N1COA
The installation of the 61COA is considered as an example. The bracket is fixed on the crossbars
on both sides of the cabinet. There are guide rails on the bracket. The 61COA is pushed onto
the bracket along the guide rails and is fixed on the bracket. One bracket can hold two 61COAs
horizontally. The front panels of the two 61COAs are on the front side of the cabinet, as shown
in Figure 18-17.
Figure 18-17 Position of the 61COA in the ETSI cabinet

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Installation Position of the 62COA
The case-shaped 62COA can be installed in the 300 mm or 600 mm ETSI cabinet through
mounting ears and screws. If the upward-wiring scheme is applied, the 62COA is installed at
the bottom of the ETSI cabinet (positions of the first and third floating nuts). If the downward-
wiring scheme is applied, the 62COA is installed in any idle place of the 2.6 m high cabinet or
in the ETSI cabinet that is not fully configured.
18.3.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the 61COA indicates the output optical power of the optical interfaces.
Table 18-17 provides the relationship between the feature code of the 61COA and the output
optical power.
Table 18-17 Relationship between the feature code of the 61COA and the output optical power
Board Feature Code Output Optical Power
SS61COA01 01 14 dBm
SS61COA02 02 17 dBm

18.3.8 Technical Specifications
The technical specifications of the COA include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 18-18 lists the parameters specified for the optical interfaces of the COA.
Table 18-18 Parameters specified for the optical interfaces of the COA
Parameter Value
61COA N1COA 62COA
Line code pattern NRZ
Operating wavelength
range (nm)
1550 1550.12
Input optical power
(dBm)
BA: -6 to +3
PA: -10 to -37
-10 to -37 -39 to -20 (2.5 Gbit/s signals
without the FEC function)
Output optical power
(dBm)
13 to 15 15 to 17 NA
Pump wavelength
(nm)
NA 1451.2
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Parameter Value
61COA N1COA 62COA
Maximum on/off gain
(dB)
NA > 15 (in the case of the G.652
fiber)
Noise figure (dB) NA < -1.5

Laser Safety Class
The safety class of the laser on the board is Class 1M. The maximum launched optical power of
the optical interfaces is within the range from 10 dBm (10 mW) to 22.15 dBm (164 mW).
Mechanical Specifications
The mechanical specifications of the 61COA and N1COA are as follows:
l Dimensions (mm): 240 (W) x 190 (D) x 50 (H)
l Weight (kg): 3.5
The mechanical specifications of the 62COA are as follows:
l Dimensions (mm): 294 (W) x 436 (D) x 86 (H)
l Weight (kg): 8.0
Power Consumption
The maximum power consumption of the 61COA at room temperature (25C) is 10 W.
The maximum power consumption of the 62COA at room temperature (25C) is 75 W.
The maximum power consumption of the N1COA at room temperature (25C) is 10 W.
18.4 RPC01
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the RPC01 (forward Raman driving board).
18.4.1 Version Description
The RPC01 is available in one functional version, namely, N1.
18.4.2 Application
The RPC01 is an external forward Raman driving board that must work with the EDFA.
18.4.3 Functions and Features
The RPC01 supports the online optical performance monitoring function and other functions.
18.4.4 Working Principle and Signal Flow
The RPC01 consists of the Raman pump optical module, driving and detecting module,
communication and control module, and power supply module.
18.4.5 Front Panel
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The front panel of the RPC01 has indicators, interfaces, and a laser safety class label.
18.4.6 Valid Slots
The RPC01 is an external forward Raman driving board. Hence, the RPC01 is not installed in
the subrack. The RPC01 is connected to the COM interface of an NE directly or though a hub
to realize the communication with the SCC. The logical slot of the RPC01 on the NMS is slot
104.
18.4.7 Jumpers and DIP Switches
The RPC01 has two groups of jumpers, namely, group J3 and group J4.
18.4.8 Feature Code
The feature code of the RPC01 contains three characters, which indicate the gain of the optical
signal processed by the RPC01.
18.4.9 Parameter Settings
You can set the parameters for the RPC01 by using the T2000.
18.4.10 Technical Specifications
The technical specifications of the RPC01 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
18.4.1 Version Description
The RPC01 is available in one functional version, namely, N1.
18.4.2 Application
The RPC01 is an external forward Raman driving board that must work with the EDFA.
Figure 18-18 shows the position of the RPC01 in an optical transmission system.
Figure 18-18 Position of the RPC01 in an optical transmission system
Transmitting Receiving
RPC01

18.4.3 Functions and Features
The RPC01 supports the online optical performance monitoring function and other functions.
Table 18-19 provides the functions and features of the RPC01.
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Table 18-19 Functions and features of the RPC01
Function and
Feature
RPC01
Basic functions l Generates multi-channel pump light of high power, which provides
energy for the amplification of signals in the fiber.
l Realizes the distributed online amplification of signals over long
distance with wide bandwidth and low noise.
Online optical
performance
monitoring function
Provides the online monitoring interface. A small amount of optical
signal can be transmitted to the spectrum analyzer through the
interface so that the spectrum and optical performance of the
multiplexed optical signal can be monitored without a service
interruption.
Performance events
and alarms
monitoring
Detects the pump optical power, temperature control current, pump
current, and back facet current.

18.4.4 Working Principle and Signal Flow
The RPC01 consists of the Raman pump optical module, driving and detecting module,
communication and control module, and power supply module.
The RPC01 is used at the transmit end of the system. The RPC01 utilizes the stimulated Raman
scattering effect of the fiber to amplify the optical signals during transmission.
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Figure 18-19 Functional block diagram of the RPC01 (forward pump)
SYS
SCC
PIN
Raman pump optical module
Splitter
Pump source
Signal light
Pump light
Signal light
CPU
MON
LINE
Driving and detecting module
Communication
Control
Memory
Communication and control module
Power supply
module
Fuse Voltages required
by the board
Backplane
(controlled by
the SCC)
DC power provided
by the backplane
Control the
pumping current
and temperature.
Detect the pump
light power and
current.
Detect the
temperature.

Signal Flow
The signal light is received at the SYS interface and transmitted to the optical line through the
LINE interface. A few supervisory signals are transmitted to the test instrument through the
MON interface for online optical performance monitoring. The pump light that is generated by
the RPC01 is transmitted to the optical line through the LINE interface in the same direction of
the signal light, to realize the distributed amplification of the optical signal. The Ethernet
interface of the RPC01 is connected to the COM interface of an NE directly or through a hub to
realize the communication with the SCC.
Functional Modules
l Raman pump optical module
The laser in the pump source module generates the pump light and sends the pump light
to the optical line for transmission. The Raman pump optical module utilizes the
stimulated Raman scattering effect of the fiber to amplify the optical signals during
transmission.
The splitter splits one channel of optical signals from the pump source module into two
channels of signals of different power. One channel of signals are transmitted through
the SYS interface to the main optical path. The other channel of signals are transmitted
to the MON interface for spectrum detection and supervising.
l Driving and detecting module
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Detects the optical power of the service signals in real time.
Detects the driving current, back facet current, cooling current, and operating
temperature of the pump inside the pump optical module in real time.
Drives the pump laser inside the pump optical module.
Reports alarms and performance events to the logic and control module.
l Communication and control module
Controls the operations on the board.
Controls the operations on each module of the board according to the CPU instructions.
Collects the alarms, performance events, working status, and voltage detection
information of each functional module of the board.
Communicates with the SCC.
l Power supply module
Converts the DC power provided by the backplane into the power required by each module
of the board.
18.4.5 Front Panel
The front panel of the RPC01 has indicators, interfaces, and a laser safety class label.
Diagram of the Front Panel
Figure 18-20 shows the appearance of the front panel of the RPC01.
Figure 18-20 Front panel of the RPC01
Board serial
number and name
Board manufacturing
information
SSN1RPC01 03793010860000002 Y
:
WARNING: FIBERS MUST
BE CONNECTED SEFORE
POWER UP
!
AVOID EYE OR SKIN
EXPOSURE TO DIRECT OR
CLASS 4 LASER
PRODUCT
SCATTERED RADIATION
LASER
RADIATION
ALM
CRPC
RUN
LINE SYS MON
RS232-1 RS232-2 LAN

Indicators
The front panel of the board has the following indicators:
l Board running status indicator (RUN) one color (green)
l Fan alarm indicator (ALM) one color (red)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the RPC01 has six interfaces. Table 18-20 describes the types and usage of
the interfaces of the RPC01.
Table 18-20 Interfaces of the RPC01
Interface Type of
Interface
Usage
LINE LSH/APC Transmits the amplified signals to the fibers.
SYS LC Is connected to the BA and receives the optical signals
transmitted from the BA.
NOTE
The permissible input power for the SYS interface on the
RPC01 board ranges from +5 dBm to +8 dBm. Therefore,
when the output power of a BA is +14 dBm or +17 dBm, you
need to add an optical attenuator ranging from 5 dB to 10 dB
in front of the SYS interface.
MON LC Monitors the optical performance.
The power of the MON interface is 1/99 of the power
of the SYS interface. That is, the power of the MON
interface is 20 dB less than the power of the SYS
interface.
LAN RJ-45 Is connected to the COM interface of an NE directly or
through a hub to realize the communication with the
SCC.
RS232-1/
RS232-2
- Is an RS-232 communication interface.

18.4.6 Valid Slots
The RPC01 is an external forward Raman driving board. Hence, the RPC01 is not installed in
the subrack. The RPC01 is connected to the COM interface of an NE directly or though a hub
to realize the communication with the SCC. The logical slot of the RPC01 on the NMS is slot
104.
18.4.7 Jumpers and DIP Switches
The RPC01 has two groups of jumpers, namely, group J3 and group J4.
Figure 18-21 shows the jumpers of the RPC01.
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Figure 18-21 Jumpers of the RPC01
CPU
J3 J4
12
9
1
0
9
1 2
1
0
RPC01

To ensure that the board can operate normally, set the jumpers as follows:
l Short-circuit jumpers 1 and 2 of group J4.
l Short-circuit jumpers 3 and 4 of group J4.
l Short-circuit jumpers 5 and 6 of group J4.
l Short-circuit jumpers 9 and 10 of group J3.
18.4.8 Feature Code
The feature code of the RPC01 contains three characters, which indicate the gain of the optical
signal processed by the RPC01.
Table 18-21 describes the feature code of the RPC01.
Table 18-21 Feature code of the RPC01
Feature Code Indication Description
The first character - Is always "G".
The second and third
characters
Gain Indicates the gain.

Consider the N1RPC01 whose feature code is "G10" as an example. "G10" indicates that the
gain of the optical signal is 10 dB.
18.4.9 Parameter Settings
You can set the parameters for the RPC01 by using the T2000.
You can set the following parameters for the RPC01 by using the T2000:
l Laser status
l Board work type
For the description of each parameter, see 25.9 Optical Amplifier Boards.
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Interface Display
Table 18-22 shows the serial numbers of the optical interfaces on the front panel of the RPC01
on the NMS.
Table 18-22 Serial numbers of the optical interfaces on the front panel of the RPC01 on the
NMS
Interface on the Front Panel Serial Number of the NMS Interface
LINE 1
SYS 2
MON 3

18.4.10 Technical Specifications
The technical specifications of the RPC01 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 18-23 lists the parameters specified for the optical interfaces of the RPC01.
Table 18-23 Parameters specified for the optical interfaces of the RPC01
Parameter Value
Pump wavelength (nm) 1400 to 1500
Operating wavelength (nm) 1529 to 1561
Maximum pump power (dBm) 29
Gain on the G.652 fiber (dB) 10
Gain on the LEAF fiber (dB) 12
Equivalent noise figure on the G.652 fiber (dB) 0
Equivalent noise figure on the LEAF fiber (dB) -1
Polarization dependent loss (dB) 0.5
Type of output connector LSH/APC or LC/PC

Laser Safety Class
The safety class of the laser on the board is Class 4. The maximum launched optical power of
the optical interfaces is more than 27 dBm (500 mW).
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Mechanical Specifications
l Dimensions (mm): 76.0 (W) x 218.5 (D) x 345.0 (H)
l Weight (kg): 4.0
Power Consumption
The maximum power consumption of the RPC01 at room temperature (25C) is 70 W.
The maximum power consumption of the RPC01 at room temperature (55C) is 121 W.
18.5 RPC02
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the RPC02 (backward Raman driving board).
18.5.1 Version Description
The RPC02 is available in one functional version, namely, N1.
18.5.2 Application
The RPC02 is an external backward Raman driving board that must work with the EDFA.
18.5.3 Functions and Features
The RPC02 supports the online optical performance monitoring function and other functions.
18.5.4 Working Principle and Signal Flow
The RPC02 consists of the Raman pump optical module, driving and detecting module,
communication and control module, and power supply module.
18.5.5 Front Panel
The front panel of the RPC02 has indicators, interfaces, and a laser safety class label.
18.5.6 Valid Slots
The RPC02 is an external backward Raman driving board. Hence, the RPC02 is not installed in
the subrack. The RPC02 is connected to the COM interface of an NE directly or though a hub
to realize the communication with the SCC. The logical slot of the RPC02 on the NMS is slot
105.
18.5.7 Jumpers and DIP Switches
The RPC02 has two groups of jumpers, namely, group J3 and group J4.
18.5.8 Feature Code
The feature code of the RPC02 contains three characters, which indicate the gain of the optical
signal processed by the RPC02.
18.5.9 Parameter Settings
You can set the parameters for the RPC02 by using the T2000.
18.5.10 Technical Specifications
The technical specifications of the RPC02 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
18.5.1 Version Description
The RPC02 is available in one functional version, namely, N1.
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18.5.2 Application
The RPC02 is an external backward Raman driving board that must work with the EDFA.
Figure 18-22 shows the position of the RPC02 in an optical transmission system.
Figure 18-22 Position of the RPC02 in an optical transmission system
Transmitting Receiving RPC02

18.5.3 Functions and Features
The RPC02 supports the online optical performance monitoring function and other functions.
Table 18-24 provides the functions and features of the RPC02.
Table 18-24 Functions and features of the RPC02
Function and
Feature
RPC02
Basic functions l Generates multi-channel pump light of high power, which provides
energy for the amplification of signals in the fiber.
l Realizes the distributed online amplification of signals over long
distance with wide bandwidth and low noise.
Online optical
performance
monitoring function
Provides the online monitoring interface. A small amount of optical
signal can be transmitted to the spectrum analyzer through the
interface so that the spectrum and optical performance of the
multiplexed optical signal can be monitored without a service
interruption.
Performance events
and alarms
monitoring
Detects the pump optical power, temperature control current, pump
current, and back facet current.

18.5.4 Working Principle and Signal Flow
The RPC02 consists of the Raman pump optical module, driving and detecting module,
communication and control module, and power supply module.
The RPC02 is used at the receive end of the system. The RPC02 utilizes the stimulated Raman
scattering effect of the fiber to amplify the optical signals during transmission. The pump light
travels in the reverse direction of the signal light. The RPC02 must work with the EDFA.
Figure 18-23 shows the functional block diagram of the RPC02.
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Figure 18-23 Functional block diagram of the RPC02 (backward pump)
SYS
SCC
PIN
Raman pump optical module
Splitter
Pump source
Signal light
Pump light
Signal light
CPU
MON
LINE
Driving and detecting module
Communication
Control
Memory
Communication and control module
Power supply
module
Fuse Voltages required
by the board
Backplane
(controlled by
the SCC)
DC power provided
by the backplane
Control the
pumping current
and temperature.
Detect the pump
light power and
current.
Detect the
temperature.
Signal Flow
The pump source of the RPC02 sends the pump light to the WDM side through the LINE optical
interface. On the line, the signals that are amplified through the distributed amplification are
received through the LINE interface. Then, the splitter splits the signals into two channels. The
service optical signals are transmitted through the SYS interface. A few supervisory signals are
transmitted to the test instrument through the MON interface for online optical performance
monitoring. The Ethernet interface of the RPC02 is connected to the COM interface of an NE
directly or through a hub to realize the communication with the SCC.
Functional Modules
l Raman pump optical module
The laser in the pump source module generates the pump light and sends the pump light
to the optical line for transmission. The Raman pump optical module utilizes the
stimulated Raman scattering effect of the fiber to amplify the optical signals during
transmission.
The splitter splits one channel of optical signals from the pump source module into two
channels of signals of different power. One channel of signals are transmitted through
the SYS interface to the main optical path. The other channel of signals are transmitted
to the MON interface for spectrum detection and supervising.
l Driving and detecting module
Detects the optical power of the service signals in real time.
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Detects the driving current, back facet current, cooling current, and operating
temperature of the pump inside the pump optical module in real time.
Drives the pump laser inside the pump optical module.
Reports alarms and performance events to the logic and control module.
l Communication and control module
Controls the operations on the board.
Controls the operations on each module of the board according to the CPU instructions.
Collects the alarms, performance events, working status, and voltage detection
information of each functional module of the board.
Communicates with the SCC.
l Power supply module
Converts the DC power provided by the backplane into the power required by each module
of the board.
18.5.5 Front Panel
The front panel of the RPC02 has indicators, interfaces, and a laser safety class label.
Diagram of the Front Panel
Figure 18-24 shows the appearance of the front panel of the RPC02.
Figure 18-24 Front panel of the RPC02
Board serial
number and name
Board manufacturing
information
SSN1 RPC02 03793010860000002 Y
:
WARNING: FIBERS MUST
BE CONNECTED SEFORE
POWER UP
!
AVOID EYE OR SKIN
EXPOSURE TO DIRECT OR
CLASS 4 LASER
PRODUCT
SCATTERED RADIATION
LASER
RADIATION
ALM
CRPC
RUN
LINE SYS MON
RS232-1 RS232-2 LAN

Indicators
The front panel of the board has the following indicators:
l Board running status indicator (RUN) one color (green)
l Fan alarm indicator (ALM) one color (red)
For the meanings of the status of the indicators, see 22 Indicators.
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Interfaces
The front panel of the RPC02 has six interfaces. Table 18-25 describes the types and usage of
the interfaces of the RPC02.
Table 18-25 Interfaces of the RPC02
Interface Type of
Interface
Usage
LINE LSH/APC Receives the optical signals transmitted from the line.
SYS LC Is connected to the BA and transmits the amplified
signals to the fibers.
MON LC Monitors the optical performance.
The power of the MON interface is 1/99 of the power
of the SYS interface. That is, the power of the MON
interface is 20 dB less than the power of the SYS
interface.
LAN RJ-45 Is connected to the COM interface of an NE directly or
through a hub to realize the communication with the
SCC.
RS232-1/
RS232-2
- Is an RS-232 communication interface.

18.5.6 Valid Slots
The RPC02 is an external backward Raman driving board. Hence, the RPC02 is not installed in
the subrack. The RPC02 is connected to the COM interface of an NE directly or though a hub
to realize the communication with the SCC. The logical slot of the RPC02 on the NMS is slot
105.
18.5.7 Jumpers and DIP Switches
The RPC02 has two groups of jumpers, namely, group J3 and group J4.
Figure 18-25 shows the jumpers of the RPC02.
Figure 18-25 Jumpers of the RPC02
CPU
J3 J4
12
9
1
0
9
1 2
1
0
RPC02
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To ensure that the board can operate normally, set the jumpers as follows:
l Short-circuit jumpers 1 and 2 of group J4.
l Short-circuit jumpers 3 and 4 of group J4.
l Short-circuit jumpers 5 and 6 of group J4.
l Do not short-circuit jumpers 9 and 10 of group J3.
18.5.8 Feature Code
The feature code of the RPC02 contains three characters, which indicate the gain of the optical
signal processed by the RPC02.
Table 18-26 describes the feature code of the RPC02.
Table 18-26 Feature code of the RPC02
Feature Code Indication Description
The first character - Is always "G".
The second and third
characters
Gain Indicates the gain.

Consider the N1RPC02 whose feature code is "G10" as an example. "G10" indicates that the
gain of the optical signal is 10 dB.
18.5.9 Parameter Settings
You can set the parameters for the RPC02 by using the T2000.
You can set the following parameters for the RPC02 by using the T2000:
l Laser status
l Board work type
For the description of each parameter, see 25.9 Optical Amplifier Boards.
Interface Display
Table 18-27 shows the serial numbers of the optical interfaces on the front panel of the RPC02
on the NMS.
Table 18-27 Serial numbers of the optical interfaces on the front panel of the RPC02 on the
NMS
Interface on the Front Panel Serial Number of the NMS Interface
LINE 1
SYS 2
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Interface on the Front Panel Serial Number of the NMS Interface
MON 3

18.5.10 Technical Specifications
The technical specifications of the RPC02 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 18-28 lists the parameters specified for the optical interfaces of the RPC02.
Table 18-28 Parameters specified for the optical interfaces of the RPC02
Parameter Value
Pump wavelength (nm) 1400 to 1500
Operating wavelength (nm) 1529 to 1561
Maximum pump power (dBm) 29.5
Gain on the G.652 fiber (dB) > 10
Gain on the LEAF fiber (dB) NA
Equivalent noise figure on the G.652 fiber (dB) NA
Equivalent noise figure on the LEAF fiber (dB) NA
Polarization dependent loss (dB) 0.5
Type of output connector LSH/APC or LC/PC

Laser Safety Class
The safety class of the laser on the board is Class 4. The maximum launched optical power of
the optical interfaces is more than 27 dBm (500 mW).
Mechanical Specifications
The mechanical specifications of the RPC02 are as follows:
l Dimensions (mm): 76.0 (W) x 218.5 (D) x 345.0 (H)
l Weight (kg): 4.2
Power Consumption
The maximum power consumption of the RPC02 at room temperature (25C) is 110 W.
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18.6 OBU1
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the TN11OBU1 (optical booster amplifier board).
18.6.1 Version Description
The OBU1 is available in one functional version, namely, TN11.
18.6.2 Application
The OBU1 is an optical booster amplifier board that amplifies optical signals.
18.6.3 Functions and Features
The OBU1 supports the online optical performance monitoring function, gain lock, transient
control, and other functions.
18.6.4 Working Principle and Signal Flow
The OBU1 consists of the EDFA optical module, driving and detecting module, communication
and control module, and power supply module.
18.6.5 Front Panel
The front panel of the OBU1 has indicators, interfaces, and a laser safety class label.
18.6.6 Valid Slots
18.6.7 Feature Code
The feature code of the OBU1 contains six characters, which indicate the gain and maximum
nominal input optical power of the optical signals processed by the OBU1.
18.6.8 Parameter Settings
You can set the parameters for the OBU1 by using the T2000.
18.6.9 Technical Specifications
The technical specifications of the OBU1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
18.6.1 Version Description
The OBU1 is available in one functional version, namely, TN11.
18.6.2 Application
The OBU1 is an optical booster amplifier board that amplifies optical signals.
The OBU1 is available in two types, namely, OBU101 and OBU102. The OBU101 is used at
the receive end and the OBU102 is used at the transmit end. Figure 18-26 shows the position
of the OBU1 in an optical transmission system.
Figure 18-26 Position of the OBU1 in an optical transmission system
Transmitting Receiving OBU102
Transmitting Receiving OBU101
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18.6.3 Functions and Features
The OBU1 supports the online optical performance monitoring function, gain lock, transient
control, and other functions.
Table 18-29 provides the functions and features of the OBU1.
Table 18-29 Functions and features of the OBU1
Function and
Feature
OBU1
Basic functions Amplifies a maximum of 40 channels of optical signals with the channel
spacing of 100 GHz at the same time.
Supports the system to transmit services over different fiber spans
without electrical regeneration.
Typical gain The typical gain of the OBU101 is 20 dB and the typical gain of the
OBU102 is 23 dB.
Online optical
performance
monitoring
function
Provides the online monitoring interface. A small amount of optical
signal can be transmitted to the spectrum analyzer through the interface
so that the spectrum and optical performance of the multiplexed optical
signal can be monitored without a service interruption.
Gain lock function The EDFA inside the board has the gain lock function. When one or
more channels are added or dropped, or optical signals of certain
channels fluctuate, the signal gain of other channels is not affected.
Transient control
function
The EDFA inside the board has the transient control function. When
channels are added or dropped, the board can suppress the fluctuation
of the optical power in the path to realize the smooth upgrading and
expansion.
Performance
events and alarms
monitoring
Checks and reports the optical power.
Controls the temperature of the pump laser.
Detects the pump driving current, back facet current, cooling current,
temperature of the pump laser, and ambient temperature of the board.

NOTE
The OBU1 is available in two types, namely, OBU101 and OBU102. The OBU101 is used at the receive
end and the OBU102 is used at the transmit end.
18.6.4 Working Principle and Signal Flow
The OBU1 consists of the EDFA optical module, driving and detecting module, communication
and control module, and power supply module.
Figure 18-27 shows the functional block diagram of the OBU1.
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Figure 18-27 Functional block diagram of the OBU1
OUT IN
Driving and detecting module
MON
PIN
EDFA optical module
Driving
current
Detect the pump
current and
temperature.
SCC
CPU Memory
Control
Communication
Communication and control module
Power supply
module
Fuse
Voltages required
by the board
DC power provided
by the backplane
Backplane
(controlled by the
SCC)
Splitter

Signal Flow
The OBU1 accesses the multiplexed optical signals, which are amplified by the EDFA optical
module. Then, the OBU1 sends the amplified optical signals to the splitter and transmits the
signals through the OUT interface. The OBU1 also sends a few supervisory signals to the test
instrument for online optical performance monitoring.
EDFA Optical Module
The EDFA optical module amplifies the input optical signals. The EDFA optical module adopts
the gain auto-adjustment technology. Hence, the gain of each operating wavelength signal can
remain in the allowed range.
Splitter
The splitter splits one channel of optical signals from the EDFA optical module into two channels
of signals of different power. One channel of signals are transmitted through the OUT interface
to the main optical path. The other channel of signals are transmitted to the MON interface for
spectrum detection and supervising.
The power of the MON interface is 1/99 of the power of the OUT interface. That is, the power
of the MON interface is 20 dB less than the power of the OUT interface.
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Communication and Control Module
The communication and control module controls and monitors the functional modules of the
board, and manages the communication.
The communication and control module collects the alarms, performance events, working status,
voltage detection information, and other information of each functional module of the board,
and reports the collected information to the SCC.
The communication and control module receives the commands issued by the SCC to control
and coordinate the operation of each functional module.
18.6.5 Front Panel
The front panel of the OBU1 has indicators, interfaces, and a laser safety class label.
Diagram of the Front Panel
Figure 18-28 shows the appearance of the front panel of the OBU1.
Figure 18-28 Front panel of the OBU1
OBU1
OBU1
M
O
N
O
U
T
I
N
STAT
ACT
PROG
SRV
LASER
RADIATION
DONOT VIEW DIRECTLY
WITHOPTICAL
INSTRUMENTS
CLASS 1MLASER
PRODUCT
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Indicators
The front panel of the board has the following indicators:
l Board hardware status indicator (STAT) two colors (red and green)
l Service activation status indicator (ACT) one color (green)
l Board software status indicator (PROG) two colors (red and green)
l Service alarm indicator (SRV) three colors (red, green, and yellow)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces
The front panel of the OBU1 has three optical interfaces. Table 18-30 describes the types and
usage of the optical interfaces of the OBU1.
Table 18-30 Optical interfaces of the OBU1
Interface Type of
Interface
Usage
IN LC Receives the multiplexed signals to be amplified.
OUT LC Transmits the amplified multiplexed signals.
MON LC Is connected to the test instrument to monitor the in-
service performance.

18.6.6 Valid Slots
18.6.7 Feature Code
The feature code of the OBU1 contains six characters, which indicate the gain and maximum
nominal input optical power of the optical signals processed by the OBU1.
Table 18-31 describes the feature code of the OBU1.
Table 18-31 Feature code of the OBU1
Feature Code Indication Description
The first character Is always "G".
The second and third
characters
Gain Indicates the gain.
The fourth character Is always "I".
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Feature Code Indication Description
The fifth and sixth characters Maximum nominal input
optical power
Indicates the maximum
nominal input optical power.

Consider the TN11OBU1 whose feature code is "G23I-3" as an example. "G23I-3" indicates
that the gain is 23 dB and the maximum nominal input optical power is 3 dBm.
18.6.8 Parameter Settings
You can set the parameters for the OBU1 by using the T2000.
You can set the following parameters for the OBU1 by using the T2000:
l Threshold of input power loss
l Laser status
l Gain
l Nominal gain upper threshold
l Nominal gain lower threshold
l Rated optical power
l Configure band
l Configure working band parity
l Actual band
l Actual working band parity
For the description of each parameter, see 25.9 Optical Amplifier Boards.
18.6.9 Technical Specifications
The technical specifications of the OBU1 include the parameters specified for optical interfaces,
laser safety class, mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 18-32 lists the parameters specified for the optical interfaces of the OBU1.
Table 18-32 Parameters specified for the optical interfaces of the OBU1
Parameter Value
OBU1C01 OBU1C02
Operating wavelength range (nm) 1529 to 1561 1529 to 1561
Nominal input optical power
(dBm)
-32 to -4 -32 to -3
Nominal output optical power
(dBm)
-12 to +16 -9 to +20
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Parameter Value
OBU1C01 OBU1C02
Input power (dBm) of a typical
single wavelength
-20 -19
Maximum nominal output optical
power (dBm) of a single
wavelength
0 4
Path gain (dB) 201.5 231.5
Noise figure (dB) 5.5 6.0
Gain flatness (dB) 2.0 2.0
Pre-incline of the gain spectral
form
00.2 1.00.2

Laser Safety Class
The safety class of the laser on the board is Class 1M. The maximum launched optical power of
the optical interfaces is within the range from 10 dBm (10 mW) to 22.15 dBm (164 mW).
Mechanical Specifications
The mechanical specifications of the OBU1 are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 1.3
Power Consumption
The maximum power consumption of the OBU101 at room temperature (25C) is 16 W.
The maximum power consumption of the OBU101 at high temperature (55C) is 18 W.
The maximum power consumption of the OBU102 at room temperature (25C) is 18 W.
The maximum power consumption of the OBU102 at high temperature (55C) is 20 W.
18.7 DCU
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the DCU (dispersion compensation board).
18.7.1 Version Description
The DCU is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to the insertion attenuation and compensation.
18.7.2 Application
The DCU is a dispersion compensation board. The DCU compensates for the dispersion that is
accumulated in the fiber during the transmission of the optical signals in the 10 Gbit/s system,
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and compresses optical signal pulse. In this manner, the optical signals that are transmitted can
be restored. In addition, the DCU can realize long-haul optical transmission when it works with
an optical amplifier board.
18.7.3 Functions and Features
The DCU can compensate for the dispersion for a maximum of 2xSTM-64 optical signals. The
DCU can be used with the BA and PA.
18.7.4 Working Principle and Signal Flow
The DCU consists of the dispersion compensation module.
18.7.5 Front Panel
The front panel of the DCU has interfaces, and a laser safety class label.
18.7.6 Valid Slots
The slots valid for the DCU vary with the cross-connect capacity and subrack of the OptiX OSN
equipment.
18.7.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the DCU indicates the compensated dispersion for the optical signals.
18.7.8 Technical Specifications
The technical specifications of the DCU include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.
18.7.1 Version Description
The DCU is available in two functional versions, namely, N1 and N2. The difference between
the two versions is with regard to the insertion attenuation and compensation.
Table 18-33 describes the versions of the DCU.
Table 18-33 Versions of the DCU
Item Description
Functional versions The DCU is available in two functional versions, namely, N1 and N2.
Commonness The working principle of the N1DCU is the same as the working
principle of the N2DCU.
Differences The insertion loss of the N2DCU is 3 to 5 dB less than the insertion
loss of the N1DCU.
In the case of the N1DCU, two compensation modes are available,
namely, 60 km and 80 km. In the case of the N2DCU, three
compensation modes are available, namely, 40 km, 60 km, and 80
km.
Substitution Use attenuators to prevent overloaded optical power when you use
the N2DCU to substitute for the N1DCU.

18.7.2 Application
The DCU is a dispersion compensation board. The DCU compensates for the dispersion that is
accumulated in the fiber during the transmission of the optical signals in the 10 Gbit/s system,
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and compresses optical signal pulse. In this manner, the optical signals that are transmitted can
be restored. In addition, the DCU can realize long-haul optical transmission when it works with
an optical amplifier board.
During the long-haul transmission (more than 80 km) of 10 Gbit/s signals, the pulse width of
the optical signals is expanded and the signals are severely distorted due to the impact of
dispersion. As a result, the optical signals cannot be normally received by the optical receiver.
Thus, the DCU is required to compensate for the dispersion. Figure 18-29 shows the position
of the DCU in an optical transmission system.
Figure 18-29 Position of the DCU in an optical transmission system
O
p
t
i
c
a
l
t
r
a
n
s
m
i
t
t
e
r
BA PA
DCU
1550.12 nm
1550.12 nm
Pulse broadening Pulse compression
O
p
t
i
c
a
l
r
e
c
e
i
v
e
r

NOTE
The operating wavelength of the chirp grating of the DCU is 1550.12 nm. Thus, the central wavelength of
the optical signals transmitted by the optical interface board on the opposite end must also be 1550.12 nm.
Otherwise, the dispersion of the optical signals cannot be compensated for and the insertion loss is high.
As a result, no optical signals can be transmitted.
18.7.3 Functions and Features
The DCU can compensate for the dispersion for a maximum of 2xSTM-64 optical signals. The
DCU can be used with the BA and PA.
Table 18-34 provides the functions and features of the DCU.
Table 18-34 Functions and features of the DCU
Function
and Feature
N1DCU N2DCU
Basic
functions
Compensates for the dispersion of a
maximum of two channels of optical
signals at the same time. Supports the
compensated dispersion of 1020 ps/
nm (for the dispersion caused by the
60 km G.652 optical fiber), 1360 ps/
nm (for the dispersion caused by the
80 km G.652 optical fiber), or any
combination.
Compensates for the dispersion of a
maximum of two channels of optical
signals at the same time. Supports the
compensated dispersion of 680 ps/
nm (for the dispersion caused by the
40 km G.652 optical fiber), 1020 ps/
nm (for the dispersion caused by the
60 km G.652 optical fiber), 1360 ps/
nm (for the dispersion caused by the
80 km G.652 optical fiber), or any
combination.
Dispersion
compensatio
n method
Compensates for the dispersion accumulated during the transmission by using
the chirp grating and suppresses the pulse signals to restore the optical signals.
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Function
and Feature
N1DCU N2DCU
Long haul
transmission
with optical
regeneration
Realizes long haul transmission with optical regeneration when working with
the BA and PA.

18.7.4 Working Principle and Signal Flow
The DCU consists of the dispersion compensation module.
Figure 18-30 shows the functional block diagram of the DCU.
Figure 18-30 Functional block diagram of the DCU
Dispersion compensation
module
IN OUT

The dispersion compensation module is used behind the PA to provide optical signals of required
compensation and path penalty.
18.7.5 Front Panel
The front panel of the DCU has interfaces, and a laser safety class label.
Diagram of the Front Panel
Figure 18-31 shows the appearance of the front panel of the one-interface DCU.
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18-53
Figure 18-31 Front panel of the one-interface DCU
DCU
DCU
CLASS 1
LASER
PRODUCT
O
U
T
I
N

Figure 18-32 shows the appearance of the front panel of the two-interface DCU.
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Figure 18-32 Front panel of the two-interface DCU
DCU
DCU
O
U
T
1
I
N
1
O
U
T
2
I
N
2
CLASS 1
LASER
PRODUCT

Interfaces
The front panel of the one-interface DCU has one optical interface. The optical interface
transmits and receives one channel of 10 Gbit/s optical signals.
The front panel of the two-interface DCU has two optical interfaces. The optical interfaces
transmit and receive two channels of 10 Gbit/s optical signals.
WARNING
If the front panel of the one-interface DCU has two LC optical interfaces, only the upper optical
interface (IN1/OUT1) is valid. In the case of the DCU whose front panel has two LC optical
interfaces, determine whether the DCU is a one-interface DCU or a two-interface DCU according
to 18.7.7 Feature Code.
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Table 18-35 describes the type and usage of the optical interface of the one-interface DCU.
Table 18-35 Optical interface of the one-interface DCU
Interface Type of
Interface
Usage
IN LC Receives one channel of optical signals.
OUT LC Transmits one channel of optical signals.

Table 18-36 describes the types and usage of the optical interfaces of the two-interface DCU.
Table 18-36 Optical interfaces of the two-interface DCU
Interface Type of
Interface
Usage
IN1 LC Receives the first channel of optical signals.
OUT1 LC Transmits the first channel of optical signals.
IN2 LC Receives the second channel of optical signals.
OUT2 LC Transmits the second channel of optical signals.

18.7.6 Valid Slots
The slots valid for the DCU vary with the cross-connect capacity and subrack of the OptiX OSN
equipment.
NOTE
The slots valid for a board are determined by the following factors:
l Slot bandwidth
l Cross-connect capacity
l Board version
The slots valid for the DCU are as follows:
l When the cross-connect capacity is 200 Gbit/s, the DCU can be installed in slots 18 and
1117 in the subrack.
18.7.7 Feature Code
The number code that follows the board name in the bar code is the feature code of the board.
The feature code of the DCU indicates the compensated dispersion for the optical signals.
Table 18-37 provides the relationship between the feature code of the DCU and the compensated
dispersion.
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Table 18-37 Relationship between the feature code of the DCU and the compensated dispersion
Board Feature Code Compensated Dispersion
SSN1DCU01 01 Compensated dispersion for a single channel: 60
km
SSN1DCU02 02 Compensated dispersion for a single channel: 80
km
SSN1DCU03 03 Compensated dispersion for dual channels: 60
km/60 km
SSN1DCU04 04 Compensated dispersion for dual channels: 80
km/80 km
SSN1DCU05 05 Compensated dispersion for dual channels: 60
km/80 km
SSN2DCU01 01 Compensated dispersion for a single channel: 40
km
SSN2DCU02 02 Compensated dispersion for a single channel: 60
km
SSN2DCU03 03 Compensated dispersion for a single channel: 80
km
SSN2DCU04 04 Compensated dispersion for dual channels: 40
km/40 km
SSN2DCU05 05 Compensated dispersion for dual channels: 60
km/60 km
SSN2DCU06 06 Compensated dispersion for dual channels: 80
km/80 km
SSN2DCU07 07 Compensated dispersion for dual channels: 40
km/60 km
SSN2DCU08 08 Compensated dispersion for dual channels: 40
km/80 km
SSN2DCU09 09 Compensated dispersion for dual channels: 60
km/80 km

18.7.8 Technical Specifications
The technical specifications of the DCU include the parameters specified for optical interfaces,
mechanical specifications, and power consumption.
Parameters Specified for Optical Interfaces
Table 18-38 lists the parameters specified for the optical interfaces of the DCU.
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Table 18-38 Parameters specified for the optical interfaces of the DCU
Parameter Value
Nominal bit rate 9953280 kbit/s
Line code pattern NRZ
Central wavelength
(nm)
1550.120.05
-0.5 dB bandwidth
(nm)
> 0.4
Compensated
dispersion (ps/nm)
680(40 km), 1020(60 km), and 1360(80 km)
Insertion loss (dB) Less than 8.3 dB in the case of the N1DCU and less than 3 dB in
the case of the N2DCU

Mechanical Specifications
The mechanical specifications of the DCU are as follows:
l Dimensions (mm): 25.4 (W) x 220 (D) x 262.05 (H)
l Weight (kg): 0.4
Power Consumption
The maximum power consumption of the DCU at room temperature (25C) is 0 W.
18 Optical Amplifier Boards and Dispersion Compensation
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19 Power Boards
About This Chapter
This topic describes the power boards such as the UPM (CAU), PIU and PIUA.
19.1 UPM
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the UPM (uninterruptible power module).
19.2 PIU
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PIU (power interface board).
19.3 PIUA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PIUA (power interface board).
19.4 PIUB
The PIUB board is the power interface unit between the DC power distribution box and each
board on the subrack. This section describes the versions, functions, working principle, front
panel, configuration, and technical specifications of the PIUB board.
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19.1 UPM
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the UPM (uninterruptible power module).
19.1.1 Version Description
None.
19.1.2 Application
The UPM is an external uninterruptible power module. The UPM can directly convert 110 V/
220 V AC mains power into -48 V DC power required by the transmission equipment. The UPM
is suitable for the telecom carriers who cannot provide -48 V DC power supply or requires
batteries.
19.1.3 Functions and Features
The UPM is a special power supply system and is numbered and EPS75-4815AF. The UPM can
directly convert 110 V/220 V AC power into 48 V DC power that the transmission equipment
requires. The UPM is suitable for the telecom carriers who cannot provide 48 V DC power for
the equipment.
19.1.4 Working Principle and Signal Flow
The UPM is fed by one 220 V AC mains power supply. The rectifier module converts the input
power into 48 V DC voltage to provide four DC branches and one battery branch.
19.1.5 Front Panel
The front panel of the UPM has indicators and interfaces of many types.
19.1.6 Valid Slots
The UPM is case shaped. Hence, the UPM does not occupy a slot in the subrack.
19.1.7 Technical Specifications
The technical specifications of the UPM include the power parameters and mechanical
specifications.
19.1.1 Version Description
None.
19.1.2 Application
The UPM is an external uninterruptible power module. The UPM can directly convert 110 V/
220 V AC mains power into -48 V DC power required by the transmission equipment. The UPM
is suitable for the telecom carriers who cannot provide -48 V DC power supply or requires
batteries.
Figure 19-1 shows the application of the UPM on the OptiX OSN equipment series.
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Figure 19-1 Application of the UPM on the OptiX OSN equipment series
Board A
Board B
-48 V
-48 V
Backplane
UPM
110 V/220 V
OptiX OSN equipment
PIU
PIU
-48 V

Table 19-1 shows different mapping policies of UPM.
Table 19-1 Mapping policies of UPM on the OptiX OSN 3500
Type of Subrack Label of Subrack Mapping PDU Mapping UPM
General OptiX OSN
3500 subrack
N1PDU N1PIU, N1PIUA EPS75-4815AF
Enhanced OptiX
OSN 3500 subrack
(1100 W)
N1PDU N1PIUA EPS75-4815AF
Enhanced OptiX
OSN 3500 subrack
(2300 W)
TN51PDU N1PIUB Not support

19.1.3 Functions and Features
The UPM is a special power supply system and is numbered and EPS75-4815AF. The UPM can
directly convert 110 V/220 V AC power into 48 V DC power that the transmission equipment
requires. The UPM is suitable for the telecom carriers who cannot provide 48 V DC power for
the equipment.
The output power of a single EPS75-4815AF power box is 1600 W. The power box is 3U high.
Figure 19-2 shows the appearance of the power box.
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Figure 19-2 Appearance of the EPS75-4815AF power box

The power box can be directly installed in the 19-inch cabinet or the ETSI cabinet.
The storage batteries of the UPM work with one EPS75-4815AF power box. When the external
AC power system supplies power normally, the batteries store power. When the 110 V/220 V
AC power supply is interrupted, the batteries can supply power for 3 to 4 hours. To supply power
to the OptiX OSN equipment, only one power box is required to be connected to the batteries.
The standard maximum configuration of each EPS75-4815AF power box includes five rectifier
modules and one monitoring module.
NOTE
The batteries do not belong to the EPS75-4815AF. Hence, the batteries need to be configured separately.
If the batteries are required, a battery cabinet is provided generally or a dedicated space in the equipment
cabinet is reserved for the batteries.
Table 19-2 provides the functions and features of the UPM.
Table 19-2 Functions and features of the EPS75-4815AF
Function and
Feature
EPS75-4815AF
Hot-swappable
function
The AC/DC rectifier module of the UPM is hot-swappable. When
you replace a faulty rectifier module, the other rectifier module can
still work normally. Therefore, the maintainability of the system is
improved.
Storage battery
protection function
The UPM provides the storage battery protection function. When the
mains supply is interrupted, the power system of the equipment
automatically switches to the storage battery, which ensures that the
equipment operates normally. The battery module provides a
capacity of 40 to 500 Ah. The default capacity is 65 Ah.
Loading capacity The loading capability of each rectifier module is 800 W.
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Function and
Feature
EPS75-4815AF
Lightning-proof
function
The rectifier module is embedded with the lightning-proof protector.
The rectifier module can bear the 1.2/50 us x 6 kV or 8/20 us x 3 kA
lightning surge. When the lightning current enters the rectifier
module along with the power cable, install category-C and category-
B light arresters before you connect the AC mains supply to the
power system to prevent the overvoltage caused by the direct
lightning strike from damaging the rectifier module.

19.1.4 Working Principle and Signal Flow
The UPM is fed by one 220 V AC mains power supply. The rectifier module converts the input
power into 48 V DC voltage to provide four DC branches and one battery branch.
When the UPM works normally, the monitoring module controls the rectifier module, storage
battery loop, and load loop, which work according to the preset parameters or user settings. The
monitoring module also monitors the status and data of the rectifier module, storage battery loop,
and load loop.
In the case of a mains supply failure, the equipment is fed by the storage battery group that is
connected to the UPM. The battery group must be connected to the UPM before the mains supply
fails. When the batteries start to discharge due to a mains supply failure, the monitoring module
reports the no-mains-supply alarm. With the discharge of the batteries, the battery voltage starts
to drop. When the battery voltage is lower than 45 V, the monitoring module reports the DC
undervoltage alarm. When the battery voltage reaches 43 V, the battery group enables the power-
off protection function to interrupt the connection between the battery group and the equipment.
As a result, the batteries are automatically protected.
When the mains supply is restored, the UPM resumes normal operations.
19.1.5 Front Panel
The front panel of the UPM has indicators and interfaces of many types.
Diagram of the Front Panel
shows the rear view of the GIE4805S (subject to the UPM on site).
Figure 19-3 shows the front view of the EPS75-4815AF (subject to the UPM on site).
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Figure 19-3 Front panel of the EPS75-4815AF
1 2 3 4 5 6
9 7 8 11 10
12
13 16 15
14
1. Control miniature circuit breaker
(MCB) of the AC input (30 A)
2. Control MCB of the battery
branch (80 A)
3. Control MCB of load 1 (10 A)
4. Control MCB of load 2 (30 A) 5. Control MCB of load 3 (40
A)
6. Control MCB of load 4 (40 A)
7. AC phase line terminal 8. AC zero line terminal 9. Negative 48 V terminal of the battery
branch
10. Negative 48 V terminal of the load
branch
11. Positive 48 V terminal of
the battery branch
12. Positive 48 V terminal of the load
branch
13. Connecting terminal of the
protection grounding cable
14. DB44 signal interface 15. Communication interface (COM)
16. Communication test interface
(TEST)

Indicators of the EPS75-4815AF
The front panel of each rectifier module has the following indicators:
l Running status indicator (RUN) one color (green)
l Alarm and protection indicator (ALM) one color (yellow)
l Faulty state indicator (FAULT) one color (red)
The front panel of the monitoring module has the following indicators:
l Power supply system fault indicator (ALM) one color (red)
l Power supply system status indicator (RUN) one color (green)
For the meanings of the status of the indicators, see 22 Indicators.
Interfaces of the EPS75-4815AF
The front panel of the EPS75-4815AF has seven interfaces. Table 19-3 describes the types and
usage of the interfaces of the EPS75-4815AF.
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Table 19-3 Interfaces of the EPS75-4815AF
Interface Type of Interface Usage
Power input
interface
Power interface "7" and "8" indicate the AC mains input
terminals, which access 110 V/220 V AC power.
Power output
interface
Power interface The power output interfaces are in the lower left
corner on the front panel of the UPM. The
terminals indicated by "9" and "11" form a
battery interface, through which the power box
is connected to the battery input socket at the
back of the storage battery box through a battery
cable. "10" and "12" indicate the output
interfaces of four loads. The output interfaces
can supply power to the OptiX OSN equipment
by using power cables.
Connecting
terminal of the
protection
grounding cable
Power interface The UPM is grounded through the cabinet.
DB44 signal
interface
DB44 The backplane of the subrack can be connected
to the sensor transfer box (an optional device)
through the DB44 signal interface and to the
monitoring module through the 96-pin DIN
connector. In addition, the sensor transfer box
can be connected to multiple sensors. As a
result, the monitoring function is extended.
Communication
interface (COM)
RJ-45 It is used for communication with the PC. The
COM interface can adopt the RS-485
communication mode or RS-232
communication mode. Three baud rates are
available, namely, 4800 kbit/s, 9600 kbit/s, and
19200 kbit/s. The baud rate can be adjusted and
the default baud rate is 9600 kbit/s.
Communication
test interface
(TEST)
RJ-45 It is used for internal test.
Switch button Button The switch buttons are on the left of the UPM,
as shown in Figure 19-3. "1" indicates the
control MCB of the AC input (30 A), which
enables and disables the input of the AC mains
supply. "2", "3", "4", and "5" indicate the load
control switches, which enable and disable the
load output.

19.1.6 Valid Slots
The UPM is case shaped. Hence, the UPM does not occupy a slot in the subrack.
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19.1.7 Technical Specifications
The technical specifications of the UPM include the power parameters and mechanical
specifications.
The equipment supports the 110 V/220 V power supply through an uninterrupted power modules
(UPM). The UPM is used to convert 110 V/220 V AC into -48 V DC, and to provide power
supply for the equipment.
A UPM consists of five power boxes and thus realizes the protected power supply. The output
power of each UPM is 5 x 800 W.
Power Parameters
Table 19-4 lists the power parameters of the UPM.
Table 19-4 Power parameters of the UPM
Parameter Value
Voltage range of
the AC input
90-290 V AC
AC input One single-phase three-wire system: 45-65 Hz
Rated input current 28 A
Output nominal
voltage
53.50.5 V
Rated output
current
DC output branches Load MCB 1: 10 A
Load MCB 2: 3 0A
Load MCB 3: 40 A
Load MCB 4: 40 A
Battery MCB: 80 A
Total output DC current 37.53 A to 753 A
Regulated voltage
precision
1%
Non-balance of
load sharing
5% (50%-100% load)
Rated efficiency of
the integrated
equipment
89%
Power factor 0.99 (nominal input or output)
Peak-to-peak noise
voltage
200mV (within the range of 20 MHz)
Electrical network
adjustment rate
0.1%
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Parameter Value
Lightning
protection
performance
When the UPM works alone, the input end can bear the simulated
lightning surge current whose waveform is 8/20s and amplitude is 5
kA for five times in both directions. The interval between two surges
must not be less than one minute. If the lightning surge current is higher
than the preceding indexes, the UPM may be damaged and cannot work
normally.
Cooling method The fan that is embedded in the rectifier module cools the module.

Mechanical Specifications
The mechanical specifications of the UPM are as follows:
l Dimensions of the UPM (mm): 436 (W) x 255 (D) x 133 (H)
l Weight: 15 kg
19.2 PIU
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PIU (power interface board).
19.2.1 Version Description
The PIU is available in one functional version, namely, N1. The N1PIU is no longer
manufactured.
19.2.2 Application
The PIU is a power interface board that is mainly used to access the power supply for the OptiX
OSN equipment.
19.2.3 Functions and Features
The PIU is used to access the power supply and to provide the lightning protection function and
filtering function.
19.2.4 Working Principle and Signal Flow
The PIU consists of the power access unit, filtering unit, and unit that detects the failure of the
lightning-proof unit.
19.2.5 Front Panel
The front panel of the PIU has power interfaces.
19.2.6 Valid Slots
The PIU can be installed in slots 27 and 28 in the subrack.
19.2.7 Technical Specifications
The technical specifications of the PIU include the mechanical specifications, power
consumption, input voltage, and fuse.
19.2.1 Version Description
The PIU is available in one functional version, namely, N1. The N1PIU is no longer
manufactured.
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19.2.2 Application
The PIU is a power interface board that is mainly used to access the power supply for the OptiX
OSN equipment.
Figure 19-4 shows the application of the PIU on the OptiX OSN equipment series.
Figure 19-4 Application of the PIU on the OptiX OSN equipment series
Board A
Board B
-48 V -48 V
Backplane
PIU
PIU
-48 V
-48 V
OptiX OSN equipment

19.2.3 Functions and Features
The PIU is used to access the power supply and to provide the lightning protection function and
filtering function.
Table 19-5 provides the functions and features of the PIU.
Table 19-5 Functions and features of the PIU
Function and
Feature
PIU
Lightning
protection function
Provides the lightning protection function and reports the alarm that
indicates the failure of the lightning protection function.
Filtering function Enhances the electromagnetic compatibility of the system by filtering
the power supply interface and shielding the structure of the board.
Power supply
interface
Provides two 50 W power interfaces for external devices such as the
COA.
Power supply of the
FAN
Provides the FAN with normal working voltages.
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Function and
Feature
PIU
Alarm monitoring Reports the board in-position alarm.
Power supply
backup
Supports the 1+1 hot backup. Any one PIU can supply power to the
entire subrack.

NOTE
One PIU can supply power to the entire subrack.
19.2.4 Working Principle and Signal Flow
The PIU consists of the power access unit, filtering unit, and unit that detects the failure of the
lightning-proof unit.
Figure 19-5 shows the functional block diagram of the PIU.
Figure 19-5 Functional block diagram of the PIU
Power
access
unit
Unit that detects
the failure of the
lightning-proof unit
Filtering
unit
Lightning-proof
unit failure alarm
Backplane
SCC unit
Filtering
unit
COA power supply interface

Power Access Unit
This unit accesses the 48 V or 60 V power supply for the system.
Unit That Detects the Failure of the Lightning-Proof Unit
This unit protects the equipment from overcurrent and lightning and reports the alarm that
indicates its failure to the SCC unit.
Filtering Unit
This unit filters the electromagnetic interference signals to ensure that the equipment can operate
stably.
19.2.5 Front Panel
The front panel of the PIU has power interfaces.
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Diagram of the Front Panel
Figure 19-6 shows the appearance of the front panel of the PIU.
Figure 19-6 Front panel of the PIU
PIU
PIU
PWR
PS1
PS2

Interfaces
The front panel of the PIU has two power interfaces. Table 19-6 describes the types and usage
of the interfaces of the PIU.
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Table 19-6 Interfaces of the PIU
Interface Type of Interface Usage
PWR Input interface for
the 48 V power
supply
Accesses the 48 V power supply.
PS1/PS2 Output interface
for the 50 W power
supply
Provides the 50 W power output and can supply
power to the COA.

19.2.6 Valid Slots
The PIU can be installed in slots 27 and 28 in the subrack.
19.2.7 Technical Specifications
The technical specifications of the PIU include the mechanical specifications, power
consumption, input voltage, and fuse.
Mechanical Specifications
The mechanical specifications of the PIU are as follows:
l Dimensions (mm): 44 (W) x 110 (D) x 262.05 (H)
l Weight: 1.2 kg
Power Consumption
At room temperature (25C), the maximum power consumption of the PIU is 8W.
Input Voltage
The input voltage range of the PIU is as follows:
l If the standard voltage of the input power is -48 V, the power voltage ranges from -38.4 V
to -57.6 V.
l If the standard voltage of the input power is -60 V, the power voltage ranges from -48 V
to -72 V.
Fuse
The main loop fuse F7 of the PIU is 250 V-20 A-0.00355 ohms.
19.3 PIUA
This topic describes the version, functions, working principle, front panel, valid slots, and
technical specifications of the PIUA (power interface board).
19.3.1 Version Description
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The PIUA is available in one functional version, namely, N1.
19.3.2 Application
The PIUA is a power interface board that is mainly used to access the power supply for the OptiX
OSN equipment.
19.3.3 Functions and Features
The PIUA is used to access the power supply and to provide the lightning protection function
and filtering function.
19.3.4 Working Principle and Signal Flow
The PIUA consists of the power access unit, filtering unit, and unit that detects the failure of the
lightning-proof unit.
19.3.5 Front Panel
The front panel of the PIUA has indicators and power interfaces.
19.3.6 Valid Slots
The PIUA can be installed in slots 27 and 28 in the subrack.
19.3.7 Technical Specifications
The technical specifications of the PIUA include the mechanical specifications, power
consumption, input voltage, and the fuse.
19.3.1 Version Description
The PIUA is available in one functional version, namely, N1.
19.3.2 Application
The PIUA is a power interface board that is mainly used to access the power supply for the OptiX
OSN equipment.
Figure 19-7 shows the application of the PIUA on the OptiX OSN equipment series.
Figure 19-7 Application of the PIUA on the OptiX OSN equipment series
Board A
Board B
-48 V -48 V
Backplane
PIUA
PIUA
-48 V
-48 V
OptiX OSN equipment
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19.3.3 Functions and Features
The PIUA is used to access the power supply and to provide the lightning protection function
and filtering function.
Table 19-7 provides the functions and features of the PIUA.
Table 19-7 Functions and features of the PIUA
Function and
Feature
PIUA
Lightning
protection function
Provides the lightning protection function and reports the alarm that
indicates the failure of the lightning protection function.
Filtering function Enhances the electromagnetic compatibility of the system by filtering
the power supply interface and shielding the structure of the board.
Power supply
interface
Provides two 50 W power interfaces for external devices such as the
COA and hub.
Alarm monitoring Reports the board in-position alarm.
Power supply
backup
Supports the 1+1 hot backup. Any one PIUA can supply power to the
entire subrack.

19.3.4 Working Principle and Signal Flow
The PIUA consists of the power access unit, filtering unit, and unit that detects the failure of the
lightning-proof unit.
Figure 19-8 shows the functional block diagram of the PIUA.
Figure 19-8 Functional block diagram of the PIUA
Power
access
unit
Unit that detects
the failure of the
lightning-proof unit
Filtering
unit
Lightning-proof
unit failure alarm
Backplane
SCC unit

Power Access Unit
This unit accesses the 48 V or 60 V power supply for the system.
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Unit That Detects the Failure of the Lightning-Proof Unit
This unit protects the equipment from overcurrent and lightning and reports the alarm that
indicates the failure of the lightning-proof unit to the SCC unit.
Filtering Unit
This unit filters the electromagnetic interference signals to ensure that the equipment can operate
stably.
19.3.5 Front Panel
The front panel of the PIUA has indicators and power interfaces.
Diagram of the Front Panel
Figure 19-9 shows the appearance of the front panel of the PIUA.
Figure 19-9 Front panel of the PIUA
PIUA
PIUA
PWR
PS1
PS2
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Interfaces
The front panel of the PIUA has two power interfaces. Table 19-8 describes the types and usage
of the interfaces of the PIUA.
Table 19-8 Interfaces of the PIUA
Interface Type of Interface Usage
PWR Input interface for
the 48 V power
supply
Accesses the 48 V power supply.
PS1/PS2 Output interface
for the 50 W power
supply
Provides the 50 W power output and can supply
power to the COA.

19.3.6 Valid Slots
The PIUA can be installed in slots 27 and 28 in the subrack.
19.3.7 Technical Specifications
The technical specifications of the PIUA include the mechanical specifications, power
consumption, input voltage, and the fuse.
Mechanical Specifications
The mechanical specifications of the PIUA are as follows:
l Dimensions (mm): 44 (W) x 110 (D) x 262.05 (H)
l Weight: 0.5 kg
Power Consumption
At room temperature (25C), the maximum power consumption of the PIUA is 3 W.
Input Voltage
The input voltage range of the PIUA is as follows:
l If the standard voltage of the input power is -48 V, the power voltage ranges from -38.4 V
to -57.6 V.
l If the standard voltage of the input power is -60 V, the power voltage ranges from -48V to
-72 V.
Fuse
The main loop fuse of the PIUA is 250 V-32 A-0.00355 ohms.
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19.4 PIUB
The PIUB board is the power interface unit between the DC power distribution box and each
board on the subrack. This section describes the versions, functions, working principle, front
panel, configuration, and technical specifications of the PIUB board.
19.4.1 Version Description
The PIUB is available in one functional version, namely, N1. The PIUB board can be used on
an enhanced subrack (2300 W) or enhanced subrack (1100 W).
19.4.2 Application
The PIUB board is a power interface board that provides power supply for the OptiX OSN
3500.
19.4.3 Functions and Features
The PIUB is a power interface board that provides power supply, lightning protection, and
filtering functions.
19.4.4 Working Principle and Signal Flow
The PIUB board consists of the filtering unit, protection unit, protection circuit failure detecting
unit, and power detecting unit.
19.4.5 Front Panel
The front panel of the PIUB has indicators and power interfaces.
19.4.6 Valid Slots
The PIUB board can be installed in slots 27 and 28 on the subrack.
19.4.7 Technical Specifications
The technical specifications of the PIUB board include the mechanical specifications, power
consumption, input voltage, and fuse.
19.4.1 Version Description
The PIUB is available in one functional version, namely, N1. The PIUB board can be used on
an enhanced subrack (2300 W) or enhanced subrack (1100 W).
19.4.2 Application
The PIUB board is a power interface board that provides power supply for the OptiX OSN
3500.
Figure 19-10 shows the application of the PIUB board in the OptiX OSN system.
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Figure 19-10 Application of the PIUB board in the OptiX OSN system
Board A
Board B
-48 V -48 V
Backplane
PIU
PIU
-48 V
-48 V
OptiX OSN equipment

19.4.3 Functions and Features
The PIUB is a power interface board that provides power supply, lightning protection, and
filtering functions.
Table 19-9 provides the functions and features of the PIUB board.
Table 19-9 Functions and features of the PIUB board
Functions and
Features
Description
Lightning
protection function
Provides the lightning protection function and reports the alarm that
indicates the failure of the lightning protection function.
Filtering function Enhances the electromagnetic compatibility of the system by filtering
the power supply interface and shielding the structure of the board.
Power supply
interface
Provides two 50 W power interfaces for external units such as the COA.
Alarm monitoring Reports the board in-position alarm.
Power supply
backup
Supports 1+1 hot backup. Any one PIUB can supply power to an entire
subrack.

19.4.4 Working Principle and Signal Flow
The PIUB board consists of the filtering unit, protection unit, protection circuit failure detecting
unit, and power detecting unit.
Figure 19-11 shows the functional block diagram of the PIUB.
OptiX OSN 3500 Intelligent Optical Transmission System
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Figure 19-11 Functional block diagram of the PIUB
Protection
unit
Filtering
unit
Power
detecting
unit
NEG(-)
RTN(+)
LED
indication
Protection circuit
failure detecting unit
COA power supply interface
COA
NEG(-)
RTN(+)
SCC
unit

Filtering Unit
This unit filters the electromagnetic interference signals to ensure that the equipment operates
stably.
Protection Unit
This unit protects the equipment from overcurrent and lightning.
Protection Circuit Failure Detecting Unit
This unit monitors the protection unit and reports the alarm that indicates the failure of the
protection unit to the SCC unit.
Power Detecting Unit
This unit checks whether the input power supply is valid, and uses the indicator to indicate the
status of the input power supply.
19.4.5 Front Panel
The front panel of the PIUB has indicators and power interfaces.
Diagram of the Front Panel
Figure 19-12 shows the appearance of the front panel of the PIUB board.
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Figure 19-12 Front panel of the PIUB
PIUB
PIUB
POWER
RTN(+) NEG(-)
R
T
N
(
+
)
N
E
G
(
-
)
PS1
PS2
R
T
N
(
+
)
N
E
G
(
-
)

Indicators
The front panel of the board has a power supply indicator (POWER). The POWER indicator is
green when it is on.
For the meanings of the status of the indicator, see 22 Indicators.
Interfaces
The front panel of the PIUB board has two power interfaces. Table 19-10 provides the types
and usage of the power interfaces of the PIUB board.
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Table 19-10 Description of the interfaces on the PIUB board
Interface Silkscreen Type of
Interface
Usage
PWR RTN(+),
NEG(-)
-48 V power
input
interface
Provides -48 V power input.
PWS PS1, PS2 50 W power
output
interface
Provides two 50 W power outputs for the COA.

Table 19-11 provides the pin description of the PS1 and PS2 interfaces on the PIUB board.
Table 19-11 Pin description of the PWS interfaces on the PIUB board
Front View Pin Usage
1
3
2
4

1 48 V
2 48 V
3 Grounding
4 Not defined

19.4.6 Valid Slots
The PIUB board can be installed in slots 27 and 28 on the subrack.
19.4.7 Technical Specifications
The technical specifications of the PIUB board include the mechanical specifications, power
consumption, input voltage, and fuse.
Mechanical Specifications
The mechanical specifications of the PIUB are as follows:
l Dimensions (mm): 44 (W) x 110 (D) x 262.05 (H)
l Weight (kg): 0.6
Power Consumption
The maximum power consumption of the PIUB at room temperature (25C) is 6 W.
19 Power Boards
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Input Voltage
The input voltage range of the PIUB is as follows:
l If the standard voltage of the input power is -48 V, the power voltage ranges from -38.4 V
to -57.6 V.
l If the standard voltage of the input power is -60 V, the power voltage ranges from -48 V
to -72 V.
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20 Pluggable Optical Module
About This Chapter
Certain boards on the OptiX OSN equipment supports the small form-factor pluggable (SFP),
enhanced small form-factor pluggable (eSFP), and 10 Gigabit small form-factor pluggable
(XFP) optical modules. When you need to adjust the type of accessed services or replace such
a faulty optical module, you just need to directly replace the pluggable optical module without
replacing its board.
20.1 Overview
The SFP/eSFP is a small form-factor pluggable optical transceiver. It is mainly used for SDH
optical communication and Ethernet data communication. The XFP is a 10-Gigabit small form-
factor pluggable optical transceiver. It is mainly for SDH optical communication, GE/10GE data
communication, and DWDM communication.
20.2 SFP/eSFP
This topic describes the BOM number, name, specifications, and supported boards of the SFP/
eSFP optical modules.
20.3 XFP
This topic describes the BOM number, name, specifications, and supported boards of the XFP
optical modules.
20.4 CWDM/DWDM
This topic describes the BOM number, name, specifications, and supported boards of the
CWDM/DWDM optical modules.
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20-1
20.1 Overview
The SFP/eSFP is a small form-factor pluggable optical transceiver. It is mainly used for SDH
optical communication and Ethernet data communication. The XFP is a 10-Gigabit small form-
factor pluggable optical transceiver. It is mainly for SDH optical communication, GE/10GE data
communication, and DWDM communication.
Appearance
Figure 20-1 shows the appearances of the SFP and eSFP optical modules, and Figure 20-2
shows the appearance of the XFP optical module.
Figure 20-1 SFP/eSFP optical module

The dimensions of the SFP and eSFP optical modules are 13.4 mm (W) 56.5 mm (D) 8.5
mm (H).
Figure 20-2 XFP optical module
20 Pluggable Optical Module
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The dimensions of the XFP optical module are 18.3 mm (W) 78 mm (D) 8.5 mm (H).
BOM
The BOM of a pluggable optical module is used to identify different types of optical modules.
The BOM can be marked on a label that is stuck on each pluggable optical module.
Figure 20-3 shows the label of a pluggable optical module.
Figure 20-3 Label of a pluggable optical module

20.2 SFP/eSFP
This topic describes the BOM number, name, specifications, and supported boards of the SFP/
eSFP optical modules.
Table 20-1 lists the BOM numbers and specifications of the SFP/eSFP optical modules.
Table 20-1 Mapping table of the BOM numbers and the types of the SFP/eSFP optical modules
BOM
Numb
er
Name Specifications
(Name-Encapsulation
Form-Operating
Wavelength-Rate-
Minimum Output
Optical Power-Maximum
Output Optical Power-
Receiver Sensitivity-
Optical Interface Type-
Optical Fiber Type-
Transmission Distance)
Compatible Board
340602
88
2.5 Gbit/s eSFP
optical module
Optical transceiver, eSFP,
1310 nm, STM16, -10 to -3
dBm, -21 dBm, LC, SM, 2
km
N1SLQ16, N2SLQ16
340604
85
Optical transceiver, eSFP,
1310 nm, 155 Mbit/s to 2.67
Gbit/s, -5 to 0 dBm, -21 dBm,
LC, SM, 15 km
Q2CXL16, Q3CXL16,
N2SL16A, N3SL16A,
R1CXLLN, R2CXLLN,
Q5CXLLN, Q6CXLLN,
N1SLO16, N1SLQ16,
N2SLQ16, N1SLD16,
R1PCXLLN
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 20 Pluggable Optical Module
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Copyright Huawei Technologies Co., Ltd.
20-3
BOM
Numb
er
Name Specifications
(Name-Encapsulation
Form-Operating
Wavelength-Rate-
Minimum Output
Optical Power-Maximum
Output Optical Power-
Receiver Sensitivity-
Optical Interface Type-
Optical Fiber Type-
Transmission Distance)
Compatible Board
340602
89
Optical transceiver, eSFP,
1310 nm, STM16, -2 to 3
dBm, -29 dBm, LC, SM, 40
km
R1CXLLN, R2CXLLN,
Q5CXLLN, Q6CXLLN
340604
88
Optical transceiver, eSFP,
1550 nm, STM16, -2 to 3
dBm, -30 dBm, LC, SM, 80
km
N1SLQ16, N2SLQ16,
N2SL16A, N3SL16A,
N1SLD16, Q5CXLLN,
Q6CXLLN, R2CXLLN,
N1SLO16, R1PCXLLN
340602
86
2.125 Gbit/s eSFP
optical module
Optical transceiver, eSFP,
850 nm, 2.125 Gbit/s (multi
rate), -9.5 to -2.5 dBm,
-17dBm, LC, MM, 0.5 km
N2EGS2, N1EGT2,
N2EMR0, N1EGS4,
N1EMS4, N3EGS4,
N2EGT2, N3EGS2,
N4EGS4, N1EMS2,
N1PEG16, N1PEG8,
R1PEGS1, Q1PEGS2
340604
73
1.25 Gbit/s eSFP
optical module
Optical transceiver, eSFP,
1310 nm, 1.25 Gbit/s, -9 to -3
dBm, -20 dBm, LC, SM, 10
km
N2EGS2, N1EGT2,
N2EGR2, N2EMR0,
N1EGS4N1EMS4,
N3EGS4, N2EGT2,
N3EGS2, N4EGS4,
N1EMS2
340602
98
Optical transceiver, eSFP,
1310 nm, 1.25 Gbit/s, -5 to -0
dBm, -23 dBm, LC, SM, 40
km
N2EGS2, N3EGS2,
N1EGT2, N2EGT2,
N2EGR2, N2EMR0,
N1EGS4, N3EGS4,
N4EGS4, N1EMS4,
N1EMS2, N1PEG16, ,
N1PEG8R1PEGS1,
Q1PEGS2
340603
60
Optical transceiver, eSFP,
1550 nm, 1.25 Gbit/s, -2 to 5
dBm, -23 dBm, LC, SM, 80
km
N1EGT2, N3EGS2,
N2EGT2, N4EGS4
20 Pluggable Optical Module
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BOM
Numb
er
Name Specifications
(Name-Encapsulation
Form-Operating
Wavelength-Rate-
Minimum Output
Optical Power-Maximum
Output Optical Power-
Receiver Sensitivity-
Optical Interface Type-
Optical Fiber Type-
Transmission Distance)
Compatible Board
340602
19
1.25 Gbit/s eSFP
optical module
Optical transceiver, eSFP,
1310 nm, 1.25Gbit/s, -9.5 to
-3 dBm, -20dBm, LC, SM, 10
km
N1PEG16, N1PEG8,
R1PEGS1, Q1PEGS2
340602
74
Optical transceiver, eSFP,
1550 nm, 1.25 Gbit/s, -2 to 5
dBm, -23 dBm, LC, SM, 80
km
N1PEG16, N1PEG8,
R1PEGS1, Q1PEGS2
340602
77
622 Mbit/s eSFP
optical module
Optical transceiver, eSFP,
1310 nm, STM4, -15 to -8
dBm, -30 dBm, LC, SM, 15
km
N1SL4, N2SL4, N1SLD4,
N2SLD4, N1SLQ4,
N2SLQ4, R1PCXLLN,
N1EDQ41
340602
80
Optical transceiver, eSFP,
1310 nm, STM4, -3 to 2 dBm,
-30 dBm, LC, SM, 40 km
N2SLQ4, N2SL4, N1SL4,
N1SLD4, N2SLD4,
N1SLQ4, N2SLQ4, R1SL4,
R1SLD4, N1ADL4,
N1IDL4, Q2CXL4,
Q3CXL4, N1MST4,
N1SL4A, N1SLD4A,
N1SLQ4A, R1CXLLN,
R2CXLLN, R1CXLD41,
R1CXLQ41, R2CXLQ41,
Q5CXLLN, Q6CXLLN,
Q5CXLQ41, Q6CXLQ41,
R3SL4, R3SLD4,
R1PCXLN, N1EDQ41
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 20 Pluggable Optical Module
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20-5
BOM
Numb
er
Name Specifications
(Name-Encapsulation
Form-Operating
Wavelength-Rate-
Minimum Output
Optical Power-Maximum
Output Optical Power-
Receiver Sensitivity-
Optical Interface Type-
Optical Fiber Type-
Transmission Distance)
Compatible Board
340602
84
Optical transceiver, eSFP,
1550 nm, STM4, -3 to 2dBm,
-30 dBm, LC, SM, 80 km
N1SL4, N2SL4, N1SLD4,
N2SLD4, N1SLQ4,
N2SLQ4, R1SL4, R1SLD4,
N1ADL4, N1IDL4,
Q2CXL4, Q3CXL4,
N1SL4A, N1SLD4A,
N1SLQ4A, R1CXLLN,
R2CXLLN, Q5CXLLN,
Q6CXLLN, R1CXLD41,
R1CXLQ41, R2CXLQ41,
Q5CXLQ41, Q6CXLQ41,
N1SL4A, N1SLD4A,
N1SLQ4A, R3SL4,
R3SLD4, R1PCXLN,
N1EDQ41
340602
76
155 Mbit/s eSFP
optical module
Optical transceiver, eSFP,
1310 nm, STM1, -15 to -8
dBm, -31 dBm, LC, SM, 15
km
N1OU08, N1SL1, N2SL1,
N1SLQ1, N2SLQ1,
R1SLQ1, R1SL1, N1ADQ1,
N1EFF8, N1IDQ1, N1SLT1,
Q2CXL1, N2SLO1,
Q3CXL1, N1SL1A,
N1SLQ1A, R1CXLLN,
R2CXLLN, Q5CXLLN,
Q6CXLLN, R1CXLD41,
R1CXLQ41, R2CXLQ41,
Q5CXLQ41, Q6CXLQ41,
N1IDQ1A, N3SLO1,
R3SL1, R3SLQ1,
N1EFF8A, R1PCXLN,
N1PEFF8, R1PEF4F,
N1EDQ41
20 Pluggable Optical Module
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BOM
Numb
er
Name Specifications
(Name-Encapsulation
Form-Operating
Wavelength-Rate-
Minimum Output
Optical Power-Maximum
Output Optical Power-
Receiver Sensitivity-
Optical Interface Type-
Optical Fiber Type-
Transmission Distance)
Compatible Board
340602
81
Optical transceiver, eSFP,
1310 nm, STM1, -5 to 0 dBm,
-37 dBm, LC, SM, 40 km
N1SL1, N2SL1, N1SLQ1,
N2SLQ1, N1ADQ1,
N1IDQ1, Q2CXL1,
Q3CXL1, N2SLO1,
N1SL1A, N1SLQ1A,
R1CXLLN, R2CXLLN,
Q5CXLLN, Q6CXLLN,
R1CXLD41, R1CXLQ41,
R2CXLQ41, Q5CXLQ41,
Q6CXLQ41, R3SL1,
R3SLQ1, N1SLT1,
R1PCXLN, N1PEFF8,
R1PEF4F, N1EDQ41
340602
82
Optical transceiver, eSFP,
1550 nm, STM1, -5 to 0 dBm,
-37 dBm, LC, SM, 80 km
N1SL1, N2SL1, N1SLQ1,
N2SLQ1, R1SLQ1, R1SL1,
N1ADQ1, N1IDQ1,
Q2CXL1, Q3CXL1,
N1SL1A, N1SLQ1A,
R1CXLLN, R2CXLLN,
Q5CXLLN, Q6CXLLN,
R1CXLD41, R1CXLQ41,
R2CXLQ41, Q5CXLQ41,
Q6CXLQ41, N3SLO1,
R3SL1, R3SLQ1, N1SLT1,
N1PEFF8, R1PEF4F,
N1EDQ41
340602
87
155 Mbit/s eSFP
optical module
Optical transceiver, SFP,
1310 nm, STM1, -19 to -14
dBm, -30 dBm, LC, MM, 2
km
N1ADQ1, N1EFF8,
N1IDQ1, N1MST4,
N1SLQ1, N1SLQ1A,
N1IDQ1A, N1EFF8A,
N1SLQ1A, N1PEFF8,
R1PEF4F

20.3 XFP
This topic describes the BOM number, name, specifications, and supported boards of the XFP
optical modules.
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Table 20-2 lists the BOM numbers and specifications of the XFP optical modules.
Table 20-2 Mapping table of the BOM numbers and the types of the XFP optical modules
BOM
Numb
er
Name Specifications
(Name-Encapsulation
Form-Operating
Wavelength-Rate-
Minimum Output
Optical Power-Maximum
Output Optical Power-
Receiver Sensitivity-
Optical Interface Type-
Optical Fiber Type-
Transmission Distance)
Compatible Board
340603
13
9.95 Gbit/s to
10.71 Gbit/s XFP
optical module
Optical transceiver, XFP,
1310 nm, 9.95 Gbit/s to 10.71
Gbit/s, -6 dBm to -1 dBm, -11
dBm, LC, SM, 10 km
N1SLD64, N1EAS2,
N1PEX1, N2PEX1,
N1PEX2
03030J
CB
9.95 Gbit/s to 11.1
Gbit/s XFP optical
module
Optical transceiver, XFP,
1550 nm, 9.95 Gbit/s to 11.1
Gbit/s, -1 dBm to 2 dBm, -17
dBm, LC, SM, 40 km
N1SLD64
340603
62
10.3 Gbit/s XFP
optical module
Optical transceiver, XFP,
850 nm, 10.3 Gbit/s, -7.3
dBm to -1.3 dBm, -7.5 dBm,
LC, MM, 0.3 km
N1PEX1, N2PEX1,
N1PEX2
340603
22
9.95 Gbit/s to 11.1
Gbit/s XFP optical
module
Optical transceiver, XFP,
1550 nm, 9.95 Gbit/s to 11.1
Gbit/s, -1 dBm to 2 dBm, -15
dBm, LC, SM, 40 km
N1PEX1, N2PEX1,
N1PEX2
340603
61
Optical transceiver, XFP,
1550 nm, 9.95 Gbit/s to 11.1
Gbit/s, 0 dBm to 4 dBm, -24
dBm, LC, SM, 80 km
N1PEX1, N2PEX1,
N1PEX2

20.4 CWDM/DWDM
This topic describes the BOM number, name, specifications, and supported boards of the
CWDM/DWDM optical modules.
CWDM Optical Module
Table 20-3 lists the BOM numbers and specifications of the 1.25 Gbit/s CWDM eSFP optical
modules.
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Table 20-3 Mapping table of the BOM numbers and the types of the 1.25 Gbit/s CWDM eSFP
optical modules
BOM
Numb
er
Name (Name-Encapsulation
Form-Operating
Wavelength-Rate-
Minimum Output
Optical Power-Maximum
Output Optical Power-
Receiver Sensitivity-
Optical Interface Type-
Optical Fiber Type-
Transmission Distance)
Compatible Board
340603
30
125 Mbit/s to 1.25
Gbit/s CWDM
eSFP optical
module
Optical transceiver, eSFP,
1471 nm, 125 Mbit/s to 1.25
Gbit/s, 0 dBm to 5 dBm, -19
dBm, LC, 40 km
N1PEG16, N1PEG8,
R1PEGS1, Q1PEGS2
340603
44
Optical transceiver, eSFP,
1491 nm, 125 Mbit/s to 1.25
Gbit/s, 0 dBm to 5 dBm, -19
dBm, LC, 40 km
340603
40
Optical transceiver, eSFP,
1511 nm, 125 Mbit/s to 1.25
Gbit/s, 0 dBm to 5 dBm, -19
dBm, LC, 40 km
340603
43
Optical transceiver, eSFP,
1531 nm, 125 Mbit/s to 1.25
Gbit/s, 0 dBm to 5 dBm, -19
dBm, LC, 40 km
340603
53
Optical transceiver, eSFP,
1551 nm, 125 Mbit/s to 1.25
Gbit/s, 0 dBm to 5 dBm, -19
dBm, LC, 40 km
340604
13
Optical transceiver, eSFP,
1571 nm, 125 Mbit/s to 1.25
Gbit/s, 0 dBm to 5 dBm, -19
dBm, LC, 40 km
340604
14
Optical transceiver, eSFP,
1591 nm, 125 Mbit/s to 1.25
Gbit/s, 0 dBm to 5 dBm, -19
dBm, LC, 40 km
340604
15
Optical transceiver, eSFP,
1611 nm, 125 Mbit/s to 1.25
Gbit/s, 0 dBm to 5 dBm, -19
dBm, LC, 40 km

OptiX OSN 3500 Intelligent Optical Transmission System
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DWDM Optical Module
Table 20-4 lists the BOM numbers and specifications of the 10 Gbit/s DWDM XFP optical
modules.
Table 20-4 Mapping table of the BOM numbers and the types of the 10 Gbit/s DWDM XFP
optical modules
BOM
Numb
er
Name (Name-Encapsulation
Form-Operating
Wavelength-Rate-
Minimum Output
Optical Power-Maximum
Output Optical Power-
Receiver Sensitivity-
Optical Interface Type-
Optical Fiber Type-
Transmission Distance)
Compatible Board
340603
42
9.95 Gbit/s to 11.1
Gbit/s CWDM
XFP optical
module
Optical transceiver, XFP,
1559.79 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
N1PEX1, N2PEX1,
N1PEX2
340604
12
Optical transceiver, XFP,
1560.61 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
32
Optical transceiver, XFP,
1558.98 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
33
Optical transceiver, XFP,
1558.17 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
34
Optical transceiver, XFP,
1557.36 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
35
Optical transceiver, XFP,
1556.55 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
20 Pluggable Optical Module
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BOM
Numb
er
Name (Name-Encapsulation
Form-Operating
Wavelength-Rate-
Minimum Output
Optical Power-Maximum
Output Optical Power-
Receiver Sensitivity-
Optical Interface Type-
Optical Fiber Type-
Transmission Distance)
Compatible Board
340604
36
Optical transceiver, XFP,
1555.75 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
37
Optical transceiver, XFP,
1554.94 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
38
Optical transceiver, XFP,
1554.13 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
39
Optical transceiver, XFP,
1553.33 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
40
Optical transceiver, XFP,
1552.52 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
41
Optical transceiver, XFP,
1551.72 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1dBm to 2dBm,
-12 dBm, LC, SM, 40 km
340604
42
Optical transceiver, XFP,
1550.92 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 20 Pluggable Optical Module
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
20-11
BOM
Numb
er
Name (Name-Encapsulation
Form-Operating
Wavelength-Rate-
Minimum Output
Optical Power-Maximum
Output Optical Power-
Receiver Sensitivity-
Optical Interface Type-
Optical Fiber Type-
Transmission Distance)
Compatible Board
340604
43
Optical transceiver, XFP,
1550.12 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
44
Optical transceiver, XFP,
1549.32 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
45
Optical transceiver, XFP,
1548.51 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
46
Optical transceiver, XFP,
1547.72 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
47
Optical transceiver, XFP,
1546.92 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
48
Optical transceiver, XFP,
1546.12 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
49
Optical transceiver, XFP,
1545.32 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
20 Pluggable Optical Module
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
20-12 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
BOM
Numb
er
Name (Name-Encapsulation
Form-Operating
Wavelength-Rate-
Minimum Output
Optical Power-Maximum
Output Optical Power-
Receiver Sensitivity-
Optical Interface Type-
Optical Fiber Type-
Transmission Distance)
Compatible Board
340604
50
Optical transceiver, XFP,
1544.53 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
51
Optical transceiver, XFP,
1543.73 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
52
Optical transceiver, XFP,
1542.94 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
53
Optical transceiver, XFP,
1542.14 nm, 9.95 to 11.1Gb/
s, -1 dBm to 2 dBm, -12 dBm,
LC, SM, 40 km
340604
54
Optical transceiver, XFP,
1541.35 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
55
Optical transceiver, XFP,
1540.56 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
56
Optical transceiver, XFP,
1539.77 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 20 Pluggable Optical Module
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
20-13
BOM
Numb
er
Name (Name-Encapsulation
Form-Operating
Wavelength-Rate-
Minimum Output
Optical Power-Maximum
Output Optical Power-
Receiver Sensitivity-
Optical Interface Type-
Optical Fiber Type-
Transmission Distance)
Compatible Board
340604
57
Optical transceiver, XFP,
1538.98 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
58
Optical transceiver, XFP,
1538.19 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
59
Optical transceiver, XFP,
1537.40 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
60
Optical transceiver, XFP,
1536.61 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
61
Optical transceiver, XFP,
1535.82 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
62
Optical transceiver, XFP,
1535.04nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
63
Optical transceiver, XFP,
1534.25 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
20 Pluggable Optical Module
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
20-14 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
BOM
Numb
er
Name (Name-Encapsulation
Form-Operating
Wavelength-Rate-
Minimum Output
Optical Power-Maximum
Output Optical Power-
Receiver Sensitivity-
Optical Interface Type-
Optical Fiber Type-
Transmission Distance)
Compatible Board
340604
64
Optical transceiver, XFP,
1533.47 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
65
Optical transceiver, XFP,
1532.68 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
66
Optical transceiver, XFP,
1531.90 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
67
Optical transceiver, XFP,
1531.12 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
68
Optical transceiver, XFP,
1530.33 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km
340604
69
Optical transceiver, XFP,
1529.55 nm, 9.95 Gbit/s to
11.1 Gbit/s, -1 dBm to 2
dBm, -12 dBm, LC, SM, 40
km

OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 20 Pluggable Optical Module
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
20-15
21 Cables
About This Chapter
This topic describes the cables that the equipment uses, including the fiber jumper, power cable,
alarm cable, management cable, signal cable, and clock cable.
21.1 Fiber Jumper
This topic describes the categories and connectors of the fiber jumpers.
21.2 Power Cable and Grounding Cable
The power cables and grounding cables include the cabinet power cable, subrack power cable,
COA power cable, and grounding cable of the cabinet door.
21.3 Alarm Cable
The alarm cables that the equipment uses include the cabinet indicator cable, alarm cascading
cable, and alarm input/output cable.
21.4 Management Cable
The management cables include the serial port cable, ordinary phone line, COA cascading cable,
and network cable.
21.5 Signal Cable
The signal cables include the E1/E3 signal cable, framed E1 signal cable, and Nx64 kbit/s signal
cable.
21.6 Clock Cable
The clock cables include the clock cable and clock transit cable.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 21 Cables
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
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21-1
21.1 Fiber Jumper
This topic describes the categories and connectors of the fiber jumpers.
21.1.1 Categories of the Fiber Jumpers
The OptiX OSN equipment uses various types of fiber jumpers.
21.1.2 Connector
The OptiX OSN equipment uses various types of fiber connectors.
21.1.1 Categories of the Fiber Jumpers
The OptiX OSN equipment uses various types of fiber jumpers.
Table 21-1 lists the categories of the fiber jumpers that the OptiX OSN equipment uses.
Table 21-1 Categories of the fiber jumpers that the OptiX OSN equipment uses
Usage Connector
1
Connector
2
Fiber Available Length
Used to connect
the OptiX OSN
equipment to the
ODF or to
connect an
interface board of
the OptiX OSN
equipment to
other equipment
LC/PC FC/PC 2 mm single-
mode fiber
6 m, 10 m, 20 m, 30 m,
and 50 m
2 mm multi-
mode fiber
3 m, 5 m, 10 m, 20 m,
30 m, and 50 m
LC/PC SC/PC 2 mm single-
mode fiber
5 m, 10 m, 20 m, 30 m,
and 50 m
2 mm multi-
mode fiber
10 m, 20 m, 30 m, and
50 m
SC/PC SC/PC 2 mm single-
mode fiber
2 m, 5 m, 10 m, 20 m,
30 m, 50 m, and 80 m
Used to connect
the OptiX OSN
equipment
LC/PC LC/PC 2 mm single-
mode fiber
1.5 m, 3 m, 5 m, 10 m,
20 m, and 30 m
2 mm multi-
mode fiber
3 m, 5 m, 10 m, 20 m,
and 30 m
LC/PC FC/PC 2 mm single-
mode fiber
6 m, 10 m, 20 m, 30 m,
and 50 m
LC/PC SC/PC 2 mm multi-
mode fiber
5 m, 10 m, 20 m, 30 m,
and 50 m

Select the fiber connector and fiber length according to the on-site survey.
21.1.2 Connector
The OptiX OSN equipment uses various types of fiber connectors.
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Hardware Description
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Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
The four types of fiber connectors are described as follows:
l Most of the optical interfaces on the front panels of the boards are the LC/PC optical
interfaces. See Figure 21-1.
l The N2OU08 and 61COA provide the SC/PC optical interfaces.
l The "IN" interface on the case-shaped 62COA that is externally installed uses the LSH/
APC connector. See Figure 21-4.
l Generally, the ODF on the client side provides the FC/PC or SC/PC optical interface.
Figure 21-3 and Figure 21-2 show the corresponding FC/PC and SC/PC fiber connectors.
Table 21-2 describes the four types of fiber connectors.
Table 21-2 Types of fiber connectors
Type of Internal
Fiber Connector
Description
LC/PC Plug-in square fiber connector/protruding polished
LSH/APC Connector with a dust-proof cover/protruding polished (eight
degrees)
FC/PC Round fiber connector/protruding polished
SC/PC Square fiber connector/protruding polished

LC/PC Fiber Connector
Figure 21-1 shows the appearance of the LC/PC fiber connector.
Figure 21-1 Appearance of the LC/PC fiber connector

The axial operation instead of rotation is required to insert or remove an LC/PC fiber connector.
To insert a fiber jumper that uses an LC/PC connector, align the head of the fiber jumper with
the optical interface and apply proper force. To remove the fiber jumper, first, press the clip,
then, slightly push the fiber connector inward, and finally, pull out the connector.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 21 Cables
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
21-3
SC/PC Fiber Connector
Figure 21-2 shows the appearance of the SC/PC fiber connector.
Figure 21-2 Appearance of the SC/PC fiber connector

FC/PC Fiber Connector
Figure 21-3 shows the appearance of the FC/PC fiber connector.
Figure 21-3 Appearance of the FC/PC fiber connector

LSH/APC Fiber Connector
Figure 21-4 shows the appearance of the LSH/APC fiber connector.
Figure 21-4 Appearance of the LSH/APC fiber connector
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Hardware Description
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Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)

21.2 Power Cable and Grounding Cable
The power cables and grounding cables include the cabinet power cable, subrack power cable,
COA power cable, and grounding cable of the cabinet door.
21.2.1 Power Cable of the Cabinet
The 48 V power cable, BGND power cable, and PGND power cable are used to supply power
to the equipment in a cabinet. One end of the power cable is connected to the power distribution
cabinet and the grounding bar in the equipment room, and the other end is connected to the DC
PDU at the top of the cabinet.
21.2.2 Grounding Cable of the Cabinet Door
The grounding cable of the cabinet door grounds the front door, rear door and side panels of the
cabinet. The grounding cables of the cabinet door are correctly connected before delivery.
21.2.3 Subrack Power Cable
The subrack power cable connects the DC PDU at the top of the cabinet and the PIU in the
subrack. The subrack power cable leads the 48 V power from the top of the cabinet to the
subrack. The subrack power cable is correctly connected before delivery.
21.2.4 COA Power Cable
The PIU can supply power to a maximum of two pieces of external equipment (for example, the
COA).
21.2.1 Power Cable of the Cabinet
The 48 V power cable, BGND power cable, and PGND power cable are used to supply power
to the equipment in a cabinet. One end of the power cable is connected to the power distribution
cabinet and the grounding bar in the equipment room, and the other end is connected to the DC
PDU at the top of the cabinet.
NOTE
Different DC PDU models work with different power cables of the cabinet.
l The N1PDU works with the general subrack and the enhanced subrack (1100 W).
l The TN51PDU works with the enhanced subrack (2300 W).
Structure of the Mapping Power Cable of the Cabinet for the N1PDU
Figure 21-5 shows the structure of the 48 V/BGND power cable of the cabinet when the
N1PDU is used. Figure 21-6 and Figure 21-7 show the structure of the PGND power cable of
the cabinet when the N1PDU is used.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 21 Cables
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
21-5
Figure 21-5 Structure of the 48 V/BGND power cable of the cabinet for the N1PDU
1 2
3
1. Cord end terminal 2. Bare crimping terminal type OT 3. Cable tie

Figure 21-6 Structure of the PGND power cable of the cabinet (JG2) for the N1PDU
1. Bare crimping terminal type OT 2. Cable tie 3. Bare crimping terminal (JG2)
4. Heat shrink tube 5. Main label 6. Wire
7. Heat shrink tube - -

Figure 21-7 Structure of the PGND power cable of the cabinet (OT) for the N1PDU
1. Bare crimping terminal type OT 2. Cable tie 3. Bare crimping terminal (OT)
4. Heat shrink tube 5. Main label 6. Wire
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Hardware Description
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Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
7. Heat shrink tube - -

Structure of the Mapping Cabinet Power Cable for the TN51PDU
Figure 21-8 shows the structure of the 48 V/BGND power cable of the cabinet when the
TN51PDU is used. Figure 21-9 shows the structure of the PGND power cable of the cabinet
when the TN51PDU is used.
Figure 21-8 Structure of the 48 V/BGND power cable of the cabinet for the TN51PDU
1. Bare crimping terminal (OT) 2. Cord end terminal

Figure 21-9 Structure of the PGND power cable of the cabinet for the TN51PDU
1. Bare crimping terminal (OT) 2. Cord end terminal

Pin Assignments
None.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 21 Cables
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
21-7
Technical Specifications
Table 21-3 Technical specifications of the power cable of the cabinet for the N1PDU
Item Description
48 V power
cable of the
cabinet
Terminal 2
Bare crimping terminal type OT 16 mm
2
M8 tin
plated round bare terminal
Terminal 1
Single cord end terminal 16 mm
2
0.024 m insertion
depth of 12 mm 80 A green
Cable type
Power cable 450 V/750 V 16 mm
2
round and blue
85 A
BGND power
cable of the
cabinet
Terminal 2
Bare crimping terminal type OT 16 mm
2
M8 tin
plated round bare terminal
Terminal 1
Single cord end terminal 16 mm
2
0.024 m insertion
depth of 12 mm 80 A green
Cable type
Power cable 450 V/750 V 16 mm
2
round and black
85 A
PGND power
cable of the
cabinet
Terminal 1
Bare crimping terminal type OT 25 mm
2
M8 tin
plated round bare terminal
Terminal 3
Bare crimping terminal JG2 25 mm
2
M6 95 A tin
plated, bare crimping terminal JG2 25 mm
2
M8 95
A tin plated, or bare crimping terminal type OT 25
mm
2
M8 tin plated round bare terminal
Cable type
Power cable 450 V/750 V 25 mm
2
round and green
85 A
Fireproof class CM
Length 10 m, 20 m, and 30 m

Table 21-4 Technical specifications of the power cable of the cabinet for the TN51PDU
Item Description
48 V power
cable of the
cabinet, BGND
power cable of
the cabinet
Terminal
Bare crimping terminal type OT 16 mm
2
M6 tin
plated round bare terminal
Cable type
Wire 450 V/750 V 16 mm
2
yellow green, 102 A
PGND power
cable of the
cabinet
Terminal
Bare crimping terminal type OT 6 mm
2
M6 tin plated
round insulated terminal
Cable type Wire - 600 V - UL3386 - 10AWG - yellow/green - 48 A

21 Cables
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
21-8 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
21.2.2 Grounding Cable of the Cabinet Door
The grounding cable of the cabinet door grounds the front door, rear door and side panels of the
cabinet. The grounding cables of the cabinet door are correctly connected before delivery.
Structure
Figure 21-10 shows the structure of the grounding cable of the cabinet door.
Figure 21-10 Structure of the grounding cable of the cabinet door
1. Bare crimping terminal type OT 2. Heat shrink tube 3. Main label

Pin Assignments
None.
Technical Specifications
Item Description
Terminal X1/X2
Bare crimping terminal OT 6 mm
2
M6 tin plated round
insulated terminal 12 to 10 AWG
Cable Type Wire 600 V UL1015 10 AWG 105-core twisted pair
yellow and green, round 50 A
Fireproof
class
CM
Length 0.35 m

21.2.3 Subrack Power Cable
The subrack power cable connects the DC PDU at the top of the cabinet and the PIU in the
subrack. The subrack power cable leads the 48 V power from the top of the cabinet to the
subrack. The subrack power cable is correctly connected before delivery.
NOTE
An enhanced subrack (2300 W) uses different power cables from those used by a general subrack or an
enhanced subrack (1100 W).
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 21 Cables
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
21-9
Structure
Figure 21-11 shows the structure of the power cable for thegeneral and enhanced subrack (1100
W) subrack.
Figure 21-11 Structure of the power cable for thegeneral and enhanced subrack (1100 W)
subrack
1. Cable connector 2. Main label 3. Cable tie 4. Label 5. Cord end terminal

Figure 21-12 shows the structure of the power cable for the enhanced subrack (2300 W).
Figure 21-12 Structure of the power cable for the enhanced subrack (2300 W)
W1
W2
1
X1
X2
L
W1
W2
1. Bare crimping terminal type OT

Pin Assignments
Table 21-5 provides the pin assignments of the subrack power cable.
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OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
21-10 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Table 21-5 Pin assignments of the general and enhanced subrack (1100 W) subrack power cable
Cable
Connector
Bare
Crimping
Terminal
Connection Color of the Core
X1.A1 X2 A1 is connected to X2. Blue (48 V power)
X1.A3 X3 A3 is connected to X3. Black (power ground)

Technical Specifications
Table 21-6 Technical specifications of the power cable for thegeneral and enhanced subrack
(1100 W) subrack
Item Description
Cable connector X1 Cable connector type D 3-pin female without intermediate
male terminals
Bare crimping terminals
X2 and X3
Single cord end terminal 4 mm
2
20 A insertion depth of 10
mm gray
Cable Type
Power cable 600 V 5.26 mm
2
10 AWG black (the core is
in blue and black) 41 A
Number of
cores
2
Fireproof
class
CM
Color The core is in blue and black.
Length 2.5 m, 3 m, and 3.5 m

Table 21-7 Technical specifications of the power cable for the large power subrack
Item Description
Cable connector
Bare crimping terminal OT2 10 mm
2
- 60 A - tin plated
Cable Type
l Wire - 450 V/750 V - H07Z - K UL3386 - 10 mm
2
- blue
l Wire - 450 V/750 V - H07Z - K UL3386 - 10 mm
2
- black

21.2.4 COA Power Cable
The PIU can supply power to a maximum of two pieces of external equipment (for example, the
COA).
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 21 Cables
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Copyright Huawei Technologies Co., Ltd.
21-11
The COA power cable connects a power interface on the PIU to a power interface of the external
equipment. Both ends of the COA power cable use the 4-pin connector. One end of the COA
power cable is connected to the PIU and the other end is connected to the power interface of the
external equipment (for example, the COA).
Structure
Figure 21-13 shows the structure of the COA power cable.
Figure 21-13 Structure of the COA power cable
1 3
2 4
A-A
1
2
3
B
B
A
A
W1
W2
X1
X2
X3
W1
W2
W1.1
W1.2
W2.1
W2.2
X3
1. Common terminal female 2. Common connector 4-pin 3. Main label A-A. Sectional view in direction
A

Pin Assignments
Table 21-8 provides the pin assignments of the COA power cable.
Table 21-8 Pin assignments of the COA power cable
Connectors X1
and X2
Cables W1 and W2 Color Connector X3
X1.1 W1.1 Brown X3.1
X2.1 W2.1
X1.3 W1.2 Black X3.3
X2.3 W2.2

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Hardware Description
21-12 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Technical Specifications
Item Description
Connector X3 Common connector 4-pin double rows/4.20 mm
Connector X1/X2 Common terminal female 4-pin 18/26 AWG 13.7 mm in
length
Model of wire W1/W2 Symmetrical twisted-pair cable 0 ohms UL2464 0.64 mm
22 AWG one pair black
Number of cores 2
Fireproof class CM
Color Black
Length 1.8 m

21.3 Alarm Cable
The alarm cables that the equipment uses include the cabinet indicator cable, alarm cascading
cable, and alarm input/output cable.
21.3.1 Cabinet Indicator Cable
The cabinet indicator cable is used to connect the AUX in the subrack to the cabinet indicators.
The cabinet indicator cable leads the indicator signal from the AUX to the cabinet indicators.
21.3.2 Indicator Cascading Cable Between Subracks or Alarm Cascading Cable Between the
OptiX OSN Equipment
The indicator cascading cable between subracks or the alarm cascading cable between the OptiX
OSN equipment cascades the indicator signals or alarm signals between the subracks of the
OptiX OSN equipment.
21.3.3 Alarm Cascading Cable Between the OptiX OSN Equipment and the Other Huawei
Transmission Equipment
The alarm cascading cable cascades the alarm signals of the OptiX OSN equipment and the
alarm signals of the other Huawei transmission equipment such as the OptiX 2500+ and OptiX
OSN 9500.
21.3.4 Alarm Input/Output Cable
The alarm input cable transmits the alarm signals of the external equipment to the OptiX OSN
equipment. The alarm output cable transmits the alarm signals of the OptiX OSN equipment to
the centralized alarm monitoring equipment.
21.3.1 Cabinet Indicator Cable
The cabinet indicator cable is used to connect the AUX in the subrack to the cabinet indicators.
The cabinet indicator cable leads the indicator signal from the AUX to the cabinet indicators.
Structure
Figure 21-14 shows the structure of the cabinet indicator cable.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 21 Cables
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
21-13
Figure 21-14 Structure of the cabinet indicator cable
X4
X3
X2
X5
X1
A-A. Sectional view in direction A B-B. Sectional view in direction B

Pin Assignments
Table 21-9 provides the pin assignments of the cabinet indicator cable.
Table 21-9 Pin assignments of the cabinet indicator cable
Connector
X1
Connector X2/X3/X4/X5 Relation Print on the
Label
X1.4 X2.2 Twisted
pair
Green
X1.5 X2.1
X1.1 X3.2 Twisted
pair
Red
X1.2 X3.1
X1.3 X4.2 Twisted
pair
Orange
X1.6 X4.1
X1.7 X5.2 Twisted
pair
Yellow
X1.8 X5.1

Technical Specifications
Item Description
Connector X1 Network interface connector 8-pin 8-bit shielded
RJ-45 connector
Connector X2/X3/X4/X5 Common connector 2-pin single row/2.5 mm
Cable type Symmetrical twisted-pair cable 120 ohms SEYPVPV
0.5 mm 24 AWG 8-core PANTONE 430U
Number of cores 8
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Item Description
Fireproof class CM
Diameter of the core 0.5 mm
Length 2.5 m, 3 m, and 3.5 m

21.3.2 Indicator Cascading Cable Between Subracks or Alarm
Cascading Cable Between the OptiX OSN Equipment
The indicator cascading cable between subracks or the alarm cascading cable between the OptiX
OSN equipment cascades the indicator signals or alarm signals between the subracks of the
OptiX OSN equipment.
Both ends of the cable use the RJ-45 connector. One end of the cable is connected to the LAMP1
or ALM02 interface of the AUX in one subrack. The other end of the cable is connected to the
LAMP2 or ALM01 interface of the AUX in another subrack.
Structure
Figure 21-15 shows the structure of the indicator cascading cable between subracks or the alarm
cascading cable between the OptiX OSN equipment.
Figure 21-15 Structure of the indicator cascading cable between subracks or the alarm cascading
cable between the OptiX OSN equipment
2
1. RJ-45 network interface connector 2. Label 1 A-A. Sectional view in direction A

Pin Assignments
Table 21-10 provides the pin assignments of the indicator cascading cable between subracks or
the alarm cascading cable between the OptiX OSN equipment.
Table 21-10 Pin assignments of the indicator cascading cable between subracks or the alarm
cascading cable between the OptiX OSN equipment
Connect
or X1
Connect
or X2
Relation Alarm Output
X1.1 X2.1 Twisted pair Critical alarm output and major
alarm output (+)
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Connect
or X1
Connect
or X2
Relation Alarm Output
X1.2 X2.2 Critical alarm signal output and
major alarm signal output ()
X1.3 X2.3 Twisted pair Minor alarm signal output and
warning alarm signal output (+)
X1.6 X2.6 Minor alarm signal output and
warning alarm signal output ()
X1.4 X2.4 Twisted pair Alarm signal output 1 (+)
X1.5 X2.5 Alarm signal output 1 ()
X1.7 X2.7 Twisted pair Alarm signal output 2 (+)
X1.8 X2.8 Alarm signal output 2 ()

Technical Specifications
Item Description
Connector X1/
X2
Network interface connector 8-pin 8-bit shielded RJ-45 connector
Cable type Symmetrical twisted-pair cable 120 ohms SEYPVPV 0.5 mm 24
AWG 8-core PANTONE 430U
Number of cores 8
Fireproof class CM
Diameter of the
core
0.5 mm
Length 3 m, 5 m, 10 m, and 20 m

21.3.3 Alarm Cascading Cable Between the OptiX OSN Equipment
and the Other Huawei Transmission Equipment
The alarm cascading cable cascades the alarm signals of the OptiX OSN equipment and the
alarm signals of the other Huawei transmission equipment such as the OptiX 2500+ and OptiX
OSN 9500.
Both ends of the cable use the RJ-45 connector. One end of the cable is connected to the ALM01
or ALM02 interface of the OptiX OSN subrack. The other end of the cable is connected to the
alarm output interface or the alarm cascading interface of the subrack of the other Huawei
transmission equipment.
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Structure
Figure 21-16 shows the structure of the alarm cascading cable between the OptiX OSN
equipment and the other Huawei transmission equipment.
Figure 21-16 Structure of the alarm cascading cable between the OptiX OSN equipment and
the other Huawei transmission equipment
1. RJ-45 network interface connector 2. Main label 3. Label 1 4. Cable connector type D 9-pin female
L: 5 m, 10 m, and 20 m - - -

Pin Assignments
Table 21-11 provides the pin assignments of the alarm cascading cable between the OptiX OSN
equipment and the other Huawei transmission equipment.
Table 21-11 Pin assignments of the alarm cascading cable between the OptiX OSN equipment
and the other Huawei transmission equipment
Connector X1 Connector X2 Relation Description
X1.1 X2.7 Twisted pair Critical alarm signal output (+)
X1.2 X2.3 Critical alarm signal output ()
X1.3 X2.6 Twisted pair Major alarm signal output (+)
X1.6 X2.1 Major alarm signal output ()

Technical Specifications
Item Description
Connector
X1
Network interface connector 8-pin 8-bit shielded RJ-45 connector
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Item Description
Connector
X2
Cable connector type D 9-pin female
Cable type Symmetrical twisted-pair cable 100 ohms SEYVP 0.48 mm 26 AWG
4-core black
Number of
cores
4
Fireproof
class
CM
Diameter of
the core
0.5 mm
Length 5 m, 10 m, and 20 m

21.3.4 Alarm Input/Output Cable
The alarm input cable transmits the alarm signals of the external equipment to the OptiX OSN
equipment. The alarm output cable transmits the alarm signals of the OptiX OSN equipment to
the centralized alarm monitoring equipment.
The alarm input/output cable uses an RJ-45 connector at one end to connect to the alarm input/
output interface of the equipment. The other end of the alarm input/output cable is connected to
the external equipment or the centralized alarm monitoring equipment. The connector needs to
be prepared on site as required. Each alarm input/output cable transmits four channels of alarm
signals.
Structure
Figure 21-17 shows the structure of the alarm input/output cable.
Figure 21-17 Structure of the alarm input/output cable
1. RJ-45 network interface connector 2. Main label A-A. Sectional view in direction A

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Pin Assignments
Table 21-12 provides the pin assignments of the alarm input/output cable.
Table 21-12 Pin assignments of the alarm input/output cable
Connector X1 Color Relation Alarm Output Alarm Input
X1.1 Blue Twisted pair Critical or major alarm (+) SW_INPUT 1 +
X1.2 White Critical or major alarm () SW_INPUT 1
X1.3 Orange Twisted pair Minor or warning alarm (+) SW_INPUT 2 +
X1.6 White Minor or warning alarm () SW_INPUT 2
X1.4 Green Twisted pair Alarm signal output 1 (+) SW_INPUT 3 +
X1.5 White Alarm signal output 1 () SW_INPUT 3
X1.7 Brown Twisted pair Alarm signal output 2 (+) SW_INPUT 4 +
X1.8 White Alarm signal output 2 () SW_INPUT 4

Technical Specifications
Item Description
Connector X1 Network interface connector 8-pin 8-bit shielded RJ-45 connector
Cable type Symmetrical twisted-pair cable 120 ohms SEYPVPV 0.5 mm 24
AWG 8-core PANTONE 430U
Number of
cores
8
Fireproof class CM
Core diameter 0.5 mm
Length 10 m, 20 m, and 30 m

21.4 Management Cable
The management cables include the serial port cable, ordinary phone line, COA cascading cable,
and network cable.
21.4.1 OAM Serial Port Cable
The OAM serial port cable is used for the management and remote maintenance of the OptiX
OSN equipment.
21.4.2 Serial 1 to 4/F1/F&f Serial Port Cable
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The serial 14/F1/F&f serial port cable uses an RJ-45 connector at one end to connect to the
serial 14 interfaces, F1 serial port, or F&f serial port, and uses a DB9 connector at the other
end to connect to the external detecting equipment or external managed equipment.
21.4.3 RS-232/RS-422 Serial Port Cable
The RS-232/RS-422 serial port cable is used to transport the management signals between
subnets.
21.4.4 Ordinary Telephone Line
The ordinary telephone line is used to connect the orderwire phone. Both ends of the ordinary
telephone line use the RJ-45 connector. One end of the ordinary telephone line is connected to
the PHONE interface of the equipment, and the other end is connected to the interface of the
orderwire phone.
21.4.5 COA Cascading Cable
When multiple COAs are installed in a cabinet, use COA cascading cables to cascade the COAs.
21.4.6 Straight Through Cable
The straight through cable uses the RJ-45 connector to connect to the equipment at both ends.
The straight through cable is used to connect the OptiX OSN equipment, network management
computer, and Ethernet to realize communication.
21.4.7 Crossover Cable
The crossover cable is used to connect the OptiX OSN equipment to an NM computer.
21.4.1 OAM Serial Port Cable
The OAM serial port cable is used for the management and remote maintenance of the OptiX
OSN equipment.
The OAM serial port cable uses an RJ-45 connector at one end to connect to the OAM interface
of the equipment and uses a DB25 connector at the other end to connect to a laptop computer,
serial NMS, or modem.
Structure
Figure 21-18 shows the structure of the OAM serial port cable (using the DB25 connector).
Figure 21-18 Structure of the OAM serial port cable
1. RJ-45 network
interface connector
2. Main label 3. Cable connector
DB25 male
A-A. Sectional view in
direction A
B-B. Sectional view in
direction B
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Pin Assignments
Table 21-13 provides the pin assignments of the OAM serial port cable.
Table 21-13 Pin assignments of the OAM serial port cable
Connector
X1
Connector X2 Relation Description
X1.2 X2.20 Single Data terminal ready (DTR)
X1.3 X2.2 Single Transmitting data (TD)
X1.6 X2.3 Single Receiving data (RD)
X1.4 X2.7 Twisted pair Signaling ground (SG)
X1.5

Technical Specifications
Item Description
Connector X1 Network interface connector RJ-45 connector 8-pin 8-bit shielded
connector
Connector X2 Cable connector type D 25-pin male, or cable connector type D
9-pin male
Type Symmetrical twisted-pair cable 120 ohms SEYPVPV 0.5 mm 24
AWG 8-core PANTONE 430U
Number of
cores
8
Fireproof class CM
Length 5000 mm

21.4.2 Serial 1 to 4/F1/F&f Serial Port Cable
The serial 14/F1/F&f serial port cable uses an RJ-45 connector at one end to connect to the
serial 14 interfaces, F1 serial port, or F&f serial port, and uses a DB9 connector at the other
end to connect to the external detecting equipment or external managed equipment.
The serial 14/F1/F&f serial port cable performs the following functions:
l Transparently transmits the environment monitoring data signal.
l Manages external devices such as the COA.
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Structure
Figure 21-19 shows the structure of the serial 14/F1/F&f serial port cable.
Figure 21-19 Structure of the serial 14/F1/F&f serial port cable
1. RJ-45 network
interface connector
2. Main label 3. Cable connector
DB9 male
A-A. Sectional view in
direction A
B-B. Sectional view in
direction B

Pin Assignments
Table 21-14 provides the pin assignments of the serial 14/F1/F&f serial port cable.
Table 21-14 Pin assignments of the serial 14/F1/F&f serial port cable
Connector X1 Connector X2 Relation Description
X1.1 X2.8 Twisted pair RS422RX+
X1.2 X2.9 RS422RX
X1.3 X2.6 Twisted pair RS422TX+
X1.6 X2.7 RS422TX
X1.4 X2.3 Twisted pair RS232RX
X1.8 X2.2 RS232TX
X1.5 X2.5 Single SG

Technical Specifications
Item Description
Connector X1 Network interface connector RJ-45 connector 8-pin 8-bit shielded
connector
Connector X2 Cable connector type D 9-pin male
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Item Description
Cable type (1) Symmetrical twisted-pair cable 120 ohms SEYPVPV 0.5 mm 24
AWG 8-core PANTONE 430U (2) Symmetrical twisted-pair cable
100 ohms SEYVP 0.48 mm 26 AWG 8-core black
Number of
cores
8
Fireproof class CM
Length 15 m in the case of cable type 1 and 3 m in the case of cable type 2

21.4.3 RS-232/RS-422 Serial Port Cable
The RS-232/RS-422 serial port cable is used to transport the management signals between
subnets.
Both ends of the RS-232/RS-422 serial port cable use the RJ-45 connector. One end of the
RS-232/RS-422 serial port cable is connected to the RS-232/RS-422 serial port of the equipment.
The other end is connected to the RS-232/RS-422 serial port of another piece of equipment that
needs to make orderwire calls to the other equipment.
Structure
Figure 21-20 shows the structure of the RS-232/RS4-22 serial port cable.
Figure 21-20 Structure of the RS-232/RS-422 serial port cable
1. RJ-45 network interface connector 2. Main label A-A. Sectional view in direction A

Pin Assignments
Table 21-15 provides the pin assignments of the RS-232/RS-422 serial port cable.
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Table 21-15 Pin assignments of the RS-232/RS-422 serial port cable
Connector
X1
Connector X2 Relation Description
X1.3 X2.1 Twisted pair RX+
X1.6 X2.2 RX
X1.1 X2.3 Twisted pair TX+
X1.2 X2.6 TX
X1.5 X2.5 Twisted pair SG
X1.4 X2.8 232RX
X1.8 X2.4 Single 232TX

Technical Specifications
Item Description
Connector X1/X2 Network interface connector RJ-45 connector 8-pin 8-bit
shielded connector
Cable type Symmetrical twisted-pair cable 120 ohms SEYPVPV 0.5 mm
24 AWG 8-core PANTONE 430U
Number of cores 8
Fireproof class CM
Length 15 m

21.4.4 Ordinary Telephone Line
The ordinary telephone line is used to connect the orderwire phone. Both ends of the ordinary
telephone line use the RJ-45 connector. One end of the ordinary telephone line is connected to
the PHONE interface of the equipment, and the other end is connected to the interface of the
orderwire phone.
Structure
Figure 21-21 shows the structure of the ordinary telephone line.
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Figure 21-21 Structure of the ordinary telephone line
1. RJ-45 connector 2. Main label

Pin Assignments
Table 21-16 provides the pin assignments of the ordinary telephone line.
Table 21-16 Pin assignments of the ordinary telephone line
Connector X1 Connector X2 Description
X1.1 X2.1 Not connected
X1.2 X2.2 Not connected
X1.3 X2.3 TIP
X1.4 X2.4 RING
X1.5 X2.5 Not connected
X1.6 X2.6 Not connected

Technical Specifications
Item Description
Connector X1/X2 Network interface connector 6-pin 26 to 28 AWG
Cable type
Power cable 150 V UL20251 0.08 mm
2
28 AWG black
1 A 2-core telephone line
Number of cores 2
Fireproof class CM
Length 15 m

21.4.5 COA Cascading Cable
When multiple COAs are installed in a cabinet, use COA cascading cables to cascade the COAs.
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Both ends of the COA cascading cable use the DB9 connector. One end of the COA cascading
cable is connected to the RS232-1 serial port of one COA, and the other end is connected to the
RS232-2 serial port of another COA.
Structure
Figure 21-22 shows the structure of the COA cascading cable.
Figure 21-22 Structure of the COA cascading cable
1. Cable connector DB9 male 2. Label A-A. Sectional view in direction A

Pin Assignments
Table 21-17 provides the pin assignments of the COA cascading cable.
Table 21-17 Pin assignments of the COA cascading cable
Connector X1 Connector X2 Remarks
3 2 One pair
2 3
5 5 Grounding

Technical Specifications
Item Description
Connector X1/X2 Cable connector type D 9-pin male
Cable type Symmetrical twisted-pair cable 100 ohms UL2464 0.32 mm
28 AWG 2P Huawei grey
Number of cores Two pairs
Fireproof class CM
Length 0.6 m and 2.5 m

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21.4.6 Straight Through Cable
The straight through cable uses the RJ-45 connector to connect to the equipment at both ends.
The straight through cable is used to connect the OptiX OSN equipment, network management
computer, and Ethernet to realize communication.
Structure
Figure 21-23 shows the structure of the straight through cable.
Figure 21-23 Structure of the straight through cable
1. RJ-45 network interface connector 2. Label 1 3. Main label 4. Label 2

Pin Assignments
Table 21-18 provides the pin assignments of the straight through cable.
Table 21-18 Pin assignments of the straight through cable
Connector X1 Connector X2 Color Relation
X1.1 X2.1 White/Orange Twisted pair
X1.2 X2.2 Orange
X1.3 X2.3 White/Green Twisted pair
X1.6 X2.6 Green
X1.4 X2.4 Blue Twisted pair
X1.5 X2.5 White/Blue
X1.7 X2.7 White/Brown Twisted pair
X1.8 X2.8 Brown

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Technical Specifications
Item Description
Connector X1/X2 Network interface connector RJ-45 connector 8-pin 8-bit
shielded connector 24 to 26 AWG CAT 6/configured with the
SFTP network cable
Cable type Communication cable 10015 ohms CAT5E SFTP 24 AWG 8-
core PANTONE 445U
Number of cores 8
Fireproof class CM
Length 5 m, 10 m, 20 m, and 30 m

21.4.7 Crossover Cable
The crossover cable is used to connect the OptiX OSN equipment to an NM computer.
Both ends of the crossover cable use the RJ-45 connector. One end of the crossover cable is
connected to the ETH interface of the equipment, and the other end is connected to the network
interface of the NM computer.
Structure
Figure 21-24 shows the structure of the crossover cable.
Figure 21-24 Structure of the crossover cable
1. RJ-45 network interface connector 2. Label 1 3. Main label 4. Network cable 5. Label 2

Pin Assignments
Table 21-19 provides the pin assignments of the crossover cable.
Table 21-19 Pin assignments of the crossover cable
Connector X1 Connector X2 Color Relation
X1.6 X2.2 Orange Twisted pair
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Connector X1 Connector X2 Color Relation
X1.3 X2.1 White/Orange
X1.1 X2.3 White/Green Twisted pair
X1.2 X2.6 Green
X1.4 X2.4 Blue Twisted pair
X1.5 X2.5 White/Blue
X1.7 X2.7 White/Brown Twisted pair
X1.8 X2.8 Brown

Technical Specifications
Item Description
Connector X1/X2 Network interface connector RJ-45 connector 8-pin 8-bit
shielded connector 24 to 26 AWG CAT 6/configured with the
SFTP network cable
Cable type Communication cable 1005 ohms CAT5E SFTP 24 AWG 8-
core PANTONE 646U
Number of cores 8
Fireproof class CM
Length 5 m and 30 m

21.5 Signal Cable
The signal cables include the E1/E3 signal cable, framed E1 signal cable, and Nx64 kbit/s signal
cable.
21.5.1 75-ohm 8xE1 Cable
The 75-ohm 8xE1 cable is used to receive and transmit E1 signals.
21.5.2 120-ohm 8xE1 Cable
The 120-ohm 8xE1 cable is used to receive and transmit E1 signals.
21.5.3 E3/T3/STM-1 Cable
The E3/T3/STM-1 cable is used to receive and transmit E3/T3/STM-1 electrical signals. The
E3/T3/STM-1 cable uses an SMB connector at one end to connect to the E3/T3/STM-1 electrical
access board. The other end of the E3/T3/STM-1 cable is connected to the DDF. The connector
needs to be prepared on site as required.
21.5.4 Framed E1 Cable
The framed E1 cable is connected to the DB44 connector of the DM12 to access eight channels
of framed E1 signals.
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21.5.5 Nx64 kbit/s Cable
The Nx64 kbit/s cable is connected to the DB28 connector of the DM12 to access one channel
of Nx64 kbit/s signals.
21.5.1 75-ohm 8xE1 Cable
The 75-ohm 8xE1 cable is used to receive and transmit E1 signals.
The 75-ohm 8xE1 cable uses a DB44 connector at one end to connect to the D75S. The other
end of the 75-ohm 8xE1 cable is connected to the digital distribution frame (DDF). The connector
needs to be prepared on site as required. Each 75-ohm 8xE1 cable can transmit 8xE1 signals.
Structure
Figure 21-25 shows the structure of the 75-ohm 8xE1 cable.
Figure 21-25 Structure of the 75-ohm 8xE1 cable
Pos.1
View A
1
Pos.44
A
MO55
Main label
X
W
L
1. Cable connector type D 44-pin male 2. Main label

Pin Assignments
Table 21-20 provides the pin assignments of the 75-ohm 8xE1 cable.
Table 21-20 Pin assignments of the 75-ohm 8xE1 cable
Connector Cable W Remarks Connector Cable W Remarks
Core No. Core No.
38 Ring 1 R1 34 Ring 9 R5
23 Tip 19 Tip
37 Ring 3 R2 33 Ring 11 R6
22 Tip 18 Tip
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Connector Cable W Remarks Connector Cable W Remarks
Core No. Core No.
36 Ring 5 R3 32 Ring 13 R7
21 Tip 17 Tip
35 Ring 7 R4 31 Ring 15 R8
20 Tip 16 Tip
15 Ring 2 T1 11 Ring 10 T5
30 Tip 26 Tip
14 Ring 4 T2 10 Ring 12 T6
29 Tip 25 Tip
13 Ring 6 T3 9 Ring 14 T7
28 Tip 24 Tip
12 Ring 8 T4 8 Ring 16 T8
27 Tip 7 Tip
Shell External braid shield layer/Without
the external braid shield layer
Shell External braid shield layer/
Without the external braid shield
layer

Technical Specifications
The external layer of the 75-ohm E1 cable may be of the shielded type or unshielded type. The
specifications of the 75-ohm E1 cable with the shielded layer are different from the specifications
of the 75-ohm E1 cable with the unshielded layer. Table 21-21 lists the specifications of the 75-
ohm E1 cable with the external braid shield layer. Table 21-22 lists the specifications of the 75-
ohm E1 cable without the external braid shield layer.
Table 21-21 Specifications of the 75-ohm E1 cable with the external braid shield layer
Item Description
Connector X Connector accessories type D 44-pin male cable welding type
3-row pins
Cable type Coaxial cable SYFVZP-LC 75-1-1x16 75 ohms 13.10 mm
1.2 mm 0.254 mm Pantone Warm Gray 1U
Fireproof class Complies with IEC603323C.
Number of cores 16 cores, 8xE1
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Item Description
Diameter of the
shielding layer
diameter of the
internal insulation
layer diameter of the
internal conductor
13.10 mm 1.2 mm 0.254 mm
Length 3 m, 10 m, 15 m, 20 m, 25 m, 30 m, 35 m, 40 m, 45 m, and 50 m

Table 21-22 Specifications of the 75-ohm E1 cable without the external braid shield layer
Item Description
Connector X Connector accessories type D 44-pin male cable welding type
3-row pins
Cable type Coaxial cable SYFVZP-LC 75-1-1x16 75 ohms 12.40 mm
1.2 mm 0.254 mm Pantone Warm Gray 1U
Fireproof class Complies with IEC603323C.
Number of cores 16 cores, 8xE1
Diameter of the
shielding layer
diameter of the
internal insulation
layer diameter of the
internal conductor
12.40 mm 1.2 mm 0.254 mm
Length 5 m, 10 m, 15 m, 20 m, 25 m, 30 m, 35 m, 40 m, 45 m, and 50 m

CAUTION
The pin assignment table is delivered with the 75-ohm 8xE1 cable in a packing bag. You must
keep the table carefully.
21.5.2 120-ohm 8xE1 Cable
The 120-ohm 8xE1 cable is used to receive and transmit E1 signals.
The 120-ohm 8xE1 cable uses a DB44 connector at one end to connect to the 120-ohm E1
electrical interface board. The other end of the 120-ohm 8xE1 cable is connected to the DDF.
The connector needs to be prepared on site as required. Each 120-ohm 8xE1 cable can transmit
8xE1 signals.
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Structure
Figure 21-26 shows the structure of the 120-ohm 8xE1 cable.
Figure 21-26 Structure of the 120-ohm 8xE1 cable
1. Cable connector type D 44-pin male 2. Label 1, marked with "W1 (TX18)"
3. Label 3, marked with "W2 (RX18)" 4. Main label

Pin Assignments
Table 21-23 provides the pin assignments of the 120-ohm 8xE1 cable.
Table 21-23 Pin assignments of the 120-ohm 8xE1 cable
Connecto
r
Cable W1 Remar
ks
Connecto
r
Cable W2 Remar
ks
Core No. Core No.
15 Blue Twisted
pair
TX1 38 Blue Twisted
pair
RX1
30 White 23 White
14 Orang
e
Twisted
pair
TX2 37 Orang
e
Twisted
pair
RX2
29 White 22 White
13 Green Twisted
pair
TX3 36 Green Twisted
pair
RX3
28 White 21 White
12 Brow
n
Twisted
pair
TX4 35 Brown Twisted
pair
RX4
27 White 20 White
11 Grey Twisted
pair
TX5 34 Grey Twisted
pair
RX5
26 White 19 White
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Connecto
r
Cable W1 Remar
ks
Connecto
r
Cable W2 Remar
ks
Core No. Core No.
10 Blue Twisted
pair
TX6 33 Blue Twisted
pair
RX6
25 Red 18 Red
9 Orang
e
Twisted
pair
TX7 32 Orang
e
Twisted
pair
RX7
24 Red 17 Red
8 Green Twisted
pair
TX8 31 Green Twisted
pair
RX8
7 Red 16 Red
Shell External braided shield Shell External braided shield

Technical Specifications
Item Description
Connector X Cable connector type D 44-pin male
Cable type Communication cable 120 ohms SEYPVPV 0.5 mm 24 AWG
16-core PANTONE 430U
Number of cores 16
Diameter of the
internal conductor
0.5 mm
Fireproof class CM
Length 10 m, 15 m, 20 m, 30 m, and 40 m

21.5.3 E3/T3/STM-1 Cable
The E3/T3/STM-1 cable is used to receive and transmit E3/T3/STM-1 electrical signals. The
E3/T3/STM-1 cable uses an SMB connector at one end to connect to the E3/T3/STM-1 electrical
access board. The other end of the E3/T3/STM-1 cable is connected to the DDF. The connector
needs to be prepared on site as required.
Structure
Figure 21-27 shows the structure of the E3/T3/STM-1 cable.
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Figure 21-27 Structure of the E3/T3/STM-1 cable
1. Coaxial connector SMB 2. Main label 3. Coaxial cable

Pin Assignments
None.
Technical Specifications
Item Description
Connector Coaxial connector SMB connector 75 ohms straight female
Cable I Coaxial cable 75 ohms 3.9 mm 2.1 mm 0.34 mm shielded
Diameter of the shielding layer diameter of the internal insulation layer
diameter of the internal conductor: 3.9 mm 2.1 mm 0.34 mm
Length: 10 m, 15 m, 20 m, and 30 m
Cable II Coaxial cable 75 ohms 4.4 mm 2.4 mm 0.4 mm shielded grey
Diameter of the shielding layer diameter of the internal insulation layer
diameter of the internal conductor: 4.4 mm 2.4 mm 0.4 mm
Length: 15 m, 20 m, 25 m, 30 m, and 40 m
Cable III Coaxial cable 75 ohms 6.7 mm 3.8 mm 0.61 mm shielded
grey
Diameter of the shielding layer diameter of the internal insulation layer
diameter of the internal conductor: 6.7 mm 3.8 mm 0.61 mm
Length: 15 m, 20 m, 25 m, 30 m, and 130 m
Cable IV Coaxial cable 75 ohms 5.80 mm 3.71 mm 0.643 mm black
Diameter of the shielding layer diameter of the internal insulation layer
diameter of the internal conductor: 5.80 mm 3.71 mm 0.643 mm
Length: 30 cm
Fireproof class CM

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21.5.4 Framed E1 Cable
The framed E1 cable is connected to the DB44 connector of the DM12 to access eight channels
of framed E1 signals.
The framed E1 cables are available in two types, namely, 75-ohm framed E1 cable and 120-ohm
framed E1 cable.
l For the structure, pin assignments, and technical specifications of the 75-ohm framed E1
cable, see the topic that describes the 75-ohm 8xE1 cable.
l For the structure, pin assignments, and technical specifications of the 120-ohm framed E1
cable, see the topic that describes the 120-ohm 8xE1 cable.
21.5.5 Nx64 kbit/s Cable
The Nx64 kbit/s cable is connected to the DB28 connector of the DM12 to access one channel
of Nx64 kbit/s signals.
Table 21-24 provides the pin assignments of the DB28 connector.
Table 21-24 Pin assignments of the DB28 connector of the DM12
Pin Signal Direction Description
1 TXD+ ---> Transmits data.
2 TXD ---> Transmits data.
3 TXC+ <--> Transmits the clock signal provided by the
DCE to the DTE.
4 TXC <--> Transmits the clock signal provided by the
DCE to the DTE.
5 NC - -
6 GND ----- Circuit_GND
7 MODE0 <--- Receives the signal that identifies the type of
cable.
8 MODE1 <--- Receives the signal that identifies the type of
cable.
9 MODE2 <--- Receives the signal that identifies the type of
cable.
10 MODE_DC
E
<--- Receives the signal that identifies the type of
DCE/DTE cable.
11 DCD+ <--> Detects the carrier.
12 DCD <--> Detects the carrier.
13 RTS+ ---> Requests for transmission.
14 RTS ---> Requests for transmission.
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Pin Signal Direction Description
15 TXCE+ ---> Transmits the data clock in the case of the
DCE and loops back the clock in the case of
the DTE.
16 TXCE ---> Transmits the data clock in the case of the
DCE and loops back the clock in the case of
the DTE.
17 RXC+ <--- Receives clock signals.
18 RXC <--- Receives clock signals.
19 RXD+ <--- Receives data.
20 RXD <--- Receives data.
21 GND ----- Shield_GND
22 LL <--> Receives the loopback control signal.
23 CTS+ <--- Permits the transmission.
24 CTS <--- Permits the transmission.
25 DSR+ <--- Receives the DCE ready signal.
26 DSR <--- Receives the DCE ready signal.
27 DTR+ ---> Transmits the DTE ready signal.
28 DTR ---> Transmits the DTE ready signal.

The Nx64 kbit/s cables are classified into the following categories according to the protocol,
which the Nx64 kbit/s signals comply with:
l V.35 DCE cable
l V.35 DTE cable
l V.24 DCE cable
l V.24 DTE cable
l X.21 DCE cable
l X.21 DTE cable
l RS-449 DCE cable
l RS-449 DTE cable
l RS-530 DCE cable
l RS-530 DTE cable
V.35 DCE Cable
Figure 21-28 shows the structure of the V.35 DCE cable.
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21-37
Figure 21-28 Structure of the V.35 DCE cable
2 1
Pos.28
Pos.1
A-A
A
3
B
D
J
N
T
X
BB
FF
LL
B
F
L
R
V
Z
DD
JJ
NN
C
H
M
S
W
AA
EE
KK
A
E
K
P
U
Y
CC
HH
MM
X1 X2
W
B-B
1. Cable connector D28 male 2. Main label
3. Cable connector D34 female + D34 plastic shell -

Table 21-25 provides the pin assignments of the V.35 DCE cable.
Table 21-25 Pin assignments of the V.35 DCE cable
Connector X1 Connector X2 Relation
19 P Twisted pair
20 S
1 R Twisted pair
2 T
15 V Twisted pair
16 X
3 Y Twisted pair
4 AA
17 U Twisted pair
18 W
11 F -
22 J -
23 C -
13 D -
25 H -
27 E -
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Connector X1 Connector X2 Relation
21 B -
6 + 7 + 8 A Pins 6, 7, and 8 are short-
circuited.

The technical specifications of the V.35 DCE cable are as follows.
Item Description
Connector X1 Cable connector type-D dualedge subassembly 28-pin straight
male cable welding type spacing 0.80 mm matching with 28 to
30 AWG, exclusively used by the OEM
Connector X2 Cable connector V35 plug 34-pin molding shell kit, exclusively
used by the OEM
Cable connector V35 DCE plug 34-pin female cable crimping
type housing core, exclusively used by the OEM
Cable type Symmetrical twisted-pair cable 100 ohms 0.38 mm 28 AWG 5
pairs 8 cores PANTONE 296U exclusively used by the OEM
Number of cores Five pairs and eight cores
Diameter of the
core
0.32 mm
Length 3 m

V.35 DTE Cable
Figure 21-29 shows the structure of the V.35 DTE cable.
Figure 21-29 Structure of the V.35 DTE cable
A-A B-B
2 1
Pos.28
Pos.1
A
D
J
N
T
X
BB
FF
LL
B
F
L
R
V
Z
DD
JJ
NN
C
H
M
S
W
AA
EE
KK
A
E
K
P
U
Y
CC
HH
MM
3 4
B
5
X2 X1
W
1. Cable connector D28 male 2. Main label 3. Cable connector D34 plastic shell
4. Ordinary terminal 5. Cable connector D34 male
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Table 21-26 provides the pin assignments of the V.35 DTE cable.
Table 21-26 Pin assignments of the V.35 DTE cable
Connector X1 Connector X2 Relation
1 P Twisted pair
2 S
19 R Twisted pair
20 T
17 V Twisted pair
18 X
3 Y Twisted pair
4 AA
15 U Twisted pair
16 W
11 F -
22 J -
13 C -
23 D -
27 H -
25 E -
21 B -
6 + 10 + 7 + 8 A Pins 6, 7, 8, and 10 are short-
circuited.

The technical specifications of the V.35 DTE cable are as follows.
Item Description
Connector X1 Cable connector type-D dualedge subassembly 28-pin straight male
cable welding type spacing 0.80 mm matching with 28 to 30 AWG,
exclusively used by the OEM
Connector X2 Cable connector V35 plug 34-pin molding shell kit, exclusively used
by the OEM
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Item Description
Cable connector V35 DTE plug 34-pin female cable crimping type
housing core, exclusively used by the OEM
Cable type Symmetrical twisted-pair cable 100 ohms 0.38 mm 28 AWG 5 pairs
8 cores PANTONE 296U exclusively used by the OEM
Number of
cores
Five pairs and eight cores
Diameter of
the core
0.32 mm
Length 3 m

V.24 DCE Cable
Figure 21-30 shows the structure of the V.24 DCE cable.
Figure 21-30 Structure of the V.24 DCE cable
2 3
Pos.1
Pos.28
A B
Pos.25
Pos.1
1
X1 X2
W
A-A B-B
1. Cable connector D25 female 2. Main label 3. Cable connector D28 male

Table 21-27 provides the pin assignments of the V.24 DCE cable.
Table 21-27 Pin assignments of the V.24 DCE cable
Connector X1 Connector X2 Relation
19 2 Twisted pair
1 3
23 4 Twisted pair
13 5
25 20 Twisted pair
27 6
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Connector X1 Connector X2 Relation
11 8 Twisted pair
22 18
3 15 Twisted pair
17 24
15 17 -
21 1 Single
6 + 7 7 Pins 6 and 7 are short-
circuited.

The technical specifications of the V.24 DCE cable are as follows.
Table 21-28 Technical specifications of the V.24 DCE cable
Item Description
Connector X1 Cable connector type-D dualedge subassembly 28-pin straight
male cable welding type spacing 0.80 mm matching with 28 to 30
AWG, exclusively used by the OEM
Connector X2 Cable connector type D 25-pin female cable welding type
Cable type Symmetrical twisted-pair cable 100 ohms 0.38 mm 28 AWG 5 pairs
8 cores PANTONE 296U exclusively used by the OEM
Number of
cores
Five pairs and eight cores
Diameter of the
core
0.32 mm
Length 3 m

V.24 DTE Cable
Figure 21-31 shows the structure of the V.24 DTE cable.
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Figure 21-31 Structure of the V.24 DTE cable
2 3 1
Pos.1
Pos.28
A B
Pos.1
Pos.25
X1
X2
W
A-A B-B
1. Cable connector D25 male 2. Main label 3. Cable connector D28 male

Table 21-29 provides the pin assignments of the V.24 DTE cable.
Table 21-29 Pin assignments of the V.24 DTE cable
Connector X1 Connector X2 Relation
1 2 Twisted pair
19 3
13 4 Twisted pair
23 5
27 20 Twisted pair
25 6
11 8 Twisted pair
22 18
3 15 Twisted pair
15 24
17 17 -
21 1 Single
6 + 10 + 7 7 Pins 6, 10, and 7 are short-
circuited.

The technical specifications of the V.24 DTE cable are as follows.
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Table 21-30 Technical specifications of the V.24 DTE cable
Item Description
Connector X1 Cable connector type-D dualedge subassembly 28-pin straight male
cable welding type spacing 0.80 mm matching with 28 to 30 AWG,
exclusively used by the OEM
Connector X2 Cable connector type D 25-pin male cable welding type
Cable type Symmetrical twisted-pair cable 100 ohms 0.38 mm 28 AWG 5 pairs
8 cores PANTONE 296U exclusively used by the OEM
Number of
cores
Five pairs and eight cores
Diameter of the
core
0.32 mm
Length 3 m

X.21 DCE Cable
Figure 21-32 shows the structure of the X.21 DCE cable.
Figure 21-32 Structure of the X.21 DCE cable
2 3
Pos.1
Pos.28
B
A
Pos.15
Pos.1
1
X1 X2
W
A-A B-B
1. Cable connector D15 female 2. Main label 3. Cable connector D28 male

Table 21-31 provides the pin assignments of the X.21 DCE cable.
Table 21-31 Pin assignments of the X.21 DCE cable
Connector X1 Connector X2 Relation
13 5 Twisted pair
14 12
23 3 Twisted pair
24 10
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Connector X1 Connector X2 Relation
19 2 Twisted pair
20 9
1 4 Twisted pair
2 11
15 6 Twisted pair
16 13
21 1
6 + 9 8 Pins 6 and 9 are short-
circuited.

The technical specifications of the X.21 DCE cable are as follows.
Table 21-32 Technical specifications of the X.21 DCE cable
Item Description
Connector X1 Cable connector type-D dualedge subassembly 28-pin straight male
cable welding type spacing 0.80 mm matching with 28 to 30 AWG,
exclusively used by the OEM
Connector X2 Cable connector type D 15-pin female cable welding type
Cable type Symmetrical twisted-pair cable 100 ohms 0.38 mm 28 AWG 5 pairs
8 cores PANTONE 296U exclusively used by the OEM
Number of
cores
Five pairs and eight cores
Diameter of
the core
0.32 mm
Length 3 m

X.21 DTE Cable
Figure 21-33 shows the structure of the X.21 DTE cable.
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21-45
Figure 21-33 Structure of the X.21 DTE cable
2 3
Pos.1
Pos.28
B
A
Pos.1
Pos.15
1
X2 X1
W
A-A B-B
1. Cable connector D15 male 2. Main label 3. Cable connector D28 male

Table 21-33 provides the pin assignments of the X.21 DTE cable.
Table 21-33 Pin assignments of the X.21 DTE cable
Connector X1 Connector X2 Relation
13 3 Twisted pair
14 10
23 5 Twisted pair
24 12
19 4 Twisted pair
20 11
1 2 Twisted pair
2 9
15 6 Twisted pair
16 13
17 6 Twisted pair
18 13
21 1
6 + 10 + 9 8 Pins 6, 10, and 9 are short-
circuited.

The technical specifications of the X.21 DTE cable are as follows.
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Table 21-34 Technical specifications of the X.12 DTE cable
Item Description
Connector X1 Cable connector type-D dualedge subassembly 28-pin straight
male cable welding type spacing 0.80 mm matching with 28 to 30
AWG, exclusively used by the OEM
Connector X2 Cable connector type D 15-pin male cable welding type
Cable type Symmetrical twisted-pair cable 100 ohms 0.38 mm 28 AWG 5 pairs
8 cores PANTONE 296U exclusively used by the OEM
Number of
cores
Five pairs and eight cores
Diameter of the
core
0.32 mm
Length 3 m

RS-449 DCE Cable
Figure 21-34 shows the structure of the RS-449 DCE cable.
Figure 21-34 Structure of the RS-449 DCE cable
2 3
Pos.1
Pos.28
B
A
Pos.1
Pos.15
1
X2 X1
W
A-A B-B
1. Cable connector D28 male 2. Main label 3. Cable connector D37 female I

Table 21-35 provides the pin assignments of the RS-449 DCE cable.
Table 21-35 Pin assignments of the RS-449 DCE cable
Connector X1 Connector X2 Relation
27 11 Twisted pair
28 29
25 12 Twisted pair
26 30
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Connector X1 Connector X2 Relation
13 9 Twisted pair
14 27
23 7 Twisted pair
24 25
11 13 Twisted pair
12 31
19 4 Twisted pair
20 22
1 6 Twisted pair
2 24
15 8 Twisted pair
16 26
17 17 Twisted pair
18 35
3 5 Twisted pair
4 23
22 10
21 1
6 + 8 19 Pins 6 and 8 are short-
circuited.

The technical specifications of the RS-449 DCE cable are as follows.
Table 21-36 Technical specifications of the RS-449 DCE cable
Item Description
Connector X1 Cable connector type-D dualedge subassembly 28-pin straight
male cable welding type spacing 0.80 mm matching with 28 to
30 AWG, exclusively used by the OEM
Connector X2 Cable connector type D 37-pin female cable welding type,
exclusively used by the OEM
Cable type Symmetrical twisted-pair cable 100 ohms communication cable
0.32 mm 28 AWG 26-core PANTONE 296U exclusively used
by the OEM
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Item Description
Number of cores 26
Diameter of the
core
0.32 mm
Length 3 m

RS-449 DTE Cable
Figure 21-35 shows the structure of the RS-449 DTE cable.
Figure 21-35 Structure of the RS-449 DTE cable
Pos.28
2 1 3
Pos.1
B A
Pos.37
Pos.1
X2
X1
W
A-A B-B
1. Cable connector D28 male 2. Main label 3. Cable connector D37 male I

Table 21-37 provides the pin assignments of the RS-449 DTE cable.
Table 21-37 Pin assignments of the RS-449 DTE cable
Connector X1 Connector X2 Relation
27 12 Twisted pair
28 30
25 11 Twisted pair
26 29
13 7 Twisted pair
14 25
23 9 Twisted pair
24 27
11 13 Twisted pair
12 31
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Connector X1 Connector X2 Relation
19 6 Twisted pair
20 24
1 4 Twisted pair
2 22
15 17 Twisted pair
16 35
17 8 Twisted pair
18 26
3 5 Twisted pair
4 23
22 10 -
21 1 -
6 + 8 + 10 19 Pins 6, 8, and 10 are short-
circuited.

The technical specifications of the RS-449 DTE cable are as follows.
Table 21-38 Technical specifications of the RS-449 DTE cable
Item Description
Connector X1 Cable connector type-D dualedge subassembly 28-pin straight male
cable welding type spacing 0.80 mm matching with 28 to 30 AWG,
exclusively used by the OEM
Connector X2 Cable connector type D SUB plug 37-pin straight male cable
welding type two rows, standard installation holes, exclusively used by
the OEM
Cable type Symmetrical twisted-pair cable 100 ohms communication cable 0.32
mm 28 AWG 26-core PANTONE 296U exclusively used by the
OEM
Number of
cores
26
Diameter of
the core
0.32 mm

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RS-530 DCE Cable
Figure 21-36 shows the structure of the RS-530 DCE cable.
Figure 21-36 Structure of the RS-530 DCE cable
Pos.1
2 3 1
Pos.1
Pos.28
A B
Pos.25
X1
X2
W
B-B A-A
1. Cable connector D25 female 2. Main label 3. Cable connector D28 male

Table 21-39 provides the pin assignments of the RS-530 DCE cable.
Table 21-39 Pin assignments of the RS-530 DCE cable
Connector X1 Connector X2 Relation
28 22 Twisted pair
27 6
26 23 Twisted pair
25 20
24 19 Twisted pair
23 4
22 18 Single
21 1 Single
20 14 Twisted pair
19 2
18 11 Twisted pair
17 24
16 9 Twisted pair
15 17
14 13 Twisted pair
13 5
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Connector X1 Connector X2 Relation
12 10 Twisted pair
11 8
4 12 Twisted pair
3 15
2 16 Twisted pair
1 3
6 + 7 + 9 7 Pins 6, 7, and 9 are short-
circuited.

The technical specifications of the RS-530 DCE cable are as follows.
Table 21-40 Technical specifications of the RS-530 DCE cable
Item Description
Connector X1 Cable connector type-D dualedge subassembly 28-pin straight
male cable welding type spacing 0.80 mm matching with 28 to 30
AWG, exclusively used by the OEM
Connector X2 Cable connector type D 25-pin female cable welding type
Cable type Symmetrical twisted-pair cable 100 ohms communication cable 0.32
mm 28 AWG 26-core PANTONE 296U exclusively used by the
OEM
Number of
cores
26
Diameter of the
core
0.32 mm
Length 3 m

RS-530 DTE Cable
Figure 21-37 shows the structure of the RS-530 DTE cable.
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Figure 21-37 Structure of the RS-530 DTE cable
A-A
Pos.28
2 3 1
Pos.1
A B
Pos.1
Pos.25
X1
X2
W
B-B
1. Cable connector D25 male 2. Main label 3. Cable connector D28 male

Table 21-41 provides the pin assignments of the RS-530 DTE cable.
Table 21-41 Pin assignments of the RS-530 DTE cable
Connector X1 Connector X2 Relation
27 20 Twisted pair
28 23
25 6 Twisted pair
26 22
13 4 Twisted pair
14 19
23 5 Twisted pair
24 13
11 8 Twisted pair
12 10
19 3 Twisted pair
20 16
1 2 Twisted pair
2 14
15 24 Twisted pair
16 11
17 17 Twisted pair
18 9
3 15 Twisted pair
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Connector X1 Connector X2 Relation
4 12
22 18
21 1
6 + 7 + 9 + 10 7 Pins 6, 7, 9, and 10 are short-
circuited.

The technical specifications of the RS-530 DTE cable are as follows.
Table 21-42 Technical specifications of the RS-530 DTE cable
Item Description
Connector X1 Cable connector type-D dualedge subassembly 28-pin straight male
cable welding type spacing 0.80 mm matching with 28 to 30 AWG,
exclusively used by the OEM
Connector X2 Cable connector type D 25-pin male cable welding type
Cable type Symmetrical twisted-pair cable 100 ohms communication cable 0.32
mm 28 AWG 26-core PANTONE 296U exclusively used by the
OEM
Number of
cores
26
Diameter of the
core
0.32 mm
Length 3 m

21.6 Clock Cable
The clock cables include the clock cable and clock transit cable.
21.6.1 Clock Cable
The clock cables are available in two types, namely, 75-ohm clock cable and 120-ohm clock
cable. The clock cable is used to receive and transmit external clock signals. In the case of the
75-ohm clock cable, the cable uses an SMB connector at one end to connect to the external clock
interface of the OptiX OSN equipment. The other end of the cable is connected to the external
clock equipment. The connector needs to be prepared on site as required. In the case of the 120-
ohm clock cable, the cable uses an RJ-45 connector at one end to connect to the external clock
interface of the OptiX OSN equipment. The other end of the cable is connected to the external
clock equipment. The connector needs to be prepared on site as required.
21.6.2 One-Channel Clock Transit Cable and Two-Channel Clock Transit Cable
The clock transit cables are available in two types, namely, one-channel 75-ohm-to-120-ohm
clock transit cable and two-channel 75-ohm-to-120-ohm clock transit cable.
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21.6.1 Clock Cable
The clock cables are available in two types, namely, 75-ohm clock cable and 120-ohm clock
cable. The clock cable is used to receive and transmit external clock signals. In the case of the
75-ohm clock cable, the cable uses an SMB connector at one end to connect to the external clock
interface of the OptiX OSN equipment. The other end of the cable is connected to the external
clock equipment. The connector needs to be prepared on site as required. In the case of the 120-
ohm clock cable, the cable uses an RJ-45 connector at one end to connect to the external clock
interface of the OptiX OSN equipment. The other end of the cable is connected to the external
clock equipment. The connector needs to be prepared on site as required.
Structure
Figure 21-38 shows the structure of the 75-ohm clock cable. Figure 21-39 shows the structure
of the 120-ohm clock cable.
Figure 21-38 Structure of the 75-ohm clock cable
1. Coaxial connector SMB 2. Label

Figure 21-39 Structure of the 120-ohm clock cable
1. Label 1 (R) and label 2 (T) 2. Communication cable 3. Main label 4. Network interface connector RJ-45

Pin Assignments
Table 21-43 provides the pin assignments of the 120-ohm clock cable.
Table 21-43 Pin assignments of the 120-ohm clock cable
X1 W Remarks
X1.1 Blue W1
X1.2 White
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X1 W Remarks
X1.4 Orange W2
X1.5 White

Technical Specifications
Item Description
75-ohm
clock cable
Connector: coaxial connector SMB 75 ohms straight female
Cable type: coaxial cable 75 ohms 3.9 mm 2.1 mm 0.34 mm shielded
Diameter of the shielding layer diameter of the internal insulation layer
diameter of the internal conductor: 3.9 mm 2.1 mm 0.34 mm
Length: 10 m, 15 m, 20 m, and 30 m
120-ohm
clock cable
Connector X: network interface connector 8-pin 8-bit shielded crystal
model connector
Cable type: symmetrical twisted-pair cable 120 ohms SEYPVPV 0.4 mm
26 AWG 2 pairs PANTONE 430U
Diameter of the internal conductor: 0.4 mm/26 AWG
Length: 5 m, 10 m, 20 m, 30 m, 40 m, 50 m, 70 m, and 100 m

21.6.2 One-Channel Clock Transit Cable and Two-Channel Clock
Transit Cable
The clock transit cables are available in two types, namely, one-channel 75-ohm-to-120-ohm
clock transit cable and two-channel 75-ohm-to-120-ohm clock transit cable.
Structure
Figure 21-40 shows the structure of the one-channel 75-ohm-to-120-ohm clock transit
cable.Figure 21-41 shows the structure of the two-channel 75-ohm-to-120-ohm clock transit
cable.
21 Cables
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Figure 21-40 Structure of the one-channel 75-ohm-to-120-ohm clock transit cable
1. Coaxial connector SMB 75 ohms straight/plug
female
2. Main label 3. 75-ohm-to-120-ohm transit PCB

Figure 21-41 Structure of the two-channel 75-ohm-to-120-ohm clock transit cable
1. Coaxial connector SMB 75 ohms straight/plug female 2. Label 1: "1#" 3. Label 2: "2#" 4. Main label
5. 75-ohm-to-120-ohm transit PCB 6. Label 3: "1#" 7. Label 4: "2#"

Pin Assignments
Table 21-44 provides the pin assignments of the two-channel 75-ohm-to-120-ohm clock transit
cable.
Table 21-44 Pin assignments of the two-channel 75-ohm-to-120-ohm clock transit cable
Connector 75-ohm Cable Color 120-ohm Cable
X1 Core Blue W3
Shielding layer White
X2 Core Blue W4
Shielding layer White

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Technical Specifications
Item Description
One
channel
Connector: coaxial connector SMB 75 ohms straight female
75-ohm cable: coaxial cable 75 ohms 3.9 mm 2.1 mm 0.34 mm shielded
75-ohm cable: diameter of the shielding layer (3.9 mm) diameter of the
internal insulation layer (2.1 mm) diameter of the internal conductor (0.34
mm)
120-ohm cable: symmetrical twisted-pair cable 120 ohms SEYPVPV 0.4
mm 26 AWG 2 pairs PANTONE 430U
Diameter of the internal conductor of the 120-ohm cable: 0.4 mm/26 AWG
Length: 30 m
Two
channels
Connector X1/X2: coaxial connector SMB 75 ohms straight female
75-ohm cable: coaxial cable 75 ohms 3.9 mm 2.1 mm 0.34 mm shielded
75-ohm cable: diameter of the shielding layer (3.9 mm) diameter of the
internal insulation layer (2.1 mm) diameter of the internal conductor (0.34
mm)
120-ohm cable: symmetrical twisted-pair cable 120 ohms SEYPVPV 0.4
mm 26 AWG 2 pairs PANTONE 430U
Diameter of the internal conductor of the 120-ohm cable: 0.4 mm/26 AWG
Length: 30 m

21 Cables
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Issue 01 (2010-01-15)
22 Indicators
About This Chapter
This topic describes the indicators on the OptiX OSN equipment and the indicators on the boards
of the OptiX OSN equipment.
22.1 Indicators on the Cabinet
This topic describes the indicators on the cabinet of the OptiX OSN equipment.
22.2 Alarm Indicators on the Boards
This topic describes the alarm indicators on the boards.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 22 Indicators
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22-1
22.1 Indicators on the Cabinet
This topic describes the indicators on the cabinet of the OptiX OSN equipment.
Indicator Description
Power indicator Power (green) On: Power is supplied to the equipment.
Off: Power is not supplied to the equipment.
Critical alarm indicator Critical (red) On: A critical alarm occurs on the equipment.
Off: No critical alarm occurs on the equipment.
Major alarm indicator Major (orange) On: A major alarm occurs on the equipment.
Off: No major alarm occurs on the equipment.
Minor alarm indicator Minor
(yellow)
On: A minor alarm occurs on the equipment.
Off: No minor alarm occurs on the equipment.

22.2 Alarm Indicators on the Boards
This topic describes the alarm indicators on the boards.
Board Hardware Status Indicator (STAT)
Status Meaning
On (green) The board operates normally.
On (red) The hardware of the board is faulty or does not match
the equipment.
Off The board is not powered on or does not start to work.

Service Activation Status Indicator/Board Status (Active/Standby) Indicator (ACT)
Status Meaning of the Service
Activation Status Indicator
Meaning of the Board Status
(Active/Standby) Indicator
On (green) The services are activated. The
board is in the working state.
The board works as the working
board.
Off The services are not activated. The board works as the
protection board.

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Board Software Status Indicator (PROG)
Status Meaning
On (green) The board software or FPGA in the flash is
successfully loaded and stored, or the board software
is successfully initiated.
On for 100 ms and off for 100 ms
repeatedly (green)
The board software is being loaded to the flash or the
FPGA software is being loaded to the FPGA.
On for 300 ms and off for 300 ms
repeatedly (green)
l The board software is being initialized and is in the
BIOS boot state.
l The board is in the BIOS state because the board
is reset for three times in five minutes.
On (red) l The board software or FPGA in the flash is lost.
l The board software fails to be loaded.
l The board software fails to be initialized.
Off l No power is accessed.
l The high-power-consumption board enters the
low-power-consumption mode.

Service Alarm Indicator (SRV)
Type of Board Status Meaning
Service board On (green) The services are normal and no
service alarm is generated.
On (red) A critical or major alarm occurs in
the services.
On (yellow) A minor or remote alarm occurs in
the services.
Off The services are not configured and
no alarm is generated, or no power is
supplied to the board.
Cross-connect and timing
board
On (green) The services are normal and no
service alarm is generated.
On (red) A critical alarm occurs.
On (yellow) A minor alarm occurs.
Off The services are not configured and
no alarm is generated, or no power is
supplied to the board.
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Type of Board Status Meaning
System control board On (green) The services are normal and no
service alarm is generated.
On (red) A critical or major alarm occurs in
the subrack.
On (yellow) A minor or remote alarm occurs in
the subrack.
Off The services are not configured and
no alarm is generated, or no power is
supplied to the board.

Synchronization Clock Status Indicator (SYNC)
Status Meaning
On (green) l The clock works in free-run mode and the system
clock priority list is not set. By default, the system
clock priority list contains only internal sources.
l The clock works in locked mode and is tracing a
clock source other than the internal sources in the
priority list.
On (red) The system clock priority list is set. All the clock
sources, however, are lost except for the internal
clock sources. The clock works in holdover mode or
free-run mode.

Alarm Mute Indicator (ALMC)
Status Meaning
On (yellow) The board is in the alarm mute state.
Off When an alarm is generated, the equipment emits an alarm
sound.

Power Monitoring Indicators
Indicator Status Meaning
48 V power supply indicator of
channel A (PWRA)
On (green) The 48 V power supply of channel
A is normal.
22 Indicators
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Indicator Status Meaning
On (red) The 48 V power supply of channel
A is faulty (lost or failed).
48 V power supply indicator of
channel B (PWRB)
On (green) The 48 V power supply of channel B
is normal.
On (red) The 48 V power supply of channel B
is faulty (lost or failed).
+3.3 V backup power supply
indicator of the system (PWRC)
On (green) The +3.3 V backup power supply of
the system is normal.
On (red) The +3.3 V backup power supply of
the system is lost.

Ethernet Indicators
Indicator Status Meaning
Connection status indicator
LINK (green)
On The fiber cable is successfully
connected to the equipment.
Off The fiber cable is not connected to the
equipment.
Data receiving and
transmission indicator ACT
(orange)
Flashing The Ethernet interface is receiving or
transmitting data.
Off The Ethernet interface is not receiving
or transmitting data.

FAN Running Status Indicator (STATE)
Status Meaning
On (green) The fan operates normally.
On (red) The fan, fan power supply board, or fan control board
is abnormal.
On (yellow) The fan stops when the temperature is very low.

Indicators on the Front Panel of the COA
Indicator Status Meaning
Running indicator
RUN (green)
Flashing once every two
seconds (green)
The COA operates normally.
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Indicator Status Meaning
Flashing once every four
seconds (green)
The COA is in database protection mode.
The communication between the COA
and the SCC is interrupted.
Flashing five times every
second (green)
The program is being started or loaded.
Alarm indicator
ALM
On (red) Errors occur during the memory self-
check.
Flashing thrice every other
second (red)
A critical alarm occurs.
Flashing twice every other
second (red)
A major alarm occurs.
Flashing once every other
second (red)
A minor alarm occurs.

Power Indicator (POWER)
Status Meaning
On (green) The input of the power supply is normal.
Off No power is supplied or the power supply fails.

Indicators on the UPM
Module Indicator Status Meaning
Rectifier
module
RUN (green) On The rectifier module operates normally.
Off The rectifier module is faulty or is disabled.
ALM
(yellow)
Off The rectifier module operates normally.
On An alarm and revertive protection occur on
the module.
Flashing The communication is interrupted.
FAULT
(red)
On The rectifier module is faulty.
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Module Indicator Status Meaning
Monitoring
module
RUN Flashing
(green)
Flashing slowly (on for 1s and off for 1s
repeatedly): The entire power system is
normal.
Flashing quickly (on for 125 ms and off for
125 ms repeatedly): The power system is not
registered or the communication is
interrupted.
ALM On (red) The entire power system is faulty. In normal
situations, the indicator is off.

Indicators on the Microwave Boards
Indicator Status Meaning
Connection status indicator 1
(LINK1) two colors (red and
green)
On (green) The link at the microwave layer is
normal.
On (red) The link at the microwave layer is
faulty.
Connection status indicator 2
(LINK2) two colors (red and
green)
On (green) The link at the microwave layer is
normal.
On (red) The link at the microwave layer is
faulty.
Active/Standby state
indicator (ACT1) one color
(green)
On (green) The board is in the active state when
the board is in the 1+1 protection
system.
The board is activated when the board
is not protected.
Off The board is in the standby state when
the board is in the 1+1 protection
system.
The board is not activated when the
board is not protected.
Active/Standby state
indicator (ACT2) one color
(green)
On (green) The board is in the active state when
the board is in the 1+1 protection
system.
The board is activated when the board
is not protected.
Off The board is in the standby state when
the board is in the 1+1 protection
system.
The board is not activated when the
board is not protected.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 22 Indicators
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Indicator Status Meaning
Working indicator of ODU 1
(ODU1) two colors (red and
green)
On (green) ODU 1 operates normally.
On (red) ODU 1 is faulty.
Working indicator of ODU 2
(ODU2) two colors (red and
green)
On (green) ODU 2 operates normally.
On (red) ODU 2 is faulty.

22 Indicators
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Hardware Description
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Issue 01 (2010-01-15)
23 Labels
About This Chapter
This topic describes the safety labels and engineering labels on the OptiX OSN equipment.
23.1 Safety Labels
Various safety labels are affixed to the equipment. This topic provides the indications and
positions of the safety labels.
23.2 Engineering Labels
The engineering labels should be prepared according to the local engineering specifications or
Huawei engineering specifications.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 23 Labels
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23.1 Safety Labels
Various safety labels are affixed to the equipment. This topic provides the indications and
positions of the safety labels.
23.1.1 Label Description
Labels, such as the ESD protection label, grounding label, and fan warning label are affixed to
the subrack.
23.1.2 Label Position
The ESD protection label and grounding label are affixed to the subrack. The laser safety class
label and APD warning label are affixed to the front panel of the board.
23.1.1 Label Description
Labels, such as the ESD protection label, grounding label, and fan warning label are affixed to
the subrack.
Table 23-1 Labels on the equipment
Label Label Name Indication
ESD protection
label
The equipment is
sensitive to static
electricity.
CLASS 1
LASER
PRODUCT

LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS
CLASS 1M
LASER
PRODUCT
Laser safety class
label
The power class of the
laser source
Grounding label The grounding
position
ATTENTION
CLEAN PERIODICALLY
!
Periodic cleaning
label
The air filter should be
cleaned periodically.

DON'T TOUCH THE

FANLEAVESBEFORE
THEYSLOW DOWN!
Fan warning label The fan blades should
not be touched when
the fan is rotating.
! APD
Receiver
MAX:-9dBm
APD warning label The overload point of
the indicator is 9
dBm.
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Label Label Name Indication
RoHS label The equipment may
contain some of the
poisonous substances
specified by the
regulations in China,
but can be safely used
within a period of 50
years. The equipment
should be recycled or
reused after 50 years.
This device complies with Part 15 of the FCC Rules.
Operation is subject to the following two conditions:
(1) this device may not cause harmful interference,
and (2) this device must accept any interference
received, including interference that may cause
undesired operation.
POWER RATING: -48 -60V ; 20A

MADE IN CHINA

OptiX OSN 3500

HUAWEI TECHNOLOGIES CO.,LTD.
N14036
In the case of the enhanced subrack:
This device complies with Part 15 of the FCC Rules.
Operation is subject to the following two conditions:
(1) this device may not cause harmful interference,
and (2) this device must accept any interference
received, including interference that may cause
undesired operation.
POWER RATING: -48 -60V ; 28.4A

MADE IN CHINA

OptiX OSN 3500

HUAWEI TECHNOLOGIES CO.,LTD.
N14036
This device complies with Part 15 of the FCC Rules.
Operation is subject to the following two conditions:
(1) this device may not cause harmful interference,
and (2) this device must accept any interference
received, including interference that may cause
undesired operation.
POWER RATING: -48 -60V; 6A

MADE IN CHINA

OptiX OSN 3500 II

HUAWEI TECHNOLOGIES CO.,LTD.
N14036
Product nameplate
label
The product name and
certification
/QUALIFICATION CARD

MADE IN CHINA HUAWEI TECHNOLOGIES CO.,LTD.
HUAWEI
Certificate of
qualification label
The equipment is
qualified.

23.1.2 Label Position
The ESD protection label and grounding label are affixed to the subrack. The laser safety class
label and APD warning label are affixed to the front panel of the board.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 23 Labels
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23-3
Figure 23-1 Positions of the labels affixed to the OptiX OSN 3500 subrack (1)
/QUALIFICATION CARD

MADE IN CHINA HUAWEI TECHNOLOGIES CO.,LTD.
HUAWEI
ATTENTION
CLEAN PERIODICALLY

This device complies with Part 15 of the FCC Rules.

Operation is subject to the following two conditions:
(1) this device may not cause harmful interference,
and (2) this device must accept any interference
received, including interference that may cause
undesired operation.
POWER RATING: -48 -60V; 28.4A

MADE IN CHINA

OptiX OSN 3500

HUAWEI TECHNOLOGIES CO.,LTD.
N14036
DON'T TOUCH THE
FAN LEAVES BEFORE
THEY SLOW DOWN !

23 Labels
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Hardware Description
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Issue 01 (2010-01-15)
Figure 23-2 Positions of the labels affixed to the OptiX OSN 3500 subrack (2)


OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 23 Labels
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Copyright Huawei Technologies Co., Ltd.
23-5
Figure 23-3 Positions of the labels affixed to the board
LASER
RADIATION
DO NOT VIEW DIRECTLY
WITH OPTICAL
INSTRUMENTS
CLASS 1M LASER
PRODUCT
BA2
SL16
CLASS 1
LASER
PRODUCT
! APD
Receiver
MAX:-9dBm

23.2 Engineering Labels
The engineering labels should be prepared according to the local engineering specifications or
Huawei engineering specifications.
Table 23-2 provides the engineering specifications of Huawei.
For information on how to prepare and affix labels, see the OptiX OSN 3500 Intelligent Optical
Transmission System Installation Guide.
23 Labels
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Table 23-2 Huawei specifications for the engineering labels
Label Illustration Description
Engineer
ing label
for the
power
cable
(1) (2)
TO:
A01 -48V2
B08
TO:
B03 -48V2
(1) Label on the loaded cabinet side, that is,
the position of the cable on the power
distribution cabinet side
(2) Label on the power distribution cabinet
side, that is, the position of the cable on the
loaded cabinet side
On the loaded cabinet side, the
label marked with "A01/B08
48V2" on the cable indicates that
the cable supplies the 48 V2
power. This cable is led out from
the eighth connecter in the second
row of the 48 V bus bar in the
power distribution cabinet in row
A and column 01 in the
equipment room.
On the power distribution cabinet
side, the label marked with "B03
48V2" on the cable indicates
that the cable supplies the 48 V2
power. This cable is led out from
the loaded cabinet in row B and
column 03 in the equipment
room. In the case of the PGND
cable and BGND cable, specify
only the row number and column
number of the power distribution
cabinet. It is not required to
specify the connecter on the bus
bar.
Engineer
ing label
for the
external
alarm
cable
The external alarm cable is
connected to the power
distribution cabinet (the first
cabinet in each row used for
power distribution). Affix labels
to the terminals of the power
distribution cabinet to indicate
the equipment that uses the
terminals. No engineering label
needs to be affixed to the
equipment side, unless otherwise
specified.
"A01" indicates that the alarm
cable connects the power
distribution cabinet and the
cabinet in row A and column 01
in the equipment room.
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Hardware Description 23 Labels
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Label Illustration Description
Engineer
ing label
for the
network
cable
"A01-03-06-05" indicates that
the local end of the network cable
is connected to network port 05 in
slot 06 of subrack 03 in the
cabinet in row A and column 01
in the equipment room.
"B02-03-12" indicates that the
opposite end of the network cable
is connected to network port 12 in
subrack 03 in the cabinet in row
B and column 02 in the
equipment room. It is not
required to specify the slot
number.
Engineer
ing label
for the
fiber that
connects
two
pieces of
equipme
nt
"A01-01-05-05-R" indicates that
the local end of the fiber is
connected to optical receiving
port 05 in slot 05 of subrack 01 in
the cabinet in row A and column
01 in the equipment room.
"G01-01-01-01-T" indicates that
the opposite end of the fiber is
connected to optical transmitting
port 01 in slot 01 of subrack 01 in
the cabinet in row G and column
01 in the equipment room.
Engineer
ing label
for the
fiber that
connects
the
equipme
nt and
the ODF
"ODF-G01-01-01-R" indicates
that the local end of the fiber is
connected to the optical receiving
terminal in row 01 and column 01
of the ODF in row G and column
01 in the equipment room.
"A01-01-05-05-R" indicates that
the opposite end of the fiber is
connected to optical receiving
port 05 in slot 05 of subrack 01 in
the cabinet in row A and column
01 in the equipment room.
23 Labels
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Label Illustration Description
Engineer
ing label
for the
trunk
cable
that
connects
the
equipme
nt and
the DDF
"A01-03-01-01-R" indicates that
the local end of the trunk cable is
connected to the receiving
terminal of trunk cable 01 in slot
01 of subrack 03 in the cabinet in
row A and column 01 in the
equipment room.
"DDF-G01-01-01-AR" indicates
that the opposite end of the trunk
cable is connected to the
receiving terminal of direction A
(connected to the optical
transmission equipment) in row
01 and column 01 of the DDF in
row G and column 01 in the
equipment room.
Engineer
ing label
for the
subscrib
er cable
T O :
"A01-03-01-01" indicates that
the local end of the subscriber
cable is connected to cable 01 in
slot 01 of subrack 03 in the
cabinet in row A and column 01
in the equipment room.
"MDF-G01-01-01" indicates that
the opposite end of the subscriber
cable is connected to the terminal
in row 01 and column 01 of the
MDF in row G and column 01 in
the equipment room.

OptiX OSN 3500 Intelligent Optical Transmission System
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24 Board Information Quick Reference
About This Chapter
This topic provides information about whether a board is supported by the OptiX OSN products,
the parameters specified for the interfaces of the boards (including the parameters specified for
optical interfaces, electrical interfaces, and auxiliary interfaces), the loopback capability of each
board, the functions supported by each board, and the protection schemes supported by each
board.
24.1 Compatibility of Board Versions with the Products
This topic provides information on whether a board of a specific version is supported by the
OptiX OSN products.
24.2 Quick Reference Table for Optical Interfaces
This topic lists the common parameters specified for the interfaces of boards.
24.3 Quick Reference of Board Functions
This topic describes the functions supported by SDH boards, PDH boards, data boards, and
packet boards.
24.4 Loopback Capability of the Boards
The SDH boards, PDH boards, and data boards of the OptiX OSN equipment support various
types of loopbacks.
24.5 Protection Schemes Supported by Each Board
The SDH boards, PDH boards, data boards, microwave boards, and packet boards of the OptiX
OSN equipment support various protection schemes.
24.6 Quick Reference of Power Consumption and Weight of Each Board
This topic lists the power consumption and weight of each board of the OptiX OSN series
equipment.
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-1
24.1 Compatibility of Board Versions with the Products
This topic provides information on whether a board of a specific version is supported by the
OptiX OSN products.
Table 24-1 provides information on whether a board of a specific version is supported by the
OptiX OSN products.
Table 24-1 Information on whether a board of a specific version is supported by the OptiX OSN
products
Product OptiX OSN
7500
OptiX OSN
3500
OptiX OSN
1500A
OptiX OSN
1500B
N1SL64 Y Y N N
N2SL64 N Y N N
N1SF64 Y Y N N
N1SF64A Y Y N N
N1SLD64 Y Y N N
T2SL64 Y N N N
T2SL64A Y N N N
N1SL16 Y Y Y Y
N2SL16 Y Y Y Y
N3SL16 Y Y Y Y
N1SL16A Y Y Y Y
N2SL16A Y Y Y Y
N3SL16A Y Y Y Y
N1SLD16 N Y N N
N1SLQ16 Y Y N N
N2SLQ16 Y Y N N
N1SLO16 Y Y N N
N1SF16 Y Y Y Y
N3SLQ41 Y Y Y Y
N1SL4 Y Y Y Y
N2SL4 Y Y Y Y
N1SL4A Y Y Y Y
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-2 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Product OptiX OSN
7500
OptiX OSN
3500
OptiX OSN
1500A
OptiX OSN
1500B
R1SL4 N N Y Y
N1SLQ4 Y Y Y Y
N2SLQ4 Y Y Y Y
N1SLQ4A Y Y Y Y
N1SLD4 Y Y Y Y
N2SLD4 Y Y Y Y
N1SLD4A Y Y Y Y
R1SLD4 N N Y Y
N1SLT1 Y Y Y Y
N1SLQ1 Y Y Y Y
N2SLQ1 Y Y Y Y
N1SLQ1A Y Y Y Y
R1SLQ1 N N Y Y
N1SL1 Y Y Y Y
N2SL1 Y Y Y Y
N1SL1A Y Y Y Y
R1SL1 N N Y Y
N1SLH1 Y Y N N
N1SEP1 Y Y Y Y
N2SLO1 Y Y Y Y
N3SLO1 Y Y Y Y
R1PL1 N N Y Y
R1PD1 N N Y Y
R2PD1 N N Y Y
N1PQ1 Y Y N Y
N2PQ1 Y Y N Y
N1PQM Y Y N Y
N1PL3 Y Y N Y
N2PL3 Y Y N Y
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-3
Product OptiX OSN
7500
OptiX OSN
3500
OptiX OSN
1500A
OptiX OSN
1500B
N1PL3A Y Y Y Y
N2PL3A Y Y Y Y
N1PD3 Y Y N Y
N2PD3 Y Y N Y
N2PQ3 Y Y N Y
N1DX1 Y Y N Y
N1DXA Y Y Y Y
N1SPQ4 N Y N Y
N2SPQ4 Y Y N Y
R1EFT4 N N Y Y
N1EFT8 Y Y Y Y
N1EFT8A Y Y Y Y
N1EGT2 Y Y Y Y
N2EGT2 Y Y Y Y
N1EFS0 N Y N Y
N2EFS0 Y Y N Y
N4EFS0 Y Y N Y
N5EFS0 Y Y N Y
N1EFS0A Y Y N Y
N1EFS4 Y Y Y Y
N2EFS4 Y Y Y Y
N3EFS4 Y Y Y Y
N2EGS2 Y Y Y Y
N3EGS2 Y Y Y Y
N1EMS4 Y Y Y Y
N1EMS2 Y Y Y Y
N1EGS4 Y Y Y Y
N3EGS4 Y Y Y Y
N4EGS4 Y Y Y Y
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-4 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Product OptiX OSN
7500
OptiX OSN
3500
OptiX OSN
1500A
OptiX OSN
1500B
N2EGR2 Y Y Y Y
N2EMR0 Y Y Y Y
N1EAS2 Y Y N N
N1ADL4 Y Y Y Y
N1ADQ1 Y Y Y Y
N1IDL4 Y Y Y Y
N1IDL4A Y Y Y Y
N1IDQ1 Y Y Y Y
N1IDQ1A Y Y Y Y
N1MST4 Y Y Y Y
N1EU08 Y Y N Y
N1OU08 Y Y N Y
N2OU08 Y Y N Y
N1D75S Y Y N Y
N1MU04 Y Y N Y
N1D34S Y Y N Y
N1C34S Y Y N Y
N1EU04 N Y N Y
N1D12S Y Y N Y
N1D12B Y Y N Y
R1L12S N N Y N
R1L75S N N Y N
N1EFF8 Y Y N Y
N1EFF8A Y Y N Y
N1ETF8 Y Y N Y
N1ETF8A Y Y N Y
N1ETS8 Y Y N Y
N1DM12 Y Y N Y
N1TSB4 N Y N Y
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
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Copyright Huawei Technologies Co., Ltd.
24-5
Product OptiX OSN
7500
OptiX OSN
3500
OptiX OSN
1500A
OptiX OSN
1500B
N1TSB8 Y Y N Y
R1PEGS1 N N Y Y
Q1PEGS2 N N Y Y
R1PEFS8 N N Y Y
N1PEG16 Y Y N N
N1PEG8 Y Y N N
N1PEFF8 Y Y N N
N1PEX1 Y Y N N
N2PEX1 Y Y N N
N1PEX2 Y Y N N
N1PETF8 Y Y N N
N1EDQ41 Y Y N N
N1EDL16 Y Y N N
R1PEF4F N N Y Y
N1CQ1 Y Y N N
N1MD75 Y Y N N
N1MD12 Y Y N N
R1ML1 N N Y Y
R1PCXLN N N Y Y
N1PSXCS N Y N N
N2PSXCSA N Y N N
T1PSXCSA Y N N N
N4GSCC Y Y N N
N6GSCC Y Y N N
R1EOW N N Y Y
T1EOW Y N N N
N1AUX N Y N N
R1AUX N N Y Y
R2AUX N N Y Y
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-6 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Product OptiX OSN
7500
OptiX OSN
3500
OptiX OSN
1500A
OptiX OSN
1500B
T1AUX Y N N N
R1AMU N N Y Y
N1FAN N Y N N
R1FAN N N Y Y
N1FANA Y N N N
TN11CMR2 Y Y Y Y
TN11CMR4 Y Y Y Y
TN11MR2 Y Y Y Y
TN11MR4 Y Y Y Y
N1MR2A Y Y Y Y
N1MR2B N N Y Y
N1MR2C Y Y N Y
N1LWX Y Y Y Y
N1IFSD1 Y Y Y Y
N1RPWR Y Y Y Y
TN11OBU1 Y Y Y Y
N1FIB Y Y Y Y
N1BA2 Y Y Y Y
N1BPA Y Y Y Y
N2BPA Y Y Y Y
61COA Y Y Y Y
62COA Y Y Y Y
N1COA Y Y Y Y
N1RPC01 Y Y Y Y
N1RPC02 Y Y Y Y
N1DCU Y Y N N
N2DCU Y Y N N
UPM
(GIE4805S)
N N Y Y
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-7
Product OptiX OSN
7500
OptiX OSN
3500
OptiX OSN
1500A
OptiX OSN
1500B
UPM
(EPS75-4815
AF)
Y Y Y Y
N1PIU N Y N N
T1PIU Y N N N
T1PIUB Y N N N
N1PIUA N Y N N
N1PIUB N Y N N
R1PIU N N N Y
R1PIUA N N Y N
R1PIUB N N N Y
R1PIUC N N Y N
NOTE
"Y" indicates that the OptiX OSN equipment supports the board and "N" indicates that the OptiX OSN
equipment does not support the board.
This table provides information on whether a specific type of board is supported by a specific type of OptiX
OSN equipment. For example, the N1SL1A is supported by the OptiX OSN 3500 and OptiX OSN 1500.

24.2 Quick Reference Table for Optical Interfaces
This topic lists the common parameters specified for the interfaces of boards.
24.2.1 Common Parameters Specified for Optical Interfaces of SDH Boards
This topic describes common parameters specified for optical interfaces of SDH boards.
24.2.2 Common Parameters Specified for Optical Interfaces of Packet Boards
This topic describes common parameters specified for optical interfaces of packet boards.
24.2.3 Common Parameters Specified for Optical Interfaces of Data Boards
This topic describes common parameters specified for optical interfaces of data boards.
24.2.1 Common Parameters Specified for Optical Interfaces of SDH
Boards
This topic describes common parameters specified for optical interfaces of SDH boards.
Table 24-2 lists the common parameters specified for the optical interfaces of the SDH boards.
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-8 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Table 24-2 Common parameters specified for the optical interfaces of the SDH boards
Board
Name
Optical Module Type
of
Fiber
Type of
Support
ed
Optical
Interface
Mean Launched Optical
Power
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d
Maximum
(dBm)
Minimum
(dBm)
SL1 and
SL1A
I-1 -8 -15 -23 -8 Single-
mode
LC
S-1.1 -8 -15 -28 -8 Single-
mode
LC
L-1.1 0 -5 -34 -10 Single-
mode
LC
L-1.2 0 -5 -34 -10 Single-
mode
LC
Ve-1.2 0 -3 -34 -10 Single-
mode
LC
SLQ1 and
SLQ1A
I-1 -8 -15 -23 -8 Single-
mode
LC
S-1.1 -8 -15 -28 -8 Single-
mode
LC
L-1.1 0 -5 -34 -10 Single-
mode
LC
L-1.2 0 -5 -34 -10 Single-
mode
LC
Ve-1.2 0 -3 -34 -10 Single-
mode
LC
Ie-1 -14 -19 -30 -14 Multi-
mode
LC
SLT1 S-1.1 -8 -15 -28 -8 Single-
mode
LC
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-9
Board
Name
Optical Module Type
of
Fiber
Type of
Support
ed
Optical
Interface
Mean Launched Optical
Power
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d
Maximum
(dBm)
Minimum
(dBm)
SL4,
SL4A,
SLD4,
SLD4A,
SLQ4, and
SLQ4A
I-4 -8 -15 -23 -8 Single-
mode
LC
S-4.1 -8 -15 -28 -8 Single-
mode
LC
L-4.1 2 -3 -28 -8 Single-
mode
LC
L-4.2 2 -3 -28 -8 Single-
mode
LC
Ve-4.2 2 -3 -34 -13 Single-
mode
LC
SL16 L-16.2 3 -2 -28 -9 Single-
mode
LC
L-16.2Je 7 5 -28 -9 Single-
mode
LC
V-16.2Je
(BA)
3 (without
the BA)
15 (with the
BA)
-2 (without
the BA)
13 (with the
BA)
-28 -9 Single-
mode
LC
U-16.2Je
(BA+PA)
3 (without
the BA or
PA)
18 (with the
BA)
-2 (without
the BA or
PA)
15 (with the
BA)
-28
(without the
BA or PA)
-32 (with
the PA)
-9
(without
the BA or
PA)
-10 (with
the PA)
Single-
mode
LC
SL16A I-16 -3 -10 -18 -3 Single-
mode
LC
S-16.1 0 -5 -18 0 Single-
mode
LC
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-10 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Board
Name
Optical Module Type
of
Fiber
Type of
Support
ed
Optical
Interface
Mean Launched Optical
Power
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d
Maximum
(dBm)
Minimum
(dBm)
L-16.1 3 -2 -27 -9 Single-
mode
LC
L-16.2 3 -2 -28 -9 Single-
mode
LC
SLD16 I-16 -3 -10 -18 -3 Single-
mode
LC
S-16.1 0 -5 -18 0 Single-
mode
LC
L-16.1 3 -2 -27 -9 Single-
mode
LC
L-16.2 3 -2 -28 -9 Single-
mode
LC
SLQ16 I-16 -3 -10 -18 -3 Single-
mode
LC
S-16.1 0 -5 -18 0 Single-
mode
LC
L-16.1 3 -2 -27 -9 Single-
mode
LC
L-16.2 3 -2 -28 -9 Single-
mode
LC
SLO16 I-16 -3 -10 -18 -3 Single-
mode
LC
S-16.1 0 -5 -18 0 Single-
mode
LC
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-11
Board
Name
Optical Module Type
of
Fiber
Type of
Support
ed
Optical
Interface
Mean Launched Optical
Power
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d
Maximum
(dBm)
Minimum
(dBm)
L-16.1 3 -2 -27 -9 Single-
mode
LC
L-16.2 3 -2 -28 -9 Single-
mode
LC
SL64 I-64.1 -1 -6 -11 -1 Single-
mode
LC
I-64.2 -1 -5 -14 -1 Single-
mode
LC
S-64.2b 2 -1 -14 -1 Single-
mode
LC
L-64.2b
(BA)
2 (without
the BA)
15 (with the
BA)
-4 (without
the BA)
13 (with the
BA)
-14 -1 Single-
mode
LC
Le-64.2 4 2 -21 -8 Single-
mode
LC
Ls-64.2 7 4 -21 -8 Single-
mode
LC
V-64.2b
(BA+PA
+DCU)
-1 (without
the BA, PA,
or DCU)
15 (with the
BA)
-4 (without
the BA, PA,
or DCU)
13 (with the
BA)
-14
(without the
BA, PA, or
DCU)
-26 (with
the PA)
-1 Single-
mode
LC
SLD64 I-64.1 -1 -6 -11 -1 Single-
mode
LC
S-64.2b 2 -1 -14 -1 Single-
mode
LC
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-12 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Board
Name
Optical Module Type
of
Fiber
Type of
Support
ed
Optical
Interface
Mean Launched Optical
Power
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d
Maximum
(dBm)
Minimum
(dBm)
SLQ41 I-1 -8 -15 -23 -8 Single-
mode
LC
S-1.1 -8 -15 -28 -8 Single-
mode
LC
L-1.1 0 -5 -34 -10 Single-
mode
LC
L-1.2 0 -5 -34 -10 Single-
mode
LC
Ve-1.2 0 -3 -34 -10 Single-
mode
LC
I-4 -8 -15 -23 -8 Single-
mode
LC
S-4.1 -8 -15 -28 -8 Single-
mode
LC
L-4.1 2 -3 -28 -8 Single-
mode
LC
L-4.2 2 -3 -28 -8 Single-
mode
LC
Ve-4.2 2 -3 -34 -13 Single-
mode
LC

Table 24-3 lists common parameters specified for optical interfaces of SDH boards (FEC
boards).
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-13
Table 24-3 Common parameters specified for optical interfaces of SDH boards (FEC boards)
Board
Name
Optical Module Type
of
Fiber
Type of
Support
ed
Optical
Interface
Mean Launched
Optical Power
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d (dBm)
Maximu
m (dBm)
Minimum
(dBm)
SF16 Ue-16.2c Without
BA or PA:
-1
With BA:
15
Without BA
or PA: -5
With BA: 13
Without BA
or PA: -27.5
With PA:
-37
-10 Single-
mode
LC
Ue-16.2d Without
BA or PA:
-1
With BA:
15
Without BA
or PA: -5
With BA: 13
Without BA
or PA: -27.5
With PA:
-37
-10 Single-
mode
LC
Ue-16.2f Without
BA, RA, or
PA: -1
With BA:
18
Without BA,
RA, or PA:
-5
With BA: 15
Without
BA, RA, or
PA: -27.5
With PA:
-42
-10 Single-
mode
LC
SF64 Ue-64.2c -1 -4 -14 -1 Single-
mode
LC
Ue-64.2d -1 -4 -14 -1 Single-
mode
LC
Ue-64.2e -1 -4 -14 -1 Single-
mode
LC
SF64A Ue-64.2c -1 -4 -14 -1 Single-
mode
LC
Ue-64.2d -1 -4 -14 -1 Single-
mode
LC
Ue-64.2e -1 -4 -14 -1 Single-
mode
LC
SFD64 Ue-64.2c -1 -4 -14 -1 Single-
mode
LC
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-14 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Board
Name
Optical Module Type
of
Fiber
Type of
Support
ed
Optical
Interface
Mean Launched
Optical Power
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d (dBm)
Maximu
m (dBm)
Minimum
(dBm)
Ue-64.2d -1 -4 -14 -1 Single-
mode
LC
Ue-64.2e -1 -4 -14 -1 Single-
mode
LC

24.2.2 Common Parameters Specified for Optical Interfaces of
Packet Boards
This topic describes common parameters specified for optical interfaces of packet boards.
Table 24-4 lists the common parameters specified for the optical interfaces of the packet boards.
Table 24-4 Common parameters specified for the optical interfaces of the packet boards
Boards
Name
Optical Module Type of
Fiber
Type of
Support
ed
Optical
Interface
Mean Launched Optical
Power
Receiver
Sensitivit
y
Minimu
m
Overloa
d (dBm)
Maximu
m (dBm)
Minimum
(dBm)
PEX1 10GBAS
E-SR/SX
-1.3 -7.3 -7.5 -1 Multi-
mode
LC
10GBAS
E-LR/LX
-1 -6 -11 -1 Single-
mode
LC
10GBAS
E-LR/LX
-1 -6 -11 -1 Single-
mode
LC
10GBAS
E-ER/EX
2 -1 -15 -1 Single-
mode
LC
10GBAS
E-ZR/ZX
4 0 -24 -7 Single-
mode
LC
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-15
Boards
Name
Optical Module Type of
Fiber
Type of
Support
ed
Optical
Interface
Mean Launched Optical
Power
Receiver
Sensitivit
y
Minimu
m
Overloa
d (dBm)
Maximu
m (dBm)
Minimum
(dBm)
PEG16 1000BAS
E-ZX (80
km)
5 -2 -23 -3 Single-
mode
LC
1000BAS
E-VX (40
km)
0 -5 -22 -3 Single-
mode
LC
1000BAS
E-LX (10
km)
-3 -11 -19 -3 Single-
mode
LC
1000BAS
E-SX (0.5
km)
0 -9.5 -17 0 Multi-
mode
LC
PEX2 10GBAS
E-SR/SX
-1.3 -7.3 -7.5 -1 Multi-
mode
LC
10GBAS
E-LR/LX
-1 -6 -11 -1 Single-
mode
LC
10GBAS
E-LR/LX
-1 -6 -11 -1 Single-
mode
LC
10GBAS
E-ER/EX
2 -1 -15 -1 Single-
mode
LC
10GBAS
E-ZR/ZX
4 0 -24 -7 Single-
mode
LC
PEG8 1000Base
-ZX
(80km)
5 -2 -22 -3 Single-
mode
LC
1000BAS
E-VX
(40km)
0 -5 -22 -3 Single-
mode
LC
1000Base
-LX
(10km)
-3 -11 -19 -3 Single-
mode
LC
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-16 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Boards
Name
Optical Module Type of
Fiber
Type of
Support
ed
Optical
Interface
Mean Launched Optical
Power
Receiver
Sensitivit
y
Minimu
m
Overloa
d (dBm)
Maximu
m (dBm)
Minimum
(dBm)
1000Base
-SX
(0.5km)
0 -9.5 -17 0 Multi-
mode
LC

24.2.3 Common Parameters Specified for Optical Interfaces of Data
Boards
This topic describes common parameters specified for optical interfaces of data boards.
Table 24-5 lists the common parameters specified for the optical interfaces of the data boards.
Table 24-5 Common parameters specified for the optical interfaces of the data boards
Board
Name
Optical Module Type of
Fiber
Type of
Support
ed
Optical
Interface
Mean Launched Optical
Power
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d (dBm)
Maximum
(dBm)
Minimum
(dBm)
EGS2,
EGS4,
EGR2,
and
EMR0
1000BAS
E-ZX (80
km)
5 -2 -23 -3 Single-
mode
LC
1000BAS
E-VX (40
km)
0 -5 -22 -3 Single-
mode
LC
1000BAS
E-LX (10
km)
-3 -11 -19 -3 Single-
mode
LC
1000BAS
E-SX (0.5
km)
0 -9.5 -17 0 Multi-
mode
LC
S-4.1 -8 -15 -28 -8 Single-
mode
LC
L-4.1 2 -3 -28 -8 Single-
mode
LC
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-17
Board
Name
Optical Module Type of
Fiber
Type of
Support
ed
Optical
Interface
Mean Launched Optical
Power
Receiver
Sensitivit
y (dBm)
Minimu
m
Overloa
d (dBm)
Maximum
(dBm)
Minimum
(dBm)
L-4.2 2 -3 -28 -8 Single-
mode
LC
Ve-4.2 2 -3 -34 -13 Single-
mode
LC
Ie-1 -14 -19 -30 -14 Multi-
mode
LC
S-1.1 -8 -15 -28 -8 Single-
mode
LC
L-1.1 0 -5 -34 -10 Single-
mode
LC
L-1.2 0 -5 -34 -10 Single-
mode
LC
Ve-1.2 0 -3 -34 -10 Single-
mode
LC
MST4 X3.296/
(DVB-
ASI)
EN50083
-9
200-M5-
SN-I
-8 -15 -31 -8 Single-
mode
LC
-14 -19 -30 -14 Single-
mode
LC
200-SM-
LC-I
-2.5 -9.5 -17 0 Single-
mode
LC
-3 -10 -21 -3 Multi-
mode
LC
0 -5 -21 0 Single-
mode
LC
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-18 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)

24.3 Quick Reference of Board Functions
This topic describes the functions supported by SDH boards, PDH boards, data boards, and
packet boards.
24.3.1 Information Quick Reference of SDH Boards
This topic describes the functions supported by different types of SDH boards.
24.3.2 Information Quick Reference of PDH Boards
This topic describes the functions supported by different types of PDH boards.
24.3.3 Information Quick Reference of Data Boards
This topic describes the functions supported by different types of data boards.
24.3.4 Information Quick Reference of Packet Boards
This topic describes the functions supported by different types of packet boards.
24.3.1 Information Quick Reference of SDH Boards
This topic describes the functions supported by different types of SDH boards.
Table 24-6 provides the functions supported by SDH boards.
Table 24-6 Basic functions of SDH boards
Func
tion
ALS REG
Speci
ficati
ons
PRBS AU-3 TCM FEC Fixed
Wave
lengt
h
Color
ed
Wave
lengt
h
Tuna
ble
Wave
lengt
h
N1SL
64
Y Y N N N N Y Y N
N2SL
64
Y Y N Y Y N Y Y N
T2SL
64
Y Y N Y Y N Y Y N
T2SL
64A
Y Y N Y Y N Y Y N
N1SF
64
Y Y N N N Y Y Y N
N1SF
64A
Y Y N N N Y Y Y Y
N1SL
D64
Y N N N N N N N N
N1SL
16
Y N N N N N Y Y N
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
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Copyright Huawei Technologies Co., Ltd.
24-19
Func
tion
ALS REG
Speci
ficati
ons
PRBS AU-3 TCM FEC Fixed
Wave
lengt
h
Color
ed
Wave
lengt
h
Tuna
ble
Wave
lengt
h
N2SL
16
Y Y N Y Y N Y Y N
N3SL
16
Y Y Y N Y N Y Y N
N1SL
16A
Y N N N N N N N N
N2SL
16A
Y Y N Y Y N N N N
N3SL
16A
Y Y Y N Y N N N N
N1SL
D16
Y N N N N N N N N
N1SL
Q16
Y N N N N N N Y N
N2SL
Q16
Y N N Y Y N N Y N
N1SL
O16
Y N N N N N N Y N
N1SF
16
Y N N N N Y Y Y N
N3SL
Q41
Y N N N N N N N N
N1SL
4
Y N N N N N N N N
N2SL
4
Y N N Y Y N N N N
R1SL
4
Y N N N N N N N N
R3SL
4
Y N Y N N N N N N
N1SL
4A
Y N N N N N N N N
N1SL
Q4
Y N N N N N N N N
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-20 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Func
tion
ALS REG
Speci
ficati
ons
PRBS AU-3 TCM FEC Fixed
Wave
lengt
h
Color
ed
Wave
lengt
h
Tuna
ble
Wave
lengt
h
N2SL
Q4
Y N N Y Y N N N N
N1SL
Q4A
Y N N N N N N N N
N1SL
D4
Y N N N N N N N N
N2SL
D4
Y N N Y Y N N N N
R1SL
D4
Y N N N N N N N N
R3SL
D4
Y N Y N Y N N N N
N1SL
D4A
Y N N N N N N N N
N1SL
T1
Y N Y N N N N N N
N1SL
Q1
Y N N N N N N N N
N2SL
Q1
Y N N Y Y N N N N
R1SL
Q1
Y N N N N N N N N
N1SL
Q1A
Y N N N N N N N N
R3SL
Q1
Y N Y N N N N N N
N1SL
1
Y N N N N N N N N
N2SL
1
Y N N Y Y N N N N
N1SL
1A
Y N N N N N N N N
R1SL
1
Y N N N N N N N N
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-21
Func
tion
ALS REG
Speci
ficati
ons
PRBS AU-3 TCM FEC Fixed
Wave
lengt
h
Color
ed
Wave
lengt
h
Tuna
ble
Wave
lengt
h
R3SL
1
Y N Y N N N N N N
N1SL
H1
Y N N N N N N N N
N1SE
P1
Y N N N N N N N N
N2SL
O1
Y N N Y Y N N N N
N3SL
O1
Y N Y N N N N N N

24.3.2 Information Quick Reference of PDH Boards
This topic describes the functions supported by different types of PDH boards.
Table 24-7 provides the functions supported by PDH boards.
Table 24-7 Basic functions of PDH boards
Function PRBS TPS E13 M13
R1PL1 Y N N N
R1PD1 Y Y N N
R2PD1 Y Y Y N
R3PD1 Y Y
Y
Note
N
N1PQ1 Y Y N N
N2PQ1 Y Y Y N
N1PQM Y Y N N
N1PL3 N Y N N
N2PL3 Y Y Y Y
N1PL3A N N N N
N2PL3A Y N Y Y
N1PD3 Y Y N N
N2PD3 Y Y Y Y
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-22 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Function PRBS TPS E13 M13
N2PQ3 Y Y Y Y
N1DX1 Y Y N N
N1DXA N N N N
N1SPQ4 N Y N N
N2SPQ4 N Y N N
NOTE
The R3PD1 supports the E13 function only in server mode.

24.3.3 Information Quick Reference of Data Boards
This topic describes the functions supported by different types of data boards.
Table 24-8 provides the functions supported by data boards.
Table 24-8 Basic functions of data boards
Fun
ctio
n
EPL EV
PL
EPL
AN
EV
PL
AN
MP
LS
Qo
S
ET
H-
OA
M
(802
.
1ag
)
ET
H-
OA
M
(802
.
3ah
)
Tes
t
Fra
mes
Qin
Q
RM
ON
IG
MP
Sno
opi
ng
R1E
FT4
Y N N N N N N N Y N Y N
N1E
FT8
Y N N N N N N N Y N Y N
N1E
FT8
A
Y N N N N N N N Y N Y N
N1E
GT2
Y N N N N N N N Y N Y N
N2E
GT2
Y N N N N N N N Y N Y N
N1E
FS0
Y Y Y N Y Y N N Y N Y Y
N2E
FS0
Y Y Y N Y Y N N Y N Y Y
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-23
Fun
ctio
n
EPL EV
PL
EPL
AN
EV
PL
AN
MP
LS
Qo
S
ET
H-
OA
M
(802
.
1ag
)
ET
H-
OA
M
(802
.
3ah
)
Tes
t
Fra
mes
Qin
Q
RM
ON
IG
MP
Sno
opi
ng
N4E
FS0
Y Y Y N Y Y Y Y Y N Y Y
N5E
FS0
Y Y Y N Y Y Y Y Y N Y Y
N1E
FS0
A
Y Y Y N Y Y Y Y Y N Y Y
N1E
FS4
Y Y Y N Y Y N N Y N Y Y
N2E
FS4
Y Y Y N Y Y Y Y Y N Y Y
N3E
FS4
Y Y Y N Y Y Y Y Y N Y Y
N2E
GS2
Y Y Y N Y Y N N Y N Y Y
N3E
GS2
Y Y Y N Y Y Y Y Y N Y Y
N1E
MS
4
Y Y Y Y N Y Y Y Y Y Y Y
N1E
MS
2
Y Y Y Y N Y Y Y Y Y Y Y
N1E
GS4
Y Y Y Y N Y Y Y Y Y Y Y
N3E
GS4
Y Y Y Y N Y Y Y Y Y Y Y
N4E
GS4
Y Y Y Y N Y Y Y Y Y Y Y
N2E
GR
2
N Y N Y Y Y N N Y N N Y
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-24 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Fun
ctio
n
EPL EV
PL
EPL
AN
EV
PL
AN
MP
LS
Qo
S
ET
H-
OA
M
(802
.
1ag
)
ET
H-
OA
M
(802
.
3ah
)
Tes
t
Fra
mes
Qin
Q
RM
ON
IG
MP
Sno
opi
ng
N2E
MR
0
N Y N Y Y Y N N Y N N Y
N1E
AS2
Y Y Y Y N Y Y N Y Y Y Y
NOTE
For the ETH-OAM functions supported by data boards, see "Availability" in the Feature Description.

24.3.4 Information Quick Reference of Packet Boards
This topic describes the functions supported by different types of packet boards.
Table 24-9 provides the functions supported by packet boards.
Table 24-9 Basic functions of packet boards
F
u
n
c
t
i
o
n
E
-
L
i
n
e
E
-
L
A
N
E
-
A
g
g
r
Q
o
S
L
A
G
M
P
L
S
T
u
n
n
e
l
A
P
S
P
W
A
P
S
M
P
L
S
O
A
M
D
H
C
P
R
e
l
a
y
M
C
-
L
A
G
V
R
R
P
B
F
D
M
S
T
P
L
P
T
M
S
-
P
W
E
T
H
-
O
A
M
Q
i
n
Q
I
G
M
P
S
n
o
o
p
i
n
g
1
5
8
8
V
2
C
E
S
I
n
b
a
n
d
D
C
N
R
M
O
N
D
N
I
A
P
S
N
1
P
E
G
1
6
Y Y Y Y Y Y N Y N N N N Y Y N Y Y Y Y N Y Y N
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-25
F
u
n
c
t
i
o
n
E
-
L
i
n
e
E
-
L
A
N
E
-
A
g
g
r
Q
o
S
L
A
G
M
P
L
S
T
u
n
n
e
l
A
P
S
P
W
A
P
S
M
P
L
S
O
A
M
D
H
C
P
R
e
l
a
y
M
C
-
L
A
G
V
R
R
P
B
F
D
M
S
T
P
L
P
T
M
S
-
P
W
E
T
H
-
O
A
M
Q
i
n
Q
I
G
M
P
S
n
o
o
p
i
n
g
1
5
8
8
V
2
C
E
S
I
n
b
a
n
d
D
C
N
R
M
O
N
D
N
I
A
P
S
N
1
P
E
G
8
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y N Y Y Y
N
1
P
E
X
1
Y Y Y Y Y Y N Y N N N N Y Y N Y Y Y Y N Y Y N
N
2
P
E
X
1
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y N Y Y Y
N
1
P
E
X
2
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y N Y Y Y
N
1
P
E
T
F
8
Y Y Y Y Y Y N Y N N N N Y Y N Y Y Y Y N Y Y N
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-26 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
F
u
n
c
t
i
o
n
E
-
L
i
n
e
E
-
L
A
N
E
-
A
g
g
r
Q
o
S
L
A
G
M
P
L
S
T
u
n
n
e
l
A
P
S
P
W
A
P
S
M
P
L
S
O
A
M
D
H
C
P
R
e
l
a
y
M
C
-
L
A
G
V
R
R
P
B
F
D
M
S
T
P
L
P
T
M
S
-
P
W
E
T
H
-
O
A
M
Q
i
n
Q
I
G
M
P
S
n
o
o
p
i
n
g
1
5
8
8
V
2
C
E
S
I
n
b
a
n
d
D
C
N
R
M
O
N
D
N
I
A
P
S
N
1
P
E
F
F
8
Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y N Y Y Y
N
1
E
D
Q
4
1
Y Y Y Y Y N N N N N N N Y N N Y Y Y N N N Y N
Q
1
P
E
G
S
2
Y Y Y Y Y Y Y Y N N N N Y Y Y Y Y Y Y N Y Y N
R
1
P
E
G
S
1
Y Y Y Y Y Y Y Y N N N N Y Y Y Y Y Y Y N Y Y N
R
1
P
E
F
S
8
Y Y Y Y Y Y Y Y N N N N Y Y Y Y Y Y Y N Y Y N
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-27
F
u
n
c
t
i
o
n
E
-
L
i
n
e
E
-
L
A
N
E
-
A
g
g
r
Q
o
S
L
A
G
M
P
L
S
T
u
n
n
e
l
A
P
S
P
W
A
P
S
M
P
L
S
O
A
M
D
H
C
P
R
e
l
a
y
M
C
-
L
A
G
V
R
R
P
B
F
D
M
S
T
P
L
P
T
M
S
-
P
W
E
T
H
-
O
A
M
Q
i
n
Q
I
G
M
P
S
n
o
o
p
i
n
g
1
5
8
8
V
2
C
E
S
I
n
b
a
n
d
D
C
N
R
M
O
N
D
N
I
A
P
S
R
1
P
E
F
4
F
Y Y Y Y Y Y Y Y N N N N Y Y Y Y Y Y Y N Y Y N
N
1
C
Q
1
N N N N N N N N N N N N N N N N N N N Y N N N
N
1
M
D
7
5
N N N N N N N N N N N N N N N N N N N Y N N N
N
1
M
D
1
2
N N N N N N N N N N N N N N N N N N N Y N N N
R
1
M
L
1
N N N N N N N N N N N N N N N N N N N Y N N N

24.4 Loopback Capability of the Boards
The SDH boards, PDH boards, and data boards of the OptiX OSN equipment support various
types of loopbacks.
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-28 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Table 24-10 provides the loopback capability of the SDH boards of the OptiX OSN equipment.
Table 24-10 Loopback capability of the SDH boards
Board Inloop at an
Interface
Outloop at
an
Interface
Inloop on a
VC-4 Path
Outloop on
a VC-4 Path
Outloop on
a VC-3 or
VC-12 Path
Q2SL1 Supported Supported Supported Not
supported
Not
supported
Q2SL4 Supported Supported Supported Not
supported
Not
supported
Q2SL16 Supported Supported Supported Not
supported
Not
supported
N1SL64 Supported Supported Supported Supported Not
supported
N2SL64 Supported Supported Not
supported
Not
supported
Not
supported
N1SF64 Supported Supported Supported Supported Not
supported
N1SF64A Supported Supported Supported Supported Not
supported
N1SLD64 Supported Supported Supported Supported Not
supported
N1SL16 Supported Supported Supported Not
supported
Not
supported
N2SL16 Supported Supported Not
supported
Not
supported
Not
supported
N3SL16 Supported Supported Supported Supported Not
supported
N1SL16A Supported Supported Supported Not
supported
Not
supported
N2SL16A Supported Supported Not
supported
Not
supported
Not
supported
N3SL16A Supported Supported Supported Supported Not
supported
N1SLD16 Supported Supported Supported Supported Not
supported
N1SLQ16 Supported Supported Supported Supported Not
supported
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
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Copyright Huawei Technologies Co., Ltd.
24-29
Board Inloop at an
Interface
Outloop at
an
Interface
Inloop on a
VC-4 Path
Outloop on
a VC-4 Path
Outloop on
a VC-3 or
VC-12 Path
N2SLQ16 Supported Supported Not
supported
Not
supported
Not
supported
N1SLO16 Supported Supported Supported Supported Not
supported
N1SF16 Supported Supported Supported Not
supported
Not
supported
N3SLQ41 Supported Supported Supported Supported Not
supported
N1SL4 Supported Supported Supported Not
supported
Not
supported
N1SL4A Supported Supported Supported Supported Not
supported
N2SL4 Supported Supported Not
supported
Not
supported
Not
supported
R1SL4 Supported Supported Supported Not
supported
Not
supported
N1SLQ4 Supported Supported Supported Not
supported
Not
supported
N1SLQ4A Supported Supported Supported Supported Not
supported
N2SLQ4 Supported Supported Not
supported
Not
supported
Not
supported
N1SLD4 Supported Supported Supported Not
supported
Not
supported
N1SL4DA Supported Supported Supported Supported Not
supported
N2SLD4 Supported Supported Not
supported
Not
supported
Not
supported
R1SLD4 Supported Supported Supported Not
supported
Not
supported
N1SLT1 Supported Supported Supported Supported Not
supported
N1SLQ1 Supported Supported Supported Not
supported
Not
supported
N1SLQ1A Supported Supported Supported Supported Not
supported
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-30 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Board Inloop at an
Interface
Outloop at
an
Interface
Inloop on a
VC-4 Path
Outloop on
a VC-4 Path
Outloop on
a VC-3 or
VC-12 Path
N2SLQ1 Supported Supported Not
supported
Not
supported
Not
supported
R1SLQ1 Supported Supported Supported Not
supported
Not
supported
N1SL1 Supported Supported Supported Not
supported
Not
supported
N1SL1A Supported Supported Supported Supported Not
supported
N2SL1 Supported Supported Not
supported
Not
supported
Not
supported
R1SL1 Supported Supported Supported Not
supported
Not
supported
N1SLH1 Supported Supported Supported Supported Not
supported
N1SEP1 Supported Supported Supported Not
supported
Not
supported
N2SLO1 Supported Supported Not
supported
Not
supported
Not
supported
N3SLO1 Supported Supported Supported Supported Not
supported

Table 24-11 provides information on whether each SDH board of the OptiX OSN equipment
supports the insertion of the AU_AIS when the board is looped back.
Table 24-11 Information on whether each SDH board of the OptiX OSN equipment supports
the insertion of the AU_AIS when the board is looped back
Board Insertion of
the AU_AIS
to the Port
Side (Inloop
at an
Interface)
Insertion of
the AU_AIS to
the Cross-
Connect Side
(Outloop at an
Interface)
Insertion of
the AU_AIS
to the Cross-
Connect Side
(Inloop on a
VC-4 Path)
Insertion of
the AU_AIS
to the Port
Side
(Outloop on
a VC-4 Path)
Q2SL1 Not supported Supported Not supported Not supported
Q2SL4 Not supported Supported Not supported Not supported
Q2SL16 Not supported Supported Not supported Not supported
N1SL64 Supported Supported Supported Supported
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-31
Board Insertion of
the AU_AIS
to the Port
Side (Inloop
at an
Interface)
Insertion of
the AU_AIS to
the Cross-
Connect Side
(Outloop at an
Interface)
Insertion of
the AU_AIS
to the Cross-
Connect Side
(Inloop on a
VC-4 Path)
Insertion of
the AU_AIS
to the Port
Side
(Outloop on
a VC-4 Path)
N2SL64 Not supported Supported Not supported Not supported
N1SF64 Supported Supported Supported Supported
N1SF64A Supported Supported Supported Supported
N1SLD64 Supported Supported Supported Supported
N1SL16 Not supported Supported Not supported Not supported
N2SL16 Not supported Supported Not supported Not supported
N3SL16 Supported Supported Supported Supported
N1SL16A Not supported Supported Not supported Not supported
N2SL16A Not supported Supported Not supported Not supported
N3SL16A Supported Supported Supported Supported
N1SLD16 Supported Supported Supported Supported
N1SLQ16 Supported Supported Supported Supported
N2SLQ16 Not supported Supported Not supported Not supported
N2SLQ16 Not supported Supported Not supported Not supported
N1SLO16 Supported Supported Supported Supported
N1SF16 Not supported Supported Not supported Not supported
N3SLQ41 Supported Supported Supported Supported
N1SL4 Not supported Supported Not supported Not supported
N1SL4A Supported Supported Supported Supported
N2SL4 Not supported Supported Not supported Not supported
R1SL4 Not supported Supported Not supported Not supported
N1SLQ4 Not supported Supported Not supported Not supported
N1SLQ4A Supported Supported Supported Supported
N2SLQ4 Not supported Supported Not supported Not supported
N1SLD4 Not supported Supported Not supported Not supported
N1SLD4A Supported Supported Supported Supported
N2SLD4 Not supported Supported Not supported Not supported
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-32 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Board Insertion of
the AU_AIS
to the Port
Side (Inloop
at an
Interface)
Insertion of
the AU_AIS to
the Cross-
Connect Side
(Outloop at an
Interface)
Insertion of
the AU_AIS
to the Cross-
Connect Side
(Inloop on a
VC-4 Path)
Insertion of
the AU_AIS
to the Port
Side
(Outloop on
a VC-4 Path)
R1SLD4 Not supported Supported Not supported Not supported
N1SLT1 Supported Supported Supported Supported
N1SLQ1 Not supported Supported Not supported Not supported
N1SLQ1A Supported Supported Supported Supported
N2SLQ1 Not supported Supported Not supported Not supported
R1SLQ1 Not supported Supported Not supported Not supported
N1SL1 Not supported Supported Not supported Not supported
N1SL1A Supported Supported Supported Supported
N2SL1 Not supported Supported Not supported Not supported
R1SL1 Not supported Supported Not supported Not supported
N1SLH1 Supported Supported Supported Supported
N1SEP1 Not supported Supported Not supported Not supported
N2SLO1 Not supported Supported Not supported Not supported
N3SLO1 Supported Supported Supported Supported

Table 24-12 provides the loopback capability of the PDH boards of the OptiX OSN equipment.
Table 24-12 Loopback capability of the PDH boards
Board Inloop at an
Interface
Outloop at an
Interface
R1PL1 Supported Supported
R1PD1 Supported Supported
N1PQ1 Supported Supported
N1PQM Supported Supported
N1PD3 Supported Supported
N1PL3 Supported Supported
N2PQ3 Supported Supported
N2SPQ4 Supported Supported
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-33

Table 24-13 provides the loopback capability of the data boards of the OptiX OSN equipment.
Table 24-13 Loopback capability of the data boards of the OptiX OSN equipment
Board Outloop
at the
MAC
Layer
Inloop at
the MAC
Layer
Outloop
at the
PHY
Layer
Inloop at
the PHY
Layer
Inloop
and
Outloop
on a
VC-4
Path
Inloop
and
Outloop
on a VC-3
Path
N1EFS4 Not
supported
Supported Not
supported
Supported Not
supported
Supported
N2EFS4 Not
supported
Supported Not
supported
Supported Not
supported
Supported
N3EFS4 Not
supported
Supported Not
supported
Supported Not
supported
Not
supported
N1EFS0 Not
supported
Supported Not
supported
Supported Not
supported
Supported
N2EFS0 Not
supported
Supported Not
supported
Supported Not
supported
Supported
N4EFS0 Not
supported
Supported Not
supported
Supported Not
supported
Supported
N5EFS0 Not
supported
Supported Not
supported
Supported Not
supported
Not
supported
N1EFS0A Not
supported
Supported Not
supported
Supported Not
supported
Not
supported
N1EGT2 Not
supported
Supported Not
supported
Supported Not
supported
Not
supported
N2EGT2 Not
supported
Supported Not
supported
Supported Not
supported
Not
supported
N1EFT8 Not
supported
Supported Not
supported
Supported Not
supported
Supported
N1EFT8A Not
supported
Supported Not
supported
Supported Not
supported
Supported
R1EFT4 Not
supported
Supported Not
supported
Supported Not
supported
Supported
N1EMS4 Not
supported
Not
supported
Not
supported
Supported Not
supported
Not
supported
N1EMS2 Not
supported
Supported Not
supported
Supported Not
supported
Not
supported
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-34 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Board Outloop
at the
MAC
Layer
Inloop at
the MAC
Layer
Outloop
at the
PHY
Layer
Inloop at
the PHY
Layer
Inloop
and
Outloop
on a
VC-4
Path
Inloop
and
Outloop
on a VC-3
Path
N1EGS4 Not
supported
Not
supported
Not
supported
Supported Not
supported
Not
supported
N3EGS4 Not
supported
Not
supported
Not
supported
Supported Not
supported
Not
supported
N2EGS4 Not
supported
Not
supported
Not
supported
Supported Not
supported
Not
supported
N2EGS2 Not
supported
Not
supported
Not
supported
Supported Not
supported
Supported
N3EGS2 Not
supported
Supported Not
supported
Supported Not
supported
Not
supported
N2EGR2 Not
supported
Supported Not
supported
Supported Not
supported
Not
supported
N1EAS2 Not
supported
Supported Not
supported
Supported Not
supported
Not
supported
N2EMR0 Not
supported
Supported Not
supported
Supported Not
supported
Not
supported
N1EMS2 Not
supported
Not
supported
Not
supported
Supported Not
supported
Not
supported
N1MST4 Not
supported
Not
supported
Not
supported
Supported Not
supported
Not
supported

Table 24-14 provides the loopback capability of the ATM/IMA boards of the OptiX OSN
equipment.
Table 24-14 Loopback capability of the ATM/IMA boards of the OptiX OSN equipment
Board Outloop at an
External
Interface
Inloop at an
External
Interface
Outloop at an
Internal
Interface
Inloop at an
Internal
Interface
N1ADL4 Not supported Supported Supported Supported
N1ADQ1 Not supported Supported Supported Supported
N1IDL4 Not supported Supported Supported Supported
N1IDL4A Not supported Supported Supported Supported
N1IDQ1 Not supported Supported Supported Supported
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-35
Board Outloop at an
External
Interface
Inloop at an
External
Interface
Outloop at an
Internal
Interface
Inloop at an
Internal
Interface
N1IDQ1A Not supported Supported Supported Supported

Table 24-15 provides the loopback capability of the packet boards of the OptiX OSN equipment.
Table 24-15 Loopback capability of the packet boards of the OptiX OSN equipment
Board Outloop
at the
MAC
Layer
Inloop at
the MAC
Layer
Outloop
at the
PHY
Layer
Inloop at
the PHY
Layer
Inloop
and
Outloop
on a
VC-4
Path
Inloop
and
Outloop
on a VC-3
Path
N1PEX1 Not
supported
Supported Not
supported
Supported Not
supported
Not
supported
N2PEX1 Not
supported
Supported Not
supported
Supported Not
supported
Not
supported
N1PEX2 Supported Supported Not
supported
Not
supported
Not
supported
Not
supported
N1PEG16 Not
supported
Supported Not
supported
Supported Not
supported
Not
supported
N1PEG8 Supported Supported Not
supported
Not
supported
Not
supported
Not
supported
N1PETF8 Supported Not
supported
Not
supported
Supported Not
supported
Not
supported
N1PEFF8 Supported Not
supported
Not
supported
Supported Not
supported
Not
supported
R1PEFS8 Supported Not
supported
Not
supported
Supported Not
supported
Not
supported
R1PEGS1 Supported Not
supported
Not
supported
Supported Not
supported
Not
supported
R1PEF4F Supported Not
supported
Not
supported
Supported Not
supported
Not
supported
Q1PEGS2 Supported Not
supported
Not
supported
Supported Not
supported
Not
supported

Table 24-16 provides the loopback capability of the dual-plane boards of the OptiX OSN
equipment
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-36 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Table 24-16 Loopback capability of the dual-plane boards of the OptiX OSN equipment
Board Inloop at
a Port
Outloop
at a Port
Inloop
on VC-4
path
Outloop
on a
VC-4
Path
Outloop on a
VC-3/VC-12
Path
N1EDQ41 Supported Supported Supported Supporte
d
Not supported

24.5 Protection Schemes Supported by Each Board
The SDH boards, PDH boards, data boards, microwave boards, and packet boards of the OptiX
OSN equipment support various protection schemes.
Table 24-17 lists the protection schemes that the SDH boards of the OptiX OSN equipment
support.
Table 24-17 Protection schemes that the SDH boards of the OptiX OSN equipment support
Board Protection Scheme
Two-
Fiber
Ring
MSP
Four-
Fiber
Ring
MSP
Linear
MSP
SNCP SNCT
P
SNC
MP
MS
P
and
SN
CP
Fibe
r-
Sha
red
Prot
ecti
on
TPS
Prote
ction
N1SL64 x
N2SL64 x
N1SF64
A
x
N1SLD6
4
x
N1SL16 x
N2SL16 x
N3SL16 x
N1SL16
A
x
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-37
Board Protection Scheme
Two-
Fiber
Ring
MSP
Four-
Fiber
Ring
MSP
Linear
MSP
SNCP SNCT
P
SNC
MP
MS
P
and
SN
CP
Fibe
r-
Sha
red
Prot
ecti
on
TPS
Prote
ction
N2SL16
A
x
N3SL16
A
x
N1SLD1
6
x
N1SLQ1
6
x
N1SLO1
6
x
N1SF16 x
N3SLQ4
1
x
N1SL4 x
N2SL4 x
N1SL4A x
R1SL4 x
N1SLQ4 x
N2SLQ4 x
N1SLQ4
A
x
N2SLD4 x
N1SLD4
A
x
R1SLD4 x
N1SLT1 x x
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-38 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Board Protection Scheme
Two-
Fiber
Ring
MSP
Four-
Fiber
Ring
MSP
Linear
MSP
SNCP SNCT
P
SNC
MP
MS
P
and
SN
CP
Fibe
r-
Sha
red
Prot
ecti
on
TPS
Prote
ction
N1SLQ1 x x
N2SLQ1 x x
R1SLQ1 x x
N1SL1 x x
N2SL1 x x
N1SL1A x x
N1SLH1 x
N1SEP1 x
N3SLO1 x x
Note: "" means that the board supports the protection scheme and "x" means that the board
does not support the protection scheme.

Table 24-18 lists the protection schemes that the PDH boards of the OptiX OSN equipment
support.
Table 24-18 Protection schemes that the PDH boards of the OptiX OSN equipment support
Board Protection Scheme
TPS
Protection
for the E1
Services
TPS
Protection
for the E1/
T1 Services
TPS
Protection
for the E3/
T3 Services
TPS
Protection
for the E4/
STM-1
Services
TPS
Protection
for the DDN
Services
R1PL1 x x x x
R1PD1 x x x x
N1PQ1 x x x x
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-39
Board Protection Scheme
TPS
Protection
for the E1
Services
TPS
Protection
for the E1/
T1 Services
TPS
Protection
for the E3/
T3 Services
TPS
Protection
for the E4/
STM-1
Services
TPS
Protection
for the DDN
Services
N1PQM x x x
N1PL3 x x x x
N2PL3 x x x x
N1PL3A x x x x x
N2PL3A x x x x x
N1PD3 x x x x
N2PD3 x x x x
N2PQ3 x x x x
N1DX1 x x x x
N1DXA x x x x
N2SPQ4 x x x x

Table 24-19 lists the protection schemes that the data boards of the OptiX OSN equipment
support.
Table 24-19 Protection schemes that the data boards of the OptiX OSN equipment support
Board Protection Scheme
LCAS STP/
RSTP
TP
S
Pro
tect
ion
B
PS
Pr
ot
ec
tio
n
PP
S
Pr
ot
ect
io
n
L
A
G
D
L
A
G
LP
T
R
P
R
MSP,
SNCP,
SNCM
P, and
SNCTP
ATM
Protecti
on
R1EFT
4
x x x x x x x x x
N1EFT
8
x x x x x x x x x
N1EGT
2
x x x x x x x x
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-40 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Board Protection Scheme
LCAS STP/
RSTP
TP
S
Pro
tect
ion
B
PS
Pr
ot
ec
tio
n
PP
S
Pr
ot
ect
io
n
L
A
G
D
L
A
G
LP
T
R
P
R
MSP,
SNCP,
SNCM
P, and
SNCTP
ATM
Protecti
on
N2EGT
2
x x x x x x x x
N2EFS
0
x x x x x x x
N4EFS
0
x x x x x x x
N5EFS
0
x x x x x x x
N1EFS
0A
x x x x x x x
N1EFS
4
x x x x x x x x
N2EFS
4
x x x x x x x x
N3EFS
4
x x x x x x x x
N2EGS
2
x x x x x x x
N3EGS
2
x x x x x x x
N1EMS
4
x x x x x
N1EMS
2
x x x x x x x
N3EGS
4
x x x x x
N4EGS
4
x x x x x
N2EGR
2
x x x x x x x x
N2EMR
0
x x x x x x x x
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-41
Board Protection Scheme
LCAS STP/
RSTP
TP
S
Pro
tect
ion
B
PS
Pr
ot
ec
tio
n
PP
S
Pr
ot
ect
io
n
L
A
G
D
L
A
G
LP
T
R
P
R
MSP,
SNCP,
SNCM
P, and
SNCTP
ATM
Protecti
on
N1EAS
2
x x x x x x x
N1ADL
4
x x x x x x x x x x
N1ADQ
1
x x x x x x x x x x
N1IDL4 x x x x x x x x x x
N1IDQ
1
x x x x x x x x x x
N1MST
4
x x x x x x x x x x x

Table 24-20 lists the protection schemes that the microwave boards of the OptiX OSN equipment
support.
Table 24-20 Protection schemes that the microwave boards of the OptiX OSN equipment
support
Board Protection schemes
1+1 HSB/FD/SD
Protection
N+1 Protection
N1IFSD1
N1RPWR x x

Table 24-21 lists the protection schemes that the packet boards of the OptiX OSN equipment
support.
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-42 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Table 24-21 Protection schemes that the packet boards of the OptiX OSN equipment support
Board Protection Scheme
MPLS
Tunnel 1
+1/1:1
Protectio
n
LAG MPLS PW
1+1/1:1
MC-LAG DNI APS
N1PEX1 x x x
N2PEX1
N1PEX2
N1PEG16 x x x
N1PEG8
N1PETF8
N1PEFF8
R1PEFS8 x x
R1PEGS1 x x
R1PEF4F x x
Q1PEGS2 x x

Table 24-22 lists the protection schemes that the dual-plane boards of the OptiX OSN equipment
support.
Table 24-22 Protection schemes that the dual-plane boards of the OptiX OSN equipment support
Board Protection Scheme
SDH Protection Packet
Protectio
n
Two-
fiber
MSP
ring
Four-
fiber
MSP
ring
Linear
MSP
SNCP SNCMP SNCTP LAG
N1EDQ
41


OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-43
24.6 Quick Reference of Power Consumption and Weight of
Each Board
This topic lists the power consumption and weight of each board of the OptiX OSN series
equipment.
Table 24-23 lists the power consumption and weight of each board.
Table 24-23 Power consumption and weight of each board
Board Power
Consumption
(W)
Weight
(kg)
Board Power
Consumption
(W)
Weight
(kg)
SDH boards
N1SLQ41 12 0.6 N1SLD4 17 0.6
N1SF64A 33(the OptiX
OSN 3500/3500
II/2500 REG
supports)
26(the OptiX
OSN 7500
supports)
1.1 N2SLD4 15 1.0
N1SF64 33(the OptiX
OSN 3500/3500
II/2500 REG
supports)
26(the OptiX
OSN 7500
supports)
1.1 R1SLD4 11 0.5
N1SLD64 41 1.2 R3SLD4 11 0.5
N1SL64A 40 1.1 N1SL4A 17 0.6
N1SL64 30(the OptiX
OSN 3500/3500
II/2500 REG
supports)
22(the OptiX
OSN 7500
supports)
1.1 N1SL4 17 0.6
N2SL64 32 1.1 N2SL4 15 1.0
T2SL64 40 1.1 R1SL4 10 0.5
N1SF16 26 1.1 R3SL4 11 0.5
N1SLO16 38 1.0 N1SEP1 17 1.0
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-44 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Board Power
Consumption
(W)
Weight
(kg)
Board Power
Consumption
(W)
Weight
(kg)
N1SLQ16 20 0.9 N1SLH1 27 1.0
N2SLQ16 35 1.3 N1SLT1 22 1.3
N1SLD16 23 0.9 N2SLO1 26 1.1
N1SL16A 20 0.6 N3SLO1 20 1.2
N2SL16A 20 1.1 N1SLQ1A 15 1.0
N3SL16A 22 0.9 N1SLQ1 15 1.0
N1SL16 19 1.1 N2SLQ1 15 1.0
N2SL16 19 1.1 R1SLQ1 12 0.4
N3SL16 22 1.1 N1SL1A 17 0.6
N1SLQ4A 17 1.0 N1SL1 17 0.6
N1SLQ4 17 1.0 N2SL1 14 1.0
N2SLQ4 16 1.0 R1SL1 10 0.3
N1SLD4A 17 0.6 R3SL1 11 0.3
T2SL64A 40 1.1 - - -
PDH boards
N1SPQ4 24 0.9 N2PL3 12 0.9
N2SPQ4 24 0.9 N1PQM 22 1.0
N1DXA 10 0.8 N1PQ1 19 1.0
N1DX1 15 1.0 N2PQ1 13 1.0
N1PQ3 13 0.9 R1PD1 15 0.6
N1PD3 19 1.1 R2PD1 15 0.6
N2PD3 12 1.1 R3PD1 8 0.4
N1PL3A 15 1.0 N1PL1 7 0.5
N2PL3A 12 0.9 R1PL1 7 0.5
N1PL3 15 1.0 - - -
EoS/EoP boards
N1MST4 26 0.9 N2EFS4 30 1.0
N1IDQ1 41 1.0 N3EFS4 18 0.6
N1IDL4 41 1.0 N1EFS0A 32 0.7
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-45
Board Power
Consumption
(W)
Weight
(kg)
Board Power
Consumption
(W)
Weight
(kg)
N1ADQ1 41 1.0 N1EFS0 35 1.0
N1ADL4 41 0.9 N2EFS0 35 1.0
N1EAS2 70 1.2 N4EFS0 35 1.0
N1EMR0 47 1.2 N5EFS0 22 0.6
N2EGR2 40 1.1 N1EGT2 29 0.9
N1EGS4A 53 1.1 N2EGT2 15 0.9
N1EGS4 70 1.1 N1EFT8A 26 1.0
N3EGS4 70 1.1 N1EFT8 26 1.0
N4EGS4 34 0.7 N1EFT4 14 0.5
N1EMS4 65 1.1 N1EFT8A 26 1.0
N1EMS2 40 0.8 N1EFT8 26 1.0
N2EGS2 43 1.0 N1EFT4 14 0.5
N3EGS2 25 0.6 R1EFT4 14 0.5
N1EFS4 30 1.0 N2EMR0 50 1.2
N1IDL4A 46 1.5 - - -
Interface boards and switching and bridging boards
N1DM12 0 0.4 N1EU08 11 0.4
N1ETS8 0 0.4 N1EU04 6 0.4
N1ETF8A 11 0.4 N1C34S 0 0.3
N1ETF8 2 0.4 N1D34S 0 0.4
N1EFF8A 15 0.4 N1D75S 0 0.4
N1EFF8 6 0.4 N1L75S 3 0.3
N1TSB8 0 0.3 N1D12S 0 0.4
N1TSB4 3 0.3 N1D12B 0 0.3
N1MU04 2 0.4 R1L12S 5 0.3
N1OU08 6 0.4 - - -
Packet boards
R1PEFS8 12 0.3 N1PETF8 8 0.4
Q1PEGS2 9 0.6 N1PEG16 137 2.3
24 Board Information Quick Reference
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description
24-46 Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
Issue 01 (2010-01-15)
Board Power
Consumption
(W)
Weight
(kg)
Board Power
Consumption
(W)
Weight
(kg)
R1PEGS1 8 0.4 N1PEX1 107 2.4
N1PEG8 80 1.2 N1PEX2 78 1.4
N2PEX1 75 1.4 N1PEFF8 14 0.5
R1PEF4F 15 0.4 - - -
Dual-Mode bridging boards
N1EDQ41 75 1.2 - - -
CES boards
N1MD75 14 0.5 N1MD12 14 0.5
N1CQ1 15 0.5 R1ML1A/
B
16 0.4
Microwave boards
N1IFSD1 24 1.1 N1RPWR 45 1.4
WDM boards
N1FIB 0 0.4 N1MR2B 0 1.0
OBU101 16 1.3 N1MR2A 0 1.0
OBU102 18 1.3 N1MR2 0 0.9
N1LWX 30 1.1 N1CMR4 0 0.9
N1MR4 0 0.9 N1CMR2 0 0.8
N1MR2C 0 1.0 - - -
Cross-Connect and system control boards
N4GSCC 19 1.0 - - -
N1PSXCS 90 2.1 R1PCXLN 60 1.0
N2PSXCS
A
80 2 - - -
N6GSCC 35 0.7 - - -
T1PSXCS
A
100 1.3 - - -
Auxiliary boards
N1FANA 19 1.2 R1AMU 8 0.5
XE1FAN 16 1.5 R1AUX 19 1.0
OptiX OSN 3500 Intelligent Optical Transmission System
Hardware Description 24 Board Information Quick Reference
Issue 01 (2010-01-15) Huawei Proprietary and Confidential
Copyright Huawei Technologies Co., Ltd.
24-47
Board Power
Consumption
(W)
Weight
(kg)
Board Power
Consumption
(W)
Weight
(kg)
XE3FAN 10 1.2 R2AUX 19 1.0
R1FAN 20 0.8 Q1AUX 10 0.5
Q1SEI 10 0.9 N1AUX 19 1.0
N1SEI 1 0.9 T1AUX 3 0.4
Q1SAP 20 0.7 T1EOW 13 0.5
Q2SAP 25 1.0 R1EOW 10 0.4
Optical amplifier boards and dispersion compensation boards
N1DCU 0 0.4 62COA 75 8.0
N2DCU 0 0.4 N1COA 10 3.5
N1RPC02 110 4.2 N1BPA 20 1.0
N1RPC01 70 4.0 N2BPA 11 1.2
61COA 10 3.5 N1BA2 20 1.0
Power interface boards
R1PIUA 2 0.5 N1PIU 8 1.2
R1PIUB 4 0.4 Q2PIU 2 0.3
R1PIUC 5 0.5 Q1PIU 8 1.3
N1PIUA 3 0.5 R1PIU 2 0.4
T1PIU 8 1.3 UPM - 15
N1PIUB 6 0.6 - - -
T1PIUB 6 0.5 - - -

24 Board Information Quick Reference
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25 Parameter Settings
About This Chapter
You can set the parameters for the SDH boards, PDH boards, data boards, WDM boards, optical
amplifier boards, and cross-connect and timing unit by using the T2000.
25.1 Packet Boards
The parameters that need to be set for the packet boards include the working mode and maximum
frame length.
25.2 Dual-Plane Bridging Boards
The parameters that need to be set for the dual-plane bridging boards include the SDH parameters
and Ethernet parameters.
25.3 CES Boards
The parameters that you need to set for CES boards include J0 byte, J1 byte, J2 byte, C2 byte,
V5 byte, SDH interfaces, Ethernet interfaces, automatic laser shutdown (ALS), and recovery
value of idle timeslots.
25.4 Data Boards
The data boards include EoS/EoP boards, ATM boards, RPR boards, and SAN boards. The
parameters that need to be set for the data boards include the SDH parameters, Ethernet
parameters, and ATM parameters.
25.5 SDH Processing Boards
The parameters that need to be set for the SDH processing boards include the J0 byte, J1 byte,
J2 byte, and C2 byte.
25.6 PDH Boards
The parameters that need to be set for the PDH boards include the J1 byte, C2 byte, J2 byte, V5
byte, and tributary loopback.
25.7 WDM Boards
The parameters that need to be set for the WDM boards include the path use status, optical
interface loopback, service type, client service bearer rate (M), laser status, automatic laser
shutdown, current bearer rate (M), actual wavelength no./wavelength (nm)/frequency (THz),
actual band type, configure wavelength no./wavelength (nm)/frequency (THz), configure band
type, and SD trigger condition.
25.8 Cross-Connect and Timing Units
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The parameters that need to be set for the cross-connect and timing units include the clock source
parameters and clock subnet parameters.
25.9 Optical Amplifier Boards
The parameters that need to be set for the optical amplifier boards include the laser status, board
work type, configure band, configure working band parity, actual band, actual working band
parity, threshold of input power loss, gain, rated optical power, nominal gain upper threshold,
and nominal gain lower threshold.
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25.1 Packet Boards
The parameters that need to be set for the packet boards include the working mode and maximum
frame length.
Working Mode
The packet boards support the following working modes: auto-negotiation, 100M full-duplex,
1000M full-duplex, and 10G full-duplex.
Maximum Frame Length
l The maximum frame length of the Ethernet service is 1500 bytes by default.
l The maximum frame length of the port is 1620 bytes by default.
l The maximum frame length of the port must not be less than the maximum frame length
of the Ethernet service.
TAG
This parameter is used to identify the type of packets. This parameter can be set to "tag aware",
"access", or "hybrid".
l When this parameter is set to "tag aware", the interface transparently transmits the packets
that contain a TAG and discards the packets that do not contain a TAG.
l When this parameter is set to "access", the interface adds a TAG to the packets that do not
contain a TAG according to the default VLAN ID of the interface, and discards the packets
that contain a TAG.
l When this parameter is set to "hybrid", the interface processes both the packets that contain
a TAG and the packets that do not contain a TAG. The interface adds a TAG to the packets
that do not contain a TAG according to the default VLAN ID of the interface.
VLAN ID
This parameter specifies the VLAN ID of the interface.
Port Mode
This parameter specifies the mode of a port. This parameter can be set to "level 2" or "level 3".
Encapsulation Type
Set the encapsulation type of a packet as follows:
l When Port Mode is set to Layer 2, Encapsulation Type can be set to Null, 802.1Q, or
QinQ.
l When Port Mode is set to Layer 3, Encapsulation Type can be set to 802.1Q only. In this
case, the interface can be used to carry the tunnel.
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Hardware Description 25 Parameter Settings
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QinQ Type
When a port carries QinQ services, you can set the QinQ type. The QinQ type can be set to a
value within the range of 0x0600 to 0xFFFF. The default value is 0x88a8.
25.2 Dual-Plane Bridging Boards
The parameters that need to be set for the dual-plane bridging boards include the SDH parameters
and Ethernet parameters.
SDH Parameters
l J0
l J1
l J2
l C2
For the description of the parameter, see 25.5 SDH Processing Boards.
Ethernet Parameters
l Ethernet interface
For the description of the parameter, see 25.1 Packet Boards.
25.3 CES Boards
The parameters that you need to set for CES boards include J0 byte, J1 byte, J2 byte, C2 byte,
V5 byte, SDH interfaces, Ethernet interfaces, automatic laser shutdown (ALS), and recovery
value of idle timeslots.
J0 Byte
The J0 byte is used to repeatedly transmit a section access point identifier so that the receive end
can verify its continuous connection to the specified transmit end. It is recommended that the
J0 byte take the default value: disabled.
J1 Byte
The J1 byte is the higher order path trace byte. This byte is used to repeatedly transmit a higher
order path access point identifier so that the receive end can verify its continuous connection to
the specified transmit end. When a J1 mismatch is detected at the receive end, the corresponding
VC-4 path generates an HP_TIM alarm.
It is recommended that the J1 byte take the default value: disabled.
J2 Byte
The J2 byte is the VC-12 lower order path trace byte. Successive transmission of a specified
lower order access point identifier through J2 at the transmit end helps the receive end learn that
its connection with the transmit end is in the continuous connection state.
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Enable the lower order monitoring. Then, you can set and query the J2 byte to be received.
C2 Byte
The C2 byte is the signal label byte, which is used to indicate the multiplexing structure of the
VC frames and the payload attribute. The C2 byte to be sent must match the C2 byte to be
received. When a C2 mismatch is detected, the corresponding VC-4 path at the local end
generates an HP_SLM alarm.
Table 25-1 shows the relationship between the service type and the parameter settings of the
C2 byte.
Table 25-1 Relationship between the service type and the parameter settings of the C2 byte
Service Type Parameter Setting of the C2 Byte
(Hexadecimal)
TUG structure 02
34M/45M into C-3 04
140M into C-4 12
Unequipped 00

V5 Byte
The V5 byte is the path status and signal label byte. The V5 byte is used to detect bit errors,
indicate the remote error and failure of the lower order path, and trigger the generation of LP_REI
and LP_RFI alarms. Table 25-2 shows the relationship between the service type and the
parameter settings of the V5 byte.
Table 25-2 Relationship between the service type and the parameter settings of the V5 byte
Service Type Parameter Setting of the V5 Byte (in
Hexadecimal)
Asynchronous 02
Byte synchronization 04
HDLC/PPP mapping 0A
Unequipped or supervisory-
unequipped
00

SDH Interfaces
The configuration of SDH interfaces include basic attribute, layer-2 attribute, layer-3 attribute,
and advanced attribute. The parameters of SDH interfaces at the Physical Layer, Data Link
Layer, and Network Layer need to be set.
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E1 Interfaces
The configuration of E1 interfaces include basic attribute, layer-3 attribute, and advanced
attribute. The parameters of E1 interfaces, including those at the Physical layer and Network
Layer, frame format, clock mode, and loopback mode, need to be set.
Ethernet Interfaces
The configuration of Ethernet interfaces include basic attribute, layer-2 attribute, layer-3
attribute, advanced attribute, and traffic control. The parameters of E1 interfaces, including those
at the Physical Layer, Data Link Layer, and Network Layer, and traffic control mode, need to
be set.
ALS
The ALS configuration refers to setting the laser parameters of optical interfaces.
Recovery Value of Idle Timeslots
To set the recovery value of idle timeslots is to improve the utilization of paths when TDM
frames are partly filled. At the transmit end, the idle slots are deleted when signals are
encapsulated and transmitted on a network. At the receive end, the idle timeslots are added when
TDM frames are recovered.
25.4 Data Boards
The data boards include EoS/EoP boards, ATM boards, RPR boards, and SAN boards. The
parameters that need to be set for the data boards include the SDH parameters, Ethernet
parameters, and ATM parameters.
25.4.1 SDH Parameters
The SDH parameters that need to be set for the data boards include the J1 byte, C2 byte, J2 byte,
and V5 byte.
25.4.2 Ethernet Parameters
The Ethernet parameters that need to be set for the data boards include the working mode and
LCAS.
25.4.3 ATM Parameters
The ATM parameters that need to be set for the ATM boards include the port type and traffic
type.
25.4.1 SDH Parameters
The SDH parameters that need to be set for the data boards include the J1 byte, C2 byte, J2 byte,
and V5 byte.
J1 Byte
J1 is the path trace byte. Successive transmission of the J1 byte at the transmit end helps the
receive end learn that its connection with the specified transmit end is in the continuous
connection state.
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When a J1 mismatch is detected at the receive end, the VC-3 path generates an LP_TIM_VC3
alarm and the VC-4 path generates an HP_TIM alarm.
When the J1 byte is set to the single-byte "" by default, the alarms are not reported.
NOTE
l In the case of the N1EFS4 and MST4, the J1 byte is set to " HuaWei SBS " by default. In the case
of the other boards, the J1 byte is set to the single-byte "" by default.
l In the case of the EMS4 and EGS4, it is recommended that you set the J1 byte to " HuaWei SBS ".
C2 Byte
C2 is the signal label byte, which is used to indicate the multiplexing structure of the VC frames
and the payload property. The C2 byte to be sent must match the C2 byte to be received.
When a C2 mismatch is detected, the VC-3 path generates an LP_SLM_VC3 alarm and the
VC-4 path generates an HP_SLM alarm.
J2 Byte
J2 is the VC-12 path trace byte. This byte is used to transmit repetitively a low order path access
point identifier so that a path receiving terminal can verify its continued connection to the
intended transmitter.
When a J2 mismatch is detected, the VC-12 path generates an LP_TIM_VC12 alarm.
When the J2 byte is set to the single-byte "" by default, the alarms are not reported.
V5 Byte
V5 is the path status and signal label byte. This byte is used to detect bit errors and indicate
remote errors or remote failures on lower order paths. The LP_REI and LP_RFI alarms are
generated accordingly.
When a V5 mismatch is detected at the receive end, the VC-12 path generates an LP_SLM_VC12
alarm.
Table 25-3 shows the relation between the service type and the value of the V5 byte.
Table 25-3 Relation between the service type and the value of the V5 byte
Service Type Value of the V5 Byte (Hexadecimal)
Asynchronous 02
Byte synchronization 04
HDLC/PPP mapping 0A
Unequipped or supervisory-
unequipped
00

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25.4.2 Ethernet Parameters
The Ethernet parameters that need to be set for the data boards include the working mode and
LCAS.
Working Mode
Generally, the Ethernet interfaces of the interconnected equipment are required to work in the
same fixed working mode. If the working modes on two sides do not match, packets may be lost
or the bit rate may decrease. In the case of large volume of traffic, services may be completely
interrupted.
Currently, the Ethernet boards support the following working modes: auto-negotiation, 10M
half-duplex, 10M full-duplex, 100M half-duplex, 100M full-duplex, 1000M full-duplex, and
10G full-duplex
LCAS
This parameter specifies whether to enable the LCAS function.
Byte Packet
When a packet with a length shorter than 64 bytes is received at the Ethernet port, the EFT8A
supports two different transmission modes (that is, discarded or transparently transmitted) for
the packet. By default, the transparently transmitted mode is used.
Maximum Frame Length
This parameter needs to be set in the case of external interfaces. By default, the maximum frame
length is 1522 bytes.
Mapping Protocol
This parameter needs to be set to consistent values in the case of the interconnected equipment.
Currently, the Ethernet boards support the following mapping protocols:
l HDLC, LAPS, or GFP. It is recommended that you adopt the default value "GFP".
l GFP-F
l LAPS or GFP. It is recommended that you adopt the default value "GFP".
l GFP-T
TAG
This parameter is used to identify the type of packets. This parameter can be set to "tag aware",
"access", or "hybrid".
1. When this parameter is set to "tag aware", the interface transparently transmits the packets
that contain a TAG and discards the packets that do not contain a TAG.
2. When this parameter is set to "access", the interface adds a TAG to the packets that do not
contain a TAG according to the default VLAN ID of the interface, and discards the packets
that contain a TAG.
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3. When this parameter is set to "hybrid", the interface processes both the packets that contain
a TAG and the packets that do not contain a TAG. The interface adds a TAG to the packets
that do not contain a TAG according to the default VLAN ID of the interface.
VLAN ID
This parameter specifies the VLAN ID of the interface.
Port Type
In the case of the boards that support the MPLS function, the ports are available in two types,
namely, provider (P) and provider edge (PE). The port of type P indicates a core network port
of a service provider. The port of type PE indicates an edge port of a service provider. You need
to set this parameter when you configure EVPL services or EVPLAN services. In the case of an
external port, set this parameter to "PE". In the case of an internal port, set this parameter to "P".
Encapsulation Format
This parameter can be set to "MartinioE" or "stack VLAN". When the port type parameter is set
to "P", this parameter becomes valid.
Port Attributes
In the case of the board that supports the QinQ function, you can set this parameter. This
parameter can be set to "UNI", "NNI", "N-UNI", "S-aware", or "C-aware".
CRC Error Frame
When a CRC error frame is received at the Ethernet port, the EFT8A supports two different
transmission modes (that is, discarded or transparently transmitted) for the packet. By default,
the discarded mode is used.
25.4.3 ATM Parameters
The ATM parameters that need to be set for the ATM boards include the port type and traffic
type.
Port Type
The port types include NNI and UNI. The default port type is UNI.
Traffic Type
The traffic type must meet the requirements of the port.
Service Type
Five service types are available, namely, CBR, rt-VBR, nrt-VBR, UBR, and UBR+.
Peak Cell Rate
Set the peak cell rate of the ATM services. This parameter must be set for each service type.
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Sustainable Cell Rate
Set the sustainable cell rate of the ATM services. In the case of the rt-VBR and nrt-VBR services,
set this parameter.
MBS
Set the MBS of the ATM services. In the case of the rt-VBR and nrt-VBR services, set this
parameter.
CDVT
Set the CDVT of the ATM services. In the case of the CBR, rt-VBR, and UBR services, set this
parameter.
25.5 SDH Processing Boards
The parameters that need to be set for the SDH processing boards include the J0 byte, J1 byte,
J2 byte, and C2 byte.
J0 Byte
The J0 byte is used to transmit repetitively a section access point identifier so that a section
receiver can verify its continued connection to the intended transmitter. It is recommended that
you set the J0 byte to the default value, namely, single-byte "Disabled".
J1 Byte
J1 is the higher order path trace byte. This byte is used to transmit repetitively a path access
point identifier so that a path receiving terminal can verify its continued connection to the
intended transmitter. When a J1 mismatch is detected at the receive end, the corresponding VC-4
path generates an HP_TIM alarm.
In the case of the SLO1, it is recommended that you set the J1 byte to " HuaWei SBS ". In
the case of the other boards, it is recommended that the J1 byte uses the default value, namely,
single-byte "Disabled".
NOTE
The J1 byte was set to " HuaWei SBS " by default. In the character string " HuaWei SBS ", there is
one blank space before "HuaWei" and five blank spaces after "SBS".
J2 Byte
J2 is the lower order path trace byte. This byte is used to transmit repetitively a low order path
access point identifier so that a path receiving terminal can verify its continued connection to
the intended transmitter.
To set and query the J2 byte to be received, enable the lower order monitoring function.
NOTE
In the case of the SDH processing boards, the J2 byte to be sent cannot be set.
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C2 Byte
C2 is the signal label byte, which is used to indicate the multiplexing structure of the VC frames
and the payload property. The C2 byte to be sent must match the C2 byte to be received. When
a C2 mismatch is detected, the corresponding VC-4 path at the local end generates an HP_SLM
alarm.
Table 25-4 shows the relation between the service type and the value of the C2 byte.
Table 25-4 Relation between the service type and the value of the C2 byte
Service Type Value of the C2 Byte (Hexadecimal)
TUG structure 02
34M/45M into C-3 04
140M into C-4 12
Unequipped 00

25.6 PDH Boards
The parameters that need to be set for the PDH boards include the J1 byte, C2 byte, J2 byte, V5
byte, and tributary loopback.
J1 Byte
J1 is the path trace byte. This byte is used to transmit repetitively a path access point identifier
so that a path receiving terminal can verify its continued connection to the intended transmitter.
When a J1 mismatch is detected at the receive end, the corresponding VC-4 path generates an
HP_TIM alarm.
The J1 byte is set to the single-byte "" by default.
NOTE
The J1 byte was set to " HuaWei SBS " by default.
C2 Byte
C2 is the signal label byte, which is used to indicate the multiplexing structure of the VC frames
and the payload property. The C2 byte to be sent must match the C2 byte to be received. When
a C2 mismatch is detected, the corresponding VC-4 path at the local end generates an HP_SLM
alarm.
Table 25-5 shows the relation between the service type and the value of the C2 byte.
Table 25-5 Relation between the service type and the value of the C2 byte
Service Type Value of the C2 Byte (Hexadecimal)
TUG structure 02
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Service Type Value of the C2 Byte (Hexadecimal)
34M/45M into C-3 04
140M into C-4 12
Unequipped 00

J2 Byte
J2 is the VC-12 path trace byte. This byte is used to transmit repetitively a low order path access
point identifier so that a path receiving terminal can verify its continued connection to the
intended transmitter.
V5 Byte
V5 is the path status and signal label byte. This byte is used to detect bit errors and indicate
remote errors or remote failures on lower order paths. The LP_REI and LP_RFI alarms are
generated accordingly. Table 25-6 shows the relation between the service type and the value of
the V5 byte.
Table 25-6 Relation between the service type and the value of the V5 byte
Service Type Value of the V5 Byte (Hexadecimal)
Asynchronous 02
Byte synchronization 04
HDLC/PPP mapping 0A
Unequipped or supervisory-
unequipped
00

Equipping Indication
When a service channel only carries the service and does not process the service, select
Unequipped or Supervisory-Unequipped.
When a service channel carries the service and also processes the service, select Equipped-
Unspecific Payload.
Tributary Loopback
The tributary loopback function is used to locate faults in the service channels.
The tributary loopback is also a diagnosis function. When the tributary loopback is performed,
related services are interrupted.
Path Service Type
This parameter is set to specify service type for the channel.
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l Select E1 or T1 for E1/T1 processing boards according to the actual service type in the
channel.
l Select E3 or T3 for E3/T3 processing boards according to the actual service type in the
channel.
Serial Port Protocol Mode
For the DX1, select the protocol mode of the N x 64 kbit/s signals. The protocol mode includes
V.35, V.24, X.21, RS449, RS530 and RS530A.
DDN Clock Source Management
The timing scheme and working clock source can be set for the DX1.
l Set the timing scheme of the DDN channels 1012 and 1416 to the DCE internal scheme,
DCE slave scheme or DTE external scheme.
l Set the timing scheme of the DDN channels 9 and 13 to the DCE internal scheme, DCE
slave scheme, DTE external scheme, DTE internal scheme, DTE slave scheme or DCE
external scheme. By default, the timing scheme is the DCE internal scheme for channels 9
and 13 is the DCE internal scheme.
25.7 WDM Boards
The parameters that need to be set for the WDM boards include the path use status, optical
interface loopback, service type, client service bearer rate (M), laser status, automatic laser
shutdown, current bearer rate (M), actual wavelength no./wavelength (nm)/frequency (THz),
actual band type, configure wavelength no./wavelength (nm)/frequency (THz), configure band
type, and SD trigger condition.
Path Use Status
Item Description
Parameter description Used to set the path use status
Parameter values Used and Unused
Parameter value description Default value: Used
Recommended value Used
Application scenarios In configuration, commissioning, and
maintenance stages
Impact on the system When the Path Use Status of an optical interface
is set to Unused, service alarms at this interface
are suppressed, which disables the automatic laser
turn on function.
Relevant boards LWX
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Item Description
Configuration requirements When the channel is not required, its Path Use
Status can be set to Unused. In this case, a
command should be issued to shut down the laser
of this path; otherwise, an alarm indicates that the
laser is forcibly turned on is reported.

Optical Interface Loopback
Item Description
Parameter description Used to set the loopback mode of the current
optical interface.
Parameter values Non-Loopback, Outloop, and Inloop
Parameter value description Default value: Non-Loopback
Non-Loopback: indicates that the equipment is in
normal state. Optical interface loopback is not
required when the equipment normally operates.
Inloop: indicates a mode that signals to be output
from the output interface of the local-end
equipment are looped back to the signal input
interface of this equipment. Inloop is used to test
the signal processing on the board.
Outloop: indicates a mode that unprocessed
signals accessed to the local-end equipment are
directly looped back to the corresponding output
interface without the signal structure changed.
Outloop is used to test connections between fiber
lines and connectors.
Recommended value Non-Loopback
Application scenarios In commissioning and maintenance stages
Impact on the system When the loopback mode is set to Inloop or
Outloop, services are interrupted.
Relevant boards RPC01 and RPC02
Configuration requirements None

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Service Type
Item Description
Parameter description Used to set the type of services at a client-side
optical interface.
Parameter values LWX: GE, FE, STM-1, STM-16, OC-3, OC-12,
OC-48, FC-100, FC-200 FICON, FICON
Express, DVB-ASI DVB-SDI, and ESCON
Parameter value description Default value: Any
Recommended value None
Application scenarios In configuration, commissioning, and
maintenance stages
Impact on the system None
Relevant boards LWX
Configuration requirements The type of actually accessed services must be the
same as the type of configured services.
Otherwise, the services are not available.

Client Service Bearer Rate (M)
Item Description
Parameter description Used to set the bearer rate of client-side services.
Parameter values(M) 16 to 2500
Parameter value
description
The bearer rate of client-side services can be set only when the
client-side services are of Any type. The set value should equal
to the maximum rate of actually accessed services.
Recommended value None
Application scenarios In configuration, commissioning, and maintenance stages
Impact on the system A SPEED_OVER alarm is reported when the rate of actually
accessed services exceeds the set value.
Relevant boards LWX
Configuration
requirements (the set
value of bearer rate
should be the same as the
rate of actually accessed
services)
Actually
accessed
services
Set value
(M)
Actually
accessed
services
Set value (M)
STM-1 155.5 GE 1250
STM-4 622 FE 125
STM-16 2488.3 FC100 1062
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Item Description
OC3 155.5 FC200 2124
OC12 622 FICON 1062
OC48 2488.3 FICON
Express
2124
HDTV 270 ESCON 200
DVB-SDI 270 FDDI 125
DVB-ASI 270 - -

Laser Status
Item Description
Parameter description Used to set the laser Open/Close status.
Parameter values Open and Close
Default value: Open
Parameter value description Open: The laser is turned on to start transmitting
services.
Close: The laser is turned off to stop service
transmitting.
Recommended value Open
Application scenarios In configuration, commissioning, and
maintenance stages
Impact on the system When the laser is set to Close, services are
interrupted.
Relevant boards LWX
Configuration requirements When an optical interface is unused or is not
connected to a fiber, the laser at this interface
should be set to Open.

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Automatic Laser Shutdown
Item Description
Parameter description Used to set whether to enable automatic laser
shutdown (ALS) of the downstream laser of the
local board in the case of loss of received signals.
If ALS is enabled, when the received signals are
lost, the laser is automatically shut down and stops
transmitting signals. ALS prolongs the service life
of a laser and avoids personal injury from the laser.
Parameter values Enabled and Disabled
Parameter value description By default, ALS of optical interfaces on client
sides is set to Enabled and ALS of optical
interfaces on WDM sides is set to Disabled.
Recommended value ALS of optical interfaces on client sides is set to
Enabled and ALS of optical interfaces on WDM
sides is set to Disabled.
Application scenarios In configuration and maintenance stages
Impact on the system None
Relevant boards LWX
Configuration requirements If the optical interface on a WDM side does not
use the ESC as the network management channel
or no fiber is connected, you can set ALS of the
optical interface to Enabled to prolong the service
life of the laser.

Current Bearer Rate (M)
Item Description
Parameter description Used to query the current bearer rate of client-side
services.
Parameter values Can only be queried
Parameter value description None
Recommended value None
Application scenarios In configuration, commissioning, and
maintenance stages
Impact on the system None
Relevant boards LWX
Configuration requirements None

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Hardware Description 25 Parameter Settings
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Actual Wavelength No./Wavelength (nm)/Frequency (THz)
Item Description
Parameter description Used to query the operating wavelength at the
WDM-side optical interface of a board.
Parameter values Can only be queried
Parameter value description None
Recommended value None
Application scenarios In configuration, commissioning, and
maintenance stages
Impact on the system None
Relevant boards LWX
Configuration requirements None

Actual Band Type
Item Description
Parameter description Used to query the band type.
Parameter values Can only be queried
Parameter value description None
Recommended value None
Application scenarios In commissioning and maintenance stages
Impact on the system None
Relevant boards LWX
Configuration requirements None

Configure Wavelength No./Wavelength (nm)/Frequency (THz)
Item Description
Parameter description Used to configure the operating wavelength at the
WDM-side optical interface of a board.
Parameter values C-band wavelength spacing: 100G
(192.100-196.00 THz)
CWDM-band wavelength spacing: 20 nm
(1271-1611 nm)
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Item Description
Parameter value description The operating wavelength of a fixed-wavelength
OTU should be set to the actual wavelength of the
OTU. The operating wavelength of a tunable-
wavelength OTU should be set according to the
network wavelength planning.
Recommended value None
Application scenarios In configuration stage
Impact on the system l The same wavelength should be used for a
service in the receive and transmit directions.
l If a service travels through multiple
regenerating stations, it is recommended that
these regenerating sections use the same
wavelength.
l It is recommended that the active and standby
channels use the same wavelength when the
inter-board channel protection or client-side
path protection is adopted.
Relevant boards LWX
Configuration requirements The configured logic wavelength must be the same
as the actual physical wavelength. Otherwise, a
CFGDATA_OUTRANGE alarm is reported. In
the case of tunable optical modules, issuing the
captioned command directly changes their
physical wavelengths (but does not change the
band). In the case of non-tunable optical modules,
issuing this command changes their logic
wavelengths only.

Configure Band Type
Item Description
Parameter description Used to configure the band type.
Parameter values(dBm) C and CWDM
Parameter value description None
Recommended value None
Application scenarios In configuration, commissioning, and
maintenance stages
Impact on the system None
Relevant boards LWX
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Item Description
Configuration requirements The configured logic band must be the same as
the actual physical band. Otherwise, a
CFGDATA_OUTRANGE alarm is reported.

SD Trigger Condition
Item Description
Parameter description Used to configure the trigger condition to perform
SD switching on the board.
Parameter values(dBm) B1_SD, OTUk_DEG, ODUk_PM_DEG, and
None
Parameter value description B1_SD: Regeneration section (B1) signal
degrade
OTUk_DEG: OTUk signal degrade
ODUk_PM_DEG: ODUk_PM signal degrade
None: No condition is configured for SD
switching.
Recommended value Set the value to None.
Application scenarios In commissioning and maintenance stages
Impact on the system When the B1_SD, OTUk_DEG, or
ODUk_PM_DEG alarm occurs, the protection
group might be triggered to perform protection
switching.
Relevant boards LWX
Configuration requirements Set the value to B1_SD, OTUk_DEG, or
ODUk_PM_DEG if the protection mechanism
needs such a trigger condition.

25.8 Cross-Connect and Timing Units
The parameters that need to be set for the cross-connect and timing units include the clock source
parameters and clock subnet parameters.
Table 25-7 lists the parameters that need to be set for the cross-connect and timing units.
25 Parameter Settings
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Table 25-7 Parameters that need to be set for the cross-connect and timing units
Domain Parameter Value Configuration
Clock
Synchroni
zation
Status
NE Name - Displays the name of an NE.
NE Clock
Working Mode
Tracing Mode,
Holdover Mode,
Free-Run Mode
This field shows the current working
mode of the clock function board on
the NE. This field is read-only.
Tracing Mode: It is the normal
working mode and indicates that the
clock is synchronized with the input
reference clock source under the
actual service conditions.
Holdover Mode: Indicates that the
clock works with the stored
frequency information as the timing
reference after all the timing
references are lost.
Free-Run Mode: Indicates that the
clock works through the internal
oscillator.
S1 Byte
Synchronization
Quality
Information
For example: NA Displays the S1 byte synchronous
quality information in the clock
function on the current NE. For query
only.
S1 Byte Clock
Synchronous
Source
For example: NA Displays the trace source of the
current NE clock. For query only.
This field displays no information
until the S1 byte (clock protection
function) is activated. Similarly, this
field displays NA until you press the
Query button, and then it displays the
related information.
Synchronous
Source
For example:
External Clock
Source 1
Displays the trace source of the
current NE clock. For query only.
Normally, the synchronous source
should be a clock source with the
highest priority among the clock
stratums. If the synchronous source
cannot be traced, try to trace a clock
source with a lower priority level
according to the sequence of the clock
stratums.
Data Output
Method in
Holdover Mode
Normal Data
Output Mode,
Keep the Latest
Data Default:
Normal Data
Output Mode
Displays the data output method.
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Domain Parameter Value Configuration
Clock
source
priority
Clock source - The clock sources currently used by
the NE are listed in sequence. The top
clock source is of the highest priority.
External clock
source mode
2 MHz and 2 Mbit/
s
Select the mode only for the input
external clock source.
Synchronous
status byte
Sa4, Sa5, Sa6,
Sa7, and Sa8
Select the synchronous status byte
only for the input external clock
source that is in 2 Mbit/s mode.
Clock
source
switching
condition
AlS alarm
generated
Selected and not
selected
This parameter specifies the
condition for determining the clock
source switching. When an AIS alarm
occurs on an NE, the NE determines
whether to perform the clock source
switching.
B1 BER
threshold-
crossing
generated
Selected and not
selected
This parameter specifies the
condition for determining the clock
source switching. When the B1 BER
on an NE crosses the threshold, the
NE determines whether to perform
the clock source switching.
RLOS, RLOF and
OOF alarms
generated
Selected When an R_LOS, R_LOF, or OOF
alarm occurs on an NE, the NE
considers that the corresponding
clock source fails.
Phase-
locked
source
output by
external
clock
External clock
output mode
when 2M output
synchronous
source is invalid
Synchronization
quality
unavailable,
output AIS, and
shut off
Default value:
Shut off
This parameter is used to set the
operation to be performed by the
system when the output of the
synchronous clock (that is, 2M phase-
locked source) fails.
Output mode of
external clock
source 1
2 Mbit/s and 2
MHz
The NE provides two external clock
outputs. This parameter is used to set
the output mode for external clock
source 1.
Output mode of
external clock
source 2
2 Mbit/s and 2
MHz
The NE provides two external clock
outputs. This parameter is used to set
the output mode for external clock
source 2.
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Domain Parameter Value Configuration
Clock source
threshold
No threshold
value, G.813 SDH
equipment timing
source (SETS)
signal, G.812
local clock signal,
G.812 transit
clock signal, G.
811 clock signal,
and unknown
Set a threshold for the 2M
synchronous output sources. The
threshold is set for the clock
protection function of the S1 byte.
The NE clock system uses this
threshold as the basis for ensuring the
quality of the output clock. If a clock
is of a quality higher than the
threshold, the clock system transmits
clock signals.
Clock
source
switching
Lock status Lockout and
unlock
This parameter is used to set whether
the clock source switching is allowed.
Switching
operation
Forced switching,
manual switching,
and clear
switching
This parameter specifies the
switching operation to be performed
on the clock source.
Clock
source
reversion
parameter
Higher priority
clock source
reversion mode
Auto-revertive
and non-revertive
When the clock source of a higher
priority degrades, the NE
automatically switches to the clock
source of a lower priority. When this
parameter is set to "Auto-revertive",
the NE automatically switches back
to the clock source of a higher priority
when the clock source of the higher
priority is restored. When this
parameter is set to "Non-revertive",
the NE does not automatically switch
back to the clock source of a higher
priority when the clock source of the
higher priority is restored.
Clock source
WTR time
0 to 12 minutes This parameter is used to set the
period from the time when the
recovery of the clock is detected to
the time when the clock selector
responds. This setting prevents
repeated switching from occurring in
the case of unstable signals.
Clock
subnet
Affiliated subnet Default value: 0 This parameter is used to set the
subnet ID.
Protection status Start extended
SSM protocol,
start standard
SSM protocol, and
stop SSM protocol
This parameter specifies whether to
start up the SSM protocol.
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Domain Parameter Value Configuration
Clock source ID 1 to 15 Huawei equipment uses the first four
bits of the S1 byte to identify the
clock source. Hence, the subnet clock
source ID is the four bits.
SSM
output
control
Line port All the line ports
of the current NE
This parameter displays the line ports
that can be controlled.
Control status Enabled and
disabled
This parameter specifies whether the
line port allows the output of the
quality information carried by the S1
byte. Generally, set this parameter to
"Disabled" at edges of a network to
prevent impact on the other
equipment.
Clock
quality
Configuration
quality
Unknown
synchronization
quality, G.811
clock signal, G.
812 transit clock
signal, G.812
local clock signal,
G.813 SDH
equipment timing
source (SETS)
signal, do not use
for
synchronization,
and automatic
extraction
Default value:
Automatic
extraction
This parameter is used to set the clock
quality. Specify the clock quality of
the clock source listed in the priority
table. If an option other than
"Automatic extraction" is selected,
the NE considers the specified clock
quality (other than the actual clock
quality) as the criteria.
Clock quality Unknown
synchronization
quality, G.811
clock signal, G.
812 transit clock
signal, G.812
local clock signal,
G.813 SDH
equipment timing
source (SETS)
signal, do not use
for
synchronization,
and automatic
extraction
The clock source quality information
actually received by the NE is
extracted by the NE from the S1 byte
of each clock source. When the
customer queries the actual clock
quality and the NE successfully
returns the result, the quality can be
displayed. Otherwise, it displays "no
information".
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Domain Parameter Value Configuration
Clock ID
status
Line port All the line ports
of the current NE
This parameter displays the line ports
that can be configured with the clock
ID.
Enabled status Enabled and
disabled
Default value:
Enabled
This parameter specifies whether to
enable the setting of the clock ID.

25.9 Optical Amplifier Boards
The parameters that need to be set for the optical amplifier boards include the laser status, board
work type, configure band, configure working band parity, actual band, actual working band
parity, threshold of input power loss, gain, rated optical power, nominal gain upper threshold,
and nominal gain lower threshold.
Laser Status
Item Description
Parameter description Used to set the laser Open/Close status.
Parameter values Open and Close
Default value of the OBU1: Open
Default value of the RPC01/RPC02: Close
Recommended value Close
Application scenarios In configuration, commissioning, and
maintenance stages
Impact on the system When the laser is set to Close, services are
interrupted.
Relevant boards OBU1, RPC01, and RPC02
Configuration requirements When services are normal, the laser of the optical
amplifying unit should be set to Open.

Board Work Type
Item Description
Parameter description Used to query and set the Board Work Type.
Parameter values C, C+L, and L
Parameter value description None
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Item Description
Recommended value C
Application scenarios In configuration, commissioning, and
maintenance stages
Impact on the system None
Relevant boards RPC01 and RPC02
Configuration requirements None

Configure Band
Item Description
Parameter description Used to configure the type of the working band of
a board.
Parameter values C
Parameter value description Supports only C band.
Recommended value None
Application scenarios In configuration, commissioning, and
maintenance stages
Impact on the system None
Relevant boards OBU1, RPC01, and RPC02
Configuration requirements None

Configure Working Band Parity
Item Description
Parameter description Selects the required parity of the working band.
Parameter values All, Even, and Odd
Parameter value description All: All 192.10 THz to 196.05 THz odd and even
wavelengths at 50 GHz channel spacing in C band.
There are 80 wavelengths in total. It is applicable
for the OBU1, RPC01, and PRC02 boards.
Even: All 192.10 THz to 196.00 THz even
wavelengths at 100 GHz channel spacing. There
are 40 wavelengths in total. It is applicable for the
RPC01 and PRC02 boards.
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Item Description
Odd: All 192.15 THz to 196.05 THz odd
wavelengths at 100 GHz channel spacing. There
are 40 wavelengths in total. It is applicable for the
RPC01 and PRC02 boards.
Recommended value Corresponding wavelengths are used according to
different requirements.
Application scenarios In commissioning and maintenance stages
Impact on the system None
Relevant boards OBU1, RPC01, and RPC02
Configuration requirements When configuring the parity of wavelengths,
make sure that the parity configured is consistent
with the parity of the actual working wavelengths.

Actual Band
Item Description
Parameter description Used to query the actual working band of the
board.
Parameter values Can only be queried
Parameter value description None
Recommended value None
Application scenarios In commissioning and maintenance stages
Impact on the system None
Relevant boards OBU1
Configuration requirements None

Actual Working Band Parity
Item Description
Parameter description Used to query the parity of the actual working band
of the board.
Parameter values Can only be queried
Parameter value description None
Recommended value None
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Item Description
Application scenarios In commissioning and maintenance stages
Impact on the system None
Relevant boards OBU1, RPC01, and RPC02
Configuration requirements None

Threshold of Input Power Loss (dBm)
Item Description
Parameter description Indicates the lower threshold of input optical
power loss (an MUT_LOS alarm is reported).
Parameter values Can only be queried
Parameter value description The default value varies with the boards and
subjects to the on-site queried result.
Recommended value None
Application scenarios In commissioning and maintenance stages
Impact on the system None
Relevant boards OBU1
Configuration requirements None

Gain (dB)
Item Description
Parameter description Used to query the optical power gain of the current
optical amplifying unit.
Parameter values Can only be queried
Parameter value description None
Recommended value None
Application scenarios In configuration, commissioning, and
maintenance stages
Impact on the system None
Relevant boards OBU1
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Item Description
Configuration requirements Normally, the queried result should range from the
nominal gain minus 2.5 dB to the nominal gain
plus 2.5 dB.

Nominal Gain Upper Threshold (dB)
Item Description
Parameter description Used to query the nominal gain upper threshold.
Parameter values Can only be queried
Parameter value description None
Recommended value None
Application scenarios In commissioning and maintenance stages
Impact on the system None
Relevant boards OBU1
Configuration requirements None

Nominal Gain Lower Threshold (dB)
Item Description
Parameter description Used to query the nominal gain lower threshold.
Parameter values Can only be queried
Parameter value description None
Recommended value None
Application scenarios In commissioning and maintenance stages
Impact on the system None
Relevant boards OBU1
Configuration requirements None

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Rated Optical Power (dBm)
Item Description
Parameter description Used to set and query the single-wavelength rated
optical power as the reference value for automatic
optical power adjustment.
Parameter values (dBm) 30.0 to 30.0
Parameter value description Default value at the input optical interface: 19
dBm
Default value at the output optical interface: 4
dBm
Recommended value OBUC01: input interface: 20 dBm; output
interface: 0 dBm
OBUC03: input interface: 19 dBm; output
interface: 4 dBm
Application scenarios In configuration, commissioning, and
maintenance stages
Impact on the system None
Relevant boards OBU1
Configuration requirements The rated input and output optical power should
be configured by referring to the actual
configurable input and output range of the optical
amplifying unit and should be the same as the
input and output values measured when the
optical amplifying unit operates normally.

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A Glossary
Numerics
1+1 protection A 1+1 protection architecture has one normal service signal,
one working SNC/trail, one protection SNC/trail and a
permanent bridge.
1:N protection A 1:N protection architecture has N normal service signals, N
working SNCs/trails and one protection SNC/trail. It may have
one extra service signal.
10BASE-T Physical layer specification for a 10 Mbit/s CSMA/CD local
area network over two pairs of twisted-pair telephone wire.
100BASE-T Physical Layer specification for a 100 Mbit/s CSMA/CD local
area network.
100BASE-TX Physical layer specification for a 100 Mbit/s CSMA/CD local
area network over two pairs of category 5 unshielded twisted-
pair (UTP) or shielded twisted-pair (STP) wire.
1PPS Pulse per second, which, strictly speaking, is not a time
synchronization signal. This is because 1PPS provides only the
"gauge" corresponding to the UTC second, but does not
provide the information about the day, month, or year.
Therefore, 1PPS is used as the reference for frequency
synchronization. On certain occasions, 1PPS can also be used
on other interfaces for high precision timing.
3R Reshaping, Retiming, Regenerating.

A
ACAP The Adjacent Channel Alternate Polarization (ACAP)
operation provides orthogonal polarizations between two
adjacent communication channels.
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ADM Add/Drop Multiplexing. Network elements that provide
access to all or some subset of the constituent signals contained
within an STM-N signal. The constituent signals are added to
(inserted), and/or dropped from (extracted) the STM-N signal
as it passed through the ADM.
Administrator A user with the authority to use the management functions of
the NMS.
Administrative unit The information structure which provides adaptation between
the higher order path layer and the multiplex section layer. It
consists of an information payload (the higher order VC) and
a AU pointer which indicates the offset of the payload frame
start relative to the multiplex section frame start.
Administrative unit group One or more Administrative Units occupying fixed, defined
positions in an STM payload are termed an Administrative
Unit Group (AUG).An AUG-1 consists of a homogeneous
assembly of AU-3s or an AU-4.
AIS Alarm Indication Signal. A signal sent downstream in a digital
network if an upstream failure has been detected and persists
for a certain time.
Alarm A visible or an audible indication to notify the person
concerned that a failure or an emergency has occurred.
Alarm correlation analysis A process wherein alarm is raised within five seconds after
alarm 1 is raised, and alarm 2 complies with the conditions
defined in the alarm correlation analysis rule. You can either
suppress alarm 2 or raise its severity level according to the
behavior defined in the alarm correlation rule.
Alarm indication On the cabinet of an NE, there are three indicators with
different colors indicating the current state of the NE. You can
stop the NE alarm indication through the NMS.
Alarm indication signal A code sent downstream in a digital network as an indication
that an upstream failure has been detected. It is associated with
multiple transport layers.
Alarm reversion A function that is used to avoid generating relevant alarm
information, thus preventing alarm interference, for the port
that has already been configured but not actually loaded with
services.
Alarm reversion mode The alarm reversion mode of an NE that defines whether the
port is automatically restored to the normal status after a
service is accessed or a fault is removed. There are three alarm
reversion modes: automatic, manual and not-revertive.
Alarm Severity Four alarm levels defined by the ITU-T Recommendations.
The four levels are critical, major, minor and warning.
Alarm suppression When alarms of various levels occur at the same time, certain
lower-level alarms are suppressed by higher-level alarms, and
thus will not be reported.
A Glossary
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Antistatic floor The floor which is ESD preventive.
Anti-Static Jack Jacks on the cabinet or subrack with the ESD label. The other
end of the antistatic wrist strap is inserted into the jack.
APS Automatic Protection Switching (APS) is the capability of a
transmission system to detect a failure on a working facility
and to switch to a standby facility to recover the traffic.
Asynchronous A network where transmission system payloads are not
synchronized and each network terminal runs on its own clock.
ATM Asynchronous Transfer Mode. A transfer mode in which the
information is organized into cells. It is asynchronous in the
sense that the recurrence of cells containing information from
an individual user is not necessarily periodic. It is a protocol
within the OSI layer 1. An ATM cell consists of a 5 octet header
followed by 48 octets of data.
ATPC Automatic Transmit Power Control. A method of
automatically adjusting the transmit power at the opposite end
based on the transmit signal detected at the receiver.
Attenuation Reduction of signal magnitude or signal loss, usually
expressed in decibels.
Attenuator A passive component that attenuates an electrical or optical
signal.
Attribute Property of an object.
Auto negotiation The algorithm that allows two devices at either end of a link
segment to negotiate common data service functions.
Automatic protection
switching
The ability of a network element to detect a failed working line
and switch the service to a spare (protection) line. 1+1 APS
pairs a protection line with each working line. 1:N APS
provides one protection line for every n working lines.

B
Backup A method to save the data to prevent damage to the original
data.
Backplane A PCB circuit board in the subrack, which is connected with
all the boards in position.
Bandwidth Information-carrying capacity of a communication channel.
Analog bandwidth is the range of signal frequencies that can
be transmitted by a communication channel or network.
BER The ratio of the number of bits received in error to the total
number of bits received.
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BIP BIP-X code is defined as a method of error monitoring. With
even parity an X-bit code is generated by the transmitting
equipment over a specified portion of the signal in such a
manner that the first bit of the code provides even parity over
the first bit of all X-bit sequences in the covered portion of the
signal, the second bit provides even parity over the second bit
of all X-bit sequences within the specified portion, etc. Even
parity is generated by setting the BIP-X bits so that there is an
even number of 1s in each monitored partition of the signal. A
monitored partition comprises all bits which are in the same
bit position within the X-bit sequences in the covered portion
of the signal. The covered portion includes the BIP-X.
BIP-8 Bit Interleaved Parity-8. A method of error checking in
SONET which allows a full set of performance statistics to be
generated. For example, a BIP-8 creates eight-bit (one-byte)
groups, then does a parity check for each of the eight bit
positions in the byte.
Binding In virtual concatenated payload configuration, to specify one
binding number to identify the VC4s of the same virtual
concatenated payload. If a fault occurs to one of the bound
services, all bound services will switch as a whole.
Binding strap The binding strap is 12.7 mm wide, with one hook side (made
of transparent polypropylene material) and one mat side (made
of black nylon material).
Bit Error An error to some bits in the digital code stream after receiving,
generation. Bit errors accompany the damage to the
transmitted ation.
Bit error rate The number of coding violations detected in a unit of time,
usually one second. Bit error rate (BER) is calculated with this
formula: BER = errored bits received/total bits sent
BITS Building Integrated Timing Supply. A building timing supply
that minimizes the number of synchronization links entering
an office. Sometimes referred to as a synchronization supply
unit.
Bound path The VC Trunk refers to the 2 Mbps paths which are bound
together to transmit Ethernet data. The VC Trunk is an entity
between the Ethernet port and the 2 Mbps path.
Bridge It refers to a functional unit that connects two or more local
area networks (LANs).
Broadcast The act of sending a frame addressed to all stations on the
network.
Build-in WDM A function which integrates some simple WDM systems into
products that belong to the OSN series . That is, the OSN
products can add or drop several wavelengths directly.

A Glossary
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C
Cabling The methods to route the cables or fibers.
Cabling frame The frame which is used for cable routing over the cabinet.
Cabling hole A hole which is used for cable routing in the cabinet.
Cabling ladder The ladder between the cabinet and the cabling rack, which is
used for cable routing.
Cabling trough The trough which is used for cable routing in the cabinet.
CAR Committed Access Rate. The CAR limits the input or output
transmission rate on an interface.
CBR Constant Bit Rate. The Constant Bit Rate service category is
used by connections that request a static amount of bandwidth
that is continuously available during the connection lifetime.
This amount of bandwidth is characterized by a peak cell Rate
(PCR) value.
CCM Connectivity check message (CCM) is a type of message that
is used to check the link status.
CDVT Cell Delay Variation Tolerance. Information sent in the
forward and backward direction to determine the upper bound
of the tolerance admitted for the time interval between cells
pertaining to a given cell flow. The backward CDVT values
included in the IAM and MOD shall be interpreted as
maximum acceptable values for the cell flow in the backward
direction.
Centralized alarm system The system that gathers all the information about alarms into
a certain terminal console.
CFM Ethernet Connectivity Fault Management (CFM) is an end-to-
end per-service-instance Ethernet layer operation,
administration, and management (OAM) protocol. It includes
proactive connectivity monitoring, fault verification, and fault
isolation for large Ethernet metropolitan area networks
(MANs) and wide area networks (WANs).
Chain network One type of network that all network nodes are connected one
after one to be in series.
Channel The smallest subdivision of a circuit that provides a type of
communication service; usually a path with only one direction.
Check alarms To compare one or more uncleared alarms on the NMS with
alarms in the NE. If an alarm is included in the current alarms
on the NE, it is kept on the NMS. If not, it will be removed
from the NMS.
Circuit A communications path or network; usually a pair of channels
providing bi-directional communication.
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Client A kind of terminal (PC or workstation) connected to a network
that can send instructions to a server and get results through a
user interface. See also server.
Clock tracing The method to keep the time on each node being synchronized
with a clock source in a network.
Clock Synchronization Also called frequency synchronization, clock synchronization
means that the signal frequency traces the reference frequency,
but the start point need not be consistent.
Concatenation Concatenation is a critical feature of the SDH. Concatenation
refers to a process in which multiple virtual containers are
combined into one group that serves as an independent
container with bit sequence integrity. This meets the
requirements of client signal transmission in capacities larger
than C-4. Concatenation is classified into adjacent
concatenation and virtual concatenation.
Configuration To set the basic parameters of an operation object.
Configuration Data A command file for an NE which defines the configuration of
the NE hardware. With the file, the NE can coordinate with
other NEs in the entire network. Configuration data is the key
factor for the normal running of the entire network.
Configuration
management
Configuration management enables inventory query of
network configuration resources, including relevant
configuration of NMS or SNMS, NE, subnet, links, SNC,
route, TP, edge point, equipment, and so on. Real-time
inventory change report can also be provided through this
resource, it will be timely reported to the upper NMS to notify
the carrier of the current network operation status and ensure
data consistency of the upper NMSs.
Congestion The condition that exists in a network if the capacity needed
for the instantaneous traffic exceeds the bandwidth available
in the network.
Connection A "transport entity" which consists of an associated pair of
"unidirectional connections" capable of simultaneously
transferring information in opposite directions between their
respective inputs and outputs.
Convergence The process of developing a model of the echo path which will
be used in the echo estimator to produce the estimate of the
circuit echo.
Convergence service A service that provides enhancements to an underlying service
in order to provide for the specific requirements of the
convergence service user.
Conversion In the context of message handling, a transmittal event in which
an MTA transforms parts of a message content from one
encoded information type to another, or alters a probe so it
appears that the described messages were so modified.
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Corrugated pipe A plastic pipe which is used for fiber routing.
CoS Class of service (CoS) is a technology or method used to
classify services into different categories according to the
service quality.
Current Alarms Alarms that have not been cleared, or those that have been
cleared but are not acknowledged.
Current Performance
Data
Performance data stored in the current register. An NE
provides two types registers for each performance parameter
of the performance monitoring entity. The registers are 15-
minute register and 24-hour register, which are used to
accumulate the performance data within the current
monitoring period.
Cyclic redundancy check A technique for using overhead bits to detect transmission
errors.

D
DDF Digital Distribution Frame. A frame which is used to transfer
cables.
Defect A limited interruption in the ability of an item to perform a
required function.
Demultiplexing A process applied to a multiplex signal for recovering signals
combined within it and for restoring the distinct individual
channels of the signals.
Digital signal An electrical or optical signal that varies in discrete steps.
Electrical signals are coded as voltages, optical signals are
coded as pulses of light.
DLAG The distributed link aggregation group (DLAG) is a board-
level port protection technology used to detect unidirectional
fiber cuts and to negotiate with the opposite end. In the case of
a link down failure on a port or a hardware failure on a board,
the services can automatically be switched to the slave board,
thus realizing 1+1 protection for the inter-board ports.
Downward cabling Route cables or fibers between the rack and other equipments
from the bottom of the cabinet.
Drop The port on a network element where the service to an end
customer may be connected, e.g., a tributary card on a SONET
ADM. For example, a drop for a DS1 customer service may
be provided by a VT1.5 card terminating a VT1.5 trail.
DSCP Differentiated services code point.
It is defined as the first six bits of the ToS field by RFC2474.
If the DSCP is used to mark the packets, the packets can be
classified into a maximum of 64 classes.
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E
ECC Embedded Control Channel. An ECC provides a logical
operations channel between SDH NEs, utilizing a data
communications channel (DCC) as its physical layer.
Ejector lever A component at the two ends of the front panel of a board,
which is used for inserting or removing the board.
EMU Environment Monitoring Unit. As one type of power and
environment monitoring unit, EMU is installed on the top of
the OptiX 155/622H equipment cabinet to monitor the
environment variables, such as the power supply and
temperature. With external signal input through the relay, fire
alarm, smoke alarm, burglary alarm, and so on can be
monitored as well. Displayed on the NMS, the change of
environment can be monitored timely and accurately.
Encapsulation In 1000BASE-X, the process by which a MAC packet is
enclosed within a PCS code-group stream.
Entity A part, device, subsystem, functional unit, equipment or
system that can be individually considered. For ETH-OAM,
an OAM entity generally refers to a specified system or
subsystem that supports the OAM protocol. For example, a
Huawei Ethernet service processing board is an OAM entity.
ESCON Enterprise System Connection. A path protocol which
connects the host with various control units in a storage system.
It is a serial bit stream transmission protocol. The transmission
rate is 200 Mbit/s.
ESD Electrostatic Discharge. The phenomena that enables energy
to be instantly produced by the electrostatic resource
discharge .
EPL Ethernet Private Line. An EPL service is a point-to-point
interconnection between two UNIs without SDH bandwidth
sharing. Transport bandwidth is never shared between
different customers.
EPLAN Ethernet Private LAN. An EPLAN service is both a LAN
service and a private service. Transport bandwidth is never
shared between different customers.
Ethernet A data line level protocol that consists of the two bottom layers
of the OSI model. Several physical media, such as twisted pairs
and co-axial cables, can be used for the Ethernet broadcast
network topology. The Ethernet uses the CSMA/CD to detect
conflict.
Ethernet Alarm Group The Ethernet alarm group periodically obtain the statistics
value to compare with the configured threshold. If the value
exceeds the threshold, an event is reported.
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Ethernet History Control
Group
The Ethernet history control group controls the method for
periodically obtaining the statistics data from networks of
different types.
Ethernet History Group The Ethernet history group records the history statistics data
of the Ethernet network.
Ethernet Statistics Group The Ethernet statistics group records the current statistics data
of the Ethernet interfaces that are monitored.
ETSI European Telecommunications Standards Institute.
EVPL Ethernet Virtual Private Line. An EVPL service is a service
that is both a line service and a virtual private service.
EVPLAN Ethernet Virtual Private Local Area Network. An EVPLAN
service is a LAN service and a virtual private service.
Exercise Switching An operation to check if the protection switching protocol
functions normally. The protection switching is not really
performed.
Extra traffic Unprotected traffic that is carried over the protection channels
when not occupied by working traffic. The extra traffic may
be preempted to provide transport channel for protected or
highly protected transport entities in the event of failure.
E-LAN Ethernet LAN. A L2VPN service type that is provided for the
user Ethernet in different domains over the PSN network. For
the user Ethernet, the entire PSN network serves as a Layer 2
switch.
E-Line Ethernet line. An point-to-point private service type that is
provided for the user Ethernet in different domains.

F
Failure If the fault persists long enough to consider the ability of an
item with a required function to be terminated. The item may
be considered as having failed; a fault has now been detected.
Fairness For any link specified in a ring network, if the data packets
transmitted by the source node are constrained by the fairness
algorithm, the source node is provided with certain bandwidth
capacities. This feature of RPR is called fairness.
Fault A fault is the inability of a function to perform a required
action. This does not include an inability due to preventive
maintenance, lack of external resources, or planned actions.
FD Frequency Diversity. Two or more microwave frequencies
with certain frequency space are used to transmit/receive the
same signal and selection is then performed between the two
signals to ease the impact of fading.
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FDDI Fiber Distributed Data Interface. A standard for a 100 Mbit/s
fiber-optic local-area network.
Feature code Code(s) used to select/activate a service feature (e.g.
forwarding, using two or three digit codes preceded by * or 11
or #, and which may precede subsequent digit selection).
FEC Forwarding equivalence class. A term used in multiprotocol
label switching (MPLS) to describe a group of packets which
are forwarded in the same manner (e.g., over the same path,
with the same forwarding treatment). FEC can be classified by
address, service type, priority of packets, and may be bound to
a MPLS label
FEC Forward error correction, It is a kind of technology for
enhancing the reliability of digital transmission. It can increase
transmission distance and improve network performance.
Fiber connector A device mounted on the end of a fiber-optic cable, light
source, receiver, or housing that mates to a similar device to
couple light into and out of optical fibers. A connector joins
two fiber ends, or one fiber end and a light source or detector.
Fiber jumper The fiber which is used to connect the subrack with the ODF.
FICON Fiber Connect. A new generation connection protocol which
connects the host with various control units. It carries single
byte command protocol through the physical path of fiber
channel, and provides higher rate and better performance than
ESCON.
Flow An aggregation of packets that have the same characteristics.
On the NMS or NE software, flow is a group of classification
rules. On boards, it is a group of packets that have the same
quality of service (QoS) operation. At present, two flows are
supported: port flow and port+VLAN flow. Port flow is based
on port ID and port+VLAN flow is based on port ID and VLAN
ID. The two flows cannot coexist in the same port.
Forced switch This command performs ring switching from working
channels to the protection channels. This switch occurs
regardless of the state of the protection channels, unless the
protection channels are satisfying a higher priority bridge
request.
Frame A cyclic set of consecutive time slots in which the relative
position of each time slot can be identified.
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Free-run mode An operating condition of a clock, the output signal of which
is strongly influenced by the oscillating element and not
controlled by servo phase-locking techniques. In this mode the
clock has never had a network reference input, or the clock has
lost external reference and has no access to stored data, that
could be acquired from a previously connected external
reference. Free-run begins when the clock output no longer
reflects the influence of a connected external reference, or
transition from it. Free-run terminates when the clock output
has achieved lock to an external reference.

G
Gateway IP IP address is used for TCP/IP communication between an NE
and the NMS, which is effective only when it is used for TCP/
IP communication. That is, only the gateway NE needs the IP
address. IP address cannot be used to identify an NE uniquely.
NEs in different TCP/IP networks may have the same IP
address. And one NE may have several IP addresses (for
example: an IP address of a dial-up network, an IP address of
the Ethernet port and so on).
Gateway NE Gateway Network Element. Gateway NE provides the
communications between NEs and network management
system.
GFP GFP is a framing and encapsulated method which can be
applied to any data type. It has been standardized by ITU-T
SG15.
Grooming Consolidating or segregating traffic for efficiency.
Guide slot A slot on the expansion bolt.

H
Half duplex Pertaining to, both parties that only one party can send data,
while the other party can only receive data on the
communication link.
Hardware loopback A method to use a fiber to connect the receiving optical
interface with the transmitting one on a board. It performs
transmission tests, which method usually does not require the
assistance of personnel at the served terminal.
HDLC A general-purpose data link control protocol defined by ISO
for use on both point-to-point and multipoint (multidrop) data
links. It supports full-duplex, transparent-mode operation. It is
used extensively in both multipoint and computer networks.
History Performance Data The performance data that is stored in the history register or
that is autoreported and stored in the NMS.
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I
IDU Indoor Unit. The indoor unit implements accessing,
multiplexing/demultiplexing, and IF processing for services.
IMA Inverse Multiplexing for ATM. The ATM inverse
multiplexing technique involves inverse multiplexing and de-
multiplexing of ATM cells in a cyclical fashion among links
grouped to form a higher bandwidth logical link whose rate is
approximately the sum of the link rates. This is referred to as
an IMA group.
IMA frame The IMA frame is used as the unit of control in the IMA
protocol. It is a logical frame defined as M consecutive cells,
numbered 0 to M-l, transmitted on each of the N links in an
IMA group.
Input jitter tolerance The maximum amplitude of sinusoidal jitter at a given jitter
frequency, which, when modulating the signal at an equipment
input port, results in no more than two errored seconds
cumulative, where these errored seconds are integrated over
successive 30 second measurement intervals.
IP address A 32-bit identifier that is unique to each network device.
IP over DCC The IP Over DCC follows TCP/IP telecommunications
standards and controls the remote NEs through the Internet.
The IP Over DCC means that the IP over DCC uses overhead
DCC byte (the default is D1-D3) for communication.
IPA The factors such as fiber cut, degradation of equipment, and
removal of connectors may result in the loss of the optical
power signals. The function of intelligent power adjusting
(IPA) enables the ROP laser and booster amplifier (BA) of a
section to be shut down automatically. In this way, the
maintainers, their eyes in particular, can be protected for the
exposed optical fibers when they are performing the repairs.
Isolation A nonreciprocal optical device intended to suppress backward
reflections along an optical fibre transmission line while
having minimum insertion loss in the forward direction.

J
Jitter Short waveform variations caused by vibration, voltage
fluctuations, and control system instability.
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Jitter tolerance For STS-N electrical interfaces, input jitter tolerance is the
maximum amplitude of sinusoidal jitter at a given jitter
frequency, which results in no more than two errored seconds
cumulative, when the signal is modulated at an equipment
input port. These errored seconds are integrated over
successive 30 second measurement intervals. Requirements on
input jitter tolerance as just stated, are specified in terms of
compliance with a jitter mask, which represents a combination
of points. Each point corresponds to a minimum amplitude of
sinusoidal jitter at a given jitter frequency which results in two
or fewer errored seconds in a 30 second measurement interval
when the signal is modulated at the equipment input port. For
the OC-N optical interface, it is defined as the amplitude of the
peak-to-peak sinusoidal jitter applied at the input of an OC-N
interface that causes a 1 dB power penalty.

L
label A mark on a cable, a subrack, or a cabinet for identification.
LACP Link Aggregation Control Protocol (LACP) is part of an IEEE
specification (802.3ad) that allows you to bundle several
physical ports to form a single logical channel. LACP allows
a switch to negotiate an automatic bundle by sending LACP
packets to the peer.
LAG Link aggregation group. A group in which multiple links
connected to the same equipment are bundled together to
increase the bandwidth and improve the link reliability. An
LAG can be regarded as one link.
LAN A local area network that covers a small area such as a family,
an office, or a building group that consists of families, offices
and/or a university. Currently, most LANs are constructed
based on the switched Ethernet or Wi-Fi technology, running
at 1000 Mbit/s (namely, 1 Gbit/s).
Laser A component that generates directional optical waves of
narrow wavelengths. The laser light has better coherence than
ordinary light. The fiber system takes the semi-conductor laser
as the light source.
Layer A concept used to allow the transport network functionality to
be described hierarchically as successive levels; each layer
being solely concerned with the generation and transfer of its
characteristic information.
Layer 2 switching Layer 2 switching can realize the packet switching between
switch ports according to MAC addresses of packets, by
adopting the 802.1d algorithm or 802.1q algorithm.
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LCAS Link Capacity Adjustment Scheme. A solution features
flexible bandwidth and dynamic adjustment. In addition, it
provides a failure tolerance mechanism, which enhances the
viability of virtual concatenations and enables the dynamic
adjustment to bandwidth (non-service affecting).
License A permission provided by a vendor to authorize the use of
specific functions of a product. Generally the license consists
of encrypted codes, and the operation authority varies with
different level of license.
Link A "topological component" that provides transport capacity
between two endpoints in different subnetworks via a fixed
(i.e., inflexible routing) relationship. The endpoints are
"subnetwork termination point pools" for SONET, and link
termination points for ATM. Multiple links may exist between
a pair of subnetworks. A link also represents a set of "link
connections".
LLC According to the IEEE 802 family of standards, Logical Link
Control (LLC) is the upper sublayer of the OSI data link layer.
The LLC is the same for the various physical media (such as
Ethernet, token ring, WLAN).
Loopback A process to return the signals to the opposite end by setting
the hardware or software.
Lower Threshold When the performance event count value is smaller than a
certain value, a threshold-crossing event occurs. The value is
the lower threshold.
LSP Label switch path. An ingress and egress switched path built
through a series of LSRs to forward the packets of a particular
FEC using a label swapping forwarding mechanism.
LSR Label switch router. LSR is to forward packets in an MPLS
network by looking only at the fixed-length label.

M
MAC Media Access Control. The data link sublayer that is
responsible for transferring data to and from the Physical
Layer.
Main Topology A basic component of man-machine interface for the NMS.
The main topology displays the networking details and the
basic ation about NEs, alarms of subnets, communication
status.
Maintenance Domain The network or the part of the network for which faults in
connectivity are to be managed, belonging to a single
administration. The boundary of a Maintenance Domain is
defined by a set DSAPs, each of which may become a point of
connectivity to a Service Instance.
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Maintenance Association That portion of a Service Instance, preferably all of it or as
much as possible, the connectivity of which is maintained by
CFM. It is also a full mesh of Maintenance Entities.
Mapping A procedure by which tributaries are adapted into virtual
containers at the boundary of an SDH network.
Mean launched power The average power of a pseudo-random data sequence coupled
into the fibre by the transmitter.
MEP Maintenance association end point. An edge node of the
maintenance association.
MIB Management information base (MIB) is the formal description
for a group a network objects that can be managed by the
SNMP. MIB is the database of the network performance
information that is saved on the agent.
MPLS Multiprotocol Label Switching. Multi-protocol label
switching. It is a standard routing and switching technology
platform, capable of supporting various high level protocols
and services. The data transmission over an MPLS network is
independent of route calculating. MPLS, as a connection-
oriented transmission technology, guarantees QoS effectively,
supports various network level technologies, and is
independent of the link layer.
MSP Multiplex Section Protection. The MSP function provides
capability for switching a signal from a working section to a
protection section.
MSTP Multi-service transmission platform. It is based on the SDH
platform, capable of accessing, processing and transmitting
TDM services, ATM services, and Ethernet services, and
providing unified management of these services.
MSTP Multiple spanning tree protocol. The MSTP can be used in a
loop network. Using an algorithm, the MSTP blocks redundant
paths so that the loop network can be trimmed as a tree
network. In this case, the proliferation and endless cycling of
packets is avoided in the loop network. The protocol that
introduces the mapping between VLANs and multiple
spanning trees. This solves the problem that data cannot be
normally forwarded in a VLAN because in STP/RSTP, only
one spanning tree corresponds to all the VLANs.
Multicast Transmission of a frame to stations specified by a group
address.
Multiplex To transmit two or more signals over a single channel.
Multiplexing A procedure by which multiple lower order path layer signals
are adapted into a higher order path or the multiple higher order
path layer signals are adapted into a multiplex section.
Multiplex section
overhead
The multiplex section overhead comprises rows 5 to 9 of the
SOH of the STM-N signal.
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Multiplex section
protection
A function provides capability for switching a signal between
and including two MST functions, from a working to a
protection channel.

N
N+1 protection A microwave link protection system that employs N working
channels and one protection channel.
NE Network Element. A stand-alone physical entity that supports
network element functions and may also support operations
system function or mediation functions. It contains managed
objects, a message communication function and a management
applications function.
NE Explorer A main operation interface of the NMS. An expandable object
tree (function tree) is absent at the lower left pane of the
interface. The user can fast locate the operation object from the
object tree and then perform configuration, management and
maintenance accordingly.
NNI Network Node Interface. NNI identifies the interface between
the ATM network nodes. See also SDH NNI.
Non-revertive In non-revertive mode, when a protection switch occurs, the
working service will be switched to the protection service and
the status will remain after it returns normal.
NRZ Non Return to Zero. A digital code in which the signal level is
low for a 0 bit and high for a 1 bit and dose not return to 0
between successive 1 bits.

O
OAM auto-discovery In the case of OAM auto-discovery, two interconnected ports,
enabled with the Ethernet in the First Mile OAM (EFM OAM)
function, negotiate to determine whether the mutual EFM
OAM configuration match with each other by sending and
responding to the OAM protocol data unit (OAMPDU). If the
mutual EFM OAM configuration match, the two ports enter
the EFM OAM handshake phase. In the handshake phase, the
two ports regularly send the OAMPDU to maintain the
neighborhood relation.
ODF Optical Distribution Frame. A frame which is used to transfer
and spool fibers.
ODU Outdoor Unit. The outdoor unit implements frequency
conversion and amplification for RF signals.
ONE Optical Network Element. A stand-alone physical entity in an
optical transmission network that supports at least network
element functions.
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Optical amplifier Devices or subsystems in which optical signals can be
amplified by means of the stimulated emission taking place in
an suitable active medium. An optical amplifier is used to
amplify optical signals in an optical transmission system.
Optical attenuator A passive component that attenuates an electrical or optical
signal.
Optical Connector A component normally attached to an optical cable or piece of
apparatus for the purpose of providing frequent optical
interconnection/disconnection of optical fibers or cables.
Optical Interface A component that connects several transmit or receive units.

Orderwire It establishes voice communication among the operators and
maintenance engineers working in each working station.
OTDR Optical Time Domain Reflectometer. An instrument that
measures transmission characteristics by sending a short pulse
of light down a fiber and observing backscattered light.
Output optical power The ranger of optical energy level of output signals.
Overhead Extra bits in a digital stream used to carry information besides
traffic signals. Orderwire, for example, would be considered
overhead information.

P
Paired slots Two slots of which the overheads can be passed through by
using the bus on the backplane. When the SCC unit is faulty
or offline, the overheads can be passed through between the
paired slots by using the directly connected overhead bus.
When two SDH boards form an MSP ring, the boards need to
be inserted in paired slots so that the K bytes can be passed
through.
Pass-through The transmission equipment directly forwards the received
higher order path overhead to the next station, and this station
only performs detection.
Path A logical connection between the point at which a standard
frame format for the signal at the given rate is assembled, and
the point at which the standard frame format for the signal is
disassembled.
Path overhead Overhead accessed, generated, and processed by path-
terminating equipment. Path overhead includes nine bytes of
STS Path Overhead and, when the frame is VT-structured, five
bytes of VT Path Overhead.
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Path protection The working principle of path protection: When the system
works in path protection mode, the PDH path uses the dual-fed
and signal selection mode. Through the tributary unit and
cross-connect unit, the tributary signal is sent simultaneously
to the east and west lines. Meanwhile, the cross-connect matrix
sends the signal dually sent from the opposite end to the
tributary board through the active and standby buses, and the
hardware of the tributary board automatically and selectively
receive the signal from the two groups of buses automatically
according to the AIS number of the lower order path.
Payload The portion of the SONET signal available to carry service
signals such as DS1 and DS3. The contents of an STS SPE or
VT SPE.
Payload pointer The pointer that indicates the location of the beginning of the
Synchronous Payload Envelope.
PCR Peak Cell Rate. An upper limit on the rate at which cells can
be submitted on an ATM connection.
PVP Virtual path. Virtual path that consists of PVCs.
PDH Plesiochronous Digital Hierarchy. PDH is the digital
networking hierarchy that is used before the advent of Sonet/
SDH.
PE Provider Edge. A PE is the name of the device or set of devices
at the edge of the provider network with the functionality that
is needed to interface with the customer.
Performance register Performance register is the memory space for performance
event counts, including 15-min current performance register,
24-hour current performance register, 15-min history
performance register, 24-hour history performance register,
UAT register and CSES register.
Performance threshold Performance events usually have upper and lower thresholds.
When the performance event count value exceeds the upper
threshold, a performance threshold-crossing event is
generated; when the performance event count value is below
the upper threshold for a period of time, the performance
threshold-crossing event is ended. In this way, performance
jitter caused by some sudden events can be shielded.
Plesiochronous A network with nodes timed by separate clock sources with
almost the same timing.
Pointer An indicator whose value defines the frame offset of a virtual
container with respect to the frame reference of the transport
entity on which it is supported.
PRBS A sequence that is random in a sense that the value of an
element is independent of the values of any of the other
elements, similar to real random sequences.
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Primitive In the hierarchy of signaling system No.7, when the upper layer
applies for services from the lower layer or the lower layer
transmits services to the upper layer, the data is exchanged
between the user and the service provider. In this case, the data
transmitted between adjacent layers is called primitive.
Private line Both communication parties are connected permanently.
Procedure A generic term for an action.
Process A generic term for a collection of actions.
Protection subnet In the NMS, the protection subnet becomes a concept of
network level other than multiplex section rings or path
protection rings. The protection sub-network involves NEs and
fibre cable connections.
Protection view A topology-based interface in the NMS. In the Protection
View, you can: 1. Search, view, create, set and manage
protection subnets. 2. Manage isolated nodes and SDH NNIs.
See also Trail View, Clock View.
PVC Permanent Virtual Connection. Traditional ATM Permanent
Virtual Connection that is established/released upon a request
initiated by a management request procedure (that is all nodes
supporting the connections need to be instructed by the
network management).
PW Pseudo wire. A mechanism that bears the simulated services
between PEs on the PSN(Packet Switched Network).

Q
QoS Quality of Service. Information sent in the forward direction
to indicate the Quality of Service class requested by the user
for a connection. QoS classes are defined to allow a network
to optimize resources in supporting various service classes.

R
Receiver Sensitivity Receiver sensitivity is defined as the minimum acceptable
value of average received power at point R to achieve a 1 x
10-10 BER.
Reference clock A clock of very high stability and accuracy that may be
completely autonomous and whose frequency serves as a basis
of comparison for the frequency of other clocks.
REG A device that performs regeneration.
Regeneration The process of receiving and reconstructing a digital signal so
that the amplitudes, waveforms and timing of its signal
elements are constrained within specified limits.
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Regenerator section
overhead
The regenerator section overhead comprises rows 1 to 3 of the
SOH of the STM-N signal.
Remote defect indication
(RDI)
A signal returned to the transmitting Terminating Equipment
upon detecting a Loss of Signal, Loss of Frame, or AIS defect.
RDI was previously known as FERF.
Remote optical pumping
amplifier (ROPA)
An remote optical amplifier sub-system designed for
applications where power supply and monitoring systems are
unavailable. The ROPA subsystem is a power compensation
solution to the ultra-long distance long hop (LHP)
transmission.
Ring network One type of network that all network nodes are connected one
after one to be a cycle.
RMON RMON is a type of the MIB defined by the Internet engineering
task force (IETF). The RMON mainly realizes the monitoring
of the data flow in a network section or in the entire network.
Root path cost Value of root bridge can be reached with the least aggregate
path is called the root path cost.
Root port It refers to the port corresponding to the cheapest path to the
root bridge.
Route The path a trail takes.
RPR Resilient Packet Ring. A metropolitan area network (MAN)
technology supporting data transfer among stations
interconnected in a dual-ring configuration.
RS232 In the asynchronous transfer mode and there is no hand-
shaking signal. It can communicate with RS232 and RS422 of
other stations in point-to-point mode and the transmission is
transparent. Its highest speed is 19.2kbit/s.
RS422 The interface can change to RS232 through the hardware
jumper and others are the same as RS232.
RSTP The Rapid Spanning Tree Protocol is an evolution of the
Spanning Tree Protocol, providing for faster spanning tree
convergence after a topology change.

S
S1 byte The byte defined in ITU-T to transmit the network
synchronization status information.
SAN Storage Area Network. A dedicated high-speed data storage
network which interconnects multiple independent storage
systems with multiple servers through fibre path switch or
other switch equipment.
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SD Space Diversity. Two or more antennas separated by a specific
distance transmit/receive the same signal and selection is then
performed between the two signals to ease the impact of fading.
Currently, only receive SD is used.
SDH Synchronous Digital Hierarchy. A hierarchical set of digital
transport structures, standardized for the transport of suitably
adapted payloads over physical transmission networks.
Section The portion of a SONET transmission facility, including
terminating points, between (i) a terminal network element and
a regenerator or (ii) two regenerators. A terminating point is
the point after signal regeneration at which performance
monitoring is (or may be) done.
Section overhead Nine bytes of overhead accessed, generated, and processed by
section terminating equipment. This overhead supports
functions such as framing the signal and performance
monitoring.
Self-healing Self-healing is the establishment of a replacement connection
by network without the NMC function. When a connection
failure occurs, the replacement connection is found by the
network elements and rerouted depending on network
resources available at that time.
Service protection The measures to make sure the service transmitting not to be
damaged or corrupted.
Settings Parameters of an operation that can be selected by the user.
SF A signal indicating that the associated data has failed. It means
that a near-end defect condition (not being the degraded defect)
is active.
SFP small form-factor pluggable.
Side mode suppression
ratio
The ratio of the largest peak of the total source spectrum to the
second largest peak.
Slide rail A component in the cabinet, which is used to place the subrack.
Simple network
management protocol
An IETF protocol for monitoring and managing systems and
devices in a network. The data being monitored and managed
is defined by a Management Information Base (MIB). The
functions supported by the protocol are the request and
retrieval of data, the setting or writing of data, and traps that
signal the occurrence of events.
Signal cable The cable which is used to transmit electrical signals, different
from the power cable or fiber.
Signal degrade A signal indicating the associated data has degraded in the
sense that a degraded defect (dDEG) condition is active.
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Signal fail A signal indicating the associated data has failed in the sense
that a near-end defect condition (not being the degraded defect)
is active.
SNCP Subnet Connection Protection. A working subnetwork
connection is replaced by a protection subnetwork connection
if the working subnetwork connection fails, or if its
performance falls below a required level.
SNCP node A node that is set on the protection subnet to support SNCP
that spans protection subnets. The SNCP node of the ring
subnet can support electric circuit dual feed and selectively
receive a time slot out of the ring, thus implementing subnet
connection protection.
SNCMP Subnetwork connection multipath protection. The only
difference is that SNCP is of 1+1 protection and SNCMP is of
N+1 protection. That is, several backup channels protect one
active channel in SNCMP.
SNCTP Subnetwork Connection Tunnel Protection. SNCTP provides
a VC-4 level channel protection. When the working channel is
faulty, the services of the entire VC-4 path can be switched
over to the protection channel.
SSM Synchronization Status Message. ITU-T defines S1 byte to
transmit the network synchronization status information. It
uses the lower four bits of the multiplex section overhead S1
byte to indicate 16 types of synchronization quality grades.
Statistical multiplexing In the statistical multiplexing mode, bandwidth is dynamically
allocated based on the data amount within the transmission
capacity of the physical equipment. This mode is suitable to
any transmission rate.
STM-N Synchronous Transport Module. An STM is the information
structure used to support section layer connections in the SDH.
It consists of information payload and Section Overhead
(SOH) information fields organized in a block frame structure
which repeats every 125 ms. The information is suitably
conditioned for serial transmission on the selected media at a
rate which is synchronized to the network. A basic STM is
defined at 155.520 kbit/s.
STP STP is a protocol that provides a loop free topology for any
bridged LAN and is used in switched networks to prevent loops
by blocking certain ports on some of the bridges in the network.
Subnet The logical entity in the transmission network and comprises
a group of network management objects. A subnet can contain
NEs and other subnets. A subnet planning can enhance the
organization of a network view.
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Subnet mask Also referred to as the network mask off code, it is used to
define network segments, so that only the computers in the
same network segment can communicate with one another,
thus suppressing broadcast storm between different network
segments.
Support The frame on the bottom of a cabinet, when installing the
cabinet on the antistatic floor.
Switching priority There may be the case that several protected boards need to be
switched; thus the tributary board switching priority should be
set. If the switching priority of each board is set the same, the
tributary board that fails later cannot be switched. The board
with higher priority can preempt the switching of that with
lower priority.
Synchronous A network where transmission system payloads are
synchronized to a master (network) clock and traced to a
reference clock.
Synchronous source A clock providing timing services to connected network
elements. This would include clocks conforming to
Recommendations G.811, G.812 and G.813.

T
T2000 A subnet management system (SNMS). In the
telecommunication management network architecture, the
T2000 is located between the NE level and network level,
which can supports all NE level functions and part of the
network level management functions.
T2000 LCT A lite version of T2000. It is an element level management
system for the optical transmission network. It can manage
SDH, DWDM and Metro optical transmission equipment. See
also LCT.
TCM Tandem Connection Monitor. In the SDH transport hierarchy,
the TCM is located between the AU/TU management layer and
HP/LP layer. It uses the N1/N2 byte of POH overhead to
monitor the quality of the transport channels on a transmission
section (TCM section).
TCP/IP Transmission Control Protocol/Internet Protocol. Common
name for the suite of protocols developed to support the
construction of worldwide internetworks.
Timeslot Single timeslot on a E1 digital interfacethat is, a 64-kbps,
synchronous, full-duplex data channel, typically used for a
single voice connection.
Time Synchronization Also called the moment synchronization, time synchronization
means that the synchronization of the absolute time, which
requires that the starting time of the signals keeps consistent
with the UTC time.
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TMN The entity which provides the means used to transport and
process information related to management functions for the
telecommunications network.
ToS Type of service. A field in an IP packet (IP datagram) that is
used for quality of service (QoS). The ToS field is eight bits,
broken into five subfields.
TPS Tributary Protection Switch. Tributary protection switching, a
function provided by the equipment, is intended to protect N
tributary processing boards through a standby tributary
processing board.
Trail A type of transport entity, mainly engaged in transferring
signal from the input of the trail source to the output of the trail
sink, and monitoring the integrality of the transferred signal.
Trail management
function
A network level management functions of the NMS. Through
trail management, you can configure end-to-end services, view
graphic interface and visual routes of a trail, query detailed
information of a trail, filter, search and locate a trail quickly,
manage and maintain trails in a centralized manner, manage
alarms and performance data by trail, and print a trail report.
Transceiver An electronic device which has both transmit and receive
capabilities.
Transparent transmission A process during which the signaling protocol or data is not
processed in the content but encapsulated in the format for the
processing of the next phase.
Tray A discal component in the cabinet, which is used to place the
chassis or other equipment.
Tributary loopback A fault location method. A fault can be located for each service
path by performing loopback on each path of the tributary
board. There are three types of loopback modes: Non-
loopback, Outloop and Inloop.
Tributary unit An information structure which provides adaptation between
the lower order path layer and the higher order path layer. It
consists of an information payload (the lower order VC) and a
TU pointer which indicates the offset of the payload frame start
relative to the higher order VC frame start.
TUG A unit group that contains one or more Tributary Units,
occupying fixed, defined positions in a higher order VC-n
payload. TUGs are defined in such a way that mixed capacity
payloads made up of different size Tributary Units can be
constructed to increase flexibility of the transport network.
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TUG-3 Tributary unit group. One or more Tributary Units, occupying
fixed, defined positions in a higher order VC-n payload is
termed a Tributary Unit Group (TUG). TUGs are defined in
such a way that mixed capacity payloads made up of different
size Tributary Units can be constructed to increase flexibility
of the transport network. A TUG-2 consists of a homogeneous
assembly of identical TU-1s or a TU-2. A TUG-3 consists of
a homogeneous assembly of TUG-2s or a TU-3.

U
U2000 To be oriented to the future network trend, the iManager U2000
that is the unifed network management system (NMS)
combines all-IP and FMC, and manages carrier equipment and
access equipment in a centralized manner.
U2000 LCT Local maintenance terminal of the U2000, the simplified
version of the U2000. It is the NE-level management system
of the transport network, and can implement comprehensive
management of multi-service transport network.
UART Universal Asynchronous Receiver/Transmitter. This is used
for serial communications. The UART translates between
serial and parallel signals, and provides data sent to or from
the computer.
UNI UNI is the abbreviation for User Network Interface. It
identifies the interface between the user and the ATM network
node.
UPC/NPC User Parameter Control/Network Parameters Control. A set of
actions taken by the ATM NE to monitor and control service.
Their main purpose is to detect violations of negotiated service
parameters and to take appropriate action.
Upload An operation to report some or all configuration data of an NE
to the NMS. The configuration data then covers the
configuration data stored at the NMS side.
Upper threshold The critical value that can induce unexpected events if
exceeded.
Upward cabling Cables or fibers connect the rack with other equipment from
the top of the cabinet.
User The user of the NMS client, and the user and password define
the corresponding authority of operation and management of
the NMS.

V
VC Virtual container.
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VCC Virtual Channel Connection. That is a VC connection between
two nodes.
VCI Virtual Channel Identifier. That is the identifier of VC.
Virtual concatenation
(VC)
Virtual concatenation refers to a scheme in which VC-12,
VC-3 or VC-4 distributed in different STM-N services are
concatenated (by using the same route or different routes) into
a VC-4-xv for transmission.
VLAN Virtual local area network. A subset of the active topology of
a Bridged Local Area Network. Associated with each VLAN
is a VLAN Identifier (VID).
VPI The VPI, shorted for Virtual Path Identifier, occupies 12 bits
in the NNI cell, and 8 bits in the UNI cell.
VPN Virtual Private Network. Enables IP service to be transmitted
securely over a public TCP/IP network by encrypting all the
services from one network to another.

W
WAN A wide area network. It uses a communication circuit to
connect medium nodes.
Wander The long-term variations of the significant instants of a digital
signal from their ideal position in time (where long-term
implies that these variations are of frequency less than 10Hz).
Washer A washer which is used to level the cabinet.
Wavelength protection
group
The wavelength protection group is important to describe the
wavelength protection structure. Its function is similar to that
of the protection subnetwork in the SDH NE. The wavelength
path protection can only work with the correct configuration
of the wavelength protection group.
WDM Wavelength Division Multiplexing. WDM technology utilizes
the characteristics of broad bandwidth and low attenuation of
single mode optical fibre, uses multiple wavelengths as
carriers, and allows multiple channels to transmit
simultaneously in a single fibre.
Winding pipe A tool for fiber routing, which acts as the corrugated pipe.
WTR Wait to Restore. This command is issued when working
channels meet the restoral threshold after an SD or SF
condition. It is used to maintain the state during the WTR
period unless it is pre-empted by a higher priority bridge
request.
WTR time A period of time that must elapse before a - from a fault
recovered - trail/connection can be used again to transport the
normal traffic signal and/or to select the normal traffic signal
from.
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B Acronyms and Abbreviations
A
ABR Available Bit Rate
AC Alternating Current
ADM Add/drop Multiplexer
AIS Alarm Indication Signal
ALS Automatic Laser Shutdown
APID Access Point Identifier
APS Automatic Protection Switching
APSC Automatic Protection Switching Control
ATM Asynchronous Transfer Mode
ATPC Automatic Transmit Power Control
AU Adaptation Unit
AUG Administrative Unit Group

B
BA Booster Amplifier
BBE Background Block Error
BER Bit Error Rate
BDI Backward Defect Indicator
BGND Backhaul Ground
BIP Bit-Interleaved Parity
BITS Building Integrated Timing Supply
BMC Best Master Clock
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BPDU Bridge Protocol Data Unit
BPS Board Protection Switching
BSC Base Station Controller
BSS Base Station Subsystem
BWS Backbone WDM System

C
CAR Committed Access Rate
CAS Channel Associated Signaling
CBPDU Configuration BPDU
CBR Constant Bit Rate
CBS Committed Burst Size
CC Connectivity Check
CCDP Co-Channel Dual Polarization
CCM Continuity Check Message
CDR Clock and Data Recovery
CDVT Cell Delay Variation Tolerance
CFM Connectivity Fault Management
CGMP Cisco Group Management Protocol
CIR Committed Information Rate
CIST Common and Internal Spanning Tree
CLP Cell Loss Priority
CoS Class of Service
CPE Customer Premises Equipment
CPU Central Processing Unit
CRC Cyclic Redundancy Check
CSF Client Signal Fail
CST Common Spanning Tree
CTS Cordless Telephony System
C-VLAN Customer VLAN

D
B Acronyms and Abbreviations
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DC Direct Current
DCC Data Communication Channel
DCD Data Carrier Detect
DCE Data Circuit-terminal Equipment
DCN Data Communication Network
DDF Digital Distribution Frame
DDN Digital Data Network
DiffServ Differentiated Service
DLAG Distributed Link Aggregation Group
DNI Dual Node Interconnection
DQDB Distributed Queue Dual Bus
DSCP Differentiated Services Code Point
DSL Digital Subscriber Line
DSLAM Digital Subscriber Line Access Multiplexer
DSR Data Set Ready
DTE Data Terminal Equipments
DTR Data Terminal Ready
DVB-ASI Digital Video Broadcast- Asynchronous Serial Interface
DVMRP Distance Vector Multicast Routing Protocol
DWDM Dense Wavelength Division Multiplexing

E
ECC Embedded Control Channel
EFM Ethernet in the First Mile
EMS Element Management System
EoS Ethernet Over SDH
EPL Ethernet Private Line
EPLAN Ethernet Private LAN
ESCON Enterprise Systems Connection
ESD Electrostatic Discharge
ES-IS End System-Intermedia System
ETSI European Telecommunications Standards Institute
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EVPL Ethernet Virtual Private Line
EVPLAN Ethernet Virtual Private LAN
E-AGGR Ethernet-Aggregation
E-Line Ethernet Line
E-LAN Ethernet LAN

F
FC Fiber Channel
FCS Frame Check Sequence
FD Frequency Diversity
FDDI Fiber Distributed Data Interface
FDI Forward Defect Indicator
FE Fast Ethernet
FEC Forwarding Equivalence Class
FEC Forward Error Correction
FICON Fiber Connection
FIFO First In First Out
FPGA Field Programmable Gate Array
FS Forced Switching
FTP File Transfer Protocol

G
GE Gigabit Ethernet
GFC Generic Flow Control
GFP Generic Framing Procedure
GND Ground
GPS Global Positioning System
GSM Global System for Mobile Communications
GTS Generic Traffic Shaping
GUI Graphic User Interface

H
B Acronyms and Abbreviations
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HDLC High level Data Link Control
HEC Header Error Control
HP Higher Order Path
HPA Higher Order Path Adaptation
HPOH Higher Order Path Overhead
HPT Higher Order Path Termination
HSB Hot Standby
HSM Hitless Switch Mode

I
IC Integrated Circuit
ICP IMA Control Protocol
ID Identity
IDU Indoor Unit
IEEE Institute of Electrical and Electronics Engineers
IETF Internet Engineering Task Force
IF Intermediate Frequency
IGMP Internet Group Management Protocol
IMA Inverse Multiplexing for ATM
IP Internet Protocol
IPA Intelligent Power Adjusting
ISDN Integrated Services Digital Network
ISO International Standard Organization
ISP Internet Service Provider
IST Internal Spanning Tree
IS-IS Intermedia System-Intermedia System
ITU-T International Telecommunication Union -
Telecommunication Standardization Sector

L
LACP Link Aggregation Control Protocol
LAG Link Aggregation Group
LAN Local Area Network
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LAPS Link Access Procedure-SDH
LB Loopback
LBM Loopback Message
LBR Loopback Return
LC Lucent Connector
LCAS Link Capacity Adjustment Scheme
LCD Liquid Crystal Display
LCT Local Craft Terminal
LLC Logical Link Control
LOC Loss of Continuity
LOF Loss of frame
LOM Loss Of Multiframe
LOS Loss Of Signal
LP Lower Order Path
LPA Linear Power Amplifier
LPT Link State Pass Through
LSP Label Switched Path
LSR Label Switching Router
LT Link Trace
LTM Link Trace Message

M
MA Maintenance Association
MAC Medium Access Control
MADM Multiple Add/drop Multiplexer
MAN Metropolitan Area Network
MBS Max Burst Size
MCF Message Communication Function
MCR Minimum Cell Rate
MD Maintenance Domain
MEP Maintenance End Point
MIB Management Information Base
B Acronyms and Abbreviations
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MIP Maintenance Intermediate Point
MODEM MOdulator-DEModulator
MP Maintenance Point
MPID Maintenance Point Identification
MPLS Multi-Protocol Label Switch
MS Multiplex Section
MSA Multiplex Section Adaptation
MSOH Multiplex Section Overhead
MSP Multiplex Section Protection
MST Multiplex Section Termination
MSTI Multiple Spanning Tree Instance
MSTP Multiple Spanning Tree Protocol
MSTP Multiservice Transport Platform
MTIE Maximum Time Interval Error
MTU Maximum Transmission Unit

N
NE Network Element
NLP Normal Link Pulse
NM Network Manager
NMS Network Management System
NNI Network Node Interface
NPC Network Parameter Control
nrt-VBR non-real time Variable Bit Rate
NRZ Non Return to Zero code
NSAP Network Service Access Point
NTP Network Time Protocol

O
OADM Optical Add/Drop Multiplexer
OAM Operations, Administration and Maintenance
OAMPDU OAM Protocol Data Unit
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OCS Optical Core Switching
ODF Optical Distribution Frame
ODU Outdoor Unit
OFS Out-of-frame Second
OHA Overhead Access Function
OLT Optical Line Terminal
ONU Optical Network Unit
OOF Out of Frame
OSI Open Systems Interconnection
OSN Optical Switch Node
OSPF Open Shortest Path First
OTDR Optical Time-Domain Reflectometer

P
PA Power Amplifier
PBS Peak Burst Size
PC Personal Computer
PCB Printed Circuit Board
PCM Pulse Code Modulation
PCR Peak Cell Rate
PDH Plesiochronous Digital Hierarchy
PE Provider Edge
PGND Protection Ground
PIM-DM Protocol Independent Multicast-Dense Mode
PIM-SM Protocol Independent Multicast-Sparse Mode
PIR Peak Information Rate
POH Path Overhead
POS Packet Over SDH
PLL Phase-Locked Loop
PPI PDH Physical Interface
PPP Point-to-Point Protocol
PPS Port Protection Switching
B Acronyms and Abbreviations
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PRBS Pseudo-Random Binary Sequence
PRC Primary Reference Clock
PS Packet Switched
PSD Power Spectral Density
PTI Payload Type Indicator
PTP Precision Time Protocol
PW Pseudo Wire
PVC Permanent Virtual Connection

Q
QinQ 802.1Q in 802.1Q
QoS Quality of Service

R
RDI Remote Defect Indication
RF Radio Frequency
RFA Request For Announcement
RFI Request for Information
RMON Remote Network Monitoring
RNC Radio Network Controller
RP Rendezvous Point
RPR Resilient Packet Ring
RSL Received Signal Level
RSOH Regenerator Section Overhead
RST Regenerator Section Termination
RSTP Rapid Spanning Tree Protocol
RTN Radio Transmission Node
rt-VBR real time Variable Bit Rate
RX Receiver/Reception

S
SAN Storage Area Network
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SC Square Connector
SCB System Control Board
SCC System Control & Communication Unit
SCR Sustained Cell Rate
SD Signal Degrade
SD Space Diversity
SDH Synchronous Digital Hierarchy
SDP Serious Disturbance Period
SEC SDH Equipment Clock
SES Severely Errored Second
SETS Synchronous Equipment Timing Source
SF Signal Fail
SFP Small Form-Factor Pluggable
SHDSL Single Pair High-bit-rate Digital Subscriber Line
SLM Single Longitudinal Mode
SNC SubNetwork Connection
SNCMP Subnetwork Connection Multiple Protection
SNCP Sub-Network Connection Protection
SNCTP Subnetwork Connection Tunnel Protection
SNMP Simple Network Management Protocol
SNR Signal-to-Noise Ratio
SOH Section Overhead
SPI SDH Physical Interface
SSM Synchronization Status Marker
SSMB Synchronization Status Message Byte
SSU Synchronization Supply Unit
STM-1 SDH Transport Module -1
STM-4 SDH Transport Module -4
STM-16 SDH Transport Module -16
SSU Synchronization Supply Unit
STG Synchronous Timing Generator
STP Spanning Tree Protocol
B Acronyms and Abbreviations
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SVC Switching Virtual Connection
S-VID Service VLAN ID
S-VLAN Service VLAN

T
TCN BPDU Topology Change Notification BPDU
TCI Tag Control Information
TCM Tandem Connection Monitor
TCP/IP Transmission Control Protocol/Internet Protocol
TDM Time Division Multiplexing
TIM Trace Identifier Mismatch
TM Terminal Multiplexer
TMN Telecommunications Management Network
ToS Type of Service
TPID TAG Protocol ID
TPS Tributary Protection Switch
TSD Trail Signal Degrade
TTL Time To Live
TU Tributary Unit
TUG Tributary Unit Group

U
UART Universal Asynchronous Receiver/Transmitter
UAS Unavailable Second
UBR Unspecified Bit Rate
UNI User Network Interface
UPC Usage Parameter Control
UPI User Payload Identifier
UPM Uninterruptible Power Module
UPS Uninterruptible Power Supply
UTC Universal Time Coordinated

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V
VB Virtual Bridge
VBR Variable Bit Rate
VC Virtual Connection
VCG Virtual Concatenation Group
VCI Virtual Channel Identifier
VLAN Virtual LAN
VP Virtual Path
VPI Virtual Path Identifier
VPN Virtual Private Network

W
WAN Wide Area Network
WDM Wavelength Division Multiplexing
WFQ Weighted Fair Queuing
WRED Weighted Random Early Detection
WTR Wait-to-Restore

B Acronyms and Abbreviations
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