In

x
Ga
1-x
Sb n-channel MOSFET: Effect of Interface States on C-V Characteristics

Muhammad Shaffatul Islam
1*
, Md. Nur Kutubul Alam
1
. Md. Rafiqul Islam
1


1
Department of Electrical and Electronic Engineering
Khulna University of Engineering & Technology
Khulna-9203, Bangladesh
*Corresponding author : mashru.islam@yahoo.com

ABSTRACT

The Capacitance-Voltage (CV) characteristics of InGaSb
based n-MOSFET are investigated by quantum mechanical
calculation solving 1D self-consistent Schrodinger-Poisson
equation using Silvacos ATLAS device simulation package.
The charge density profile is determined by wave function
penetration effect within the oxide layer and Neuman
boundary condition. Low and high frequency CV
characteristics are studied both for the positive and negative
interface charge densities. The results obtained from the
simulation demonstrate that the CV characteristics are not so
sensitive in the shift of threshold voltage for high frequency
operation. On the other hand, a significant shift in threshold
voltage is noticed for the low frequency operation and the shift
is entirely depends on the density of interface charge density
and its type.


INTRODUCTION

Silicon is the most widely used semiconductor in digital logic
applications. As silicon based devices are scaling down to their
ultimate limits , some adverse effects arise which degrade the
device performance. For the limitation of the silicon and quest
for better performing material, researchers are looking into the
possibilities of CMOS circuits that utilize III-V material
either alone or in hybrid form with Si or Ge [1].

III-V materials have emerged as a promising candidate for
channel material of MOSFET to be used in future logic
applications due to excellent electron and transport properties
[2]. Since the modern complementary metal oxide
semiconductor technology is aggressively scaling down, the
device dimension and the thickness of the material has also
been scaled [3]. For compensating gate leakage and good
control over electrostatic potential, High-k oxides are suitable.
In scaled down III-V devices High-K gate oxide integration on
compound semiconductor is a challenging issue. The low
quality interface can generate interface states in the oxide-
semiconductor interface. The generation of interface trap states
at oxide/semiconductor interface and oxide trapped charge of
MOS structures has long been demonstrated as the prime
factors behind the degradation of MOS device performances
[4,5]. When bias is applied on the gate at elevated temperature
or for long time, an increase in oxide trap charge density
causes the shift in threshold voltage and decrease in carrier
mobility. However, charge trapping induced through bias is
extremely high in high-k gate stacks because of high densities
of intrinsic defect in material [6.7]. The bias-induced charging
and discharging greatly influence the device performance by
reducing the drive current due to electrostatic interaction with
trapped charges [8].This kind of degradation on device
parameters can led to circuit failures in analog and digital
applications [5].

Among all the III-V semiconductors, antimonide based
materials have higher electron mobility and can be used as a
potential material in the channel of MOSFET. Recently,
InGaSb-based surface channel p-MOSFET [2] and
n-MOSFET [9] was experimentally demonstrated. In this
study logic figure of merits (e.g. SS,DIBL,I
ON
/I
OFF
ratio) and
mobility for p-MOSFET and channel mobility behavior for
n-MOSFET has been investigated. Self-Consistent
capacitance-voltage (CV) characterization was reported
considering direct tunneling gate leakage current for InGaSb
n-channel MOSFET in[10]. To best of our knowledge there is
no study on effect of interface states on InGaSb n-channel
MOSFETs including the CV characteristics.

In this work coupled Schrodinger and Poisson equations have
been solved self consistently [11] in order to calculate the
quantum mechanical charge distribution in MOS devices
incorporating wave function penetration effect within the
oxide layer using SILVACOs ATLAS device simulation
package. The solver employs Finite Element Method. The CV
characteristics are calculated using the electrostatics of the
device revealed by the solver. The results obtained from the
simulation indicate that the density of interface states and its
type have significant influence on the shift in threshold voltage
for low frequency (LF) operation. However, at the high
frequency (HF) operation, the shift in threshold is found to be
almost negligible with interface states.
SELF CONSISTENT MODELING
A. Device Structure













Fig. 1 Proposed In
x
Ga
1-x
Sb surface channel MOSFET structure.

Al
Al
2
O
3

In
x
Ga
1-x
Sb Channel S D
GaAs Substrate
Al
x
Ga
1-x
Sb Buffer
197 978-1-4673-4842-3/13/$31.00 c 2013 IEEE
The structure of the device under study shown in Fig.1 consists
of Al as gate contact and Al
2
O
3
as gate dielectric with 10nm
dimension, The In
x
Ga
1-x
Sb is used as channel material with
very thin dimension of 7nm, and 1m Al
x
Ga
1-x
Sb buffer layer
is used on the top of the GaAs substrate to minimize the lattice
mismatch between the substrate and the channel material. In
this study, we have investigated HFCV and LFCV
characteristics of InGaSb n-MOSFET for both positive and
negative interface charge densities at room temperature
(300K).


B. Self- Consistent Theory

The quantum mechanical solver used in SILVACOs Atlas
device simulation package uses classical PDE to solve the
Schrodinger and Poisson equation. The Poisson equation in
coefficient form is given as.

-7. (c7u) = (1)

The equation for MOS electrostatic potential is

e
0
e
d
2
(y)
dy
2
= q|p(y) -n(y) + N

- N
A
] (2)

where n(y) and p(y) are electron and hole concentration and N
D

and N
A
are ionized donor and acceptor concentration,
respectively. is the relative dielectric constant and
0
is the
free space permittivity. The electron concentration n(y) is
obtained for the n-MOS structure [11]by

n(y) = N
]
]
|
]
(y)|
2
(S)

N
]
=
n
i
m
di
K1
n
2
ln[1+exp(
L
F
-L
i]
K1
)] (4)

Here N
ij
is the carrier concentration in the j th subband of the I
th valley, n
vi
and m
di
are the i th valley degeneracy and the i th
density of effective mass of the channel material. N
inv
is the
total inversion layer carrier concentration and E
F
is the Fermi
energy. E
ij
and
ij
are the eigenvalue and eigenfunction of the j
th energy level of the i th valley, which are obtained from the
one dimensional solution of the Schrodinger equation.

The equation of one dimensional Schrodinger equation with
effective mass approximation can be defined as

_-

2
2m
-
d
2
dy
2
+I(y)_
]
(y) = E
]

]
(y) (S)

At first the Poisson equation has been solved (1) using the
semi-classical approximation assuming zero charge density.
Then the charge density profile n(y) is determined from (3) and
(4) by solving (5) using SILVCOs quantum effect module
with Neuman boundary condition. The charge density profile
is added to the Poisson equation, and (1) and (5) are solved
iteratively until the Fermi level. After this processes, the CV
characteristics can be found from the device electrostatics.

C. Effect of interface states on CV profile


In III-V devices, interface states are originated from native
interface defects in oxide-semiconductor interface [12]. The
interface states are located at or very close to the
semiconductor/oxide interface with energy distributed along
the bandgap of the semiconductor , designated as D
it
(cm
-2
ev
-1
),
Q
it
(C cm
-2
). Electron and holes get trapped in these states and
act like generation/recombination center and threshold voltage
shift [13] which is given by

AI
1
= -
A
t
(1
S
)
C
ox
(6)

where 1
S
is the surface potential, C
ox
.is the capacitance in
oxide layer. The position of the donor and acceptor like
interface states with respect to charge neutrality level is shown
in Fig. 2. This often expressed by an equivalent distribution
with a charge neutrality level E
CNL
above which the states are
acceptor type and below which they are donor type. The
energy levels marked by E
C
, E
v
, and E
P
represent conduction,
valance, and Fermi energies, respectively.


Fig. 2 Typical interface system consisting of (a) donor states and (b)
acceptor states.

In HFCV measurement, HF AC is superimposed on a DC bias
that is changed from accumulation to inversion. Interface
trapped charges cannot respond to HF AC signal but, they can
respond to the DC bias. As a result, the measured capacitance
does not depend on the amount of interface traps present. But
the threshold voltage is modified. In LFCV measurement, the
interface traps respond to the LF AC signal along with DC bias.
Thus the capacitance changes with the alteration of the
threshold voltage is given by

C
g
=
A
tctcl
Av
G
(7)
where Q
total
is the change in total charge due to change in gate
voltage V
G
. The total charge can be calculated by

totuI
=
dcpIcton
+
ncson
+
t
(8)



198 2013 IEEE 5
th
International Nanoelectronics Conference (INEC)
RESULTS AND DISCUSSIONS

Room temperature HFCV and LFCV characteristics are
studied considering positive and negative interface charge
densities at oxide semiconductor interface. It is seen from Figs.
3 (a) and (b) that the shift in threshold voltage is less
significant both for positive and negative interface charge
density of states in HF operation. With increasing positive
interface charge density, the CV profiles are shifted from more
negative gate voltage side to less negative gate voltage side.
The opposite results are found with increasing the amount of
negative interface charge density. In case of positive interface
charge, the position of the CV profile is found to shift in
opposite direction with respect to negative interface charge.
The shift in CV profile with the amount of interface charge
density, as well as, with its polarity, is occurred to oppose the
band banding at oxide/semiconductor interface in order to have
flat band condition. It is also found in Figs 3 (a) and (b) that
the capacitance changes slightly in accumulation and depletion
regions both for negative and positive interface charge
densities. However, almost negligible change in capacitance is
found in weak, moderate and strong inversion regions with
both types of interface charge densities. Figs. 4 (a) and (b)
show the LFCV characteristics obtained for different interface
charge densities. It is evident that the shift in threshold voltage
is more significant in LF operation and found in opposite
direction for positive and negative interface charge densities.
In contrast to HF operation, interface charges respond to low
LF operation with DC bias. Consequently, the capacitance at
the oxide/semiconductor interface is changed and, thereby the
threshold voltage is also changed. To understand the shift in
threshold voltage with the amount of interface charge density,
as well as with its polarity, the threshold voltage is plotted as a
function of interface charge density in Fig. 5. The maximum
shift is found from 0 V to -0.47V for the variation of positive
interface charge density and 0V to 0.35V for the negative
interface charge density.


Fig. 3 Room temperature HFCV characteristics (a) positive interface
charge density and (b) negative interface charge density.



Fig. 4 Room temperature LFCV characteristics (a) positive interface
charge density and (b) negative interface charge density.






2013 IEEE 5
th
International Nanoelectronics Conference (INEC) 199

Fig. 5 Threshold voltage as a function of interface charge density


CONCLUSION

In this study, the HFCV and LFCV characteristics are
simulated for InGaSb-based surface channel MOS structure
incorporating the effect of interface states using Silvacos
ATLAS device simulation package. The study is carried out
for different positive and negative interface states. The results
obtained from the simulation indicate that, at LF operation, the
effect of interface states on CV characteristics is more
prominent than at HF operation. The position of the CV profile
depends of the amount and polarity of the interface states. It is
also found that the shift in threshold voltage have strong
dependence on the positive and negative interface charge
densities. Thus the operation of InGaSb-based surface channel
MOSFETs in VLSI circuits to be modeled considering the
effect of interface states and its polarity.


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200 2013 IEEE 5
th
International Nanoelectronics Conference (INEC)