Akron 1280110386

ANALOG NON-LINEAR MULTI-VARIABLE FUNCTION EVALUATION BY
PIECE-WISE LINEAR APPROXIMATION

A Thesis
Presented to
The Graduate Faculty of The University of Akron

In Partial Fulfillment
of the Requirements for the Degree
Master of Science

Dileep Reddy Desai

August, 2010
ii
ANALOG NON-LINEAR MULTI-VARIABLE FUNCTION EVALUATION BY
PIECE-WISE LINEAR APPROXIMATION

Dileep Reddy Desai

Thesis

Approved: Accepted:

Co-Advisor Dean of the College
Dr. Joan E. Carletta Dr. George K. Haritos

Co-Advisor Dean of the Graduate School
Dr. Robert Veillette Dr. George R. Newkome

Committee Member Date
Dr. Kye-Shin Lee

Department Chair
Dr. Alex De Abreu-Garcia

iii
ABSTRACT
A method for the evaluation of non-linear multi-variable functions using analog
circuits is developed. The non-linear multi-variable functions are approximated with
piece-wise linear functions using a Chebyshev approximation technique. Then the
obtained linear equations are implemented using current-mode analog circuitry consisting
of current comparators and current mirrors. A quarter cycle of a sinusoidal function has
been approximated with two lines with a maximum error of 2.75% of the full-scale
output current range in the circuit simulations. A more complicated logarithmic function
of two variables that is useful as a logarithmic number system subtractor is also
approximated with two lines, with a maximum error of 4.26% in the circuit simulations.
Implementation of the logarithmic number system subtractor requires a min-max current
selector; this circuit sorts two input currents. The min-max current selector works for
input currents over a 20A range, from 70A to 90A, and has a maximum output
current error of 10nA. It uses a current comparator that has a worst-case input-offset
current of 5nA and a differential gain of 2.025V/nA. The logarithmic number system
subtractor can be used for image processing applications such as finding the forward and
backward differences of the neighboring pixels of an image.
iv
DEDICATION
Dedicated to my Parents and Sister.
v
ACKNOWLEDGEMENTS
I would like to thank my committee members Dr. Joan E. Carletta, Dr. Robert
Veillette and Dr. Kye-Shin Lee for their guidance and support throughout my Masters
program. I would like to specially thank Dr. Joan E. Carletta and Dr. Robert Veillette for
helping me throughout this thesis work and shaping my thoughts and research work into a
good manuscript.
I am much obliged for the assistance provided by the Department of Electrical
and Computer Engineering for supporting me as a graduate research assistant. I would
like to specially thank Dr. Alex De Abreu-Garcia and Mr. Michael Ward for supporting
me financially during my Masters program. I would like to specially thank Dr. Firas
Hassan for guiding me in my thesis work. I appreciate Mrs. Gay Boden for her help right
from the day I have received admission into the University of Akron.
I owe my heartfelt regards to my father, mother, sister, friends and God who have
been my constant source of inspiration, motivation and encouragement. I would like to
thank my friends, Dinesh, Pradeep, Madhu, Nikhil and Utthej in this regard.

vi
TABLE OF CONTENTS
........................................................................................................................................ Page
LIST OF TABLES ........................................................................................................... viii
LIST OF FIGURES ........................................................................................................... ix
CHAPTER
I INTRODUCTION ............................................................................................................ 1
II BACKGROUND ............................................................................................................. 6
2.1 Piece-wise linear approximation ............................................................................... 6
2.2 Linear arithmetic units .............................................................................................. 9
2.3 Piece-wise linear function evaluator ....................................................................... 11
III DESIGN OF A MIN-MAX CURRENT SELECTOR................................................. 15
3.1 Design of the current comparator ............................................................................ 16
3.2 Design of the Schmitt trigger .................................................................................. 21
3.3 Design of the current mirrors and multiplexers ...................................................... 25
IV ANALOG IMPLEMENTATION OF A SINUSOIDAL FUNCTION OF ONE
VARIABLE ................................................................................................................ 33
4.1 Approximation of sin(x
1
) ......................................................................................... 33
4.2 Circuit implementation of the function sin(x
1
) ........................................................ 36
vii
4.2.1 Design of the arithmetic unit ............................................................................ 37
4.2.2 Design of the current comparator and the multiplexer ..................................... 39
4.3 Simulation Results................................................................................................... 43
V ANALOG IMPLEMENTATION OF LOGARITHMIC NUMBER SYSTEM (LNS)
SUBTRACTION......................................................................................................... 46
5.1 Approximation of LNS subtraction ......................................................................... 47
5.2 Circuit implementation of LNS subtraction ............................................................ 51
5.2.1 Design of the min-max current selector ........................................................... 52
5.2.2 Design of the arithmetic unit ............................................................................ 52
5.2.3 Design of the current comparator and the multiplexer ..................................... 55
5.3 Simulation results .................................................................................................... 57
5.4 Application of LNS subtraction .............................................................................. 65
VI CONCLUSION AND FUTURE WORK .................................................................... 67
BIBLIOGRAPHY ............................................................................................................. 70
APPENDIX A ................................................................................................................... 73
viii
LIST OF TABLES
Table .............................................................................................................................. Page
3.1 Maximum absolute current errors from corner simulations of the min-max current
selector ........................................................................................................................ 30
A.1 Channel dimensions of transistors in min-max current selector ................................ 73
A.2 Channel dimensions of transistors in the analog implementation of the sine
function ....................................................................................................................... 74
A.3 Channel dimensions of transistors in the analog implementation of LNS
subtraction ................................................................................................................... 75
ix
LIST OF FIGURES
Figure ............................................................................................................................. Page
2.1: Linear arithmetic unit using a voltage-mode approach ............................................... 9
2.2: Block diagram of a linear arithmetic unit using a current-mode approach ............... 10
2.3: Block diagram of piece-wise linear function evaluator ............................................. 11
3.1: Block diagram of a min-max current selector ........................................................... 15
3.2: Block diagram of proposed current comparator ........................................................ 16
3.3: Schematic of a current comparator ............................................................................ 17
3.4: Transfer characteristics of different transistors of a current comparator in common-
mode for two different common-mode input currents .............................................. 19
3.5: Differential response of current comparator for three different common-mode
currents showing voltages V
out1
and V
out2
................................................................. 21
3.6: Schematic of Schmitt trigger circuit .......................................................................... 22
3.7: Voltage transfer characteristics of the Schmitt trigger circuit ................................... 23
3.8: Output voltage of current comparator (V
out
) and Schmitt trigger (V
st
) for three
different common-mode input currents ..................................................................... 24
3.9: Schematic of current mirrors and multiplexers.......................................................... 25
3.10: Schematic of min-max current selector ................................................................... 26
3.11: Output currents (I
high
and I
low
) of min-max current selector for 85A common-mode
current, both full scale and magnified ....................................................................... 27
x
high
and I
low
high
and I
low
3.14: Step response of min-max current selector .............................................................. 31
4.1: Plot of piece-wise linear approximation of sin(x
1
) with two lines ............................. 34
4.2: Plot of error between sin(
1
) and its piece-wise linear approximation with two
lines ........................................................................................................................... 35
4.3: Block diagram of analog implementation of the function sin(x
1
) .............................. 37
4.4: Schematic of the arithmetic unit ................................................................................ 38
4.5: Schematic of current comparator and multiplexer ..................................................... 39
4.6: Differential response of the current comparator and its expanded version ............... 40
4.7: Total schematic of sine function implementation ...................................................... 42
4.8: Sinusoidal function results when I
in
is varying from 70A to 90A ......................... 43
4.9: Plots of error between function sin(
1
), piece-wise linear approximation, and analog
implementation .......................................................................................................... 44
5.1: Plot of piece-wise linear approximation of with two lines ..................................... 49
5.2: Plot of error between () and its piece-wise linear approximation ......................... 50
5.3: Block diagram of analog implementation of LNS subtraction .................................. 51
5.4: Schematic of the arithmetic unit ................................................................................ 53
5.5: Schematic of the current comparator and multiplexer ............................................... 55
5.6: Differential response of current comparator for three different common-mode
currents ...................................................................................................................... 56
xi
5.7: Total schematic of analog implementation of LNS subtraction. ............................... 58
5.8: LNS subtraction results when
1
is fixed at 80A and
2
is varying. ....................... 59
5.9: Plots of error between outputs when
1
is fixed at 80A and
2
is varying. ............ 60
1
is fixed at 70A and
2
is varying. ..................... 61
1
is fixed at 70A and
2
is varying. .......... 62
1
is fixed at 90A and
2
is varying. ..................... 63
1
is fixed at 90A and
2
is varying. ......... 64

1
CHAPTER I
INTRODUCTION
Evaluating a function using hardware is a common task required for many real-
time applications. Any processing of data or signals involves some type of calculation
which is nothing but evaluation of functions. The level of complexity involved in
evaluating a function using hardware depends on two things; one is the complexity of the
function, and the other is the limits of the available hardware resources. One category of
functions that are difficult to evaluate is non-linear multi-variable functions. An example
of such a function involving two variables is log(10
1
10
2
).
Hardware-based function evaluation is commonly implemented using digital
circuits. A function may be calculated using a polynomial approximation on hardware
consisting of registers, adders, and multipliers; alternatively, the outputs of the function
over some range of inputs may be stored in a look-up table. The accuracy of the
evaluated function and the speed of operation depend on the bit-widths of the registers,
adders, and multipliers used, or on the number of bits stored in the look-up tables used.
The underlying hardware might be a microcontroller, a digital signal processor (DSP), a
field-programmable gate array (FPGA), or other digital hardware.
Methods for evaluating functions like log, sine and cosine using embedded DSPs
are presented in [1, 2]. There are several ways of evaluating a function using polynomial
2
approximations implemented using FPGAs, some of which are presented in [3, 4, 5, 6].
All of these techniques use digital hardware and operate on digital inputs.
In some applications, functions must be evaluated on analog input signals. In this
case, one implementation possibility is to first convert the analog input signals to digital
signals and then use digital function evaluation methods. This requires the use of analog-
to-digital converters (ADCs). The accuracy of the evaluated function depends on the
resolution of the ADC, and the speed of evaluation depends on the ADCs conversion
time.
Alternatively, a function can be evaluated on analog input signals directly by
using analog electronics, using components such as operational amplifiers and
comparators. Implementing functions with analog circuitry has several advantages. No
ADCs are needed, and so the delay associated with the ADC conversion time is
eliminated. The analog circuitry is typically lower in cost, simpler, and much faster than a
digital implementation.
The goal of this thesis is to show a process for the design of analog evaluation
hardware for non-linear multi-variable functions using analog circuits with analog input
signals. The ranges of the input and the output variables are mapped to ranges of currents
or voltages. Then the non-linear multi-variable function is represented with a piece-wise
linear approximation, by breaking the input space into regions and approximating the
function within each region with a linear function. The linear functions and the
boundaries between regions are chosen so as to minimize the worst-case error between
the approximation and the original function. Then the linear functions are implemented
using analog circuitry and the output from the correct linear function for the given set of
3
inputs is selected. For the examples given in this thesis, the goal is that the maximum
error in the piece-wise linear approximation itself should not exceed 10% of the output
current or voltage range, and that the additional error introduced by the analog circuit
implementation should not be more than another 2%.
To determine in which region a particular set of input values lies, so that the
appropriate line in the piece-wise linear approximation can be routed to the output,
comparators are needed. In this thesis, a current-mode approach is followed, so a current
comparator is designed to compare linear combinations of input currents with constant
currents. A current comparator of similar design is also used in a min-max current
selector, which is needed to sort currents for our second example function which includes
an absolute value. For the min-max current selector application, both inputs to the current
comparator may vary through the full input current range; therefore, the common-mode
input current range of this current comparator must cover this full current range. In this
thesis, a novel current comparator is designed which has the required full-scale common-
mode input current range and also a high differential gain.
In this thesis two non-linear functions are implemented as examples. A non-linear
function of a single variable sin(
1
) on the interval 0,
2
has been approximated using a
piece-wise linear approximation with two regions and then implemented using analog
circuitry. The input current corresponding to
1
ranges from 70A to 90A. The
maximum error in the output current of the analog implementation is 2.75% of the full-
scale output current range.
With a similar approach, a more complicated nonlinear function of two variables
is implemented. This function is referred to as a logarithmic number system (LNS)
4
subtraction; if two real values and are represented in LNS representation as
1
=
log
10
+, and
2
= log
10
+, respectively, their difference in LNS
representation is defined as log
10
+ . To ensure that LNS subtraction is
always defined, the absolute value of the difference is calculated. The inputs
corresponding to
1
and
2
range from 70A to 90A. The maximum error in the analog
implementation is 4.26% of the full-scale output current range.
The application motivating the work in this thesis to implement LNS subtraction
involves processing the outputs of a logarithmic CMOS image sensor. Each pixel
produced by a logarithmic CMOS image sensor is in the form of an analog current; this
current is a shifted and scaled version of the logarithm of the current produced by the
photodiode in the corresponding pixel sensor, which is in turn related to the intensity of
the light falling on the photodiode. Thus, the pixel sensor output current can be viewed as
an LNS representation of the light intensity.
Usually, the individual pixel sensor output currents of the logarithmic CMOS
image sensor are converted one by one into digital pixels and then processed digitally.
The analog-to-digital conversion itself needs several clock cycles. To reduce the time and
hardware required for processing the outputs of a logarithmic CMOS image sensor,
analog circuits may be used. It is common to need to calculate forward differences or
backward differences, which require the subtraction of neighboring pixels. Because the
pixels themselves are in LNS representation, this subtraction of neighboring pixels
requires LNS subtraction. In this thesis, the designed LNS subtraction circuit is
appropriate for this application.
5
The remainder of this thesis is organized as follows. Related background work is
described in Chapter II. The design, operation and performance of a min-max current
selector are discussed in Chapter III. The implementation of a non-linear function of a
single variable sin(
1
) using analog circuits is described in Chapter IV. The
implementation of a non-linear function of two variables log + using
analog circuits, when log
10
+ and log
10
+ are given as inputs, is
discussed in Chapter V. Finally, conclusions are drawn and possible future work is
described in Chapter VI.
6
CHAPTER II
BACKGROUND
Analog circuits are capable of evaluating functions that are linear combinations of
variables and constants with ease. Such linear combinations of variables and constants
require the multiplication of variables by constant scaling factors and the addition of
variables. If variables are represented as analog voltages, multiplication by scaling factors
and addition can be done simply using operational amplifiers and resistors. If variables
are represented as analog currents, current mirrors can be used.
A non-linear multi-variable function can be implemented with analog circuits if it
can be approximated as a piece-wise linear function, using different linear functions for
different ranges of the inputs. Generally, the more linear functions pieced together to
produce an approximation, the lower the error of that approximation, since the
approximation will be better able to follow the bends of the function. This chapter
describes a technique for piece-wise linear approximation, methods for evaluating linear
functions of multiple variables, and finally an architecture for implementing a piece-wise
linear function.
2.1 Piece-wise linear approximation
A piece-wise linear approximation to a non-linear multi-variable function divides
the input space of the function into a number of regions, and approximates the function in
each region as a linear combination of the inputs. Any one of the several piece-wise
7
linear approximation techniques described in [7, 8, 9] can be used to approximate a
function. Consider a non-linear multi-variable function
1
,
2
, ,
that is
approximated with a set of linear expressions as

1
,
2
, ,
1,1
1
+
1,2
2
++
1,
+
1
,
1
,
2
, ,
2,1
1
+
2,2
2
++
2,
+
2
,
1
,
2
, ,
,1
1
+
,2
2
++
,
,
1
,
2
, ,

(2.1)
where
1
,
2
, ,
are the input variables to the function,

,
is the scaling factor for the
variable
in the region
, and
1
,
2
, ,
are the constants corresponding to each

region.
For the examples in this thesis, the Chebyshev approximation technique [9] is
used to find an appropriate piece-wise linear approximation. The Chebyshev
approximation guarantees that the worst-case errors in each region of the approximation
are equal in magnitude. To use the Chebyshev approximation technique, the non-linear
multi-variable function is first rearranged so that it is expressed in terms of another
function of a single variable; the single variable must be a linear combination of the input
variables. If the non-linear multi-variable function cannot be represented in terms of
another function of a single variable, piece-wise linear approximation techniques other
than the Chebyshev approximation can be used.
The following algorithm is followed to produce a piece-wise linear approximation
for a function with a single input variable over a given interval using the Chebyshev
approximation technique. The algorithm works by iteratively refining an initial
approximation. At each step, the approximation is defined by a set of 2r fitting points, or
input values at which the approximation exactly matches the function to be
8
approximated. Together, the 2r fitting points define a set of r lines to be used for the
piece-wise linear approximation; if the 2r fitting points are sorted in the order of
increasing input values, and then split into pairs, each pair defines one line. The
breakpoints between the subintervals are the intersections between pairs of successive
lines.
1. To start, an initial set of 2r fitting points is required. Fitting points are placed at the
start and the end points of the range of the input variable. These are the terminal points
of the function. The remaining 2r2 fitting points are chosen arbitrarily within the
range. The initial piece-wise linear approximation is constructed using these 2r fitting
points.
2. The error between the resulting piece-wise linear approximation and the function is
calculated, and the points corresponding to the worst-case errors in each subinterval
are found. These points are termed local error peaks.
3. In each subinterval, the fitting point nearer to the local error peak is moved a given
distance towards the local error peak. Moving the fitting points in this way will cause
the worst-case error to decrease.
4. Steps 2 and 3 are repeated until the local error peaks in all subintervals are equal in
magnitude.
The result of the Chebyshev approximation technique is a set of lines that approximates
the function throughout the input space in such a way that the worst-case errors of the
approximation in each region are equal in magnitude.
9
2.2 Linear arithmetic units
Implementation of the proposed analog non-linear multi-variable function
evaluator requires analog implementation of linear functions of the form
=
1
1
+
2
2
++
+, (2.2)
where
1
,
2
, ,
are the input variables to the function,
is the scaling factor

corresponding to the variable
, and c is a constant. A block of analog circuitry that

evaluates a linear function is termed a linear arithmetic unit. A linear arithmetic unit is
implemented using either a voltage-mode or a current-mode approach. For a voltage-
mode approach, the input variables
1
,
2
, ,
and the output y are mapped to a set of

voltages
1
,
2
, ,
and
. For a current-mode approach, they are mapped to a set of

currents
1
,
2
, ,
and
.
To implement the linear function using a voltage-mode approach, an operational
amplifier with some resistors is required as shown in Fig. 2.1. The operational amplifier
v
1
v
2
v
n
v
c
R
1
R
2
R
n
R
R
f
v
o
c
f
n
n
f f f
o
v
R
R
v
R
R
v
R
R
v
R
R
v
2
2
1
1

Figure 2.1: Linear arithmetic unit using a voltage-mode approach

10
circuit scales each input voltage
by its respective scaling factor
and produces
an output voltage equal to the sum of all the scaled input voltages. The scaling factors of
the input voltages (i.e., the resistor ratios
) are related to the linear function

coefficients
in a way that depends on the mappings between the input variables
and
the input voltages
. Similarly, the constant c is implemented using a voltage
and a
resistor R.
To implement the linear function using the current-mode approach, several scaled
current mirrors are required as shown in Fig. 2.2. The current mirrors produce mirrored
versions of the input currents
1
,
2
, ,
, each scaled by its respective scaling factor. The

scalings are achieved by setting the aspect ratios of the transistors in the current mirrors
appropriately. The constant in the linear function can be implemented by using a constant
Scaled
current
mirror
i
1
i
2
i
n
p
1
i
1
p
2
i
2
p
n
i
n
Output (i
o
)
Constant
current
source
i
c
Scaled
current
mirror
Scaled
current
mirror
c n n o
i i p i p i p i
2 2 1 1

Figure 2.2: Block diagram of a linear arithmetic unit using a current-mode approach

11
current source. The scaling factors for the input currents (i.e., the coefficients
) are
related to the linear function coefficients
in a way that depends on the mappings

between the input variables
and the input currents
. Similarly, the constant c is

mapped to a current
which is produced by the constant current source. Finally, the

linear function is implemented by summing all of the currents at a node.
2.3 Piece-wise linear function evaluator
Fig. 2.3 shows the block diagram of an analog implementation of a piece-wise
linear function of multiple variables. Linear arithmetic units are used to implement each
of the linear expressions in the piece-wise linear function. The region decoder determines
which one of the linear expressions represents the correct output, and controls the r-to-1
multiplexer to pass the output of the corresponding linear arithmetic unit through to the
output of the piece-wise linear function evaluator.
To implement the region decoder, a set of comparators is needed to select the
correct region for the given set of inputs. The input variables
1
,
2
, ,
(coded in
Region
Decoder
Linear
Arithmetic
Unit1
Linear
Arithmetic
Unit 2
Linear
Arithmetic
Unit r
x
1
x
2
x
n
y
1
y
2
y
r
r-to-1
Multiplexer
Select
Output f(x
1
, x
2
, , x
n
)

Figure 2.3: Block diagram of piece-wise linear function evaluator
12
implementation as either voltages or currents) will satisfy a particular linear inequality
condition for each region. To implement these conditions, the region decoder may
incorporate additional linear arithmetic units as well as comparators and decoding logic.
The outputs of the decoding logic are fed to the multiplexer as select control signals.
In addition to the region decoder and the linear arithmetic units already described,
the piece-wise linear function evaluator requires an r-to-1 multiplexer. The multiplexer
routes the output of the one arithmetic unit selected by the region decoder to the output of
the system. The multiplexer can be implemented using transmission gates.
When the voltage-mode approach and the current-mode approach to analog
evaluation of a piece-wise linear function are compared, the current-mode approach has
the advantage that it requires less hardware than the voltage-mode approach. It uses no
operational amplifiers; further, it requires no resistors, which are difficult to implement
accurately in integrated circuits. For these reasons a current-mode approach is a good
choice for analog evaluation of piece-wise linear functions and is used in this thesis.
To implement the region decoder needed for a current-mode approach, a current
comparator is needed. A current comparator should work with a specified accuracy over
its entire input current range. Several different current comparator design strategies have
been reported. In [10], a single input current is compared with multiple fixed threshold
currents using simple current mirrors. Circuits in [11, 12] are designed to determine
whether a single input current is leaving or entering the circuit, effectively comparing the
input current with zero. Another current comparator circuit in [13] compares a single
input current with a fixed reference current by using a modified Wilson current mirror.
All of these designs effectively compare one variable current with a fixed value; for our
13
application, two variable input currents must be compared. The current comparator
circuit presented in this thesis is designed by modifying the circuit proposed in [10] to
accommodate two variable input currents, while achieving good sensitivity and common-
mode response.
In some cases, including the example in Chapter V, the inputs to the non-linear
multi-variable function must be sorted before evaluating the piece-wise linear function.
As the current-mode approach is implemented, a current sorter is needed to sort the
inputs. A current sorter takes in a number N of input currents, and provides copies of the
same currents, sorted in order of magnitude, at N outputs. The basic building block for a
current sorter is a min-max current selector. This is a circuit that takes two input currents,
and provides two output currents, one a mirrored copy of the smaller of the two input
currents, and one a mirrored copy of the larger of the two input currents.
Several min-max current selectors have been proposed in the literature [14-19].
Some are based on current-mode winner-take-all networks [14, 15, 16, 17]; a current
conveyer [18] and self-controlled cross-coupled transistors [19] have also been proposed.
The circuits can be compared in terms of the range of input currents on which they work,
and how closely the output currents match the input currents. Of the winner-take-all
networks [14, 15, 16, 17], the most accurate has an input range of 29A and a maximum
output current error of 10nA. The other approaches [18, 19] provide less accuracy and a
smaller input range. In this thesis, conventional current mirrors and the current
comparator already mentioned are used to construct the min-max current selector, to
obtain accuracy similar to that of the most accurate of the current-mode winner-take-all
circuits. Chapter III presents the design of a min-max current selector, including the
14
current comparator that accommodates two variable inputs. The comparator is also used
in Chapters IV and V in region decoders for evaluating our two example non-linear
functions.
15
CHAPTER III
DESIGN OF A MIN-MAX CURRENT SELECTOR
When a non-linear multi-variable function evaluation is implemented with analog
circuits, it may require the input variables of the function to be sorted. For a current-mode
approach, a current sorter is needed to sort the variables. Any number of currents may be
sorted by sorting two currents at a time. A min-max current selector is a circuit that takes
as input two currents, and provides as output two currents, one a mirrored copy of the
smaller of the two input currents, and one a mirrored copy of the larger of the two input
currents.
The min-max current selector described in this chapter operates for input currents
ranging from 70A to 90A. The block diagram of the min-max current selector is
Current
Comparator
Schmitt
Trigger
Current
Mirrors and
Multiplexer
I
1
I
2
V
out2
I
low
I
high
Select

Figure 3.1: Block diagram of a min-max current selector
16
shown in Fig. 3.1. The min-max current selector has three distinct parts: a current
comparator that determines which input current is larger, a Schmitt trigger circuit that
sharpens the output of the current comparator, and current mirrors and multiplexers that
mirror the input currents and route the appropriate mirrored current to each output. These
three parts are described separately.
3.1 Design of the current comparator
A block diagram of the current comparator is shown in Fig. 3.2. The current
comparator has two stages, a differential current amplifier stage to produce a voltage
proportional to the difference between the input currents, and a gain stage to drive the
output towards the rails. The differential current amplifier stage consists of a PMOS
cascode current mirror and two NMOS cascode current mirrors, with the two NMOS
cascode current mirrors acting as a differential pair, and the PMOS cascode current

Figure 3.2: Block diagram of proposed current comparator
PMOS Cascode
Current Mirror
Gain Stage
V
out1
V
out2
I
1
NMOS Cascode
Current Mirror 2
V
DD
I
2
NMOS Cascode
Current Mirror 1
I
1
Differential Current Amplifier Stage
17
mirror acting as the load. It is similar to the structure in [17], but replaces simple current
mirrors with cascode current mirrors. Using cascode current mirrors increases the
resolution of the current comparator while keeping the area of the overall current
comparator reasonably small, because even relatively short transistors in a cascode
current mirror can mirror current more accurately than longer transistors in a simple
current mirror.
A transistor-level circuit diagram for the proposed current comparator is shown in
Fig. 3.3, where the two input currents are shown as current sources I
1
and I
2
within the
circuit. The first NMOS cascode current mirror produces a copy of input current I
1
at the
drain of transistor M2, and then the PMOS cascode current mirror produces another copy
of I
1
at the drain of transistor M6. Simultaneously, the second NMOS cascode current
mirror produces a copy of input current I
2
at the drain of transistor M4. The differential
M1 M2
M5 M6
M4A
M10
M9
M3A
M6A M5A
V
DD
Gain Stage
M2A M1A
M4 M3
M7
M8
V
out1
V
out2
I
1
I
2
PMOS Cascode
Current Mirror
NMOS Cascode
Current Mirror 1
NMOS Cascode
Current Mirror 2
V
1
Differential Current
Amplifier Stage

Figure 3.3: Schematic of a current comparator
18
operation of the comparator results from connecting the drains of M6 and M4 in series.
When current I
1
is greater than current I
2
, the PMOS source tries to force a larger current
through the NMOS sink. As a result, the voltage V
out1
increases. Similarly, when I
2
is
greater than I
1
, the voltage V
out1
decreases.
The sizes of the transistors in the differential current amplifier stage are chosen
considering both the differential gain and the bias point. The gain of the differential
current amplifier is determined by the output resistances of the PMOS and NMOS current
mirrors. The gain of the differential current amplifier stage can be increased by increasing
the transistor lengths, or, as done here, by using cascoded transistors. The relative sizes of
the PMOS cascode current mirror and the two NMOS cascode current mirrors were
chosen so as to give a V
out1
of half of V
DD
(2.5V) for a midrange common-mode input of
80A.
Because the current comparator must work over a range of input currents, the
common-mode response of the differential current amplifier is important. A look at the
transfer characteristics of transistor combinations M2/M2A, M4/M4A, M5/M5A, and
M6/M6A helps to illustrate how V
out1
changes with the common-mode input. Fig. 3.4
shows these transfer characteristics. Transistors M5 and M5A are a cascoded
combination of diode-connected transistors; together they follow a square-law
characteristic, as shown in the figure. This curve remains fixed irrespective of variations
in the input currents. If the two input currents I
1
and I
2
are equal, the transistors M1 and
M1A will have the same gate voltages, respectively, as M3 and M3A. Further, the
transistor combinations M2/M2A and M4/M4A will have the same drain transfer
characteristics.
19
The voltage V
1
is determined by the point of intersection of the drain transfer
characteristic of transistor combination M2/M2A and the square-law curve of transistor
combination M5/M5A. As we vary the input currents, this point of intersection will vary
along the square-law curve of transistors M5/M5A. Thus as I
1
and I
2
increase together, V
1

will decrease.
The voltage V
out1
is determined by the point of intersection of the drain transfer
characteristics of M6/M6A and M4/M4A. The drain transfer characteristic of M6/M6A
will be governed by the gate voltages of M5/M5A (which are equal to the gate voltages
of M6/M6A) and this curve intersects the square-law curve of M5/M5A at the point
where V
D,M6
= V
G,M6
. This means that the point of intersection of the drain transfer

Figure 3.4: Transfer characteristics of different transistors of a current comparator in
common-mode for two different common-mode input currents
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
10
20
30
40
50
60
70
80
90
100
D
r
a
i
n

C
u
r
r
e
n
t
s

(

A
)
Drain Voltages (V)

Transfer characteristics of
M2/M2A & M4/M4A for
80A Input Current
M2/M2A & M4/M4A for
90A Input Current
M6/M6A for 80A
Input Current
M6/M6A for 90A
Input Current
M5/M5A
V
out1
for 90A
Common mode current
V
out1
for 80A
Common mode current
20
characteristics of M4/M4A and M6/M6A is the same as the intersection point of the drain
transfer characteristic of M2/M2A and the square-law curve of M5/M5A. Since M4/M4A
and M2/M2A have the same drain transfer characteristics, the voltage V
out1
is equal to V
1
.
As the common-mode input current varies, V
out1
varies according to the square-
law characteristic of M5/M5A. Fig. 3.4 shows the drain characteristics of M4/M4A and
M6/M6A for two different common-mode input currents. At higher common-mode input
currents, V
out1
is decreased, and at lower common-mode input currents, V
out1
is increased.
The sensitivity of V
out1
to the common-mode input current depends on the W/L ratio of
the PMOS current mirror; for bigger W/L ratios, the PMOS transistors M5/M5A have
steeper square-law curves, so that their drain-to-source voltages (and therefore V
out1
) vary
less with the current through them. The W/L ratio of the PMOS current mirror should be
made large enough that variations in the bias point V
out1
are small.
The differential current amplifier is followed by a gain stage, implemented as a
pair of cascaded push-pull amplifiers that drives the output voltage closer to the supply
rails. The push-pull amplifier outputs are biased at half of V
DD
for a midrange common-
mode input. The variation in V
out1
resulting from the common-mode variations of the
input currents is small enough that the comparator output is not driven to a supply rail
unless a differential input current is applied.
Fig. 3.5 shows the differential response of the current comparator for three
different common-mode input currents. From the plot for a midrange common-mode of
80A, we can see that the voltage V
out1
correctly indicates which input current is larger; it
is above 2.5V (half of V
DD
) when the input current difference is negative, and below
2.5V when the difference is positive. With common-mode changes, the plots cross the
21
2.5V mark in slightly the wrong place; this contributes to input-offset error in the
comparator. The gain stage after the differential current amplifier ensures that V
out2
, also
shown in Fig. 3.5, is a railed version of V
out1
. The differential gain of the current
comparator, including the gain stage, is measured from the slope of the transition as
2.025V/nA. The worst-case input-offset current of the current comparator, including the
gain stage, over the full common-mode input range is 5nA. This worst-case value occurs
for a common-mode input of 90A.
3.2 Design of the Schmitt trigger
In order to produce an unambiguous digital signal from the output of the current
comparator, a Schmitt trigger is used. The Schmitt trigger produces an output voltage V
st

that is railed to V
DD
if V
out2
is small enough, and railed to ground V
out2
is large enough. It

Figure 3.5: Differential response of current comparator for three different common-
mode currents showing voltages V
out1
and V
out2
-200 -150 -100 -50 0 50 100 150 200
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
I
2
-I
1
(nA)

V
o
u
t
1

,

V
o
u
t
2

(
V
)

V
out1
for I
1
=70A
V
out1
for I
1
=80A
V
out1
for I
1
=90A
V
out2
for I
1
=70A
V
out2
for I
1
=80A
V
out2
for I
1
=90A
22
cannot produce intermediate output voltages, except in transition between one rail and the
other. Further, it provides hysteresis that prevents chattering of the output between the
two stable output states.
A transistor-level diagram of the Schmitt trigger circuit is shown in Fig. 3.6. It is
based on one given in [20]. When the output of the current comparator V
out2
is V
DD
,
indicating that I
1
is the larger of the two input currents, the transistors M11 and M11A are
off and M12 and M12A are on, so that the Schmitt trigger output Vst is ground. Similarly,
when the output of the current comparator is ground, indicating that I
2
is the larger of the
two input currents, the Schmitt trigger output is V
DD
. The operation of the Schmitt trigger
involves positive feedback that tends to push the output towards one rail or the other,
resulting in a pronounced hysteresis in its characteristic. Fig. 3.7 shows the voltage
transfer characteristic of the Schmitt trigger circuit. The Schmitt trigger output makes a
sharp transition from V
DD
(5V) to ground (0V) when the input crosses 3V in a rising
V
DD
M11
M12A
M11A
M12
M15
M16
M
1
3
M
1
4
V
out2 Select
V
st

Figure 3.6: Schematic of Schmitt trigger circuit
23
direction. The output makes a sharp transition from 0V to 5V when the input crosses
1.9V in a falling direction.
The positive feedback in the Schmitt trigger circuit and the resulting hysteresis in
its characteristic are caused by transistors M13 and M14. When the input of the Schmitt
trigger is low, M11 and M11A are on, and the output V
st
is at V
DD
. The transistor M14 is
also on, providing a positive feedback that tends to keep the output high, by pulling the
source terminal of M12 above ground. When the input rises to 3V, transistors M12 and
M12A begin to turn on in spite of M14s positive feedback. When this happens V
st
begins
to fall, and transistor M14 turns off, eliminating the positive feedback that had been
pulling V
st
up. Then, V
st
decreases abruptly toward a steady state near ground. At the
same time, M13 turns on, providing positive feedback to pull V
st
down, and transistors
M11 and M11A turn off. Thus, the output voltage is stable at the two rails, and makes
abrupt transitions between them depending on the variations in the input voltage.

Figure 3.7: Voltage transfer characteristics of the Schmitt trigger circuit
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
out2
(V)
V

s
t

(
V
)

V
st
when V
out2
is increasing
V
st
when V
out2
is decreasing
24
The Schmitt trigger output V
st
and its complement (Select), derived using an
inverter, are used as the select control signals for the multiplexers that route the mirrored
input currents, smoothly and unambiguously, to the proper outputs. The abrupt switching
of the Schmitt trigger output minimizes the transient current spikes that could otherwise
occur at the multiplexer outputs.
The differential transfer characteristics of the current comparator and the Schmitt
trigger, considered together for three different common-mode current inputs, are shown
in Fig. 3.8. All of the transitions are sharp; the Schmitt trigger output makes a transition
from supply rail to supply rail for a 0.1nA change in the differential input current. The
output transitions for rising and falling differential input currents are so close together
that they cannot be distinguished in the figure. The transitions happen not always at zero,

Figure 3.8: Output voltage of current comparator (V
out
) and Schmitt trigger (V
st
) for three
different common-mode input currents
-30 -20 -10 0 10 20 30
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
I
2
-I
1
(nA)

V
o
u
t
2

&

V
s
t

(
v
o
l
t
s
)

V
out2
for I
1
=70A
V
out2
for I
1
=80A
V
out2
for I
1
=90A
V
st
for I
1
=70A when
I
2
is increasing
V
st
for I
1
=80A when
I
2
is increasing
V
st
for I
1
=90A when
I
2
is increasing
V
st
for I
1
=70A when
I
2
is decreasing
V
st
for I
1
=80A when
I
2
is decreasing
V
st
for I
1
=90A when
I
2
is decreasing
25
but at different values of the differential input current depending on the common-mode
input current. The figure shows that over the common-mode range, an input current
difference of 5nA can be resolved; i.e., a difference of 5nA or more in the input currents
will result in the proper digital output voltage, regardless of the common-mode input
current.
3.3 Design of the current mirrors and multiplexers
In addition to the current comparator and the Schmitt trigger circuits already
described, a min-max current selector needs current mirrors to produce copies of the
input currents and current multiplexers to route the appropriate copy to each output. The
circuit diagram for these additional components is shown in Fig. 3.9.
When Select
, which is the output V

st
of the Schmitt trigger, is V
DD
, indicating that
I
2
is the larger of the two input currents, transistors M27, M28, M29 and M30 are off and
M17
M18 M19
M19A M18A
V
DD
M17A
M26 M25
M20
M20A
`
`
M21
M22 M23
M23A M22A
M21A
M24
M24A
`
`
M1
M3A M1A
M3
M27 M28 M29 M30 M31 M32
I
low
I
high
I
1
'
Mux1 Mux2
I
1 I
2
Load Load
I
2
'
Select
Select
(V
st
)

Figure 3.9: Schematic of current mirrors and multiplexers
26

F
i
g
u
r
e

3
.
1
0
:

S
c
h
e
m
a
t
i
c

o
f

m
i
n
-
m
a
x

c
u
r
r
e
n
t

s
e
l
e
c
t
o
r

27
transistors M25, M26, M31 and M32 are on. Then the mirrored version I
1
' of input
current I
1
is passed through Mux1 to I
low
, and the mirrored version I
2
' of input current I
2
is
passed through Mux2 to I
high
. Similarly, a Schmitt trigger output of ground routes I
2
' to
I
low
and I
1
' to I
high
. The current mirrors used to produce I
1
' and I
2
' must be long enough to
mirror the currents accurately, independent of the load connected to them. The transistors
in the multiplexers should be wide enough that there is not much voltage drop across
them when they are on.
The full schematic of the min-max current selector is shown in Fig. 3.10. The
channel dimensions of the transistors are listed in Table A.1 in Appendix A. In addition
70 72 74 76 78 80 82 84 86 88 90
70
75
80
85
90
I
2
(
A)
I

l
o
w

,

I
h
i
g
h

(
A
)

I
low
I
high
I
1
I
2
84.99 84.992 84.994 84.996 84.998 85 85.002 85.004 85.006 85.008 85.01
84.985
84.99
84.995
85
85.005
85.01
85.015
I
2
(
A)
I

l
o
w

,

I
h
i
g
h

(
A
)

I
low
I
high
I
1
I
2
Currents routed
incorrectly
Currents mirrored
inaccurately
{

Figure 3.11: Output currents (I
high
and I
low
) of min-max current selector for 85A
common-mode current, both full scale and magnified
28
to the channel dimensions (i.e. W L), the number of fingers in each transistor is also
given in the table. When a transistor has multiple fingers, it means that it is composed of
multiple transistors of the given channel dimensions connected in parallel. Thus, the
effective width of the transistor is the given dimension W multiplied by the number of
fingers.
The min-max current selector is simulated with both the input currents (I
1
and I
2
)
varying from 70A to 90A. Fig. 3.11 shows the current outputs (I
high
and I
low
) of a min-
max current selector for an example with one input current fixed at 85A, and the other
input current swept from 70A to 90A. The first plot in the figure indicates that the
input currents are correctly routed to the proper outputs. The second plot of Fig. 3.11 is a

high
and I
low
69 69.2 69.4 69.6 69.8 70 70.2 70.4 70.6 70.8 71
69
69.5
70
70.5
71
I
2
(A)
I

l
o
w
,
I
h
i
g
h

(
A
)

I
low
I
high
I
1
I
2
69.985 69.988 69.991 69.994 69.997 70 70.003 70.006 70.009 70.012 70.015
69.99
70
70.01
70.02
I
2
(A)
I

l
o
w
,
I
h
i
g
h

(
A
)

I
low
I
high
I
1
I
2
29
magnified view centered on the point at which both currents are 85A. This plot shows
that the input currents are routed to the correct outputs except for input current
differences between 2nA and 0nA, i.e., for I
2
between 84.998A and 85.000A.
Simulations for common-mode input currents of 70A and 90A are also
performed. For a 70A common-mode input simulation, one input current is fixed at
70A and the other input current is swept from 69A to 71A; the simulation results for
this case are shown in Fig. 3.12. The second plot of Fig. 3.12 shows that the output
currents are correctly routed except for current differences between 0nA and 3.5nA. For a
90A common-mode input simulation, one input current is fixed at 90A and the other
input current is swept from 89A to 91A; the simulation results for this case are shown
in Fig. 3.13. The second plot of Fig. 3.13 shows that output currents are correctly routed

high
and I
low
89 89.2 89.4 89.6 89.8 90 90.2 90.4 90.6 90.8 91
89
89.5
90
90.5
91
I
2
(A)
I

l
o
w
,
I
h
i
g
h

(
A
)

I
low
I
high
I
1
I
2
89.98 89.985 89.99 89.995 90 90.005 90.01 90.015 90.02
89.97
89.98
89.99
90
90.01
I
2
(A)
I

l
o
w
,
I
h
i
g
h

(
A
)

I
low
I
high
I
1
I
2
30
except for current differences between 5nA and 0nA. This maximum absolute error of
5nA is the worst-case routing error over the entire common-mode input range.
Output errors are also introduced by the current mirror circuits, regardless of the
common-mode or differential current values. Figures 3.11, 3.12, and 3.13 show that the
error introduced by the current mirrors is about 5nA over all simulated conditions. When
combined with the worst-case routing error of 5nA, this results in a total worst-case error
of 10nA in the output current. The output currents of the min-max current selector are
used as inputs to the region decoder and the arithmetic unit while evaluating a function.
The errors in the output currents may cause the region decoder to select the wrong region
for a set of input currents if they are very near to the boundary of a region. The errors in
the output currents will also affect the calculations done in the arithmetic units, which
will increase the error in the output of the function evaluated.
The input-offset error and the total output current error reported above were found
for a typical-typical (TT) model neglecting any process variations. The simulations were
repeated using 3 process variation models for four process corners: slow-slow (SS),
Table 3.1 Maximum absolute current errors from corner simulations of the min-max
current selector

Corner Input-offset error Total output current error
TT 5nA 10nA
SS (worst speed) 286.7nA 485.8nA
FF (worst power) 42.1nA 86.5nA
FS (worst one) 16.8nA 32.2nA
SF (worst zero) 12.5nA 22nA

31
fast-fast (FF), fast-slow (FS), and slow-fast (SF). Table 3.1 lists the maximum absolute
errors found over the common-mode input current range for each case. The worst case,
which is for the SS corner, represents about a 1.5% input offset error and a 2.5% output
current error. The issue of reducing the sensitivity of the design to process variations will
be a possible subject of future work.
To determine the speed of response of the min-max current selector, a transient
simulation is done in which a fixed current of 80A is applied to the input I
2
, while a step
from 70A to 90A is applied to the other input I
1
. The results are shown in Fig. 3.14.
Both the output currents I
high
and I
low
settle to within 1% of their final values in 168ns.

Figure 3.14: Step response of min-max current selector
0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4
70
80
90
Time (s)
I

1

,

I
2

(
A
)

I
1
I
2
0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4
40
60
80
95
Time (s)
I

l
o
w

(
A
)
0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4
40
60
80
95
Time (s)
I

h
i
g
h

(
A
)
32
The first 100ns of delay is the propagation delay through the current comparator. During
this time, I
low
follows the change in I
1
. At about t = 1.11s, the output of the comparator
switches. The current spikes seen at this time, result from imperfect synchronization of
the switching of the transmission gates in the multiplexers.
Thus the design of a min-max current selector is completely described and
verified with all the simulation results in this chapter. The min-max current selector is
needed to sort the variables in some multi-variable functions. In the next chapter, the
design of a non-linear function of a single variable sin(
1
) using analog circuits is
discussed. In Chapter V, the implementation of a logarithmic number system (LNS)
subtraction using current-mode analog circuits is discussed. The LNS subtraction is a
more complicated non-linear function of two variables in which a min-max current
selector is needed to sort the two input currents.
33
CHAPTER IV
ANALOG IMPLEMENTATION OF A SINUSOIDAL FUNCTION OF ONE
VARIABLE
In this chapter, the design of an integrated circuit to evaluate a nonlinear function
of a single variable is presented. The function sin(
1
) is implemented as an example. A
piece-wise linear approximation of sin(
1
) on the interval 0,
2
is found, and analog
circuitry is designed to evaluate the linear functions and to select the appropriate one to
produce the output. With a similar approach, the implementation of a logarithmic number
system subtraction, which is a more complicated function of two variables, is discussed
in Chapter V.
4.1 Approximation of sin(
1
)
On the interval 0,
2
, the function sin(
1
) is to be approximated as a piece-wise
linear function using the Chebyshev approximation algorithm. This algorithm chooses the
slopes and y-intercepts of the lines, and the breakpoints between the lines, so as to
minimize the worst-case error between the approximation and the function sin(
1
).
Providing an approximation to evaluate the function sin(
1
) over the input interval 0,
2

is enough to be able to evaluate sin(
1
) for all other real inputs; other input ranges are
simply shifted or reflected copies of the interval 0,
2
.
34
The piece-wise linear approximation to be used here involves the combination of
two linear expressions, as
sin
1

1
+
1
, 0
1

1
+
2
,
1
2

(4.1)
where
1
and
2
are the slopes of the lines,
1
and
2
are the y-intercepts of the lines
and b is the breakpoint between the two lines. These equations can be implemented using
analog circuits once the slopes and the y-intercepts have been determined.
Fig. 4.1 shows the first quarter cycle of the function sin(
1
) and its piece-wise
linear approximation using two lines, found with a Chebyshev approximation. On the
figure, the two lines are annotated with their slopes and y-intercepts. Fig. 4.2 shows the

Figure 4.1: Plot of piece-wise linear approximation of sin(x
1
) with two lines

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.5708
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1

X: 0
Y: 0.02425
x
1
(radians)

S
i
n
(

x
1
)
X: 1.571
Y: 1.024
X: 0.9299
Y: 0.8255
Function Sin(x
1
)
Piece-wise linear approximation
Slope=0.8623255
Y-intercept=0.024251
Slope=0.310189
Y-intercept=0.53701
35
plot of the error between the non-linear function and its approximation. From Fig. 4.2, it
is seen that the maximum and minimum errors for the piece-wise linear approximation
are equal in magnitude.
Knowing the slopes and y-intercepts of the two lines for the approximation, the
approximation can be easily implemented with analog circuitry. To implement the linear
functions using analog circuitry, the input and output variables of the function sin(
1
)
have to be mapped to analog signals. The analog input current I
in
from 70A to 90A is
used to represent the range of input
1
from 0 to
2
. A linear mapping is assumed between
the independent variable
1
and the input current I
in
, so that I
in
=
1
+, where
=
20A
= 12.7324A and = 70A. Similarly, a range of analog output currents I

out

Figure 4.2: Plot of error between sin(
1
) and its piece-wise linear approximation with two
lines

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.5708
-0.025
-0.02
-0.015
-0.01
-0.005
0
0.005
0.01
0.015
0.02
0.025
X: 0
Y: -0.02425
E
r
r
o
r

A
m
p
l
i
t
u
d
e
x
1
(radians)
X: 0.9287
Y: -0.02425
X: 1.571
Y: -0.02425
X: 1.254
Y: 0.02425
X: 0.53
Y: 0.02425
36
from 0 to 20A is used to represent the range of the function sin(
1
) in the first quarter
cycle from 0 to 1. A linear mapping is assumed between the function value and the output
current, so that I
out
= sin(
1
), where = 20A. Substituting these mappings into
Equation (4.1), the function approximation becomes
I
out
= sin
1

(
1

I
in
+
1
), 70A
(
2

I
in
+
2
),
90A

. (4.2)
After replacing the coefficients , , ,
1
,
2
,
1
, and
2
with their values, Equation (4.2)
becomes
I
out
= 20A sin
1

1
I
in
I
b1
, 70A I
in
I
th
2
I
in
I
b2
, I
th
I
in
90A

(4.3)
Where
1
= 1.3545 ,
2
= 0.4872, I
b1
= 94.3326A, I
b2
= 23.3669A, and I
th

represents the output current at the point of intersection between the two lines. Equation
(4.3) shows the two linear functions that must be implemented in analog circuitry in order
to design a hardware unit to evaluate the function sin(
1
). At the point of intersection of
the two lines, the value of x
1
is 0.9287, which corresponds to a current of I
th
=
81.8244A.
4.2 Circuit implementation of the function sin(
1
)
The block diagram in Fig. 4.3 shows the analog implementation of the function
sin(x
1
). The circuit has three distinct parts: an arithmetic unit that implements the two
linear functions, a current comparator that determines which one of the two lines should
be used to approximate the function sin(
1
), given the input current I
in
, and a multiplexer
that routes the corresponding current to the output. These three parts are described in the
next two sections.
37
4.2.1 Design of the arithmetic unit
The arithmetic unit is used to implement the two linear functions which
approximate the function sin(
1
). The two linear expressions to calculate the output
current I
out
in Equation (4.3) have to be implemented with the help of current subtractors.
In these linear expressions, there are negative coefficients for the bias currents and
positive coefficients for I
in
, which means that the two bias currents have to be subtracted
from the corresponding scaled versions of the input current.
A transistor-level schematic of the arithmetic unit is shown in Fig. 4.4. The input
current I
in
, which is shown as a current source in the circuit diagram, is mirrored from the
drain of transistor of M1 to the drain of transistor M18 to produce a copy of I
in
. This
current is mirrored again to the drains of transistors M20 and M21 to produce two
different scaled versions of I
in
, shown in Fig. 4.4 as
1
and
2
I
in
. The two scaling
Current
Comparator
Subtractor 1 Subtractor 2
a
1
I
in
I
th I
in
I
b1
a
2
I
in
I
b2
Multiplexer
Output
Arithmetic
Unit
I
in
varies from
70A to 90A
Select
I
diff1
I
diff2

Figure 4.3: Block diagram of analog implementation of the function sin(x
1
)
38
factors used here are
1
= 1.3545 and
2
= 0.4872, which are the coefficients of the
input current I
in
in Equation (4.3). These scaling factors are implemented simply by
constructing the cascode current mirrors with the appropriate geometric ratios.
Simultaneously, the bias currents I
b1
and I
b2
are produced using two different voltage
divider circuits which consist of diode-connected transistors. The bias current I
b1
is
produced by the voltage divider formed by transistors M22, M23, and M23A, and then
mirrored to the drain of transistor M24. Similarly, the bias current I
b2
is produced by the
voltage divider formed by transistors M25, M26, and M26A, and then mirrored to the
drain of transistor M27. Here I
b1
= 94.3326A, and I
b2
= 23.3669A.
The positive parts in the linear expressions in Equation (4.3) are produced by the
PMOS cascode transistors which act as current sources, and the negative parts are
M18A
M18
M24A
M24
M27A
M27
M19 M20
M20A M19A
V
DD
M23
M22
M23A
M21
M21A
M26
M25
M26A
I
in
M1A
M1
I
diff1
I
diff2
a
1
I
in
a
2
I
in
I
b1
I
b2

Figure 4.4: Schematic of the arithmetic unit
39
produced by the NMOS cascode transistors which act as current sinks. The first linear
expression in Equation (4.3) is implemented by producing
1
I
in
from transistor M20 and
subtracting I
b1
by sinking the current through transistor M24. Similarly the second linear
expression in Equation (4.3) is implemented by producing
2
I
in
from transistor M21 and
subtracting I
b2
by sinking the current through transistor M27. The current differences I
diff1

and I
diff2
, which are the currents left after subtracting the bias currents from their
respective scaled versions of the input current, are the outputs of the arithmetic unit.
These currents will flow to the load through the multiplexer.
4.2.2 Design of the current comparator and the multiplexer
The current comparator used in the function evaluation is similar to the one
incorporated in the min-max current selector, as described in Chapter III. The first input
to the comparator is the input current I
in
and the second is the constant threshold current
I
th
that corresponds to the point of intersection of the two lines used to approximate the
function sin(x
1
). This current comparator produces a digital output, which conveys
I
in
M2
M5 M6
M4A
M11
M10
M6A M5A
M2A
M4
M8
M9
V
out1
V
1
M12
M13A
M12A
M13
M16
M17
M
1
4
M
1
5
`
V
DD
Select
M1A
M1
M3A
M7
M3
V
out2
I
th
I
in
NMOS Cascode
Current Mirror 1
NMOS Cascode
Current Mirror 2
PMOS Cascode
Current Mirror
Schmitt Trigger
Select
M29 M28 M30 M31
I
output
Load
M32A
M32 Multiplexer
I
diff1
I
diff2

Figure 4.5: Schematic of current comparator and multiplexer
40
whether the input current is greater than or less than the threshold current. The output of
this current comparator is used to determine which one of the two lines used to
approximate the function sin(x
1
) should be selected.
A transistor-level circuit diagram for the current comparator and multiplexer is
shown in Fig. 4.5. The input current I
in
is shown as a current source in the schematic. The
input current I
in
is mirrored from the drain of transistor M1 to produce a copy of the input
current I
in
at the drain of transistor M6. The threshold current I
th
is produced by the
voltage divider consisting of M7, M3, and M3A and then mirrored to the drain of
transistor M4. The current I
th
, which corresponds to the point of intersection of two lines
used to approximate the function sin(x
1
), is 81.8244A.

Figure 4.6: Differential response of the current comparator and its expanded version

70 72 74 76 78 80 82 84 86 88 90
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
I
in
(A)
V
o
u
t
2

(
V
)
81.8 81.81 81.82 81.83 81.84 81.85
0
1
2
3
4
5
Expanded version
41
The operation of the comparator is similar to that of the current comparator in the
min-max current selector. The main difference is that, because it has only one variable
input current, the design is optimized to switch states at a fixed threshold. The relative
sizes of the PMOS cascode current mirror and the two NMOS cascode current mirrors
were chosen so as to give a V
out1
of half of V
DD
when the input current I
in
is equal to I
th
.
Two cascaded push-pull amplifiers are implemented to amplify the variations of V
out1

from the bias point. Values of V
out1
above or below half of V
DD
drive the push-pull
amplifier outputs to the appropriate supply rail. The response of the current comparator is
shown in Fig.4.6. The expanded plot shows that the output voltage V
out2
rises sharply
from ground to V
DD
within a short span of 10nA change in the input current. The
transition is centered within 0.1nA of the nominal threshold current I
th
= 81.8244A
and has a differential gain of 1.285V/nA.
A Schmitt trigger is used to produce an unambiguous digital signal from the
output of the current comparator. The Schmitt trigger used here is the same as the one
incorporated in the min-max current selector, as described in Chapter III. The Schmitt
trigger output Select
and its complement (Select), derived using an inverter, are used as

the select control signals for the multiplexer.
Based on the control signals Select and Select
, the multiplexer routes one of the

two current differences I
diff1
or I
diff2
to the output. When Select is V
DD
, indicating that I
in

is larger than I
th
, transistors M28 and M29 are off and transistors M30 and M31 are on, so
as to pass the current difference corresponding to the second linear expression in
Equation (4.3) through the multiplexer to I
out
. Similarly, when Select is ground, the
transmission gates route the current difference corresponding to the first linear expression
42

F
i
g
u
r
e

4
.
7
:

T
o
t
a
l

s
c
h
e
m
a
t
i
c

o
f

s
i
n
e

f
u
n
c
t
i
o
n

i
m
p
l
e
m
e
n
t
a
t
i
o
n

43
in Equation (4.3) to I
out
. The schematic of the whole circuit is shown in Fig. 4.7. The
channel dimensions of all the transistors are listed in Table A.2 of Appendix A. The
channel dimensions of the transistors used in this comparator are different from the
channel dimensions of the transistors used in the comparator of the min-max current
selector. The reason for this is that only one of the input currents to this current
comparator may vary, while the other is fixed; so, it is designed to have a zero offset
when I
in
=I
th
. In the case of the current comparator in the min-max current selector, both
the input currents may vary; it is designed to have a zero offset when I
1
= I
2
= 80A.
4.3 Simulation Results
The whole circuit schematic shown in Fig. 4.7 is simulated with the input current
(I
in
) varying from 70A to 90A. Fig. 4.8 shows plots of the function sin(
1
), the piece-

Figure 4.8: Sinusoidal function results when I
in
is varying from 70A to 90A

70 72 74 76 78 80 82 84 86 88 90
0
2
4
6
8
10
12
14
16
18
20

X: 70
Y: 0.5383
I
in
(A)
I

o
u
t

(
A
)
X: 90
Y: 20.51
X: 81.83
Y: 16.49
Function sin(x
1
)
Analog implementation
44
wise linear approximation (i.e., the Matlab result), and the output of the analog
implementation. The graphs of piece-wise linear approximation and the output of the
analog implementation cannot be distinguished from one another in the figure.
The differences among the function sin(
1
), the piece-wise linear approximation,
and the output of the analog implementation are shown in Fig. 4.9. The maximum error in
the piece-wise linear approximation is 0.48A, which is 2.4% of the full-scale output
current range. The maximum additional error introduced by the electronics is 57nA. The
maximum error between the function sin(
1
) and the analog implementation is 0.55A.
The additional error introduced in the analog implementation is slightly larger than 10%
of the error in the piece-wise linear approximation itself. The overall maximum error
percentage is 2.75% of the full-scale output current range.

Figure 4.9: Plots of error between function sin(
1
), piece-wise linear approximation, and
analog implementation
70 72 74 76 78 80 82 84 86 88 90
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
I
in
(A)
E
r
r
o
r

C
u
r
r
e
n
t

(
A
)

Error between function
sin(x
1
) and piece-wise
linear approximation
Error between piece-wise
linear approximation and
Error between function
sin(x
1
) and
45
From the simulation results, it is observed that most of the error in the output is
due to the piece-wise linear approximation of the function sin(
1
). If the approximation
were done with more than two linear functions, the overall error in the output would be
reduced. However, the amount of circuitry needed for the analog implementation would
increase considerably.
If the function sin(
1
) were evaluated using a voltage-mode approach, the
implementation of the arithmetic unit would require two operational amplifiers, whereas
it requires only a few current mirrors with the current-mode approach. This means that
the voltage-mode approach requires more hardware than the current-mode approach.
With the voltage-mode approach, changes in the linear expressions require the resizing of
resistors. With the current-mode approach, changes in the linear expressions require the
redesign of the current mirrors.
This chapter discusses a method to evaluate the function sin(x
1
) which depends on
only a single variable. The approximation of function sin(x
1
) and its implementation with
current-mode analog circuits have been discussed in detail. The overall error percentage
in the analog implementation is 2.75%. In the next chapter, an analog implementation of
a more complicated function of two variables, log
10
+ when
log
10
+ and log
10
+ are given as inputs, will be discussed in detail.

46
CHAPTER V
ANALOG IMPLEMENTATION OF LOGARITHMIC NUMBER SYSTEM (LNS)
SUBTRACTION
In this chapter, a method of evaluating the logarithmic number system (LNS)
subtraction of two numbers using analog integrated circuits is discussed. LNS subtraction
finds the difference between two numbers represented in a logarithmic number system. If
1
= log
10
+ and
2
= log
10
+ are the base-10 LNS representations
of two numbers and , the absolute difference is represented by
log
10
+ . Thus LNS subtraction evaluates this non-linear function, given
1
and
2
as inputs. Several papers [22-27] have been published on how to evaluate LNS
subtraction using digital implementations based on a field-programmable gate array. Our
approach to evaluate LNS subtraction is to rearrange the function so that it can be
approximated using a piece-wise linear function of a single variable, and then implement
the piece-wise linear function using analog circuitry. This LNS subtraction can be used to
find the forward and backward differences of neighboring pixels of an image obtained
from a logarithmic CMOS camera.
47
5.1 Approximation of LNS subtraction
A base-10 logarithmic number system is assumed, such that two numbers and
are represented as
1
= log
10
+ and
2
= log
10
+. Assuming that
> , the LNS subtraction of
1
and
2
can be rewritten as
log
10
+ = log
10
+ log
10
1
+. (5.1)
In Equation (5.1), log
10
+ can be replaced by
1
, and
can be replaced by
10
1
/
. With these substitutions, Equation (5.1) may be written as

log
10
+ =
1
+ log
10
1 10
1
/

=
1
+
2
1

. (5.2)
Equation (5.2) is in a form that is ready to be implemented in current-mode analog
circuitry. For the implementation, the difference
2
1
can be found easily from the
difference of the two input currents; the difference is used as the input to a piece-wise
linear approximation of the non-linear function . Finally the LNS subtraction is
completed by summing the output of with the input
1
.
To calculate log
10
+ from Equation (5.2) using analog circuits,
only (
2
1
) has to be approximated using a piece-wise linear approximation. The
simplest approximation involves the use of two linear functions. Using more than two
linear functions would increase the accuracy of the approximation, but would also
increase the amount of hardware required for the implementation. In any case, the
Chebyshev approximation algorithm may be used. Before starting the algorithm, first the
range of the inputs to the function which is being approximated has to be found. Here in
1
, the variable is
2
1
. The range of the variable
2
1
depends on the
range of the inputs
1
and
2
.
48
The range of the input variables
1
and
2
depends on the system from which the
inputs are taken. Here
1
and
2
are the pixel output currents of a logarithmic CMOS
image sensor. Any pixel output current of a logarithmic CMOS image sensor is a shifted
and scaled version of the logarithm of the current produced by a photodiode, due to the
input light illumination on the photodiode. The range of input to the photodiode is five
decades of light illumination, for which a typical photodiode produces a current from
1pA to 100nA [27]. The photodiode produces the current linearly only from 4pA to
100nA for a 4.398 decade range of input light illumination, and only this slightly reduced
range should be considered for the simulations. The photodiode current is amplified by a
pixel readout circuit, which produces the pixel output current. For our assumed readout
circuitry, taken from [28], a photodiode current of 100nA, which corresponds to the
highest illumination, results in a pixel output current of 70A, and a photodiode current
of 4pA, which corresponds to the lowest illumination, results in a pixel output current of
90A. Thus, the variables
1
and
2
range from 70A to 90A.
In addition to determining the range of the input variables, it is now possible to
calculate the value of the coefficient p in the expressions for the pixel currents
1
and
2
.
From Equation (5.2), to evaluate log
10
+ from the inputs
1
and
2
, only
the value of the coefficient has to be calculated; the value of q is not required. The
value of can be found by subtracting the two pixel currents
1
and
2
, as

2
1
= log
10
. (5.3)
If
2
= 90A, which is the largest pixel current, and
1
= 70A, which is the smallest
pixel current, the value of
may be found from the ratio of the corresponding photodiode

49
currents as
=
4pA
100nA
= 4 10
5
. Hence, from Equation (5.3), = 4.548A. Note
that is negative, as
1
<
2
implies > .
Returning to the discussion of the range of
2
1
, as the range of the inputs
1

and
2
to the LNS subtraction has been determined as 70A to 90A, the maximum
difference between the inputs is 20A. The minimum difference can be zero; however,
because the logarithm of zero is infinity, the piece-wise linear approximation cannot be
expected to be accurate at that point. The minimum value of
2
1
for which the
approximation of (
2
1
) will be evaluated is chosen as 20nA. The value of the
function f when
2

1
= 20nA is 9.0813A. If the minimum value of
2
1
were
reduced, the maximum value of f would increase. Thus, the errors in the piece-wise linear
approximation throughout the range would be greater.

Figure 5.1: Plot of piece-wise linear approximation of with two lines
0 2 4 6 8 10 12 14 16 18 20
-1
0
1
2
3
4
5
6
7
8
9

X: 0.4795
Y: 1.929
f
(
x
)

(
A
)
x(A)
f(x)
Piece-wise linear approximation with two lines
slope=-13.1640
y-intercept=8.2405
slope=-0.1552
y-intercept=2.0033
50
After setting the range of the difference variable (
2
1
), assuming
1
is less
than
2
since > , the expression (
2

1
) is approximated using two linear
functions as

1
+
1
, 20nA
2
+
2
, 20A

. (5.4)
Equation (5.4) shows the most simplified approximation of the function (), where
1

and
2
are the slopes of the lines,
1
and
2
are the y-intercepts of the lines and b is the
breakpoint between the two lines. The slopes and y-intercepts of the lines are calculated
using the Chebyshev approximation algorithm.
Fig. 5.1 shows the function and its piece-wise linear approximation. On the
figure, the two lines are annotated with their slopes and y-intercepts. The breakpoint
= 479.5nA is also shown. The range over which the curves are plotted is 20nA to

Figure 5.2: Plot of error between () and its piece-wise linear approximation

0 2 4 6 8 10 12 14 16 18 20
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
E
r
r
o
r

A
m
p
l
i
t
u
d
e

i
n

A
x(A)
X: 0.02001
Y: 1.102
X: 0.4795
Y: 1.102
X: 0.1446
Y: -1.102
X: 20
Y: 1.102
X: 4
Y: -1.102
51
20A. The error between the function and its piece-wise linear approximation over this
range is shown in Fig. 5.2. The maximum and minimum errors between the two lines and
the function are equal in magnitude. Substituting the linear expression (5.4) into
Equation (5.2) yields the final linear expression for the LNS subtraction of
1
and
2
as
log
10
+

1
1

1
+
1

2
+
1
, 20nA
2
1

1
2

1
+
2

2
+
2
,
2
1
20A
.

(5.5)
The two linear expressions shown in Equation (5.5) are used to implement the LNS
subtraction using analog circuits.
5.2 Circuit implementation of LNS subtraction
The block diagram in Fig. 5.3 represents an analog implementation of LNS
subtraction. The LNS subtraction circuit has four distinct parts: a min-max current
Current
Comparator
Adder 1 Adder 2
I
high
I
low
+I
bias I
low
I
b1
m
2
I
high
I
b2
Multiplexer
Output
Arithmetic
Unit
m
1
I
high
1-m
1
I
low
1-m
2
Min-max
current
selector
x
1
x
2
Select
I
low
I
high
I
sum1
I
sum2

Figure 5.3: Block diagram of analog implementation of LNS subtraction
52
selector, which sorts the two input currents so as to provide a copy of the smaller of the
two input currents at one output and a copy of larger of the two input currents at the other
output; an arithmetic unit which scales the larger and the smaller currents and adds a bias
current to each of them; a current comparator, which determines which one of the two
lines used to approximate the function f should be selected for the given input currents;
and a multiplexer, which routes the corresponding current sum to the output. These four
parts are described in the next three sections.
5.2.1 Design of the min-max current selector
The min-max current selector takes two input currents, and provides as output two
currents, one a mirrored copy of the smaller of the two input currents, and the other a
mirrored copy of the larger of the two input currents. This operation is essential to the
LNS subtraction, which involves evaluating the absolute value of a difference. The
design, operation and performance of the min-max current selector are already discussed
in Chapter III.
5.2.2 Design of the arithmetic unit
The arithmetic unit is used to implement the two linear expressions which
approximate the function . In deriving Equation (5.5), it is assumed that > . Since p
is negative, this implies that
1
is less than
2
. So
1
and
2
can be replaced in Equation
(5.5) by the currents I
low
and I
high
, respectively. If the slopes and y-intercepts of the lines
are inserted in Equation (5.5), two equations are obtained which could be implemented
using the analog circuits. The two equations obtained are
53
log
10
+

1
1
I
low
+
1
I
high
+I
b1
0 I
high
I
low
I
th

1
2
I
low
+
2
I
high
+I
b2
, I
th
I
high
I
low
20A

, (5.6)
where
1
= 13.1640,
2
= 0.1552, I
b1
= 8.2405A, and I
b2
= 2.0033A. The
point of intersection between the two lines is defined by I
th
= 479.5nA. In both linear
expressions in Equation (5.6), the coefficients of I
high
(that is,
1
and
2
) are negative,
and the coefficients of the other terms are positive. This means that the scaled versions of
the current I
high
have to be subtracted from the respective sums of the other two currents.
The minimum value of the output of the LNS subtraction, obtained when I
low
= 70A
and I
high
= 90A, is equal to 68.8993A. The maximum value of the output, obtained
when both input currents are equal to 90A, is equal to 98.2405A. Therefore, the full-
M52A
M52
M34A
M34
M60A
M60
M53 M54
M54A M53A
V
DD
M56 M57
M57A
M58
M62
M62A
M63
M59
M59A
M61
M61A M56A
I
low
M33
M33A
M55
M55A
I
high
I
sum1 I
sum2
I
b1
(1-m
1
)I
low
I
b2
(1-m
2
)I
low
high 1
I m
high 2
I m

Figure 5.4: Schematic of the arithmetic unit
54
scale output current range of the LNS subtraction is from 68.8993A to 98.2405A, a
range of 29.3412A.
A transistor-level schematic for the arithmetic unit is shown in Fig. 5.4. The input
currents I
low
and I
high
to the arithmetic unit, which are shown as current sources in the
circuit diagram, are provided by the min-max current selector. The current I
low
is mirrored
from the drain of transistor of M33 to the drain of transistor M52 to produce a copy of
I
low
. This current is then mirrored to the drains of transistors M54 and M59 to produce
two different scaled versions of I
low
, shown on Fig. 5.4 as 1
1
I
low
and 1
2

I
low
. The two scaling factors used here are 1
1
= 14.164 and 1
2
= 1.1552,
which are the coefficients of I
low
in Equation (5.6). Simultaneously, I
high
is also mirrored
from the drain of transistor M34 to the drains of transistors M55 and M60 to produce two
different scaled versions of current I
high
, shown on Fig. 5.4 as
1
I
high
and
2
I
high
.
The two scaling factors used here are derived from
1
= 13.164 and
2
= 0.1552,
which are the coefficients of I
high
in Equation (5.6). The bias currents I
b1
and I
b2
are
produced using two different voltage divider circuits. Here I
b1
= 8.2405A and I
b2
=
2.0033A. The implementation of the two linear functions in Equation (5.6) is similar to
the implementation of the arithmetic unit for approximating the function sin(x
1
) as
discussed in Chapter IV.
The current sums I
sum1
and I
sum2
are the currents left after subtracting the scaled
versions of I
high
from the corresponding sums of two currents (scaled versions of the
current I
low
and the bias currents). These current sums are the outputs of the arithmetic
unit. These currents will flow to the load through the multiplexer.
55
5.2.3 Design of the current comparator and the multiplexer
The current comparator has two inputs; the first input is the larger of the two input
currents I
high
and the second input is the sum of the smaller of the two input currents and
the threshold current (I
low
+ I
th
). This current comparator produces a digital output, which
conveys whether the difference between the larger and the smaller of the two input
currents is greater or less than the threshold current. The output of this current
comparator is used to select which one of the two linear functions implemented to
approximate the function has to be selected.
A transistor-level schematic for the current comparator and the multiplexer is
shown in Fig. 5.5. The min-max current selector provides I
low
and I
high
to this current
comparator. The current comparator is similar to the one in the min-max current selector,
except that a constant current I
th
is added to one of the inputs. The current I
low
is mirrored
from the drain of the transistor M33 to produce a copy of it at the drain of the transistor
M38. Simultaneously, the current I
high
is mirrored from the drain of the transistor M34 to
I
low
M35
M37 M38
M34A
M45
M44
M38A M37A
M35A
M34
M42
M43
V
out3
V
2
M39 M40
M40A M39A
M41
M46
M47A
M46A
M47
M50
M51
M
4
8
M
4
9
M33
M33A
M36
M36A
I
high
Select
V
DD
V
out4
I
th
I
high
I
low
NMOS Cascode
Current Mirror 1
NMOS Cascode
Current Mirror 2
PMOS Cascode
Current Mirror
Schmitt Trigger
Select
M65 M64 M66 M67
I
output
Load
M68A
M68
Multiplexer
I
sum1
I
sum2

Figure 5.5: Schematic of the current comparator and multiplexer
56
produce a copy of it at the drain of transistor M36. The constant current I
th
is produced by
the voltage divider consisting of M40, M40A, and M41, and then mirrored to the drain of
transistor M39. This constant current I
th
is added to the current I
low
.
The operation of the current comparator is similar to that of the one in the min-
max current selector. The relative sizes of the PMOS cascode current mirror and the two
NMOS cascode current mirrors were chosen so as to give a V
out3
of half of V
DD
when
I
high
I
low
= I
th
. Values of V
out3
above or below half of V
DD
drive the push-pull
amplifier outputs to the appropriate supply rail. The differential response of the current
comparator for three different common-mode currents is shown in Fig. 5.6. The figure
shows that the comparator characteristic crosses
1
2
V
DD
at the desired threshold current of
479.5nA for a common-mode input current of 80A. For the other common-mode input

Figure 5.6: Differential response of current comparator for three different common-mode
currents

420 440 460 480 500 520 540
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
I
high
-I
low
(nA)
V
o
u
t
4

(
v
o
l
t
s
)

V
out4
for I
low
=70A
V
out4
for I
low
=80A
V
out4
for I
low
=90A
57
currents, there is a maximum input-offset current of 9nA. The current comparator has a
differential gain of 1.7025V/nA.
A Schmitt trigger is used to produce an unambiguous digital signal from the
output of the current comparator. The Schmitt trigger produces an output voltage Select

that is railed to V
DD
if I
high
I
low
> I
th
, and railed to ground if I
high
I
low
< I
th
. The
Schmitt trigger output Select
and its complement (Select), derived using an inverter, are

used as the select control signals for the multiplexer.
Based on the control signals Select and Select
, the multiplexer routes one of the

two current sums I
sum1
or I
sum2
to the output. When Select is V
DD
, indicating that
I
high
I
low
< I
th
, transistors M64 and M65 are off and transistors M66 and M67 are on,
so as to pass the current sum corresponding to the second linear expression in Equation
(5.5) through the multiplexer to I
out
. Similarly, when Select is ground, the transmission
gates route the current sum corresponding to the first linear expression in Equation (5.6)
to I
out
. The schematic of the whole analog circuit to implement the LNS subtraction is
shown in Fig. 5.7. The channel dimensions of all the transistors are listed in Table A.3 in
Appendix A.
5.3 Simulation results
The circuit schematic shown in Fig. 5.7 is simulated with both input currents
(
1
and
2
) varying from 70A and 90A. The simulation results showing the ideal LNS
subtraction, the piece-wise linear approximation (i.e., the Matlab result), and the output
of the analog implementation is provided for three different sets of inputs, with one input
current fixed at 70A, 80A or 90A, and the other input swept over the full range of
inputs. The best result is obtained when one input current is held at 80A while the other
58

F
i
g
u
r
e

5
.
7
:

T
o
t
a
l

s
c
h
e
m
a
t
i
c

o
f

a
n
a
l
o
g

i
m
p
l
e
m
e
n
t
a
t
i
o
n

o
f

L
N
S

s
u
b
t
r
a
c
t
i
o
n
.

59
swept over full range of inputs, because the circuit is optimized for a common-mode
input of 80A, which is in the middle of the input range. The worst-case errors are
obtained when one input current is held at one of the extremes of the input range, 70A
or 90A, while the other input current is swept over the full input range.
Fig. 5.8 shows the simulation results when one of the input currents
1
is held at
80A, while the other
2
is swept over the full range of inputs (i.e., from 70A to 90A).
The figure shows the ideal LNS subtraction, the piece-wise linear approximation and the
output of analog implementation. The plots of the piece-wise linear approximation and
the output of the analog implementation cannot be distinguished from one another in the
figure. The error introduced due to the piece-wise linear approximation can be seen
clearly. When the difference
1
2
is less than 20nA, the output of ideal LNS

Figure 5.8: LNS subtraction results when
1
is fixed at 80A and
2
is varying.
70 72 74 76 78 80 82 84 86 88 90
70
72
74
76
78
80
82
84
86
88
90
x
2
(A)
y

(
A
)

Ideal LNS subtractor
60
subtraction is not plotted. This is done to limit the plotted values near the singular point.
We are not interested in the ideal values of the function within 20nA of the singular
point, because the piece-wise linear approximation has not been constructed to be
accurate in that region.
The differences among the ideal LNS subtraction, the piece-wise linear
approximation, and the output of the analog implementation are shown in Fig. 5.9. The
maximum error in the piece-wise linear approximation is 1.2A, which is 4.09% of the
full-scale output current range. The maximum additional error introduced by the
electronics, i.e. the error between the piece-wise linear approximation and the analog
implementation, is 0.1A. The maximum total error between the ideal LNS subtraction
and the analog implementation is 1.21A, which occurs for a common-mode current of

Figure 5.9: Plots of error between outputs when
1
is fixed at 80A and
2
is varying.
70 72 74 76 78 80 82 84 86 88 90
-1.25
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
1.25
x
2
(A)
E
r
r
o
r

i
n

A

Error between ideal LNS
subtractor and piece-wise
linear approximation
Error between piece-wise
linear approximation and
Error between ideal LNS
subtractor and analog
implementation
61
80A. The additional error introduced in the analog implementation is less than 10% of
the error in the piece-wise linear approximation itself.
1
is held at
2
The figure shows the ideal LNS subtraction, the piece-wise linear approximation, and the
output of the analog implementation. The graphs of the piece-wise linear approximation
and the analog implementation almost coincide with each other throughout the input
range, although not as exactly as in the case of the 80A common mode simulation.
maximum total error between the ideal LNS subtraction and the output of the analog

1
is fixed at 70A and
2
is varying.
70 72 74 76 78 80 82 84 86 88 90
69
70
71
72
73
74
75
76
77
78
79
x
2
(A)
y

(
A
)

62
implementation is 1.25A, which is 4.26% of the full-scale output current range. The
maximum error introduced by the electronics is 0.2A. Most of the error is introduced by
the piece-wise linear approximation and not by the electronics; sometimes the error
introduced by electronics compensates the error introduced by the piece-wise linear
approximation, reducing the total error.
1
is held at
2
The figure shows the ideal LNS subtraction, the piece-wise linear approximation and
output of the analog implementation. The graphs of the piece-wise linear approximation

1
is fixed at 70A and
2
is varying.
70 72 74 76 78 80 82 84 86 88 90
-1.25
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
1.25
x
2
(A)
E
r
r
o
r

i
n

A

Error between ideal LNS subtractor
and piece-wise linear approximation
Error between piece-wise linear
approximation and analog implementation
and analog implementation
63
and the output of the analog implementation almost coincide with each other throughout
the input range, as in the case of 70A common mode simulation.
maximum total error between the ideal LNS subtraction and the analog implementation is
same as that of 70A common mode simulation. The maximum error introduced by the
electronics is 0.21A, which is slightly more than that of 70A common mode
simulation.
From the simulations, it is seen that the most of the error in the output is due to
the piece-wise linear approximation used, rather than the electronics. The additional error

1
is fixed at 90A and
2
is varying.
70 72 74 76 78 80 82 84 86 88 90
70
75
80
85
90
95
100
x
2
(A)
y

(
A
)

64
introduced by the analog implementation is less than 20% of the error in the piece-wise
linear approximation itself. The overall maximum error is 4.26% of full-scale output
current range. If the approximation were done with more than two linear functions, the
overall error in the output would be reduced. However, the amount of circuitry needed
would increase considerably.
If the LNS subtraction is implemented using a voltage-mode approach, then it
requires: a two-input voltage sorter to sort the two input voltages; an arithmetic unit,
which consists of two operational amplifiers, to implement the two linear functions; and
an operational amplifier, a comparator and a multiplexer to select the correct linear
function for the given input voltages. The big difference in hardware between this

1
is fixed at 90A and
2
is varying.
70 72 74 76 78 80 82 84 86 88 90
-1.25
-1
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
1
1.25
x
2
(A)
E
r
r
o
r

i
n

A

and piece-wise linear approximation
Error between piece-wise linear
approximation and analog implementation
and analog implementation
65
approach and a current-mode approach is the arithmetic unit and the hardware used for
selecting the correct line. The voltage-mode approach requires three operational
amplifiers, a comparator and a multiplexer, whereas the current-mode approach requires
a few current mirrors, a current comparator and a multiplexer to implement the arithmetic
unit and the hardware used for selecting the correct line. This means that the voltage-
mode approach requires a lot more hardware than the current-mode approach.
5.4 Application of LNS subtraction
The calculation of finite differences is the basic step of any image edge detection
technique. Calculating these finite differences in the linear domain is straightforward
[29]. However, when the CMOS image sensor being used is a logarithmic one, the
meaning of a difference between pixels is changed; a difference between logarithmic-
domain pixels is equivalent to a ratio of linear-domain pixels.
In order to directly apply edge detection techniques that have been developed in
the linear domain to the logarithmic domain, i.e., in order to calculate what is equivalent
to a difference of linear-domain pixels, it is necessary not to subtract the logarithmic
pixels, but instead to implement a logarithmic number system (LNS) subtraction of the
pixels. The analog circuitry to evaluate LNS subtraction already discussed in this chapter
can be used for finding the finite differences. This LNS subtraction circuit can be
incorporated in the read-out circuitry of a logarithmic CMOS image sensor to make a
smart camera with real-time edge detection capability.
Another application for which LNS subtraction can be used is on-chip capture of
color images in a logarithmic YC
b
C
r
color space. Such a calculation would be useful
66
given a camera that produces logarithmic R, B and Y values for each pixel. Given the Y,
R and B values, the C
b
and C
r
values may be calculated in the linear domain as [29]
C
b
= 0.564B Y (5.7)
C
r
= 0.713R Y. (5.8)
In the logarithmic domain, these equations become
logC
b
= log0.564 +logB Y (5.9)
logC
r
= log0.713 + logR Y. (5.10)
Thus, image pixels in a logarithmic YC
b
C
r
color space can be calculated for a color
logarithmic CMOS image camera using LNS subtraction.
It is noted that the output of the LNS subtractor depends only on the absolute
value of the difference , and does not indicate which of the corresponding pixels is
brighter. However, this information can be obtained from the output of the current
comparator in the min-max current selector.
67
CHAPTER VI
CONCLUSION AND FUTURE WORK
A design method for analog circuitry for evaluating a piece-wise linear
approximation of a non-linear multi-variable function is developed. Analog circuits for
implementation of two different non-linear functions have been designed and verified in
simulation. In some cases, to implement non-linear functions of more than a single
variable, the input variables to the function have to be sorted. For this purpose, a min-
max current selector is designed. This min-max current selector is a basic block of a
current sorter. The min-max current selector works for input currents over a 20A range,
from 70A to 90A. It uses a current comparator that has a worst-case input-offset
current of 5nA and a differential gain of 2.025V/nA. The maximum output current error
for the min-max current selector is 10nA.
A non-linear function of a single variable sin(x
1
) has been approximated with two
linear functions using the Chebyshev approximation algorithm. These two linear
functions are then implemented using analog circuitry. A current comparator is designed
to control a multiplexer that selects one of the two implemented linear function outputs to
approximate the function sin(x
1
) for the given input current. This current comparator
selects the correct line without any significant error and has a differential gain of
1.285V/nA. The maximum error in the circuit simulation results is 2.75% of the full-scale
output current range.
68
Similarly, a more complicated non-linear function representing the LNS
subtraction of two variables is also approximated with two linear functions using the
Chebyshev approximation algorithm. The min-max current selector previously designed
is used to sort the two input currents. A current comparator that has a maximum input-
offset current of 9nA and a differential gain of 1.7025V/nA is used in this design. The
maximum error in the circuit simulation results is 4.26% of the full-scale output current
range. Due to the more severe non-linearity in the logarithmic function, this error is
greater than that for the approximation of the function sin(x
1
).
The analog circuits designed to implement the two non-linear functions have been
simulated with nominal devices. The future work involves studying the various factors
which contribute to the error in the output due to process variations. The output error due
to the process variations has to be reduced. All the circuits which generate bias currents
in this thesis are designed using a combination of PMOS and NMOS diode-connected
transistors. If they were designed either with NMOS transistors only or with PMOS
transistors only, then the sensitivity to process variations could be reduced a bit. In the
corner simulation results of the min-max current selector circuit, it is seen that about half
of the error is due to routing errors caused by the current comparator and the other half is
due to the currents being mirrored incorrectly by the current mirrors. The current
comparator also has some current mirrors. Thus, most of the error in the process
variations is due to the current mirrors. If the current mirrors are analyzed separately
using corner simulations and Monte Carlo simulations, the parameters which cause the
process variations can be observed and studied. Then proper steps can be taken to reduce
the effects of the variations. This could in turn significantly reduce the effects of the
69
variations in the circuits, as the current mirrors are an essential part of each analog circuit
implemented.
70
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73
APPENDIX A
Table A.1 Channel dimensions of transistors in min-max current selector
Device WL No. of fingers

M1, M1A, M2, M2A, M3,
M3A, M4, M4A, M17,
M17A, M21, M21A
40m6m 1
M5, M5A, M6, M6A 30.7m6m 6
M7, M9, M15 27.1m8m 1
M8, M10, M16 10m8m 1
M11, M11A 13m1.3m 6
M12, M12A, M14 15m1.2m 2
M13 17m1.3m 3
M18, M18A, M19, M19A,
M20, M20A, M22, M22A,
M23, M23A, M24, M24A
47.9m3.8m 5
M25, M27, M29, M31 6m1.5m 1
M26, M28, M30, M32 15m1.5m 2

74
Table A.2 Channel dimensions of transistors in the analog implementation of the sine
function


M1, M1A, M2, M2A, M3,
M3A, M4, M4A, M18, M18A
23.1m5m 5
M5, M5A, M6, M6A 30m2m 5
M7 12.8m3.3m 1
M8, M10 27.1m8m 1
M9, M11 10m8m 1
M12, M12A 20m1.3m 1
M13, M13A, M15 10m1.2m 1
M14 6m1.3m 1
M16 9.1m1.5m 1
M17 3m1.5m 1
M19, M19A, 46m5m 4
M20, M20A 41m5m 4
M21, M21A 23m5m 4
M22 18.5m4m 1
M23, M23A, M24, M24A 21.6m3m 3
M25 1.7m1.4m 1
M26, M26A, M27, M27A 16.4m2m 1
M28, M30 6m1.5m 1
M29, M31 15m1.5m 2
M32, M32A 25m3m 6

75
Table A.3 Channel dimensions of transistors in the analog implementation of LNS
subtraction

M1, M1A, M2, M2A, M3, M3A, M4,
M4A, M17, M17A, M21, M21A
40m6m 1
M5, M5A, M6, M6A 30.7m6m 6
M7, M9, M15, M42, M44, M50 27.1m8m 1
M8, M10, M16, M43, M45, M51 10m8m 1
M11, M11A 13m1.3m 6
M12, M12A, M14 15m1.2m 2
M13 17m1.3m 3
M18, M18A, M19, M19A, M20, M20A,
M22, M22A, M23, M23A, M24, M24A
47.9m3.8m 5
M25, M27, M29, M31, M48 M64, M66 6m1.5m 1
M26, M28, M30, M32, M65, M67 15m1.5m 2
M33, M33A, M34, M34A, M35, M35A,
M36, M36A, M52, M52A, M68, M68A
25m3m 6
M37, M37A, M38, M38A 32.4m2.5m 5
M39, M39A, M40, M40A 1m9m 1
M41 8.9m9m 1
M46, M46A 20m1.3m 1
M47, M47A, M49 10m1.2m 1
M53, M53A 30.6m4m 4
M54, M54A 35.2m4m 4
M55, M55A 23.3m3m 1
M56, M56A, M57, M57A 1m2m 1
M58 13m2m 1
M59, M59A 30.6m4m 56
M60, M60A 25m3m 78
M61, M61A, M62, M62A 1.7m1.4m 1
M63 19.8m2m 2

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ANALOG NON-LINEAR MULTI-VARIABLE FUNCTION EVALUATION BY

PIECE-WISE LINEAR APPROXIMATION

are the input variables to the function,

are the constants corresponding to each

are the input variables to the function,

is the scaling factor

, and c is a constant. A block of analog circuitry that

and the output y are mapped to a set of

. For a current-mode approach, they are mapped to a set of

by its respective scaling factor

) are related to the linear function

in a way that depends on the mappings between the input variables

. Similarly, the constant c is implemented using a voltage

, each scaled by its respective scaling factor. The

in a way that depends on the mappings

and the input currents

. Similarly, the constant c is

which is produced by the constant current source. Finally, the

, which is the output V

= 12.7324A and = 70A. Similarly, a range of analog output currents I

and its complement (Select), derived using an inverter, are used as

, the multiplexer routes one of the

may be found from the ratio of the corresponding photodiode

and its complement (Select), derived using an inverter, are

, the multiplexer routes one of the

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