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Chapter 4
Wafer Manufacturing
and Epitaxy Growing
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Objectives
Give two reasons why silicon dominate
Wafer orientations
Basic steps from sand to wafer
Describe the CZ and FZ methods
Explain the purpose of epitaxial silicon
Describe the epi-silicon deposition process.
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Crystal Structures
Amorphous
No repeated structure at all
Polycrystalline
Some repeated structures
Single crystal
One repeated structure
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Amorphous Structure Polycrystalline Structure
Single Crystal Structure
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Why Silicon?
Abundant, cheap
Silicon dioxide is very stable, strong
dielectric, and it is easy to grow in thermal
process.
Large band gap, wide operation temperature
range.
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Name Silicon
Symbal Si
Atomic number 14
Atomic weight 28.0855
Discoverer Jns Jacob Berzelius
Discovered at Sweden
Discovery date 1824
Origin of name From the Latin word "silicis" meaning "flint"
Bond length in single crystal Si 2.352
Density of solid 2.33 g/cm
3
Molar volume 12.06 cm
3
Velocity of sound 2200 m/sec
Electrical resistivity 100,000 cm
Reflectivity 28%
Melting point 1414 C
Boiling point 2900 C
Source: http://www.shef.ac.uk/chemistry/web-elements/nofr-key/Si.html
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Unit Cell of Single Crystal Silicon
Si
Si
Si
Si
Si
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Unit Cells in Material
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Miller Indices
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Crystal Orientations: <100>
x
y
z
(100) plane
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Crystal Orientations: <111>
x
y
z
(100) plane
(111) plane
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Crystal Orientations: <110>
x
y
z
(110) plane
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<100> Orientation Plane
Atom Basic lattice cell
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<111> Orientation Plane
Silicon atom Basic lattice cell
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<100> Wafer Etch Pits
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<111> Wafer Etch Pits
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Illustration of the Defects
Silicon Atom Impurity on substitutional site
Frenkel Defect Vacancy or Schottky Defect
Impurity in
Interstitial Site
Silicon
Interstitial
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Dislocation Defects
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Stress and Defects
Defects can be usually generated
during high temperature steps in wafer
formation or thermal process due to
intrinsic stress.
Thermal gradient can be another factor
to cause stress, e.g. from oxidation,
diffusion, RTA, RTO etc.
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From Sand to Wafer
Quartz sand: silicon dioxide
Sand to metallic grade silicon (MGS)
React MGS powder with HCl to form TCS
Purify TCS by vaporization and condensation
React TCS to H
2
to form polysilicon (EGS)
Melt EGS and pull single crystal ingot
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From Sand to Wafer (cont.)
Cut end, polish side, and make notch or flat
Saw ingot into wafers
Edge rounding, lap, wet etch, and CMP
Laser scribe
If an epitaxial layer is needed ,
Epitaxy deposition
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From Sand to Silicon
Heat (2000 C)
SiO
2
+ C

Si + CO
2
Sand Carbon MGS Carbon Dioxide
Heat (1100 C)
SiHCl3 + H2
Si + 3HCl
TCS Hydrogen EGS Hydrochloride
Heat (300C)
Si + HCl TCS + H2
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Crystal Pulling: CZ method
Graphite Crucible
Single Crystal
silicon Ingot
Single Crystal Silicon Seed
Quartz Crucible
Heating Coils
1415 C
Molten Silicon
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CZ Crystal Pullers
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CZ Crystal Pulling
Source: http://www.fullman.com/semiconductors/_crystalgrowing.html
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Floating Zone Method
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Comparison of the Two Methods
CZ method is more popular
Cheaper
Larger wafer size (300 mm in production)
Reusable materials
Floating Zone
Pure silicon crystal (no crucible)
More expensive, smaller wafer size (150 mm)
Mainly for power devices.
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Ingot Polishing, Flat, or Notch
Flat, 150 mm and smaller Notch, 200 mm and larger
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Wafer Sawing
Orientation
Notch
Crystal Ingot
Saw Blade
Diamond Coating
Coolant
Ingot
Movement
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Parameters of Silicon Wafer
Wafer Size (mm) Thickness m) Area (cm
2
) Weight (grams)
279 20.26 1.32
381 45.61 4.05
100 525 78.65 9.67
125 625 112.72 17.87
150 675 176.72 27.82
200 725 314.16 52,98
300 775 706.21 127.62
50.8 (2 in)
76.2 (3in)
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Wafer Edge Rounding
Wafer
Wafer movement
Wafer Before Edge Rounding
Wafer After Edge Rounding
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Wafer Lapping
Rough polished
conventional, abrasive, slurry-lapping
To remove majority of surface damage
To create a flat surface
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Wet Etch
Remove defects from wafer surface
4:1:3 mixture of HNO
3
(79 wt% in H
2
O),
HF (49 wt% in H
2
O), and pure CH
3
COOH.
Chemical reaction:
3 Si + 4 HNO
3
+ 6 HF 3 H
2
SiF
6
+ 4 NO + 8 H
2
O
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Chemical Mechanical Polishing
Slurry
Polishing Pad
Pressure
Wafer Holder
Wafer
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Wafer Polishing Operation
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200 mm Wafer Thickness and
Surface Roughness Changes
76 m
914 m
After Wafer Sawing
After Edge Rounding
76 m
914 m
12.5 m
814 m
<2.5 m
750 m
725 m
Virtually Defect Free
After Lapping
After Etch
After CMP
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Epitaxy Grow
Definition
Purposes
Epitaxy Reactors
Epitaxy Process
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Epitaxy: Definition
Greek origin
epi: upon
taxy: orderly, arranged
Epitaxial layer is a single crystal layer on a
single crystal substrate.
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Epitaxy: Purpose
Barrier layer for bipolar transistor
Reduce collector resistance while keep high
breakdown voltage.
Only available with epitaxy layer.
Improve device performance for CMOS and
DRAM because much lower oxygen,
carbon concentration than the wafer crystal.
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Epitaxy Application, Bipolar
Transistor
n-Epi
p n
+
n
+
P-substrate
Electron flow
n
+
Buried Layer
p
+
p
+
SiO
2
AlCuSi
Base Collector Emitter
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Epitaxy Application: CMOS
P-Wafer
N-Well
P-Well
STI
n
+
n
+
USG
p
+
p
+
Metal 1, AlCu
BPSG
W
P-type Epitaxy Silicon
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Silicon Source Gases
Silane SiH
4
Dichlorosilane (DCS) SiH
2
Cl
2
Trichlorosilane (TCS) SiHCl
3
Tetrachlorosilane SiCl
4
Diborane B
2
H
6
Phosphine PH
3
Arsine AsH
3
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DCS Epitaxy Grow, Arsenic Doping
Heat (1100

C)
SiH
2
Cl
2
Si + 2HCl
DCS Epi Hydrochloride
AsH
3
As + 3/2 H
2
Heat (1100

C)
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Schematic of DCS Epi Grow and
Arsenic Doping Process
SiH
2
Cl
2
Si
AsH
3
As
AsH
3
H
HCl
H
2
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Epitaxial Silicon Growth Rate Trends
G
r
o
w
t
h
R
a
t
e
,
m
i
c
r
o
n
/
m
i
n
1000/T(K)
Temperature (C)
0.7 0.8 0.9 1.0 1.1
0.01
0.02
0.05
0.1
0.2
0.5
1.0
1300 1200 1100 1000 900 800 700
SiH
4
SiH
2
Cl
2
SiHCl
3
Surface reaction limited
Mass transport
limited
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Barrel Reactor
Radiation
Heating
Coils
Wafers
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Vertical Reactor
Heating
Coils
Wafers
Reactants
Reactants and
byproducts
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Horizontal Reactor
Heating Coils
Wafers
Reactants
Reactants and
byproducts
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Epitaxy Process, Batch System
Hydrogen purge, temperature ramp up
HCl clean
Epitaxial layer grow
Hydrogen purge, temperature cool down
Nitrogen purge
Open Chamber, wafer unloading, reloading
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Single Wafer Reactor
Sealed chamber, hydrogen ambient
Capable for multiple chambers on a mainframe
Large wafer size (to 300 mm)
Better uniformity control
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Single Wafer Reactor
Heating Lamps
Heat
Radiation
Wafer
Quartz
Window
Reactants
Reactants &
byproducts
Quartz
Lift
Fingers
Susceptor
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Epitaxy Process, Single Wafer
System
Hydrogen purge, clean, temperature ramp up
Epitaxial layer grow
Hydrogen purge, heating power off
Wafer unloading, reloading
In-situ HCl clean,
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Why Hydrogen Purge
Most systems use nitrogen as purge gas
Nitrogen is a very stable abundant
At > 1000 C, N
2
can react with silicon
SiN on wafer surface affects epi deposition
H
2
is used for epitaxy chamber purge
Clean wafer surface by hydrides formation
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Defects in Epitaxy Layer
Dislocation
Stacking Fault from
Surface Nucleation
Impurity Particle
Hillock
Stacking Fault form
Substrate Stacking Fault
After S.M. Zses VLSI Technology
Substrate
Epi Layer
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Future Trends
Larger wafer size
Single wafer epitaxial grow
Low temperature epitaxy
Ultra high vacuum (UHV, to 10
-9
Torr)
Selective epitaxy
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Summary
Silicon is abundant, cheap and has strong,
stable and easy grown oxide.
Miller indices and wafer orientation
CZ and floating zone (FZ), CZ is more
popular
Sawing, edging, lapping, etching and CMP
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Summary
Epitaxy: single crystal on single crystal
Needed for bipolar and high performance
CMOS, DRAM.
Silane, DCS, TCS as silicon precursors
B
2
H
6
as P-type dopant
PH
3
and AsH
3
as N-type dopants
Batch and single wafer systems
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Future Trend
Silicon on insulator (SOI) is emerging !
SOI technology for next generation IC
Compound semiconductor is rising !
SiC , GaN for fast speed and high power
devices