Preface p.

xi
Acknowledgments p. xv
Nomenclature p. xvii
Low-Power CMOS VLSI Design p. 1
Introduction p. 1
Sources of Power Dissipation p. 2
Static Power Dissipation p. 3
Transistor leakage mechanisms p. 3
Channel engineering for leakage reduction p. 25
Active Power Dissipation p. 31
Short-circuit dissipation p. 32
Switching dissipation p. 34
Conclusions p. 37
Circuit Techniques for Low-Power Design p. 41
Introduction p. 41
Designing for Low-Power p. 41
Circuit Techniques for Leakage Power Reduction p. 43
Standby leakage control using transistor stacks (self reverse bias) p. 45
Multiple V[subscript th] techniques p. 46
Dynamic V[subscript th] technique p. 53
Supply voltage scaling technique p. 54
Leakage reduction techniques for cache (SRAM) p. 56
Conclusions p. 60
Low-Voltage Low-Power Adders p. 63
Introduction p. 63
Standard Adder Cells p. 64
Half adders p. 64
Full adders and their various schematic configurations p. 65
CMOS Adder's Architectures p. 72
Ripple Carry Adders (RCA) p. 72
Carry Look-Ahead Adders (CLA) p. 75
Carry Select Adders (CSL) p. 81
Carry Save Adders (CSA) p. 83
Carry Skip Adders (CSK) p. 85
Conditional Sum Adders (COS) p. 87
Performance evaluation of various adder architectures p. 89
BiCMOS Adder p. 90
PT-BiCMOS Gate p. 90
Low-Voltage Low-Power Design Techniques p. 95
Trends of technology and power supply voltage p. 95
Low-voltage low-power logic styles p. 96
Current-Mode Adders p. 100
Current-Mode CMOS Adders using multiple-valued logic p. 100
Residue adders based on binary adders p. 107
Fast addition using the new Signed-Digit number system p. 112
Conclusions p. 115
Low-Voltage Low-Power Multipliers p. 119
Introduction p. 119
Overview of Multiplication p. 119
Unsigned multiplication p. 120
Shift/add multiplication algorithms p. 121
Multiplication of signed numbers p. 122
Types of Multiplier Architectures p. 122
Serial multipliers p. 123
Parallel multipliers p. 123
Serial-parallel multipliers p. 123
Braun Multiplier p. 124
Architecture of Braun multiplier p. 125
Performance of Braun multiplier p. 125
Speed consideration p. 125
Enhanced Braun multiplier p. 127
Baugh-Wooley Multiplier p. 127
Architecture of Baugh-Wooley multiplier p. 127
Algorithm of Baugh-Wooley multiplier p. 128
2's complement number system p. 131
Performance consideration p. 131
Booth Multiplier p. 131
Booth's algorithm p. 133
Standard radix-2 Booth multiplication rules p. 134
Modified Booth algorithm p. 135
Booth encoder p. 137
Wallace Tree Multiplier p. 139
4:2 compressors p. 140
Wallace tree construction p. 143
Conclusions p. 145
Low-Voltage Low-Power Read-Only Memories p. 147
Introduction p. 147
Types of ROM p. 148
Standard ROM p. 149
Mask-programmed ROM (MROM) p. 149
Programmable ROM (PROM) p. 150
Floating gate memory arrays p. 150
Basic Physics of Floating Gate Nonvolatile Devices p. 151
Hot carrier injection p. 151
Fowler-Nordheim (F-N) tunneling p. 154
Ultraviolet light erase p. 155
Floating Gate Memories p. 156
Erasable programmable ROM (EPROM) p. 156
Electrically erasable programmable ROM (EEPROM) p. 158
Flash memory p. 161
Basics of ROM p. 163
Chip architecture p. 163
ROM cell arrays p. 164
Low-Power ROM Technology p. 167
Sources of power dissipation p. 167
Low-power techniques at architecture level p. 169
Low-power techniques at circuit level p. 170
Future Trend and Development of ROMs p. 171
Conclusions p. 173
Low-Voltage Low-Power Static Random-Access Memories p. 177
Introduction p. 177
Basics of SRAM p. 178
Memory Cell p. 181
The race between 6T and 4T memory cells p. 181
Low-voltage low-power (LVLP) SRAM cell designs p. 185
Precharge and Equalization Circuit p. 192
Decoder p. 193
Dynamic decoder p. 194
Static decoder p. 195
Address Transition Detection (ATD) p. 198
Sense Amplifier p. 198
Voltage sense amplifier p. 199
Current sense amplifier p. 201
Output Latch p. 206
Low-Power SRAM Technologies p. 207
Sources of SRAM power p. 207
Development of low-power circuit techniques p. 208
Future Trend and Development of SRAM p. 212
Conclusions p. 213
Low-Voltage Low-Power Dynamic Random-Access Memories p. 217
Introduction p. 217
Types of DRAM p. 218
Conventional DRAM p. 218
Fast Page Mode DRAM (FPM DRAM) p. 219
Enhanced DRAM (EDRAM) p. 219
Extended Data Out DRAM (EDO DRAM) p. 219
Burst Extended Data Output DRAM (BEDO DRAM) p. 220
Synchronous DRAM (SDRAM) p. 221
Enhanced Synchronous DRAM (ESDRAM) p. 222
Double Data-Rate DRAM (DDR DRAM) p. 222
Synchronous Link DRAM (SLDRAM) p. 222
Rambus DRAM (RDRAM) p. 223
Direct Rambus DRAM (DRDRAM) p. 224
Video RAM (VRAM) p. 224
Embedded DRAM (EmDRAM) p. 225
Basics of DRAM p. 226
Basic architecture p. 226
Read and Write Operation p. 227
Self-Refresh Circuit p. 228
General mechanism p. 228
Reference Signal Generator (RSG) p. 229
Test memory cell p. 230
The nMOS differential amplifier p. 231
CMOS differential-to-digital converter p. 232
Half-Voltage Generator (HVG) p. 233
Conventional half-voltage generator p. 233
Speed-enhanced half-V[subscript DD] generator p. 234
Dynamic half-voltage generator (Dynamic HVG) p. 235
Back-Bias Generator (BBG) p. 236
Conventional charge pump circuit p. 236
Low-voltage back-bias generator using hybrid pumping scheme p. 237
Two-phase back-bias generator p. 238
Boosted-Voltage Generator (BVG) p. 240
Conventional BVG p. 241
Two-phase boosted-voltage generator p. 243
Reference-Voltage Generator (RVG) p. 244
Conventional RVG p. 244
Low-power dynamic RVG p. 246
RVG using pure enhancement-mode transistors p. 247
Voltage-Down Converter (VDC) p. 249
The on-chip differential amplifier-based VDC p. 249
Voltage follower p. 250
Complete VDC circuit p. 252
Future Trend and Development of DRAM p. 253
Conclusions p. 254
Large Low-Power VLSI System Design and Applications p. 257
Behavioral Level Transforms p. 258
Algorithm and Architecture Level Transforms for Low Power p. 258
Differential coefficients for FIR filters p. 258
Algorithm using first-order differences p. 259
Algorithm using generalized mth order differences p. 261
Negative differences p. 262
Sorted recursive differences p. 262
Shared multiplier based vector scaling operation p. 263
Architecture-driven voltage scaling p. 265
Power optimization using operation reduction p. 267
Power optimization using operation substitution p. 268
Precomputation-based optimization for low power p. 269
Multiple and Dynamic Supply Design p. 273
Multiple supply voltage design p. 273
Dynamic supply voltage design p. 275
Choice of supply voltages p. 277
Rate of change of supply voltages p. 277
Power-supply network p. 277
Varying the clock speed p. 278
Varying the V[subscript DD] of RAM structures p. 278
Level conversion on the path from V[superscript L subscript DD] to V[superscript H
subscript DD]
p. 280
Gated Clocking p. 280
Conclusions p. 282
Index p. 283
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