GONZALES, JONN KENNETH LAURENCE A.

COE121-C5
MAPUA INSTITUTE OF TECHNOLOGY
SCHOOL OF EE-ECE-CPE
QUIZ#4
MICROPROCESSOR
INSTRUCTIONS:
1. Use only yellow book in answering the questions.
2. Ask your questions directly to your instructor/proctor.
I.
IDENTIFICATION
1. One of the addresses stored in the cache matches the address being used for the
memory read. HIT
2. This is one of the solutions to the performance bottleneck. RISC
3. This helps to identify possible interruptions to the normal flow of instructions
through the U and V pipelines. BRANCH PREDICTIONS
4. The number of floating-point registers contained in the Pentium. 8
5. This is the dead state between two consecutive cycles. TD
6. This cycle is used to read and write 32 bytes. BURST CYCLE
7. This means to lock the bus. LOCKED OPERATION
8. This means that caches are flushed. CACHE FLUSH
9. This machine is capable of parallel execution of multiple instructions.
SUPERSCALAR
10. This pipeline only executes simple instructions. V PIPELINE
11. This happens when the required instruction or data is not found in the internal
cache. MISS
12. This happens when results are written only to the cache. WRITEBACK
13. This means that tags in the data cache can be accessed from three different places
at the same time. TRIPLE PORTED
14. This is used to translate virtual address into physical address. TRANSLATION
LOOKASIDE BUFFER
15. This is a cache-consistence protocol that uses 2 bits stored with each line of data
to keep track of the state of the cache line. MESI
16. This is the floating-point execute, stage one. X1
17. This allows the use of minimal logic in each stage and a higher clock speed for
the pipeline. HYPER-PIPELINED TECHNOLOGY
18. This enables one instruction to perform its work on multiple operands
simultaneously. SIMD (SINGLE INSTRUCTION, MULTIPLE DATA)
19. These new instructions give the programmer ways to organize data for SIMD
computations. NEW MEDIA
20. This allows 64-bit computing on integers, pointers, and registers. EM64T
21. This is a small portion of a program. THREAD

cco

GOODLUCK!!

22. This is a new security feature of Pentium 4 that helps prevent malicious buffer
overflow attacks, a common computer security violation technique. EXECUTE
DISABLE BIT
23. In this technique, data is preloaded before it is needed, while the other instructions
are also being executed. SPECULATION OR SPECULATIVE LOADING
24. This is the ability of Pentium 4 to run two threads of code simultaneously.
HYPERTHREADING
25. This is used to map temporary result registers to the actual processor registers.
REGISTER RENAMING

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II.

ILLUSTRATION
Illustrate how the following instructions will be executed using:
a. non-pipelining b. pipelining
Instructions 1-10 is an entire program.
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10

STC
STD
STI
MOV AL, ED
MOV BL, 67
ADD AL, BL
CLC
MOV CL, AL
MOV AL, F1
SUB CL, AL

II. A.
NON-PIPELINING

cco

I1

I1

I1

I2

I2

I2

I3

I3

I3

I4

I4

I4

I5

I5

I5

I6

I6

I6

I7

I7

I7

I8

I8

I8

I9

I9

I9

I10

I10

I10

GOODLUCK!!

II. B.
PIPELINING
PF

I1

I2

D1

I3

I4

I5

I6

I7

I8

I9

I10

I1

I2

I3

I4

I5

I6

I7

I8

I1

I2

I3

I4

I5

I6

I1

I2

I3

I4

I1

I2

D2

EX

WB

Clock
Cycle

cco

GOODLUCK!!

III.
ENUMERATION
1-6
Bus Cycle States
TI, T1, T2, T12, T2P, TD
7-11
The Five-stage U and V Pipeline
PF, D1, D2, EX, WB
12-14
Three features of Pentium 4
HYPER-PIPELINED TECHNOLOGY, RAPID EXECUTION ENGINE,
EXECUTION TRACE CACHE
15-17
Division of SSE instructions.
SIMD-FP, NEW MEDIA, STREAMING MEMORY
18-21
MESI states
MODIFIED, EXCLUSIVE, SHARED, INVALID
22-29
The Eight-stage FPU Pipeline
PF, D1, D2, EX, X1, X2, WF, ER

cco

GOODLUCK!!

IV.

Match the items in column A with the items in column B.

COLUMN A
COLUMN B
Bus Cycle States
Register Renaming
Atomic Operation
Semaphore
Pipelining
Invalid
Cache Flush
Explicitly Parallel Instruction Computing
Cache Coherency
Writeback
FPU Pipeline
Least Recently USed
Itanium 2
Error Report
Pentium 4
Execute Disable Bit
SSE
T2P
Dynamic Execution Streaming Memory
Intel Mobile CPUs
Direct-mapped Cache

BUS CYCLE STATES

T2P

ATOMIC OPERATION

SEMAPHORE

PIPELINING

WRITEBACK

CACHE FLUSH

LEAST RECENTLY USED

CACHE COHERENCY

INVALID

FPU PIPELINE

ERROR REPORT

ITANIUM 2

EXPLICITLY PARALLEL INSTRUCTION COMPUTING

PENTIUM 4

EXECUTE DISABLE BIT

SSE

STREAMING MEMORY

DYNAMIC EXECUTION

REGISTER RENAMING

cco

GOODLUCK!!