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PROIECTAREA CIRCUITELOR NUMERICE CU STRUCTURI PROGRAMABILE DE TIP FPGA (II)

1. Scopul lucrării

Prezentarea structurii unui sistem de dezvoltare realizat în jurul circuitului integrat programabil FPGA (Field Programmable Gate Array) Virtex 4 – FX12 (circuitul XC4VFX12, care conţine 12312 blocuri logice, 86 kbiţi de memorie RAM, 36 blocuri de memorie de 648 kbiţi, 32 blocuri Xtreme DSP şi 320 intrări/ieşiri programabile) şi verificarea funcţionării sistemului prin aplicaţia oferită de fabricant.

2. Aparate necesare

- calculator compatibil Pentium, minim 500MHz, minim 256MB RAM

- mediul de programare ISE (Integrated Software Environment)-versiunea

6.1i, furnizat de firma Xilinx, instalat pe o platformă Windows 2000 (SP2 sau SP3) sau XP. Programul poate fi instalat şi pe sistemele de operare Linux sau Solaris.

- modulul ML 403 Development Kit.

- alimentator de reţea pentru modulul ML 403 Development Kit.

- cablu de conectare a modulului cu calculatorul pe portul serial.

- cablu de reţea pentru conectarea modulului la reţea (sau la server).

3. Consideraţii teoretice

Conform foii de catalog prezentate în anexă, sistemul de dezvoltare ML 403 Virtex 4-FX Evaluation Platform a fost construit în jurul circuitului FPGA XC4VFX12 produs de firma Xilinx. Circuitul conţine 12312 blocuri logice, într-o structură care mai conţine şi 32 blocuri Xtreme DSP (multiplicatoare şi sumatoare) şi 36 blocuri de memorie RAM de câte 18 Kbiţi (în total 648Kbiţi). Pe placă există şi o memorie FLASH de 512MB, memorie DDR SDRAM de 64 MB, precum şi capacităţi mai mici de memorii SRAM şi EEPROM. Sistemul mai conţine un display LCD cu două rânduri de câte 16 caractere alfanumerice, precum şi porturi VGA, Ethernet, RS232, JTAG, USB, PS/2 şi intrări/ieşiri audio. Placa mai conţine şi alte elemente de interfaţare cu utilizatorul: 5 butoane cu revenire care permit navigarea prin meniul afişat pe monitorul conectat la portul VGA sau pe afişajul LCD (săgeţile orientate în cele 4 direcţii şi butonul de selecţie), butonul cu revenire de RESET şi de reprogramare, sau CPU RESET, precum şi LED-uri care indică starea de normalitate sau prezenţa unor erori. Ceasul sistemului este fixat la 100 MHz. Foaia de catalog sumară a plăcii (două pagini) se găseşte în prima anexă. A doua anexă conţine documentul UG092 de la Xilinx, intitulat "Getting Started with the PowerPC and MicroBlaze Development Kit – Virtex-4 FX12 Edition". Acest document de 25 de pagini descrie programele demonstrative oferite de producător pe cardul de 512 MB livrat odată cu placa.

1

4. Modul de lucru

Platform din anexă,

identificând amplasarea subansamblelor descrise la punctul 3. Se studiază descrierea funcţională a modulului şi conectarea lui la portul serial în vederea programării. Se

studiază funcţionarea oscilatorului, modul de conectare la circuitul integrat FPGA a blocurilor componente din sistem.

4.1. Se studiază modulul ML403

Development

4.2. Se pregăteşte modulul ML403 Development Platform, se face

conectarea portului serial la calculator şi se configurează portul serial, aşa cum se indică în anexă. Se alimentează placa şi se testează comunicaţia pe portul serial, prin

mesajele primite la consolă şi prin starea LED-urilor de pe placă, aşa cum este descris în anexă.

4.3. Se conectează la portul VGA al modulului ML403 Development

Platform un monitor, iar la portul audio de ieşire (Line Out) un sistem de difuzoare. Se verifică prima aplicaţie din meniu. Se verifică toate celelalte aplicaţii, inclusiv conectarea la reţea prin portul Ethernet.

4.4. Sugeraţi alte aplicaţii posibile folosind acest sistem de dezvoltare şi

indicaţi pe scurt etapele de implementare a lor.

Anexe: (vezi paginile următoare)

2

ML403 Virtex-4 FX Evaluation Platform The Low-Cost, Embedded PowerPC Development Solution Evaluating, designing and
ML403 Virtex-4 FX
Evaluation Platform
The Low-Cost, Embedded PowerPC
Development Solution
Evaluating, designing and testing
complex embedded systems present
significant challenge with today's
shrinking budget and design cycles.
Xilinx provides the answer
with the ML403 Virtex ™ -4 FX
Evaluation Platform. Powered
by the XC4VFX12 device and
supported by industry-standard
peripherals, connectors and
interfaces, the ML403 Virtex-4 FX
Evaluation Platform offers a rich
The Ideal Platform for Your FPGA Embedded System Development
feature set that spans a wide range
Explore the Rich Feature Set of the ML403 Virtex-4 FX Evaluation Platform
of applications. Designed for
• Support for multiple clock sources and differential clock inputs
• Memory interfaces for DDR SDRAM, ZBT SRAM, and Flash
use with the Xilinx Embedded
• Multiple FPGA programming modes: Platform Flash, System ACE, Linear Flash, and PC4
Development Kit (EDK) and award
• Audio and video interfaces
winning Platform Studio Tool Suite,
• Multiple user interfaces: dual PS/2, IIC Bus, RS-232, USB, and Tri-Mode Ethernet
the ML403 FX Virtex-4 Evaluation
Optimize Your Design with Unique Built-In Silicon Features
Platform provides a comprehensive
• Embedded IBM PowerPC 405 RISC processor core
environment for developing
embedded designs based on the
• Auxiliary Processor Unit (APU) controller provides a high-bandwidth interface
between the PowerPC 405 core and co-processors to execute custom instructions
in the FPGA fabric
Virtex-4 FX FPGA.
Virtex-4 FX FPGAs feature
• Two fully integrated UNH-certified 10/100/1000 Ethernet MACs enable system
communication and management functions
up to two embedded PowerPC ™ 405
• ChipSync ™ source-synchronous technology embedded in every I/O ensures reliable
data capture
processor cores with an integrated
• Xesium ™ differential global clocks minimize skew and jitter for increased design margins
Auxiliary Processor Unit (APU)
Finish Faster Using Proven Reference Designs
controller to deliver breakthrough
• Reference designs and IP cores for numerous applications accelerate your design cycle
performance.
• A comprehensive suite of application notes guides you every step of the way

ML403 Virtex-4 FX Evaluation Platform Contents

• Xilinx Devices

- XC4VFX12-FF668-10C

- XC95144XL

- XCCACE (System ACE CF)

- XCF32P (Platform Flash)

• Clocks

- RS-232 Serial Port

- 3 USB Ports (2 Peripherals/1 Host)

- PC4 JTAG

- DB15 VGA Display

- RJ-45 Ethernet Port

- General-Purpose I/O (Buttons/LEDs)

-

100 MHz Oscillator

Additional Tools and Services

-

2 Clock Sockets

• Xilinx Integrated Software Environment (ISE)

• Memory

- 64 MB DDR SDRAM

- 1 MB ZBT SRAM

- 512 MB Compact Flash

- 8 MB Linear Flash

- 4 kb IIC EEPROM

• Display - 16 x 2 Character LCD

• Connectors and Interfaces

- 4 SMA Connectors (Differential Clocks)

- 2 PS/2 Connectors (Keyboard/Mouse)

- 2 Audio (In/Out, Microphone, Head Phone)

• Xilinx Embedded Development Kit (EDK)

• ChipScope Pro – Debug, analyze and verify your design in real time

• IP Center – Comprehensive suite of verified IP cores

• Education Services – Increase your skill set and reduce your time-to- knowledge

Take the Next Step Order your ML403 Virtex-4 FX Evaluation Platform today and get a head start on your Virtex-4 embedded design. For more information about the Virtex-4 FPGA family, visit www.xilinx.com/virtex4.

Ordering Information Part Number: HW-V4-ML403

t e x 4 . Ordering Information Part Number: HW-V4-ML403 Corporate Xilinx, Inc. 2100 Logic Drive

Corporate Xilinx, Inc. 2100 Logic Drive San Jose, CA 95124 Tel: 408-559-7778 Fax: 408-559-7114 Web: www.xilinx.com

Tel: 408-559-7778 Fax: 408-559-7114 Web: www.xilinx.com Europe Xilinx, Ltd. Citywest Business Campus Saggart, Co.

Europe Xilinx, Ltd. Citywest Business Campus Saggart, Co. Dublin Ireland Tel: +353-1-464-0311 Fax: +353-1-464-0324 Web: www.xilinx.com

Japan Xilinx, K. K. Shinjuku Square Tower 18F 6-22-1 Nishi-Shinjuku Shinjuku-ku, Tokyo 163-1118, Japan Tel: 81-3-5321-7711 Fax: 81-3-5321-7765 Web: www.xilinx.co.jp

Asia Pacific Xilinx, Asia Pacific No. 3 Changi Business Park Vista, #04-01 Singapore 486051 Tel: (65) 6544-8999 RCB no: 20-0312557 Web: www.xilinx.com

Tel: (65) 6544-8999 RCB no: 20-0312557 Web: www.xilinx.com The Programmable Logic Company S M Distributed By:

The Programmable Logic Company SM

Distributed By:

© 2005 Xilinx Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the proiperty of their respective owners.

Printed in U.S.A.

PN 0010860

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Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.

Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.

THE DESIGN IS PROVIDED “AS IS” WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.

The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail- safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.

© 2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

Getting Started with the PowerPC and MicroBlaze Development Kit - Virtex-4 FX12 Edition

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Revision History

The following table shows the revision history for this document.

 

Version

Revision

7/5/05

1.0

Initial Xilinx release.

02/28/06

1.1

Revised for upgrade to EDK 8.1i

Getting Started with the PowerPC and MicroBlaze Development Kit - Virtex-4 FX12 Edition

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Table of Contents

Preface: About This Guide

Guide Contents Additional Resources

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Conventions

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Online Document

 

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Getting Started with the PowerPC and MicroBlaze Development Kit - Virtex-4 FX12 Edition

Overview

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9

Quick Start

Information

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Kit Contents

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Development Kit Reference CD

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Software Installation

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12

Board ML403 Reference Systems on the CD

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. ML403 Embedded Processor Reference System

Installation Instructions

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ML403 Embedded Processor Reference System (PowerPC 405-based)

 

16

ML403 DCM Phase Shift Reference System (MicroBlaze-based)

16

ML403 Demonstrations in System ACE

17

Bootloader

. Wind River VxWorks Demonstration

. Virtex-4 Slide Show

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MontaVista Linux Demonstration

19

Web Server Demonstration for PowerPC 405 and MicroBlaze

20

DCM Phase Shift

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Mentor ATI Nucleus WebServ Demonstration

22

Development Kit Known Issues

25

Getting Started with the PowerPC and MicroBlaze Development Kit - Virtex-4 FX12 Edition

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Getting Started with the PowerPC and MicroBlaze Development Kit - Virtex-4 FX12 Edition

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About This Guide

Preface

The PowerPC™ and MicroBlaze™ Development Kit - Virtex™-4 FX12 Edition showcases various features of the ML403 Development Platform. This kit includes reference designs and demonstrations. This document describes how to use and run them.

Guide Contents

This manual contains one chapter:

“Getting Started with the PowerPC and MicroBlaze Development Kit - Virtex-4 FX12 Edition,” page 9

Additional Resources

To search the database of silicon and software questions and answers, or to create a technical support case in WebCase, see the Xilinx website at:

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

Convention

Meaning or Use

Example

Courier font

Messages, prompts, and program files that the system displays

speed grade: - 100

Courier bold

Literal commands that you enter in a syntactical statement

ngdbuild design_name

Helvetica bold

Commands that you select from a menu

File Open

Keyboard shortcuts

Ctrl+C

Getting Started with the PowerPC and MicroBlaze Development Kit - Virtex-4 FX12 Edition

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Preface: About This Guide

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Convention

 

Meaning or Use

Example

 

Variables in a syntax statement for which you must supply values

ngdbuild design_name

Italic font

References to other manuals

See the Development System Reference Guide for more information.

Emphasis in text

If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.

Square brackets

[

]

An optional entry or parameter. However, in bus specifications, such as bus[7:0], they are required.

ngdbuild [option_name] design_name

Braces

{

}

A list of items from which you must choose one or more

lowpwr ={on|off}

Vertical bar

|

Separates items in a list of choices

lowpwr ={on|off}

Vertical ellipsis

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IOB #1: Name = QOUT’

Repetitive material that has

IOB #2: Name = CLKIN’

 

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been omitted

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Horizontal ellipsis

 

Repetitive material that has been omitted

allow block block_name

loc1 loc2

locn;

Online Document

The following conventions are used in this document:

Convention

Meaning or Use

Example

 

Cross-reference link to a location in the current document

See the section “Additional Resources” for details.

Blue text

Refer to “Title Formats” in Chapter 1 for details.

Red text

Cross-reference link to a location in another document

See Figure 2-5 in the Virtex-4 User Guide.

Blue, underlined text

Hyperlink to a website (URL)

Go to http://www.xilinx.com for the latest speed files.

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Getting Started with the PowerPC and MicroBlaze Development Kit - Virtex-4 FX12 Edition

Overview

The PowerPC™ and MicroBlaze™ Development Kit - Virtex™-4 FX12 Edition is designed to help you use the ML403 Development Platform more efficiently. This getting started guide provides a detailed description of what is included in the kit along with instructions on how to use the resources included in this kit. The development kit comes with a number of pre-installed demonstrations and examples. This document describes how to use and run them.

The development kit includes reference systems and demonstrations. These are included on the Development Kit Reference CD as well as on the Compact Flash Card included in the development kit. Please read the remainder of the document for specific details on these resources.

The best way to get started with the development kit is by inserting the Development Kit Reference CD located in box 1 of your kit. The CD will guide you to the desired demo or reference system including instructions on how to set up the development platform and install software.

The reference systems included in this kit require the use of a computer installed with the following software:

Integrated Software Environment™ (ISE) 8.1i, including Service Pack 2

Xilinx Embedded Development Kit (EDK) 8.1i, including Service Pack 1

Note: These software configurations are required for the reference systems to function properly. Please ensure the proper versions prior to working with the reference systems. Detailed information about how to properly install your software is included in the Software Installation section later in this document.

For current information about the included development platform, visit the following Web page:

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Quick Start Information

The following section is provided to help you get up and running with the development kit quickly. It contains basic instructions and requirements to get started with the development kit without having to read the entire manual. This is recommended for users familiar with Xilinx products. If you are new to Xilinx products, it is recommended that you read the rest of this document as it contains more detailed information and instructions on the resources included in this development kit.

Step 1 - Install the ISE WebPack and Xilinx Platform Studio™ (XPS/EDK) software. You will find the XPS software in box 1 and the ISE WebPack software in box 2. Please make sure to install the necessary software as indicated below:

ISE 8.1i WebPack, including Service Pack 2

EDK 8.1i, including Service Pack 1

The software service packs are in the Development Kit Reference CD under the ML403_Dev_kit\software_service_packs directory. Detailed installation instructions are included later in this document.

Step 2 - Set up the development board and connect it to the host machine. This includes connecting the following:

Board power supply

Download cable - host to target

Serial cable - host to target

Cross-over ethernet cable - host to target

Detailed instructions of how to accomplish these tasks are found later in this document.

Step 3 - Choose the reference system or demo of choice. Demo designs are only located on the Compact Flash device and are as follows:

Position 1 - Virtex-4 Slide Show

Position 2 - Wind River VxWorks Demo

Position 3 - MontaVista Linux Demo

Position 4 - WebServer Demo - PowerPC

Position 5 - WebServer Demo - MicroBlaze

Position 6 - DCM Phase Shift Demo - MicroBlaze

Position 7 - Mentor ATI Nucleus WebServ Demo

For detailed instructions on how to use the Compact Flash Card with System ACE™, please see the ML40x Getting Started Guide Tutorial. Detailed instructions of how to accomplish these tasks are found later in this document.

In addition to the CF card, the Development Kit Reference CD contains an Installer to create the source files for the reference systems. The reference systems created by the Installer, which are also included on the CD, are:

PowerPC Reference System

MicroBlaze Reference Syatem

DCM Phase Shift Design for MicroBlaze

To use these designs, run the Installer which will install any or all of the included reference systems. Once installed, invoke Xilinx Platform Studio (XPS) from the Start menu and open the project file.

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Kit Contents

Detailed instructions for these designs and the Installer are included in the remaining sections of this document. Please refer to these sections for more information.

Kit Contents

The information below describes the contents of the development kit. The development kit contains all of the following items.

Box 1 Contents:

Virtex-4 FX12 ML403 board

Compact Flash Card - 512 MB

EDK/Xilinx Platform Studio Software

Development Kit Reference CD - includes reference systems, tutorials and documentation.

Box 2 Contents:

ISE WebPack Software

Power supply

Download cable (PCIV or USB)

Serial cable

Cross-over ethernet cable

Development Kit Reference CD

The development kit includes a resource CD that contains useful materials for expediting the creation of embedded designs using Xilinx platforms. An Installer utility has been included to simplify the installation of the reference systems on the host machine. The necessary directory structure and files will automatically be set up for each of the chosen references systems. The installation utility (setup.exe) is located at the top level of the CD (<cdrom>\setup.exe). The top level directories included on the CD are:

images – contains the web page images.

ML403_Dev_Kit – contains all the kit specific reference information. A detailed list of these items include:

demo – includes the VxWorks and Linux demos found on the CF card. This directory includes the executable files and the bitstreams necessary to run these demos.

documentation – includes this document and the reference system user guide.

reference_systems - contains the XPS source projects for the references systems (EDK_projects directory) as well as the software applications (sw directory) that run these references systems. Note: the Installer creates a directory under each reference system called ready_for_download. This directory contains the compiled bitstream file that can be quickly downloaded using iMPACT.

software_service_packs - contains the required service pack installs for XPS and ISE software packages. The next section details how to install these files.

tutorials - includes the PowerPC tutorial provided on the Xilinx web site.

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Board Setup

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Software Installation

The development kit includes the required design software to work with the reference systems. A full version of EDK and ISE WebPack are included. To use the reference systems included in this kit, both software packages are required to be installed. To properly install the software packages, please insert the installation CD and follow the installation instructions. To obtain an installation code, each software package must be registered. Information on how to accomplish this is included in the install.

Once the software package has been installed, it is necessary to add the latest service packs. These have been included on the Developmemt Kit Reference CD as well. Navigate into the software_service_packs directory on the CD. Each software package has a directory containing the required service pack. Nagivate into each drectory and double click on the setup.exe file. This will launch the service pack installer. Follow the installation directions to complete the process.

Board Setup

1. Position the ML403 board so the Virtex-4 and XILINX logos are oriented near the top edge of the board.

2. Make sure the power switch, located in the upper right corner of the board, is in the off position.

3. Locate the CF card slot (on the back side of the ML403 board), and carefully insert the System ACE CF card with its front label facing away from the board. Figure 1 shows the back side of the board with the CF card properly inserted.

Note: The CF card provided with your board might differ.

Caution! Be careful when inserting or removing the CF card from the slot. Do not force it.

UG092_01_010406
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Figure 1:

ML403 Prototype Platform with CompactFlash Card

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Board Setup

4. Connect the AC power cord to the power supply brick. Plug the power supply adapter cable into the ML403 board. Plug in the power supply to AC power.

5. Set the following switches:

Configuration Address and Mode DIP switch (6-position DIP switch) to 000111

Set the Configuration Source Selector switch (3-position slide switch) to SYS ACE

6. Connect a null modem serial cable between your PC and the ML403 board and open a serial terminal program:

Select Start Programs Accessories Communications HyperTerminal

In the Connection Description window, type 9600 in the Name box, then click OK

In the Connect To window, click Cancel

In the 9600-HyperTerminal window, select File Properties

- Select the Connect To tab

- Select COM1 in the Connect using box (see Figure 2)

- Click Configure

the Connect using box (see Figure 2 ) - Click Configure UG092_02_010406 Figure 2: HyperTerminal Setup

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Figure 2: HyperTerminal Setup and Properties

Use the pull-down menu to set the COM1 properties (see Figure 3) to the following:

- Bits per second = 9600

- Data bits = 8

- Parity = None

- Stop bits = 1

- Flow control = None

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ML403 Reference Systems on the CD

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Click OK OK to accept settings

on the CD R ♦ Click OK → OK to accept settings UG092_03_010406 Figure 3: COM1

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Figure 3: COM1 Properties Setup

7. Connect the VGA monitor to the board, if available.

8. Turn on the ML403 board’s main power switch, and press the System ACE RST button. When the FPGA has been programmed, the LEDs in the lower left corner should be:

Bus “Error 1” = off

FPGA INIT = green

FPGA DONE = green

System ACE “Err” = off

System ACE “Stat” = green

Note: When the CF card is ejected or not installed, the System ACE “Err” LED blinks.

ML403 Reference Systems on the CD

This development kit comes with three reference systems on the CD. This section of the document briefly describes each reference system and instructs on how to install the reference systems to the host machine using the Installer Utility. The included reference systems are listed below:

“ML403 Embedded Processor Reference System (MicroBlaze-based),” page 15

“ML403 Embedded Processor Reference System (PowerPC 405-based),” page 16

“ML403 DCM Phase Shift Reference System (MicroBlaze-based),” page 16

Installation Instructions

As mentioned previously, an Installation utility is supplied to simplify the installation of the reference system to the host machine. The procedure is as follows:

Run "setup.exe" which will take you through the install process via the InstallShield Wizard.

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ML403 Reference Systems on the CD

Choose which of the reference system or systems you want to install and the destination folder where you want the reference systems installed on the host machine. By default, the Installer will install all three reference systems. You can choose to not install a reference system.

At the end of the install, there is an option to View the accompanying documentation. If you choose not to view the documentation at this time, it will also be installed in the destination folder for future reference.

If at anytime you want to remove all of the installed files and folders, just run the Installer again and select the Remove button and click Next. All of the installed features will then be removed.

The reference systems are also included on the CD if you wish to copy them to your host machine manually. The location on the CD for each reference system is:

reference_systems/EDK_projects/ml403_emb_ref_mb (MicroBlaze-based)

reference_systems/EDK_projects/ml403_emb_ref_ppc (PowerPC 405-based)

reference_systems/EDK_projects/ml403_dcm_phase_shift (MicroBlaze-based)

Note: The sw directory, which holds all of the source files for the software applications, needs to be two directory levels above the directory where the reference system project file resides. This sw directory holds all of the source files for the three reference systems.

ML40 3 Embedded Processor Reference System (MicroBlaze-based)

Location on the host machine (after install)

reference_systems/EDK_projects/ml403_emb_ref_mb

Description

The ML403 Embedded Processor Reference System demonstrates the features of the ML403 Evaluation Platform product. It utilizes the MicroBlaze processor core, which is connected to numerous peripherals using the Processor Local Bus (PLB), the On-Chip Peripheral Bus (OPB), and the Device Control Register (DCR) Bus. This system contains a variety of peripherals, including General Purpose I/O (GPIO), UART, External Memory Controllers, and PLB Double Data Rate (DDR) SDRAM Controller. This reference system also includes various standalone software applications that demonstrate different features of the system.

The ready_for_download directory under the project root directory contains the files necessary for a quick and easy download to the development board. The download.bit file downloads the system configuration to the board. This bitstream also contains a bootloop program that effectively idles the processor. This file can be quickly downloaded to the board using iMPACT. The .elf files for all the software applications also reside in the ready_for_download directory. These can be downloaded and run on the development board using XMD.

For more information on the ML403 Embedded Processor Reference System, please see User Guide, UG082, ML40x EDK Processor Reference Design User Guide. This guide can be found at the following location on the CD:

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documentation/ug082.pdf

ML40 3 Embedded Processor Reference System (PowerPC 405-based)

Location on the host machine (after install)

reference_systems/EDK_projects/ml403_emb_ref_ppc

Description

The ML403 Embedded Processor Reference System demonstrates the features of the ML403 Evaluation Platform product. It utilizes the PowerPC 405 processor core, which is connected to numerous peripherals using the Processor Local Bus (PLB), the On-Chip Peripheral Bus (OPB), and the Device Control Register (DCR) Bus. This system contains a variety of peripherals, including General Purpose I/O (GPIO), UART, External Memory Controllers, and PLB Double Data Rate (DDR) SDRAM Controller. This reference system also includes various standalone software applications that demonstrate different features of the system.

The ready_for_download directory under the project root directory contains the files necessary for a quick and easy download to the development board. The download.bit file downloads the system configuration to the board. This bitstream also contains a bootloop program that effectively idles the processor. This file can be quickly downloaded to the board using iMPACT. The .elf files for all the software applications also reside in the ready_for_download directory. These can be downloaded and run on the development board using XMD.

For more information on the ML403 Embedded Processor Reference System, please see User Guide, UG082, ML40x EDK Processor Reference Design User Guide. This guide can be found at the following location on the CD:

documentation/ug082.pdf

ML40 3 DCM Phase Shift Reference System (MicroBlaze-based)

Location on the host machine (after install)

reference_systems/EDK_projects/ml403_dcm_phase_shift

Description

The ML403 DCM Phase Shift Reference System determines the optimal phase shift for a DDR memory feedback clock on the ML403 development board. This is to ensure that the DDR memory controller writes/reads data at the optimal time. This is accomplished with the use of a Digital Clock Manager (DCM), which has a built in phase shifter component. This reference system uses the GPIO output to control the output phase shift of the DCM. The GPIO output is controlled by a software application that is run on a MicroBlaze microprocessor. This application is run out of an internal FPGA BRAM and it traverses the entire range of possible phase shifts (-255 to 255) that correspond to the complete 360 degree phase shift cycle. At each phase shift value, the application performs memory tests and records if the tests passed or failed. The passing ranges are reported by printing them to a hyperterminal through a UART. The optimal phase shift values are simply calculated by choosing the middle values for the passing ranges.

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ML403 Demonstrations in System ACE CF

The ready_for_download directory under the project root directory contains the files necessary for a quick and easy download to the development board. The download.bit file downloads both the system and the software application to the board.

For more information on the DCM Phase Shift Reference System, please see User Guide, UG178, User Guide to Determine the Optimal DCM Phase Shift for the DDR Feedback Clock. This guide can be found at the following location on the CD:

documentation/ug178.pdf

ML403 Demonstrations in System ACE CF

Bootloader

Location

System ACE Configuration Address 0.

Description

The ML403 Bootloader demonstration displays a menu of demonstration designs that can be loaded by using the System ACE controller’s reconfiguration feature. The menu is displayed on the serial terminal, LCD, and VGA.

To choose a demonstration, use the North-East-South-West navigation buttons on the board, then press the center button to start the demonstration. Alternatively, you can select a demonstration by entering its number into the serial terminal. These steps will load the demonstrations:

“Virtex-4 Slide Show,” page 17

“Wind River VxWorks Demonstration,” page 18

“MontaVista Linux Demonstration,” page 19

“Web Server Demonstration for PowerPC 405 and MicroBlaze,” page 20

“DCM Phase Shift Demonstration,” page 22

“Mentor ATI Nucleus WebServ Demonstration”, page 22

To return to the ML403 bootloader at anytime, press the System ACE RST button. The bootloader runs only if the leftmost configuration address DIP switches are set to 000 and the Configuration Source Selector switch (3-position slide switch) is set to SYS ACE.

Virtex-4 Slide Show

Location

System ACE Configuration Address 1.

From the bootloader menu, select option 1 to start the Virtex-4 Slide Show demonstration.

Description

The Slide Show demonstration displays a sequence of picture files stored on the CF card accompanied by audio playback of a music file stored on the CF card. Pressing the East/West buttons on the board manually switches to the previous/next slide. The North/South buttons on the board change the volume. The center button toggles between

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pausing and continuing the slide show. This demonstration requires a VGA monitor connected to the VGA port and a headphone or external speaker connected to the audio jacks.

In this program, the processor reads the CF file system through the System ACE MPU port and loads the audio/video data into DDR SDRAM. The processor then controls the flow of data to the VGA controller and audio controller connected to the internal CoreConnect™ bus.

Setup

The picture files must be located in the root directory and named image<XX>.bmp where <XX> is a numerical sequence starting from 01 and counting up. The program reads the picture files through the System ACE MPU interface starting from image01.bmp then counts upward. A maximum of 16 images can be read. The BMP files must be sized as 640x480 pixels with 24-bit color. The sound file must be named sound.wav and encoded as a 44.1 KHz, 16-bit stereo wave file (CD format). The sound file cannot be greater than 32 MB in size.

Note: When adding additional images or larger sound files, it might be necessary to utilize a higher capacity System ACE CF card than the one shipped with the ML40 3 board.

How to Change or Customize the Slide Show

Try to add your own slides and music. (For example, in Microsoft PowerPoint, you can export a presentation to HTML for a 640x480 screen. You can then convert the JPG or GIF slides to BMP format using Microsoft Photo Editor which is installed on many PCs. Rename the BMP files to image<XX>.bmp and copy to the System ACE CF card. Now you can run your own customized slide show. For audio, try to extract a song from a CD into a WAV file and copy it into the System ACE CF card named as sound.wav.

Wind River VxWorks Demonstration

Location

System ACE Configuration Address 2.

From the bootloader menu, select option 2 to start the VxWorks demonstration.

Note: If the ML403 development board is not connected to a network with a DHCP server, there will be a delay (~2 minutes) before the DHCP request times out and the target shell is displayed on the serial output.

Description

This demonstration shows VxWorks running on the PowerPC 405 processor. This VxWorks demonstration includes a number of supported features, including demonstrations that use the VGA monitor and the buttons and LEDs on the ML403 board. The supported features of this demonstration are listed below.

Supported Features

Target shell

Target shell is included in the image and executed automatically once the OS is booted.

Stand-alone symbol table

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ML403 Demonstrations in System ACE CF

Stand-alone symbol table is enabled so commands like help or any function defined in the image is executable interactively in the target shell.

DHCP client

DHCP client is included in the image to automatically get an IP from a DHCP server. You may view the dynamically assigned IP and other network information by running ifShow in the target shell.

Telnet server

It is possible to telnet and ping the target from the network once the IP address information is available. View the IP address by running ifShow in the target shell.

VGA Demo

In the target shell, execute vga_demo and follow the printed instruction to print a vertical bar pattern on a monitor connected to the VGA port of the board.

GPIO driven LCD/Button/LED demo

Execute lcd_button_led_demo in the target shell. A greeting message GPIO driven LCD/Button/LED will be printed on the character LCD.

Press any North/East/South/West button. The LED beside the pressed button should blink and the LCD should print a message like North button pressed!.

Press the Center button to terminate the demonstration. The LCD and the terminal console will display a Bye-bye message.

MontaVista Linux Demonstration

Location

System ACE configuration Address 3.

From the bootloader menu, select option 3 to start the Linux demonstration.

Description

This demonstration shows MontaVista Linux running on the PowerPC 405 processor. Linux includes support for the peripherals, such as PS/2 mouse and keyboard, VGA (x-windows), 10/100 Ethernet, UART, and file system mounted on the CF card using the System ACE CF controller. Linux console input/out is available using the UART. On the VGA output, a web browser is displayed. The PS/2 mouse and keyboard can be used to interact with the X Window display. The user names and passwords are:

ML403: username = root, password = 403ml (root account)

username = linux, password = ml403 (user account)

Note: Remember to logoff and shutdown using the GUI shutdown button shutdown -h now Linux command before turning off or resetting the board. This ensures the Linux file system is shut down correctly. The message system halted indicates the shutdown process has completed.

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Web Server Demonstration for PowerPC 405 and MicroBlaze

Location

PowerPC 405 System: System ACE Configuration Address 4.

MicroBlaze System: System ACE Configuration Address 5.

From the bootloader menu, select option 4 to start the PowerPC 405 Web Server demonstration. Select option 5 to start the MicroBlaze Web Server demonstration.

Description

There are two versions of this demonstration. One version shows the webserver demonstration running on the PowerPC 405 processor. The second version uses the MicroBlaze processor to run the webserver demonstration. This demonstration is an Ethernet-controlled GPIO interface where the ML403 board acts as a Web server. A remote host, such as a PC running a Web browser, can communicate with the ML403 board using the Ethernet to read the value of the ML403 board’s DIP switches or to set the LEDs on the board. Refreshing or reloading the remote PC's Web browser causes the background color to change and the current DIP switch values to be re-read. By default, the IP address of the ML403 board is 1.2.3.4, but it can be changed by recompiling the software.

Setup

1. Connect an Ethernet cable (straight or crossover) from the host PC to the ML403 board.

Note: The Ethernet PHY chip on the ML403 board has an auto-crossover feature.

2. Configure the remote PC host's IP address to 1.2.3.9 (Subnet mask can be 255.0.0.0).

Note: Record the previous network settings so they will be easier to restore after the lab. The screen shots and icon names might be slightly different depending on your PC's operating system version.

Right click My Network Places on the PC and select Properties

Right click Local Area Connection and select Properties

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ML403 Demonstrations in System ACE CF

Select Internet Protocol (TCP/IP) and click Properties (see Figure 4)

Protocol (TCP/IP) and click Properties (see Figure 4 ) UG092_06_010406 Figure 4: Local Area Connection Properties

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Figure 4: Local Area Connection Properties Setup (ML403)

Check Use the following IP address: (see Figure 5)

Enter this information: IP address = 1.2.3.9 and Subnet mask = 255.0.0.0. Click OK, then click OK again

Subnet mask = 255.0.0.0 . Click OK , then click OK again UG092_07_010406 Figure 5: IP

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Figure 5: IP Settings (ML403)

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3. Make sure the connection is running at 10 or 100 Mb/s and the ML403 board’s link lights are on. The ML403 board’s link lights are located in the upper left corner of the board. The link LEDs labeled 10, 100, and 1000 indicate that the link is established at that speed.

You might need to force your PC to link in 10 or 100 Mb/s (duplex) mode. If so, then:

Right-click Local Area Connection Properties Configure Advanced tab Speed

4. On the remote PC host, open a Web browser connection to http://1.2.3.4:8080, and follow the instructions on the loaded Web page.

You might need to turn off your browser's proxy (use direct Internet connection mode) especially if there are multiple networking devices on the PC.

On the remote PC host, ping 1.2.3.4 to confirm that the network connection is alive.

5. Restore the PC's network settings when finished.

DCM Phase Shift Demonstration

Location

System ACE Configuration Address 6.

From the bootloader menu, select option 6 to start the DCM Phase Shift Demonstration.

Description

The DCM Phase Shift Demonstration is created from the“ML403 DCM Phase Shift Reference System (MicroBlaze-based)”. This demonstration runs the software application that is included with that reference system. The purpose of this demonstration is to determine the optimal phase shift for a DDR memory feedback clock on the ML403 development board. It utilizes the MicroBlaze microprocessor to run memory tests for the entire range of possible phase shifts. The ranges that pass the memory tests are recorded and printed out to the hyperterminal through the UART. The optimal phase shift values are calculated by choosing the middle values for the passing ranges. These optimal values are also printed out to the hyperterminal.

Mentor ATI Nucleus WebServ Demonstration

Location

System ACE Configuration Address 7.

From the bootloader menu, selection option 7 to start the Nucleus WebServe Demonstration.

Description

The Nucleus WebServ demonstration shows ATI Nucleus running on the PowerPC 405 processor. The ML403 board acts as the Web server. A remote host, such as a PC running a Web browser, can communicate with the ML403 board over the Ethernet. Several different web pages highlight the capabilities of the Nucleus operating system. This is a

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point-to-point Ethernet set-up where you assign the IP address and subnet mask for the ML403 board.

Setup

1. Connect a serial cable between the target and the host PC using the following table for correct cable type and connector locations as shown in Table 1:

Table 1: Cable type and connector locations

Type

Description

Serial cable

Null modem

Target connection

UART host

Host connection

Any available COM port

2. Start a terminal program (i.e. HyperTerminal for Windows) using the correct COM port used above on the host PC with the following framing parameters as shown in Table 2:

Table 2: Framing parameters

Parameter

Setting

Baud rate

9600

Data bits

8

Stop bits

1

Parity

None

Flow control

None

Ethernet

1. Connect the RJ45 network cable to the Ethernet port labeled “Ethernet” of the development board.

2. Make sure the connection is running at 10 or 100 Mb/s and the ML403 board’s link lights are on. The ML403 board’s link lights are located in the upper left corner of the board. The link LEDs labeled 10, 100, and 1000 indicate that the link is established at that speed.

You might need to force your PC to link in 10 or 100 Mb/s (duplex) mode. If so, then:

Right-click Local Area Connection Properties Configure Advanced tab Speed

3. Restore the PC's network settings when finished.

Configuring Nucleus WebServe Demo

1. Power On the board and you should see the demo menu on the terminal program, as shown in Figure 6

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ML403 Demonstrations in System ACE CF R UG092_0 8 _020606 Figure 6: HyperTerminal showing Demo Menu

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Figure 6: HyperTerminal showing Demo Menu selections

2. Press 7 on the keyboard and the Nucleus WebServ will boot up.

3. Enter the IP address and the subnet address for the target board. At the end of the input, review the data and if correct press y on the terminal. If you want to modify the data press n and re-enter the data.

Note: This demo requires that the user input an IP address. The elements of the IP address are separated by a period (dot separator). When entering the desired IP address, the user will also need to include or type the period to move to the next field.

4. The Nucleus WebServ Demo is now ready and the URL (<target IP>) should be displayed on both the terminal program and the LCD display.

5. Open up a browser on the host system and type the following URL to access the target board Nucleus WebServ Demo:

http://< target IP >

6. The Nucleus WebServ Demo should appear as in Figure 7.

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Development Kit Known Issues

R Development Kit Known Issues UG092_09_020606 Figure 7: Nucleus WebServ Demo on Web browser Development Kit

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Figure 7: Nucleus WebServ Demo on Web browser

Development Kit Known Issues

USB printer demonstration supports the Epson USB printer

At the time of this release, only the Epson USB printer is supported by the USB printer demonstration design included in the kit.

Potential warnings when running the webserver demonstration

When running the webserver demonstration on the development board in the MicroBlaze system, the following warning may appear: send: no such socket. The warning does not affect the operation of the webserver demonstration.

When running the webserver demonstration on the development board in MicroBlaze or PowerPC versions, you may get a File not found warning. The warning does not affect the design in any way.

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