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6, JUNE 2000 645

Principles of Substrate Crosstalk Generation in

CMOS Circuits
J. Briaire and K. S. Krisch, Member, IEEE

Abstract—Substrate noise injection is evaluated for a 0.25- m

CMOS technology, to determine the mechanisms that contribute
to substrate crosstalk. At the transistor level, we find that impact
ionization current and capacitive coupling from the junctions are
the most significant contributors to substrate current injection. An
Fig. 1. Substrate crosstalk is due to electrical fluctuations which (A) are
investigation of substrate fluctuations at a circuit level included
generated and locally couple into the substrate, (B) propagate through the
switching transients, capacitive damping, and separate substrate substrate and (C) are received by a sensitive device or circuit.
biasing. This investigation revealed that voltage transients on
power-supply lines can be the dominant source of substrate
fluctuations. Finally, a statistical analysis of signal cancellation couple to the source, drain, and well junctions of MOSFET’s
in an integrated circuit was performed. The results indicate that and to bipolar collectors.
more cancellation will take place for the high-frequency noise To date, most published work on substrate crosstalk has
components than for the average and low-frequency components.
concentrated on propagation of noise through the substrate.
As a consequence, the dc and low-frequency components of the
transient that results from an individual switching event can not Lumped-element models of the substrate impedance have been
be neglected even if they are a relatively small fraction of the developed and compared with measurements up to 40 GHz
single transient. [1], [2]. Other works have compared the substrate isolation of
Index Terms—Crosstalk, noise, semiconductor device modeling. SOI, junction-isolated wells, guard rings, and normal silicon
substrates through measurements and simulations [3], [4].
There is also a substantial body of work on efficient techniques
I. INTRODUCTION for numerically simulating substrate coupling [5], [6]. The
NALOG circuits are increasingly being integrated with large injection of noise into the substrate has received less attention.
digital circuits to form high-performance mixed-signal chips. Some aspects of it have been described, such as the influence
This aggressive integration places new demands on on-chip of bond wire inductance [7] and efficient schemes to evaluate
electrical isolation. Noise due to switching of digital circuitry the injection of a complete circuit [8], but a general treatment
can couple to the sensitive analog circuits and degrade overall that considers the importance of different injection sources has
performance. One significant path for this noise coupling is been lacking.
through the common silicon substrate. In order to correctly In this paper, we focus on the mechanisms of substrate noise
model and predict substrate crosstalk, and to develop tech- injection, and investigate local generation of substrate pertur-
niques to minimize it, a detailed understanding is required of bations by direct injection into the substrate from a MOSFET.
how the coupling occurs. This analysis is then applied to the simple circuit situation of an
Substrate crosstalk can be broken down into three parts, as inverter. Next we will discuss indirect fluctuations that result
illustrated schematically in Fig. 1. First, unwanted fluctuations from coupling of integrated-circuit parasitics into the substrate.
are injected into local substrate nodes [Fig. 1(A)]. Once the sub- Finally, the behavior of noise injected from an ensemble
strate fluctuation is generated, it then has to propagate through of switching circuits will be examined. To keep this work
the substrate [Fig. 1(B)]. The key parameter for this transmis- focused on generation, we treat our substrates as single-node
sion is the impedance of the substrate path, as compared to the equipotentials, such that the effects of substrate impedance,
impedances of the injection and reception points, and of the transmission, and attenuation can be ignored.
grounded tub ties. Finally, the substrate fluctuations are received
at a sensitive node [Fig. 1(C)], where they modify device charac- II. INJECTION MECHANISMS
teristics. Perturbations in the substrate voltage can modify MOS To assess the various mechanisms by which individual
device behavior via the body effect, and also can capacitively MOSFET’s can inject current into the substrate, we measured
and simulated CMOS devices from an experimental 0.25- m,
3.3-V technology, fabricated on a -epi/ -Si substrate. In
Manuscript received September 25, 1999; revised January 23, 2000. This this section, we will describe and quantify the different device
paper was recommended by Associate Editor E. Charbon.
J. Briaire is with Eindhoven University of Technology, Department of Elec-
injection mechanisms.
trical Engineering, Mixed-signal Microelectronics Group, 5600 MB Eindhoven,
The Netherlands. A. Impact Ionization Current
K. S. Krisch is with Lucent Technologies Microelectronics, Murray Hill, NJ
07974 USA. When a MOS transistor is biased in the saturation regime, a
Publisher Item Identifier S 0278-0070(00)05341-0. high electric field develops in the depleted region of the channel
0278–0070/00$10.00 © 2000 IEEE

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Fig. 2. N-channel drain and substrate currents for channel width W = 15 m Fig. 3. P-channel drain and substrate currents for channel width W = 15 m
and channel length L as shown. V = 3:5 V for all measurements. The bias and channel length L as shown. V = 3:5 V for all measurements. For low
and geometry dependence indicates that impact ionization is the primary cause source-gate voltages GIDL is the dominant substrate contribution, for higher
of the observed substrate current. voltages impact ionization current dominates.

near the drain. Some fraction of the carriers in this region will
gain enough energy to become “hot” [9], [10]. When these hot
carriers do eventually scatter, they can dissipate their excess en-
ergy by creating additional, energetic electron-hole pairs, in a
process known as impact ionization. For an NMOS transistor,
the holes created by impact ionization are swept to the substrate,
such that the transistor has current flowing from the drain into
the substrate. In studies addressing the damaging effects of hot
electrons, this substrate current is often examined, because it is
an easily measurable quantity that is correlated to the hot car-
riers of interest. In contrast, the focus of this work is the sub-
strate current itself, since it can lead to fluctuations in bulk po-
tential as it flows through the resistive substrate.
Fig. 2 shows the drain and substrate currents measured on
NMOS transistors with three different channel lengths, as a Fig. 4. Normalized substrate currents for n-channel and p-channel MOS
transistors. The relative n-channel impact ionization current is seen to be at
function of the gate-source voltage . The observed substrate least a factor of ten higher than for the p-channel devices.
current is due to impact ionization over this entire range of bias
conditions. Fig. 3 shows the same currents measured on PMOS
pact-ionization coefficient , which depends on the local elec-
transistors. For these -channel devices, gate-induced drain
tric field
leakage (GIDL) also causes significant substrate current at low
values of . (1)
The proportionality between and is shown in Fig. 4,
for both NMOS and PMOS transistors. The relative level of where and are positive parameters [11]. For long-channel
impact ionization current is seen to exponentially depend on devices, it is then straightforward to relate this electric field to
. At low gate voltages, where the transistors are in deep the applied terminal voltages [8], [12]. However, for smaller
saturation, the impact ionization current is independent of geometries, the channel electric fields in saturation are affected
channel length. At higher gate voltages, the behavior of dif- by velocity saturation, such that carrier behavior depends on the
ferent channel-length devices diverges, reflecting differences in nonlocal electric field [13]. Thus, recent work in this area relies
how the channel electric field evolves as a function of voltage. on Monte Carlo simulations [14], and no robust compact models
It is clear that the relative impact ionization current in our exist to describe impact-ionization currents in submicrometer
PMOSFET’s is about an order of magnitude less than in the MOSFET’s [15].
NMOSFET’s. This lower substrate current, in combination We require a predictive description of impact-ionization
with capacitive shielding from the -well junction, makes substrate current to allow quantitative comparisons to other
the PMOSFET contribution to impact-ionization current in substrate injection mechanisms within the framework of a
the common substrate negligible. Thus, we will model the circuit simulator. As expected from the previous discussion,
impact-ionization component of substrate crosstalk using only existing long-channel substrate current models were not
the -channel substrate current. successful in describing our measured short-channel results.
Simple models have been used to describe the relationship Instead, we fit our measured results to an interpolated empirical
between the drain current and substrate current with an im- function, based on the long channel model, over the entire

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Fig. 6. The switching current of an inverter as a function of the input voltage

Fig. 5. The measured relative impact ionization current of a W=L = 15=0:32
n-channel MOSFET is fitted with an interpolation function to allow prediction and the resulting impact ionization substrate current. The dimensions of the
transistors are W =L = 3:6=0:32 and W =L = 2:66=0:32.
of the impact ionization current of the transistor under arbitrary biasing
conditions in a circuit.

of device operating frequencies. Thus, capacitive coupling to the

range of and . The function was created by changing substrate can be modeled as a current injection mechanism.
the constant parameters in the long channel model to depend
weakly on the bias voltages, thereby introducing a number C. Gate Induced Drain Leakage (GIDL)
of fitting parameters. As shown in Fig. 5, this empirical fit Gate-induced drain leakage occurs when high fields across
successfully captures the bias dependence of for a the drain/gate overlap region form a deep-depletion layer in
given channel-length device. Using the ADVICE circuit sim- the drain. When the voltage drop across this layer is sufficient,
ulator [16], along with MOSFET model parameters extracted band-to-band tunneling of valence electrons results in the cre-
for this 0.25- m process, the drain currents in a circuit can be ation of holes, which are then swept into the substrate [18].
accurately simulated. We then applied our empirical expression GIDL depends exponentially on the gate-drain voltage, and also
to the simulated drain-current characteristics to calculate the depends significantly on the details of drain doping and gate
impact-ionization substrate current from that circuit, for a overlap. The characteristic behavior of GIDL could only be ob-
given bias. For example, when an inverter switches, as shown served in our NMOS devices when they were biased at negative
in Fig. 6, the substrate current peaks at a few microamperes as gate-source voltages (not shown); under normal bias conditions,
the inverter input switches from low to high. In this treatment, no gate-induced drain leakage was observed (Fig. 2). In general,
we assume that impact ionization current is a quasi-static, the substrate current level at low gate biases is negligible com-
frequency-independent phenomenon, which should be valid up pared to the impact-ionization current at higher gate biases, and
to frequencies on order of the channel transit time. thus GIDL will have no effect on the overall current injected
into the substrate during NMOS device switching.
B. Capacitive Coupling to the Substrate In our PMOS devices, the characteristic behavior of GIDL
is observed from to V, and it dominates
Another mechanism by which MOSFET’s inject current into
the drain and well currents in this low gate-voltage bias regime
the substrate is capacitive coupling. Voltage fluctuations on the
(Fig. 3). However, the -channel GIDL current in this range
source or drain can couple to the bulk through the source/bulk
is still small relative to the impact ionization current at higher
and drain/bulk junction capacitances. Additionally, the gate
gate voltages, and thus makes a negligible contribution to the
electrode is coupled to the substrate through the gate oxide
total substrate current during switching of the gate voltage. So,
and channel capacitances. We evaluated the influence of the
while the off-state current flow due to PMOS gate-induced drain
capacitive coupling to the substrate with the ADVICE simu-
leakage may increase the power dissipation, it will not lead to
lator. The ASIM3 MOS compact model [17], which is based on
significant substrate crosstalk. Overall, for the 0.25- m devices
charge conservation and calibrated to this 0.25- m technology,
studied here, GIDL substrate current does not have an impact
was used to capture the channel-substrate capacitance. The
on substrate crosstalk, and we do not consider it further.
area- and perimeter-dependent junction capacitances, along
with their voltage dependencies are explicitly included in the
ASIM3 model, and are calibrated to measurements on large D. Photon-Induced Current (PIC)
test structures. In addition to impact ionization, another way that channel hot
For our submicrometer devices, we find that capacitive sub- electrons can release their excess energy is by emission of a
strate coupling is dominated by the area component of the junc- photon [19]. When these photons are reabsorbed by the lattice,
tion capacitances, which are on the order of tens of fF. It is im- electron–hole pair creation can occur. The photons can travel
portant to note that the dc impedance from the bulk to the tub ties significant distances before being absorbed, even through sub-
(typically on order of hundreds of /tub tie) is low when com- strates that would normally block direct currents [20]. It is im-
pared to the impedance from these capacitances over the range portant to note that any locally generated minority carriers can

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be efficiently collected into sensitive, high-impedance nodes

that would normally be capacitively isolated.
Since the source of the photons is hot electrons, PIC will de-
pend on bias and device geometry in the same way as impact
ionization does, but will be observed at distances far beyond the
minority-carrier recombination length. We measured the cur-
rents of an NMOS transistor with a large ratio of
and a bias condition of V in a 3.3 V process, to gen-
erate as large a substrate current as possible. The substrate was
-type, and we used -wells as minority-carrier pick-up points,
at distances of 200 m and 400 m away. The resulting drain,
substrate, and -well currents are shown in Fig. 7. The sub-
strate current shows a characteristic impact-ionization bias de-
pendence, which is mirrored in the well current 200 m away. Fig. 7. Measured currents of an 80=0:6 NMOS device biased at a drain voltage
The current measured at 400 m was limited by the resolution of V = 4:0 V. A significant drain current and impact-ionization substrate
of the test equipment, and does not reflect any pick-up from the current is measured. A n =p-substrate diode 200 m from the device picks up
minority current in proportion to the substrate current, while at a distance of 400
MOSFET. m from the device, the pick up current is limited by the 20-fA measurement
In one report of measurements similar to ours, PIC was ob- floor.
served, with an effective photon decay length of 780 m, as
compared to the minority carrier decay length of 31 m [21]. If
similar decay lengths and collection efficiencies are applicable
to our measurements, then the current measured at 200 m can
be attributed to substrate minority carriers, perhaps generated by
secondary impact ionization. If there is any photon-induced cur-
rent at our 400- m pick up, it must be less than the 20-fA mea-
surement floor. Scaling appropriately for a 300- A impact ion-
ization current, any PIC in our measurement is at least 100 times
lower than the PIC reported in [21]. We also repeated our mea-
surement for a large -channel device, and again did not observe
any evidence of PIC. The difference between our results and
those in [21] may be due to 1) the fact that they used -substrates
while ours were -type, 2) a difference in the areas of the diffu-
sions used for pick-up, or 3) technology-related differences in
the generation or transmission of photons. Whatever the cause, Fig. 8. The measured reverse-bias leakage current of an n-well/p-substrate
diode, as a function of the diode voltage. This reversed biased diode has
a minimum effective resistance of 1 T
(line), in parallel with the diode
our measurements indicate that for this 0.25- m technology,
photon-induced current does not result in any long-range cou- capacitance. The well area is approximately 2:2 10 m .
pling, and will, therefore, not play a role in substrate crosstalk.


E. Diode Leakage Current Because impact ionization and capacitive coupling both de-
pend on device biasing and switching dynamics, substrate injec-
The MOSFET source and drain junctions are reverse-biased tion can only be realistically evaluated in the context of a circuit.
diodes, so in addition to the capacitive coupling that we have We will consider the relative importance of these two substrate
already discussed, current can flow into the substrate from gen- injection mechanisms for an inverter under different frequen-
eration in the depletion layer. Such currents also flow across the cies and loading, and in different parasitic environments. In all
-well/ -substrate junction, which can cover a significant frac- of the following simulations, -channel impact ionization cur-
tion of the total die. The reverse diode current depends on the rent is not included, as its magnitude was shown in the previous
processing details, and is very low in our technology. For ex- section to be negligible compared to -channel impact ioniza-
ample, as can be seen in Fig. 8, the effective parallel resistance tion current.
of a m , reverse-biased -well/ -tub junction is 1 T
or greater, at the voltages of interest. Thus, fluctuations on one A. Substrate Current due to an Ideal Inverter
side of the diode will not strongly couple to the other side via re- We first consider an ideal inverter, without any parasitic el-
verse leakage current. Substantial current could, however, flow ements. In this situation, the NFET bulk node (i.e., the sub-
into the substrate if any of the junctions becomes forward bi- strate) is tied directly to ground, and the PFET bulk node (i.e.,
ased. Such forward-biased transients depend on the circuit de- the -well) is tied directly to . In this idealized situation,
sign and operation, and must be prevented by suitable design the PFET makes no contribution to the substrate current, since
approaches. the zero-impedence bulk connection to shunts away all

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Fig. 9. Simulated substrate current due to impact ionization (solid) and due Fig. 11. Simulated substrate current due to impact ionization (solid) and
to capacitive coupling (dashed) during switching of a single, unloaded CMOS due to capacitive coupling (dashed) during switching of a single inverter.
inverter. The input excitation is a 10-MHz sine wave, as shown in the inset, and The input excitation is a square wave with a 0.2-ns rise time, as shown in
the output voltage is dashed. The device sizes are W =L = 3:6=0:32 and the inset. The output voltage is also shown (dashed). The device sizes are
W =L = 2:66=0:32. W =L = 3:6 m=0:32 m and W =L = 2:66 m=0:32 m, and
100-fF load capacitors are connected from the inverter output to V and from
the inverter output to V .

Fig. 10. The simulated rms substrate current in a single inverter, as a function
of input frequency. The input excitation and device sizes are as shown in Fig. 9. Fig. 12. The simulated rms substrate current in a single inverter, as a function
The rms inverter switching current, i.e., the transient current that flows from of the load capacitance. The input excitation and device sizes are as shown
V to V during switching, is plotted for comparison. The average currents in Fig. 11. Substrate current is dominated by capacitive coupling through the
are also shown, illustrating the net inverter and net substrate current flow during junctions over the range of loads investigated. The rms inverter switching current
a switching cycle. and average currents are also plotted for comparison.

bulk-current. Fig. 9 shows the NFET substrate current due to currents are about an order of magnitude smaller than capaci-
each mechanism as a function of time, for an unloaded inverter tive currents, which are in turn an order of magnitude smaller
driven by a 10-MHz sine-wave input. The resulting impact-ion- than the switching current through the inverter.
ization substrate current is always greater than or equal to zero,
while the capacitive current has larger peak-to-peak fluctua- B. The Influence of Circuit- and Substrate Parasitics
tions, but an average value of zero. We summarize these results So far, we have only described substrate coupling due to cur-
in terms of the root-mean-square (rms) and the average current rent injection from active devices in an ideal inverter. In prac-
over a switching cycle. In Fig. 10, we compare the currents from tice, these injected currents will be shunted to and ground
the two injection mechanisms as a function of input signal fre- through resistive wells and tub-ties, setting up a potential distri-
quency. For low-frequency excitations, impact ionization is seen bution throughout the substrate. It is these voltage fluctuations
to cause the larger rms current. The capacitive coupling current, in the substrate, and not the injected current itself, which couple
which is linearly proportional to frequency, begins to dominate to the sensitive analog transistors and cause crosstalk. Conse-
around 10 MHz. quently, we now focus on substrate voltage, and discuss the role
Similarly, we also simulated substrate injection from an in- that different integrated-circuit parasitics in the injecting circuit
verter as a function of the output load. In this case we applied a play in substrate voltage fluctuations. Both the NFET and PFET
square wave to the input with rise and fall times of about 0.2 ns. bulk currents are included in these simulations, as the PFET cur-
The time response of the substrate currents, for a 100-fF load, is rent can couple to the substrate via the -well to substrate ca-
shown in Fig. 11. The rms and average values of the currents as pacitance.
a function of the load are given in Fig. 12. It is clear from these 1) Substrate- Impedance and the Bond Wire Impedance:
simulations that, for typical internal loads, impact ionization A schematic of the parasitic circuit environment for a single

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Fig. 13. Circuit model of a single inverter stage, with the associated substrate- Fig. 14. The substrate voltage (dashed), and the difference between the
and power-supply parasitics that influence substrate injection. substrate voltage and V (solid) that result when the circuit in Fig. 13 is
simulated with the dotted lines taken as short circuits. The input (solid) and
output voltages (dashed) are as shown in the inset. The values of the parasitic
elements are chosen to reflect the values in a large digital circuit. The results
inverter is shown in Fig. 13. For now, we assume that the dotted indicate that V and V are almost equal during switching.
lines in Fig. 13 are solid, such that the substrate node is
resistively connected, via , to the rail of the circuit.
The substrate is also capacitively connected to , through
the capacitance between the metal lines and the substrate, and
more significantly, through all the NMOSFET source junctions
connected to . We previously noted that an individual
FET has a capacitance to the substrate in the range of tens of
fF. If there are such devices, then the total capacitance
that each device sees is already is above 1 nF.
At 1 GHz, which is a typical frequency for switching of
submicrometer MOSFET’s, has an impedance of
less than 1 , such that it is effectively shorted out. There is
also a series resistance, , in this path, due to wiring,
contact resistance and the substrate resistance of the source
diffusion and substrate. Finally, a voltage can develop between
and ground, across the bond wire inductance and the
line resistance . Fig. 15. The substrate voltage (dashed), and the difference between the
substrate voltage and V (solid) that result when the circuit in Fig. 13 is
The substrate voltage that results from simulation of this cir- simulated with the dotted lines taken as open circuits. The input (solid) and
cuit is shown in Fig. 14. We have assumed some typical values output voltages (dashed) are as shown in the inset. The result is that V and
for these parasitic elements, with fF, V have an equivalent high-frequency behavior to the previous case, but V
has additional low-frequency fluctuations, and a nonzero average component.
nF, nF, , , ,
and nH. The difference between and is also
plotted, which reveals strong coupling between and the sub- transmitted to the substrate. Overall, this result suggests that
strate, and substrate fluctuations that are nearly identical to those separate connections of and to ground will not result
on . Therefore, for the parasitic values used in this example, in significant improvements in substrate isolation. While this is
substrate voltage fluctuations are mainly governed by the circuit true for a single inverter, we will describe in Section IV how
switching current and not by the MOSFET substrate current. the low-frequency components can play a significant role in a
2) Separate Connection of the Substrate to the Power complete integrated circuit, such that separate power-supply
Supply: If separate bias connections are used for the and connections are advantageous.
nodes, the dotted lines in Fig. 13 are open circuits and 3) Parasitic Decoupling Capacitance: The discussions in
there will only be capacitive coupling left between and the previous sections are based on a model in which there is a
. To examine this scenario, this modified circuit was low-impedance connection between the substrate and , in
re-simulated with the same parameter values used in Fig. 14. combination with a relatively small current flowing between the
As shown in Fig. 15, is still seen to follow the high-fre- two. The latter assumption is not necessarily true. In addition
quency behavior of , due to coupling via the source diodes. to the fact that there is a large capacitance between and the
The difference between the two node voltages reveals that the substrate, there also is a large capacitance between and all
current at has an additional low-frequency component the -wells combined. Furthermore, the junction capacitance
with a nonzero average, which does not couple to the substrate. between these -wells and the substrate, , can be very
When the substrate was resistively connected to the line, large, due to the large -well area. The combination of these
this small average component of the switching current was three capacitances leads to a parasitic decoupling capacitance

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between and with small series impedance, as shown

in Fig. 13.
At the first moments of a switching transient, it is possible
that this decoupling capacitance will supply the switching cur-
rent instead of the power supply itself, because of the bond wire
inductances. While all of these terms were included in our sim-
ulations, it is complicated to determine the net effect of this de-
coupling capacitance on substrate crosstalk in a general sense.
On the one hand, it will damp fluctuations due to the fact that the
collective well-substrate capacitor acts as a battery during the
first moments of a switching transient, thereby decreasing the
and voltage transients. On the other hand, when this
damping occurs, more current will flow via the substrate, which
will increase substrate voltage fluctuations. The final outcome
will depend on the relative values of these parasitic elements, Fig. 16. The total rms signal resulting from 10 individual switching signals,
as shown in the inset. The rms signal is calculated as a function of a Gaussian
and on the presence of other decoupling capacitors. What is
most important to recognize is that decoupling capacitances can p
uncertainty ( ) in starting times of the individual switches. For a large spread
in  , the total sum is N times the value of a single signal.
significantly alter the substrate fluctuations and must be taken
into account. To analyze this scenario we simulated individual,
Finally, it is important to note that the presence of both single sine wave periods at the fundamental frequency, with a
capacitances and inductances in the same packaged integrated Gaussian distribution of starting moments. The total rms signal
circuit can lead to oscillations and significant transient signals of this ensemble of pulses was calculated over different uncer-
after switching. These are unwanted because they can amplify tainties in the Gaussian distribution. The results, shown
substrate voltage fluctuations by orders of magnitude in a in Fig. 16, indicate that if the uncertainty in the starting time is
frequency range in which the analog circuit operates. Modeling within 10% of the sine wave period, then the total rms signal
and damping of several forms of resonance have already been is simply times the rms signal of a single switching event.
well discussed in the crosstalk literature [1], [7], [22], and However, if the uncertainty becomes ten times larger than the
should not be neglected when analyzing the coupling of a total switching time, the rms value of the total noise due to
specific circuit. switches will be proportional to . In this case, there is sig-
nificant cancellation of the total rms signal, and the ensemble of
switching events can be treated as a source of random noise.
IV. SUBSTRATE VOLTAGES DUE TO A LARGE CIRCUIT Fig. 16 also shows the normalized rms signal calculated when
the signal consists of two sine wave periods at twice the fre-
So far, we have only discussed how the switching of a quency. This curve is shifted by a factor of two compared to
single inverter or a cluster of identical inverters can affect the original curve, because the relative uncertainty is twice as
the substrate voltage. The transients that result from a large large at double the frequency. Therefore, for a fixed uncertainty
clocked circuit will not necessarily be the same as the tran- , the axis of Fig. 16 can also be interpreted as the frequency
sient of an individual element multiplied by the number of axis. As a consequence, high-frequency components will be sta-
elements that switch. For instance, if two elements switch tistically cancelled more than lower frequencies. The value of
at approximately the same moment in opposite directions, the corner frequency will be determined by the switching un-
partial cancellation of the resulting substrate transients can certainty, relative to the switching period of a single element.
occur. In the same way, noise reduction can also take place Since this noise cancellation is less effective for the low-fre-
if all elements switch in the same direction but not at ex- quency and average components, it is important to reconsider
actly the same time. In this section, we examine an idealized the results of Section III, which were performed for a single de-
switching circuit, to examine how the statistics of large num- vice. While the noise of a large circuit will certainly be larger
bers of devices can affect the conclusions made in previous than that of an individual device, the total high-frequency com-
sections about dominant substrate injection mechanisms. ponent of the fluctuations can increase by up to less than
In the following example, we examine how the cancellation the low frequency and average component of the noise. There-
of transients takes place when all elements switch in the same fore, low-frequency noise injection mechanisms such as impact
direction. Let us assume that element 1 switches at moment , ionization may still play an important role in large circuits. From
element 2 at moment , up to element . We will assume that this perspective, it may be better if and the substrate are not
the distribution of switching moments is symmetric around coupled together, because the relatively small average fluctua-
the average switching moment and follows, as an example, a tion shown in Fig. 15 could become dominant in larger circuits.
Gaussian distribution. Figs. 14 and 15 show the transients due In this analysis, we have modeled an ensemble of switching
to the switching of one inverter and each such transient can elements in a large digital circuit as a set of independent events
be described as a sum of sine waves. For illustration purposes, added together. In reality, some correlations would be expected,
we will consider just the fundamental sine wave period and the and these correlations will have the effect of reducing the effec-
sine-wave period with double the frequency. tive spread in switching times, thereby reducing the amount of

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noise cancellation. In general, the more complex a circuit be- [3] J.-P. Raskin, A. Viviani, D. Flandre, and J.-P. Colinge, “Substrate
comes, the greater the spread in switching times and the better crosstalk reduction using SOI technology,” IEEE Tran. Electron
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The authors would like to thank G. Alers, J. Bude, H.-I. Cong,
P. Davis, R. Gupta, P. Kinget, P. Larsson, S. Martin, and D.
Monroe for their helpful advice, suggestions, and technical dis-
J. Briaire received the M.Sc. degree in electrical
engineering at Eindhoven University of Technology,
REFERENCES Eindhoven, The Netherlands, in 1996 . Presently, he
[1] D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental re- is working toward the Ph.D. degree in his final year
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1993. 1=f noise in the ferromagnet Ni Fe .
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K. S. Krisch (S’85–M’87) received the S.B. and

S.M. degrees, and the Ph.D. degree in electrical
engineering from Massachusetts Institute of Tech-
nology, Cambridge, in 1988 and 1992, respectively.
Her Ph.D. work was on reoxidized nitrided oxide
MOS gate dielectrics.
In 1992, she joined Bell Laboratories, Lucent
Technologies, Murray Hill, NJ, where she was a
Member of Technical Staff in the Silicon Electronics
Research Laboratory. In 1998, she became head
of the Device Modeling Department in Lucent
Microelectronics, and currently she is the director of Technology Modeling
and Verificaton. Her interests include substrate crosstalk, noise, and novel gate

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