IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO.
6, JUNE 2000 671
Measurements and Analyses of Substrate Noise
Waveform in Mixed-Signal IC Environment
Makoto Nagata, Associate Member, IEEE, Jin Nagai, Takashi Morie, and Atsushi Iwata, Member, IEEE
Abstract—A transition-controllable noise source is developed in
a 0.4- m -substrate -well CMOS technology. This noise source
can generate substrate noises with controlled transitions in size, in-
terstage delay and direction for experimental studies on substrate
noise properties in a mixed-signal integrated circuit environment.
Substrate noise measurements of 100 ps, 100- V resolution are
performed by indirect sensing that uses the threshold voltage shift
in a latch comparator and by direct probing that uses a PMOS
source follower. Measured waveforms indicate that peaks reflecting
logic transition frequencies have a time constant that is more than
ten times larger than the switching time. Analyses with equivalent
circuits confirm that charge transfer between the entire parasitic
capacitance in digital circuits and an external supply through par-
asitic impedance to supply/return paths dominates the process, and
the resultant return bounce appears as the substrate noise.
Index Terms—Mixed analog–digital integrated circuits, sub-
strate coupling, substrate Noise measurements, signal integrity.
I. INTRODUCTION
S YSTEMS-ON-A-CHIP (SOC) very large scale integra-
tions (VLSI’s) require functional analog circuits such as
analog-to-digital/digital-to-analog (AD/DA) converters, radio
frequency (RF) circuits, and CMOS imagers to be placed on
a die with high-speed digital processing circuits comprising
millions of logic elements.
Crosstalk from the digital circuits is a major cause of
degrading analog signal integrity. Prediction of the system
performance through a full-chip crosstalk verification is an
essential part of a reliable mixed-signal LSI design. However,
there is some difficulty caused by the fact that the crosstalk
transmits mainly as substrate noise and is mixed with the analog
signals through nonideal operations among analog circuits.
Accordingly, it is necessary to develop compact substrate
noise simulation models for efficient time-domain continuous
analyses.
Differential analog circuits show crosstalk rejection to a fi-
nite extent. The timing separation of analog clocks from their
digital counterparts alleviates this problem as long as discrete
time analog systems are used. Remedies widely used in the
layout work include separate routing of analog supply/return
paths from that for digital paths, guard-banding with dedicated
Manuscript received October 1, 1999; revised February 4, 2000. This work is
supported by Semiconductor Technology Academic Research Center (STARC).
This paper was recommended by Associate Editor R. Saleh.
The authors are with the Faculty of Engineering, Hiroshima University 1-4-1
Kagamiyama, Higashi-Hiroshima, 739-8527 Japan.
Publisher Item Identifier S 0278-0070(00)05343-4.
0278–0070/00$10.00 © 2000 IEEE
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pads, and insertion of on-chip decoupling capacitors to the dig-
ital supply paths. Each of those measures has proven itself to
be effective; however, the effective use of them has relied on
the experience of designers. Early optimization in floor plans,
timing, performance margins, and circuit topologies based on
figures of their effects are necessary for meeting the short turn-
around-time developments required by current industrial appli-
cations, which also necessitate chip-level substrate noise simu-
lation techniques.
The substrate itself can be treated as an equivalent resistive
mesh or expressed in the form of an impedance matrix, thanks
to well-established efficient node reduction techniques [1]–[4],
point to point impedance calculation methods [5], and other ad-
vances.
However, for simulating the noise generation process in large
scale logic circuits, dynamic treatments are necessary. Here,
simplification methodologies play a major role.
A solver proposed in [6] formulates all of the parasitic
effects between capacitors in the logic circuits, inductors in
an assembly, resistors in the substrate mesh, and so on in a
Laplace domain by applying asymptotic waveform evaluation
[7]. A set of impulse stimuli representing logic switching
currents are input to the system, and transient noise waveforms
are calculated from the frequency domain responses by inverse
Laplace transformation.
On the other hand, the entire system is evaluated at a de-
signer-specified frequency in [8], where all memory compo-
nents can be treated as memoryless and, thus, resistive, and the
reduced admittance matrix for the system response is prepared.
Spatial noise amplitude distribution is estimated by injecting a
sinusoidal supply current with a magnitude preestimated from
power analyses to the matrix.
Other approaches use behavioral modeling in an HDL-based
simulation environment [9], [10], where acquisition of digital
transition frequency from the event driven simulator and sub-
strate noise synthesis as a function of that quantity in the con-
tinuous time simulator can be integrated. We have proposed
mixed-level full-chip substrate noise verification techniques that
use a macroscopic substrate noise model and have reported their
validity based on the fact that performance deterioration in a
second-order modulator coupled with a digital noise source
could be simulated in several hours, which would take more than
a month or be impossible with conventional circuit simulators
[11].
In order to achieve reliable substrate noise analyses with those
methodologies, exact and detailed understanding of the sub-
strate noise properties is necessary. Although in-depth studies
672 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 6, JUNE 2000

with weights. Hence, the circuit can generate substrate noises

with controlled transitions in size, interstage delay and direc-
tion.
The noise source block includes 30 inverters operating in par-
allel. Each inverter has a 50-fF load capacitor against the sub-
strate, corresponding to two-gate input capacitances and 400 m
AL1 wires. Gate widths are chosen to have a switching time
of 200 ps for both rise and fall transitions while driving the load
capacitor. The minimum gate length is used. Multiple drivers
from the delay element to the inverters shape the clock signal
and make the delay time dependence of negligible.
Two substrate noise measurement techniques have been de-
veloped (Fig. 2). Both use a comparator based equivalent sam-
Fig. 1. Circuit schematic of transmition-controllable noise source. pling technique developed by Fukuda et al. [13]. The differen-
tial latch comparator (LC) shown in Fig. 3(a) has been chosen
for the substrate noise detector circuits in our design because a
high temporal resolution can be expected due to the large gain
in positive feedback.
In the first method shown in Fig. 2(a), substrate voltage
change is traced as threshold voltage shifts in the latch
comparator. The shift represented as is measured as a
difference between a static threshold voltage adjusted at
with a conventional offset canceling technique and a dynamic
threshold voltage determined when amplifying a small
voltage difference at the differential input. Here, sensitivity
to the substrate potential arises mainly from body coefficient
mismatches among MOSFET’s in the cross-coupled latch of
the comparator, where common-mode rejection capability ex-
pected from the differential and symmetric design is degraded.
This circuit is named the LC detector.
Fig. 2. Substrate noise measurement techniques. (a) LC: Indirect sensing by
Determination of follows to (1), where input voltage
+
the threshold voltage shift in a latch comparator. (b) SF LC: Direct probing by increases with a step of , and probability , which is defined
a PMOS source follower. as an average of test outputs, is measured at each step. at
the largest slope in a meta-stable region is a good approximation
on substrate noise propagation have been reported [2], [12], sub- of
strate noise generation mechanisms in large scale digital cir-
cuits have not been clarified. Further experimental research is at (1)
required to elucidate this issue.
Section II describes a design of a transition-controllable Fig. 3(b) shows a timing diagram. Clock pulses
noise source and proposes two substrate noise measurement are for the comparator, where determines a test point at
techniques for realizing 100 ps, 100- V resolution. A set of , separates time zones of the decision from that of an
measurement results clarifying the substrate noise generation offset canceling for the static adjustment, and latches
mechanism will be also provided. Then, substrate noise mod- the output. stimulates the multiphase clock generator of the
eling with equivalent circuit models is proposed and substrate noise source.
noise analyses by circuit simulation are discussed. A test period is 2000 ns, where with a 200-ns pulse width
is located sufficiently within the decision zone and the sub-
II. SUBSTRATE NOISE MEASUREMENT WITH HIGH TEMPORAL strate is expected to be stable outside the vicinity of . Thus,
RESOLUTION the comparator only senses the substrate voltage change at just
. is moved backward with a step of relative to ,
A. Noise Source and Detector Circuit Design and the test is iterated until is determined according to (1)
A transition-controllable noise source (TCNS) is shown in with in every time step. Resolutions of
Fig. 1. The circuit has a multiphase clock (Ck[0:10]) generator, V and 100 ps are achieved.
which consists of odd delay elements in series, and a matrix of The other method shown in Fig. 2(b) is a direct probing tech-
noise source blocks. The delay element has bias voltages nique. A -channel source follower (SF) isolated from the sub-
and for regulating rise and fall delay, respectively. Inverse or strate by an -well is used as a front-end level shifter for the
noninverse transition among the adjacent noise source blocks substrate potential picked up at a -contact probe. The latch
are selective. The number of noise source blocks to be activated comparator serves as a back-end voltage reader. The most ap-
by Ck[0:10] can be 0–15, which is set by address signals x[0:3] proximate voltage in to is determined according to

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NAGATA et al.: MEASUREMENTS AND ANALYSES OF SUBSTRATE NOISE WAVEFORM IN MIXED-SIGNAL IC ENVIRONMENT
Fig. 3. Latch comparator. (a) Circuit schematic. (b) Timing diagram.
(1) at each time step, as with the first method. This combination
is called the SF LC detector.
Mutual evaluation of substrate noise waveforms measured
by the two techniques can improve data reliability. Large
bandwidth can be expected for the LC detector because of very
small input capacitance in the back terminals of MOSFET’s.
However, nonlinear sensitivity is disadvantageous. On the other
hand, using the SF LC detector’s source follower results in
highly linear sensitivity within a bandwidth of several GHz in
a typical design. Note that the SF LC detector alone enables
absolute evaluation, including consideration of polarity.
We have developed two test chips in a 0.4- m CMOS, -type
bulk substrate with a single -well, triple-metal double-poly-Si
technology. Circuits are designed with 3.3-V supply voltage.
Fig. 4 shows chip microphotographs. While both chips (A,B)
have the same TCNS and LC detector, Chip B additionally has
the SF LC detector. These chips differ in the distance between
the detectors and the noise source, which are placed approxi-
mately 750 m apart in Chip A and 300 m apart in Chip B.
The -contact probe of SF LC is located behind the latch
comparator and is roughly 500 m from the noise source. A
symmetric axis of LC faces TCNS so as to eliminate asymmetry
in the noise intensity due to the disparity in distance. Exclusive
pairs of power supply and return wirings with dedicated bond
pads are provided for the noise source matrix in TCNS, for the
clock generators/drivers in TCNS and LC detectors, and for the
other analog parts. The analog return wirings are isolated from
the substrate.
Another chip for testing the SF LC detector is fabricated
with a 0.6- m CMOS technology, where an external input ter-
minal is provided to the source follower.
A mixed-signal LSI test system (HP9494) is used for the sub-
strate noise measurement because of such advantages as inte-
grated functions for test pattern generation and data acquisition
with precisely controlled synchronization, programmable edge
timing, programmable pin-to-module assignments, and a C-lan-
guage based programming interface. Application programs for
automatic measurement executions that have been developed for
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673
(a)
(b)
Fig. 4. Microphotographs of 0.4-m CMOS test chips. (a) Chip A. (b) Chip
B.
both detectors include control of the comparator clocking, noise
source stimulation, and data processing for extracting .
Chips are packaged in ceramic 120-pin QFP’s. device under
test (DUT) boards for electrical connection to the LSI tester are
provided for each of the chips. Each of the power supply/re-
turn pairs is connected to an individual dc resource of the tester,
and all of the return paths are connected to ground plates of the
DUT board. In particular, isolated power sources are assigned
to the pair for the noise source matrix and the pair for the analog
parts of the detectors in order to avoid intersupply couplings in a
measurement system. Both sides of the boards are covered with
copper thin films patterned but not stripped off in order to form
a large ground plate, where a QFP socket, 100-nF ceramic and
10- F electrolytic shunt capacitors on every supply/return pair,
and some monitor terminals are soldered.
B. Measurement Results
First, the performance of the SF LC detector was verified.
Fig. 5 shows sensing results of external sine waves up to
100 MHz with 10-mV amplitude centered at 0.0 V by the
SF LC detector in the 0.6- m CMOS test chip with reso-
lutions of 200 V and 100 ps. The detector is
operated in the same way as in the substrate noise measurement.
Uncertainty in reproduced waveforms can be reduced to the
order of 100 V by averaging. Linear sensitivity was confirmed
as shown in Fig. 6. Inputs are 100-MHz sine waves centered
at 0.0 V with 6-dB increments in the amplitude where 0 dB
corresponds to 10 mV. The detector can be calibrated by the
measured gain of 3.7 dB over a 24-dB input range in order
674 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 6, JUNE 2000
+
Fig. 5. Traces of external sine waves by SF LC detector in 0.6-m CMOS.
Fig. 6. +
Linear sensitivity of SF LC detector in 0.6-m CMOS.
Fig. 7. Substrate noise waveforms for rise transitions in Chip B with the
number of active noise source blocks as a parameter. (a) Measured by LC
+
detector. (b) Measured by SF LC detector.
to realize an absolute substrate noise evaluation. However, the
calibration is not applied for the measured results reported
here because unfortunately the substrate noise test chips shown
in Fig. 4 use a different CMOS process. Simulated gain and
3-dB bandwidth for the SF LC detector in a 0.4- m CMOS
technology that is biased at 1.9 V are 1.3 dB and 2.4
GHz, respectively.
Figs. 7 and 8 are measured substrate noise waveforms for rise
and fall transitions in TCNS in Chip B, respectively. Eleven sub-
peaks that coincide with the noise source block action driven by
the 11 noninverse phase clocks Ck[0:10] are clearly observed.
Subpeak amplitudes increase with the number of active noise
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Fig. 8. Substrate noise waveforms for fall transitions in Chip B with the
number of active noise source blocks as a parameter. Arrows indicate the
subpeaks corresponding to the noise source block operation driven by Ck[0:10].
+
(a) Measured by LC detector. (b) Measured by SF LC detector.
Fig. 9. Substrate noise waveforms for rise transitions measured by LC detector
in Chip A. Interstage delay increases from (a) to (d).
source blocks. Note that all of the subpeaks show positive in-
crease for both rise and fall transitions. The mechanisms behind
these results are discussed in a later section.
Traces obtained by the LC and the SF LC detectors are very
consistent, which justifies these measurement techniques. Di-
rect coupling of LC to SF inside the chip prevents bandwidth
degradation since SF is segregated from parasitic passive ele-
ments in assembly and in probes of measurement equipment.
However, slight bluntness is seen in the traces by the SF LC de-
tector due to an unavoidable bandwidth limitation in the source
follower.
Fig. 9 shows change in the substrate noise waveforms for
rising transitions while increasing the interstage rise delay from
approximately 1.5 ns to 2.5 ns [Fig. 9(a)–(d)], by adjusting
while 0.0 V. rises at 2 ns and then 15 noise source
blocks each are activated by noninverse Ck[0:10]. from the
clock generator in TCNS is monitored for estimating the inter-
stage delay ( ) prior to the waveform measurements, and an
output driver for is disabled during the measurements to
prevent interference with output load driving current.
Intensive peaks followed by slow large ringing appear in
Fig. 9(a). The peaks start to split into subpeaks and the ringing
decreases in Fig. 9(b). Finally, the subpeaks corresponding
NAGATA et al.: MEASUREMENTS AND ANALYSES OF SUBSTRATE NOISE WAVEFORM IN MIXED-SIGNAL IC ENVIRONMENT 675

Fig. 10. Substrate noise waveforms for inverse transitions measured by LC

detector in Chip A. Rise-to-fall delay increases from (a) to (b) while fall-to-rise
delay is minimized.

1 
Fig. 12. Ringing peak amplitude V versus =T . Points (a e) correspond to
labeled substrate noise waveforms in the inset. Waveforms right after the noise
+
source operations are obtained by SF LC detector in Chip B.

shown in Fig. 10. for large indicates that each

substrate voltage change arising from the corresponding noise
source block becomes independent, while increases with
for small due to interference among adjacent subpeaks. Fully
Fig. 11. Subpeak interval T and with T at dc level versus bias voltage
independent subpeaks obtained with a considerably large inter-
V regulating interstage rise delay, measured by LC detector in Chip A. T stage delay have of 2.5 ns, which is on the order of ten times
estimated from P , simulated switching time T are also shown. (a) Rise larger than , as shown in Figs. 7 and 8.
transitions. (b) Inverse transitons.
Another significant component of the substrate noise is the
ringing, as shown in Fig. 9(a). Rapid change in the supply cur-
to the 11 delayed edges become clear in Fig. 9(d). Here, the rent leads to the ringing, generally at the beginning and/or at the
largest peaks in the supply current from Fig. 9(a) to Fig. 9(d) end of a processing series in a digital block. Fig. 12 shows the
are induced in Fig. 9(a), which leads to strong interference ringing peak amplitude versus obtained from wave-
between the ringing and the subpeaks during the noise source forms given in the inset taken right after completing the state
at work and also the subsequent ringing. As the current transitions in all of the noise source blocks driven by Ck[0:10].
reduces, the ringing is suppressed and the subpeaks become Since the ringing arises from large in the supply current at
distinctive. Amplitude modulation in Fig. 9(d) results from the end of the operation, has a strong relation to . There
beating between the subpeaks and fast ringing. Obviously, these is little change in ringing frequency among these waveforms,
processes indicate the effect of inductances that are parasitic to since it is inherently determined from where , are
the supply/return paths. the components that are parasitic to the supply/return paths.
Fig. 10 shows substrate noise waveforms for inverse transi- For these measurements, the LC detector in Chip A is used in
tions. The delay time from rise to fall transitions is larger in Figs. 9–11, and the SF LC detector in Chip B is used in Fig. 12.
Fig. 10(b) than in Fig. 10(a), while that from fall to rise transi- Resolutions are 100 V and 100 ps in Figs. 7–12.
tions is minimized ( 0.0 V) and estimated at about 800 ps Observed features of the substrate noise are: 1) principal com-
by simulation. Note that each of the subpeaks includes substrate ponents in the substrate noise are subpeaks and ringing; 2) sub-
voltage changes originating from the fall and the next rise tran- peaks reflect the logical transition activity and show relaxation
sitions. is defined as the interval between these pairs and is processes with a time constant on the nanosecond order; and 3)
approximately 2.5 ns in Fig. 10(a) and 6.0 ns in Fig. 10(b). subpeaks have positive amplitude unrelated to the direction of
Fig. 11 summarizes the subpeak interval and width at included state transitions.
0 V extracted from measured substrate noise wave- These results confirm that voltage bounce on the return path
forms. Obvious agreement between and estimated by appears directly in the substrate noise.
monitoring proves the correspondence of the subpeaks to
the noise source blocks. The graph shows that is always more III. SUBSTRATE NOISE ANALYSES
than a few times larger than the switching time , although all
of the state transitions involved in each subpeak are completed A. Analyses by Equivalent Circuit Models of Substrate Noise
at the same time among parallel inverters in the noise source Injection
blocks belonging to Ck[i]. Here, simulated is 210 ps/170 Fig. 13 shows simplified equivalent circuits of a logic element
ps for rise/fall transitions and its dependence on is negli- Fig. 13(a) and a digital functional block Fig. 13(c). Switching
gible, as was mentioned. Moreover, becomes larger for the action to charge or discharge load capacitance determines log-
inverse transition with the minimum delay time from the fall ical output. Here, selects a logical state from a truth table
to rise transitions. This is because each of the subpeaks merges for inputs. Switches are realized by -MOSFET’s with
changes in substrate voltage through successive transitions, as channel resistance in CMOS technology. The load capacitance

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676 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 6, JUNE 2000

Fig. 14. Spatial distribution of parasitic capacitance. C , C , and C

are collectives of the capacitances in logic element groups switching in rise,
switching in fall, and remaining in current states, respectively.

For logic operations during , charge transfer

of needs to take place. A set
Fig. 13. Equivalent circuits for substrate noise simulation. (a) A logic element of fast logic state transitions is initiated by rapid charge redis-
and (b) its symbol. (c) A digital block. tribution among the capacitances ( , , ). These transi-
tions are then completed by charge transfer of between
includes output capacitances , formed by S/D diffu- all of the distributed capacitances and an external supply with a
sions and a total input capacitance , in the following time constant given roughly by the product of
logic elements where gate-to-channel and interconnect ca- and . Here, is approximately time-invariant, assuming a
pacitances are major components. Here, these capacitors para- steady logic activity.
sitic to -MOSFET’s and to N-MOSFET’s are denoted by sub- The former process uses as a local distributed charge
scripts “ ” and “ ,” respectively. Other dominant capacitors are reservoir and guarantees the switching time . Here, is
, which includes on-chip decoupling capacitors and parasitic large enough to dominate all of the parasitic capacitances and
components in packages and wires due to assembly, and well stores . For example, a gate-block
capacitance . with a 20% activation ratio results in about 250 pF in a
Supply(Vdd) and return(Gnd) routes append parasitic 0.4- m CMOS technology.
impedance and , respectively, to the circuit. Since The current due to the charge redistribution is a minor contrib-
local impedance on Vdd/Gnd within the digital block is negli- utor to the substrate noise. Thus, it can be conceived that the sub-
gible among packed logic elements, these are block-to-block or strate noise amplitude shows a weak dependence on . A part
chip-to-supply lumped impedances. Here, the -substrate and of the current injected to the substrate through capacitive cou-
-wells are tied to Gnd and Vdd, respectively. pling at S/D diffusions and interconnecting wires is immediately
For modeling substrate noise generation, a large digital block collected to through the neighboring substrate contacts
is partitioned into a set of logic element groups switching in and, thus, does not spread widely in the substrate. Other parts,
rise, switching in fall, and remaining in current states, as shown including a capacitively coupled current at the gate-to-channel
in Fig. 14. , , and are collectives of parasitic capaci- capacitance and a short circuit current due to the finite switching
tances included in those groups and distributed spatially inside time in -MOSFET’s, flow directly in highly conductive
the digital block. These are defined according to the following metallic wirings to .
equations: On the other hand, supply currents have slow changes due to
the latter process and cause supply/return bounces, including the
broad subpeaks and ringing components from flowing through
and . Since the substrate surface is tightly coupled to
the return paths through distributed substrate contacts, the return
bounce leaks to the substrate and appears as the substrate noise.
(2)
These microscopic views are supported by the measured sub-
strate noise waveforms.
First, since the return current always flows toward the system
(3)
ground via after the charge redistribution, the substrate
noise has positive amplitude regardless of the composition ratio
of rise-to-fall transitions as long as inductive interaction such as
(4)
ringing is negligible, as shown in Figs. 7 and 8.
Second, if capacitances being discharged are considerably
Here, we introduce a constant as the total number of logic larger than those being charged, most of the charge transfers
elements in the block, and variables as the num- finish locally by short circuit currents of the discharging capac-
bers of active elements switching in the rise/fall directions, and itors, and smaller supply current is required. in
as those of stable elements in the H/L state. for rising transition, and in for falling
These are not instantaneous values at but integrated values transition, are possible cases. This imbalance happens in TCNS
around over a period of about , which is a time constant in- since the noise source inverters have 50 fF capacitances against
trinsic to the circuit. the substrate. As a result, the substrate noise amplitudes for the

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NAGATA et al.: MEASUREMENTS AND ANALYSES OF SUBSTRATE NOISE WAVEFORM IN MIXED-SIGNAL IC ENVIRONMENT 677

falling transitions are smaller than those for the rising transi-
tions. We can say that such strongly biased distribution of the
parasitic capacitance does not occur in ordinary integrated cir-
cuits.

B. Simulation Results
Fig. 15 gives SPICE simulation results for TCNS working
in the rise transitions with 2.2 ns ( 1.8 V, and
0.0 V), where waveforms corresponding to the first three
stages in Ck[0:10] are shown. and of 1 without
any inductance are placed between TCNS and external power
supplies.
Analyses with a full transistor description of TCNS and those
with an equivalent circuit description based on Fig. 13 show Fig. 15. SPICE simulation results with a full transistor description and with the
equivalent circuits of TCNS. (a) Node voltages V ; i at noise source inverter
consistent results for the node voltage ( ) at the noise source outputs in each stage i. (b) Substrate voltage V . (c) Supply current I
inverter outputs in each of the noise source blocks that are driven flowing in Z and currents inside noise source blocks I .
one after another by Ck[0:10]. There are also consistent results
for the substrate voltage ( ) after . The supply current
( ) flowing in and currents inside each of the noise
source blocks ( ) are shown in Fig. 15(c), where the full
transistor description is used. Very sharp peaks in result
from the rapid charge redistribution that realizes the approxi-
mately 200-ps gate switching time shown in . On the other
hand, broad and reduced peaks in due to the slow charge
transfer from the external supply determine , which has a
width that is a few times larger than the switching time.
Fig. 16 shows simulated substrate noise waveforms for the
rise transitions with different interstage delay. The test circuit
includes TCNS with the full transistor description, passive com-
ponents parasitic to the Vdd/Gnd paths, and decoupling. Here,
the extracted value of by measurement is 59 nH. This includes
inductances parasitic to the bonding wires, package leads, and
socket leads, as well as wirings on the DUT board of the mea-
surement system. The tendency in the waveforms where the sub-
peaks become clear for the larger interstage delay is consistent
with the measured waveforms shown in Figs. 9 and 7. Detailed Fig. 16. Substrate noise waveforms with different interstage delay simulated
structure differs due mainly to simplification of parasitic circuit by SPICE. (a) Simulated circuits including passive components parasitic to
supply/return paths. Full transistor description of TCNS is used. (b) Simulated
networks, however, the test circuit can serve as a tester for opti- waveforms for different interstage delays.
mizing the decoupling circuit design.
These simulation results qualitatively prove the substrate
noise generation process discussed in the previous section.
Quantitative estimation becomes possible if a substrate model Measured waveforms indicate that the voltage bounce on the
with an appropriate resistive mesh is intermediate between return path leaks to the substrate and appears as the substrate
digital and analog circuits, where decay due to the distance, noise, where the dominant components are subpeaks reflecting
suppression by guard banding, and geometrical effects due to logic transition frequencies, which have a time constant that is
substrate contact arrangements can be properly evaluated. more than ten times larger than the switching time, and slow
ringing.
IV. CONCLUSION Analyses with equivalent circuits confirm that the bounce re-
sults from the charge transfer between the parasitic capacitance
A transition-controllable noise source is developed in a of all of the digital circuits and an external supply, operating
0.4- m CMOS, -substrate -well technology. This noise through supply/return parasitic impedance.
source can generate substrate noises with controlled transi- Ringing must be considered for digital designs with intermit-
tions in size, interstage delay and direction. Substrate noise tent processing, such as those in portable electronics, since it
measurements of 100 ps, 100- V resolution are performed by appears at the beginning and at the end of a series of logic tran-
indirect sensing that uses the threshold voltage shift in a latch sitions.
comparator and by direct probing that uses a PMOS source These results can be the basis of reliable substrate noise mod-
follower. eling methodologies that target chip-level verification. Precise

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678 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 6, JUNE 2000
and compact supply current models incorporating the charge re-
distribution effect and continuous re-charging process of the en-
tire set of logic capacitances will play essential roles in future
developments.
ACKNOWLEDGMENT
The authors would like to thank Dr. T. Kozawa, Dr. K.
Mashiko, Dr. T. Iida, Dr. H. Ishikawa, and Dr. M. Yotsuyanagi
for helpful discussions. The chips were fabricated by Rohm
Corporation and Toppan Printing Corporation through VLSI
Design and Education Center (VDEC), the University of
Tokyo, and also by Ricoh Corporation
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Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:24 from IEEE Xplore. Restrictions apply.
Makoto Nagata (M’95–A’96) received the B.S. and
M.S. degrees in physics from Gakushuin University,
Tokyo, Japan, in 1991 and 1993, respectively.
From 1994 to 1996, he was a Research Associate
at Research Center for Integrated Systems, Hi-
roshima University, Higashi-Hiroshima, Japan,. He
is currently a Research Associate of the department
of Electrical Engineering, Hiroshima University.
His research interests focus on mixed-signal LSI
design techniques. Substrate crosstalk modeling
and reduction methodologies, circuit modeling
techniques in Analog HDL, and development of merged analog-digital PWM
based time domain signal processing architectures are included. He is a
member of the IEICE.
Jin Nagai was born in Hiroshima, Japan, on
February 28. He is presently with the Department of
Engineering, University of Hiroshima, Higashi-Hi-
roshima, Japan, and working toward the B.E. degree.
His research interests are measurements of substrate
Noise in AD mixed LSI’s.
Takashi Morie received the B.S. and M.S. degrees
in physics from Osaka University, Osaka, Japan,
and the Dr.Eng. degree from Hokkaido University,
Hokkaido, Japan, in 1979, 1981, and 1996, respec-
tively.
From 1981 to 1997, he was a member of the Re-
search Staff at Nippon Telegraph and Telephone Cor-
poration (NTT). Since 1997, he has been Associate
Professor at the Faculty of Engineering, Hiroshima
University, Higashi-Hiroshima, Japan. His main in-
terest is in the area of VLSI implementation of neural
networks, analog-digital mixed/merged circuits, and new functional devices.
Dr. Morie is a member of the IEICE of Japan, the Japan Society of Applied
Physics, and the Japanese Neural Network Society.
Atsushi Iwata (M’87) received the B.E., M.S.,
and Ph.D. degrees in electronics engineering from
Nagoya University, Nagoya, Japan, in 1968, 1970,
and 1994 respectively.
From 1970 to 1993, he was at the Electrical
Communications Laboratories, Nippon Telegraph
and Telephone Corporation (NTT). Since 1994, he
has been a Professor of Electrical Engineering at
Hiroshima University, Higashi-Hiroshima, Japan.
His research is in the field of integrated circuit design
where his interest have included, circuit architecture
and design techniques for analog-digital mixed LSI’s, analog-to-digital
converters, image processors, and bio-inspired intelligent processing LSI’s.
Dr. Iwata received an Outstanding Panelist Award for the 1990 International
Solid-State Circuits Conference. He is a member of IEICE and the Japanese
Neural Network Society. He was the Program Chairman for the 1995 Sympo-
sium on VLSI Circuits. He has been the Chairman for the 1999 Symposium
on VLSI Circuits, and an Associate Editor of IEEE JOURNAL OF SOLID STATE
CIRCUITS from 1996.