Documente Academic
Documente Profesional
Documente Cultură
Philippe Duchene
duchene@simplex.com
Power Integrity
VoltageStorm™ SoC
Timing Integrity
Fire & Ice® QX
ClockStorm™
Signal Integrity
SubstrateStorm™
SI Report™
Reliability
ElectronStorm™
© Copyright 2001 Simplex Solutions, Inc. 2
The Substrate Crisis
At 0.13 micron
Noise generation increases by 50%
Noise
© Copyright 2001 Simplex Solutions, Inc. sensitivity increases by 100% 3
ADI Disaster Example:
Trial & Error
• Video converter
with 27 MHz PLL
failed
• VCO locked to
substrate clock
• Various solution
techniques
attempted
• What worked?
www.imse.cnm.es/esd-msd/WORKSHOPS/ESSDERC2000
IC Design
SubstrateStorm
Substrate
Layout Edit
Abstract View
Substrate Technology
LVS/LPE Extraction Description
Netlist
Technology
Technology
description
description Layout
Layout
IN
3-D
3-DModel
Model
OUT
Electrical
Electrical Visual
simulation Visual
simulation analysis
analysis
Bonding Wire
P+ contacts Nwell
N+ contact
• RC Model Extraction
© Copyright 2001 Simplex Solutions, Inc. 9
3D Modeling
poly
p+
nwell
} LAYOUT
interconnect
y contact device
x
(doping profiles)
p+
PROCESS
z nwell
p-substrate
poly
p+ n+ p+
nwell
well-substrate
resistive junction resistive
p-substrate substrate capacitance well
Modeling
• Non-manhattan shapes
Technology
TCAD Measurement
Characterization
Substrate Technology
Extraction Description Doping
Profiles
Patents granted
© Copyright 2001 Simplex Solutions, Inc. 13
Simplex Foundry Partners
Doping Designer
Profiles
Technology
Description
Technology
Characterization
Tool
Substrate
Extraction
© Copyright 2001 Simplex Solutions, Inc. 14
Full-chip Analysis
• Design Example
– Effect of pad ring switching
noise on PLLs
• Exploration Questions
– Noise frequency dependence
– Splitting ground lines
– Backside grounding
– Number of VSS pins (package
inductance)
– Guard rings
– etc.
• Design
– 1M gates, 0.18µ
– 100MHz clock (PLL)
Substrate Noise
Abstract Color
GDS View Map
abstraction analysis
not shown
on customer
request
extraction
SPICE substrate
simulation
subnetlist
• SubstrateStorm
– surface distribution of the
noise
• Conditions
– 400ps rise/fall time
– 30pF off-chip load
– 2nH bond inductance
– Plotted @ 350MHz
BUT
DC 350 MHz
Noise isolation typically degrades at higher frequencies
Isolation is 6dB @ DC, but -0.42dB @ 350MHz
© Copyright 2001 Simplex Solutions, Inc. 20
Splitting Power Reduces Noise
VSS1 VSS1 VSS2
• What if you:
– added a N-well guard ring around your PLL?
– used a triple-well process?
– used a low-resistivity substrate?
– introduced a grounded backside connection?
– took the seal ring into account?
– cut the VSS ring to avoid noise transportation
– … Etc …
Goal: locate the most sensitive parts of the analog cell and improve
the noise immunity (lightly doped substrate)
© Copyright 2001 Simplex Solutions, Inc. 24
Simulation Set-Up
Noise source
s e t Output
i
No pac
im Noise
220mV
Noise source
Through the substrate
tr = 350 ps
© Copyright 2001 Simplex Solutions, Inc. 26
What Is the Most Sensitive Part?
SPICE simulation
Substrate
No impact from this stage
© Copyright 2001 Simplex Solutions, Inc. 28
Active Devices < 1% Total Noise
SPICE simulation
1st Solution:
extending the n-well under the
compensation devices
Result:
1: noise immunity improved: 50%
2nd Solution:
p+ ring around the cell
Result:
2: noise immunity improved: 80%
• Flow Integration
– Standalone: GDS to Spice
– Diva, Calibre, Assura, Dracula
– Seamless Integration in Cadence Virtuoso and Analog Artist
• 2 Use Models
– Detailed Cell Analysis and Simulation
– Chip-level Floorplan Analysis
• Foundry Program
– TSMC, ST, UMC