Substrate Noise Analysis with Compact Digital Noise Injection and

Substrate Models

Makoto Nagata1 Yoshitaka Murasaka2 Youichi Nishimori1 Takashi Morie1

Atsushi Iwata1,2
1
Integrated Systems Laboratory, Hiroshima University
1-3-1 Kagamiyama, Higashi-Hiroshima, 739-8526 Japan
2 A-R-Tec Corp.

Email: {nagata, morie, iwa}@dsl.hiroshima-u.ac.jp

Abstract CMOS digital circuits were embedded with a highly linear

This paper presents a substrate noise analysis method-
ology that employs chip-level substrate modeling based
on F-matrix computation and digital substrate-noise injec-
tion modeling with a time-series divided parasitic capaci-
tance model for time-domain power-supply current estima-
tion. System-level simulation models generated accordingly
to the methodology provide reliable substrate noise wave-
forms.
Simulated waveforms for practical digital circuits on a
0.6-µm CMOS 4.5-mm square chip are well consistent with
measurements with a 100-ps 100-µV resolution. Peak-to-
peak substrate noise amplitudes for reduced-substrate noise
as well as conventional designs show roughly the error of
10% compared with the measurements.
1. Introduction
Advanced system-on-a-chip (SoC) VLSIs much ben-
efit from mixed-signal integration of analog functional
sub-systems for such as ADC/DAC and RF with high-
speed/large-scale digital signal processing cores on a single
Si die. However, time-to-market designs need reliable ways
to estimate mixed-signal circuit performance with the ef-
fect of digital-to-analog substrate crosstalk [1, 2] especially
in closing physical designs.
This paper proposes a suite of substrate noise analysis
methodologies that includes chip-level substrate modeling
based on fundamental matrix (F-matrix) computation and
digital-substrate noise injection modeling based on rapid
yet accurate power-supply current waveform estimation.
We applied the methodologies to a 0.6-µm CMOS test
chip in which conventional and reduced-substrate noise
substrate noise detector. Simulation results are compared
with measurements with a 100-ps 100-µV resolution.
2. Full-chip substrate noise analysis
The substrate crosstalk is a phenomenon where noises
injected into a common substrate by digital circuits prop-
agate toward embedded analog circuits and leak to analog
signal paths, which finally interfere with analog operation
and degrade analog circuit performance. Such noise, gener-
ally referred to as a substrate noise, has a waveshape closely
correlating with a change in logic activity in a digital circuit,
and more complicatedly, is considerably attenuated when
propagating through a Si substrate.
The goal of substrate noise analysis is to estimate the
change in substrate voltage quantitatively both in time
and space domains in the vicinity of victim analog cir-
cuits [3, 4]. However, great difficulties in performing full-
chip substrate noise analysis are due mainly to dealing with
the hundred thousands of gate elements in digital circuits
and the millions of connections between ground wirings
and a substrate on the surface, which are non-uniformly dis-
tributed within the die area of up to 20-mm square. There-
fore, we need macro-modeling techniques for digital cir-
cuits as noise injectors and also for a substrate and surface
power-supply/ground wiring systems as transmitting media,
on the basis of general understandings on substrate noise
properties. Our proposed techniques are outlined in follow-
ing sections.
Note that one can predict the response of an analog cir-
cuit to substrate noise through conventional time-domain
circuit simulation, where the circuit senses the noise mainly
through the back-gate effect of MOSFETs and capacitive
coupling of parasitic components.

Proceedings of the 15th International Conference on VLSI Design (VLSID’02)

0-7695-1441-3/02 $17.00 © 2002 IEEE
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:35 from IEEE Xplore. Restrictions apply.
 2.1. Chip-level substrate modeling using F-matrix
computation I11 V11 V21 V31 Vm1 V(m+1)1 I(m+1)1

I12 V12 V22 V32 Vm2 V(m+1)2 I(m+1)2

We can deal with a silicon substrate as an equivalent re- F1 F2 Fm
sistive mesh, as long as the frequency of interest is within a I1n I(m+1)n
few giga-hertz. However, accurate analysis requires a finer V1n V2n V3n Vmn V(m+1)n
mesh, which demands a greater analysis time and memory
and is of less practical use. Figure 1. F-matrix computation for m-stage
Network reduction methods such as [5] can involve mesh cascaded circuit.
nodes other than some of explicitly designated surface anal-
ysis nodes into a transfer matrix and thus remove them from
an actual nodal matrix for circuit simulation, without loss
of accuracy. We have developed a chip-level substrate mod-
eling technique which uses fundamental matrix (F-matrix) Chip
computation in conjunction with such the network reduction
principle and provides a general way to compute an admit-
tance matrix of the explicit analysis nodes for a substrate
with surface ground-wiring systems [6]. The computed ad-
mittance matrix can be easily transformed to netlists com-
patible with conventional circuit simulators such as SPICE. Fh,wire
A multi-terminal F-matrix relates voltage V 2 and current
I2 of n output terminals to those of n input terminals V 1 and Fv,con
I1 as follows:



V1 V
=F 2 . (1)
Fh
I1 I2
Fv
Cascading F-matrices of sub-circuits gives a synthesized
system F-matrix as shown in Fig. 1 where all of the in- Fh
termediate nodes are included to a single F-matrix, which
is the most attractive feature of the F-matrix computation.
Fv
The F-matrix of the m-stage cascaded circuits is described
as follows:
Fcas = F1 F2 · · ·Fm , (2)
Figure 2. Chip-level F-matrix cascade.
where F1 , F2 , · ··, Fm denote F-matrices of sub-circuit net-
works, and Fcas the synthesized matrix. All of these matri-
ces have n input and n output terminals. F-matrices, respectively, and obtain general forms of F-
We can deal with a chip as a resistive network in alter- matrices as follows:
nate piles of horizontal and vertical layers, as Fig. 2 shows.


E A E 0
Since an F-matrix can be defined for each of the layer, a Fv = , Fh = . (4)
0 E B E
chip-level F-matrix cascade can be formed as follows:


 Here, A, B are sub-matrices representing vertical resistive
Vtop V elements determining vertical voltage differences and hor-
= Fh,wire Fv,con Fh Fv Fh Fv · · · btm , (3)
Itop Ibtm izontal resistive elements determining horizontal currents
induced from voltage differences from four neighboring
where (Vtop , Itop ) stand for the voltage and current of n nodes, respectively, and E an identity matrix.
nodes on the chip surface, (Vbtm , Ibtm) those on the chip Although the synthesized system F-matrix relates (V, I)
bottom, Fh,wire a horizontal F-matrix for a ground wiring of all the surface nodes to those of the bottom nodes,
system, Fv,con a vertical F-matrix for ties between the we choose a few of the nodes as explicit analysis nodes
ground wirings and substrate, F h and Fv horizontal and ver- for connecting the substrate to active circuits and system
tical F-matrices within a substrate mesh, respectively. power-supply/ground terminals and leave the other nodes
From the Kirchhof’s laws, we can find I1 = I2 in de- floated, in macroscopic treatments. Further network re-
termining vertical and V 1 = V2 in determining horizontal duction can be performed in converting the F-matrix to a

Proceedings of the 15th International Conference on VLSI Design (VLSID’02)

0-7695-1441-3/02 $17.00 © 2002 IEEE
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:35 from IEEE Xplore. Restrictions apply.
 Y-matrix of the explicit analysis nodes under a condition
A
A AA
where Itop−floated = 0 and Ibtm−floated = 0 for the other (a)
AA A (b)
floated nodes. The final form of the chip-level substrate AA AA AA AAA A
model is a SPICE compatible sub-circuit netlist, where the
ports corresponding to the explicit analysis nodes are fully
AA
AAAAA
A A AAA AAA A
connected each other with the resistors constituting the Y- ΣC (nT) ΣC dis, (nT) ΣCch, (nT) ΣC (nT) ΣCdis, (nT) ΣCch, (nT)
matrix.
(c)

AAAAAAAAAAAAAAA AAAAAAA
Note that the proposed chip-level substrate modeling Lp Rp

AA A AAAA AA
AA
A AA
A A
AA
technology with the F-matrix computation considerably re-
duces the size of the nodal matrix of a chip-level resistive Vdd Cs
mesh network in an error-free way, except for round-off er-
rors in actual computing. Vsub (n-2)T (n-1)T nT (n+1)T

2.2. Digital substrate noise injection modeling Figure 3. Capacitances parasitic to logic el-
ements switch (a) in rise and (b) in fall.
The leakage of voltage bounce on power-supply/return (c) Time-series divided parasitic capacitance
rails into a substrate is the most dominant source of sub- (TSDPC) model.
strate noises in large-scale digital circuits [7]. This fact nat-
urally indicates that a precise expression of power-supply
current waveforms in digital circuits must be key in simu-
lating the substrate noise injection, since the interaction of
(a) CMOS (b) SGW
the current with power-supply parasitic impedance results
Nwell z0 z1
in the bounce. VDD&Nwell
z0 z1 Cj z0 z1
VDD
We have developed a time-series divided parasitic capac- Cp Cp
TSDPC TSDPC Cp
itance (TSDPC) model shown in Fig. 3(c), where a digi-
tal circuit is equivalently expressed as a series of capaci- z0 z1 GND z0 z1
GND&Psb Noise Cj
z0 z1
tors to be charged by an external power source [8]. Groups injection Psb

of capacitances parasitic to gate elements switching in rise

and those in fall in the digital circuit are defined as ΣC ↑ , (c) RSB Nwell
Cj
z0 z1
ΣC↓, respectively. Each of the active gate element involves Cd VDD
Cp
both charging (C ch) and discharging (Cdis) capacitances in z0 z1 TSDPC
Cd
both of the switching directions, as shown in Figs. 3(a) GND
Cj z0 z1
and (b). Here, the discharging process is mostly completed Psb
through local shorts formed in MOSFETs with channel re-
sistance. On the other hand, sub-nano second logic switch- Figure 4. Substrate noise injection models for
ing operation is mostly completed through charge redistri- (a) conventional, (b) separated guard wiring
bution, where stably charged capacitances work as locally (SGW), and (c) reduced supply bounce (RSB)
distributed charge reservoirs which rapidly feed charges to CMOS topologies.
the charging capacitors. The primal role of external power
sources is to feed charges equal to ΣCch ·Vdd to the circuit,
and it consumes the entire energy of ΣCch ·Vdd 2 required from

completing logic operations in this process. While the loss

of charges due to sub-threshold leakage and short-circuit
currents shares other parts of power consumption, its effect
on the noise injection is minor.
Now we introduce a time division to the continuous
distribution of logic transitions in a digital circuit. The
charging capacitance is integrated in every time interval of
nT ∼ nT + T , where T and n stand for the period and the
number of the interval, respectively. The resulting time-
series capacitances of {Cch,↑(nT ),Cch,↓ (nT )} is the TSDPC
model of the circuit. This model generation is required once
per an input vector for the circuit, however, which can be
achieved in parallel with conventional post P&R gate-level
or transistor-level time-domain simulations.
A compact time-domain power-supply current estimator
is formed by connecting the model with a power-supply par-
asitic impedance network and a stable parasitic capacitor Cs
between the circuit and the external power source, as shown
in Fig. 3(c). The size of Cs can be roughly equal to the to-
tal sum of parasitic capacitances between power-supply and
ground terminals of the circuit and on-chip de-caps. The
model greatly reduces the cost of computation since only
a few passive components are to be solved in every sim-

Proceedings of the 15th International Conference on VLSI Design (VLSID’02)

0-7695-1441-3/02 $17.00 © 2002 IEEE
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:35 from IEEE Xplore. Restrictions apply.
 ulation steps while maintains the accuracy comparable to
full-transistor level circuit simulation. In addition, once a
TSDPC model is generated, it can be re-used for simulat- 5pcs. CMOS 5pcs.
ing power-supply current with the power-supply networks
with various component values or even in different topolo- SGW-CMOS
gies, since the model simply provides the amount of charges
required per every time interval from a digital circuit.
Figure 4 shows substrate noise injection models, where
reduced-substrate noise designs including separate guard RSB-CMOS(1)
wiring (SGW) CMOS and reduced supply bounce (RSB)
CMOS [8] employ the same TSPDC model as well as in a RSB-CMOS(2)
conventional design. The voltage bounce induced at para-
sitic impedances on return wirings appears as the substrate RSB-CMOS(3)
noise through distributed P + substrate contacts on the sur-
face of a P-type substrate. Guard wirings for substrate/well
ties are isolated from the bouncing power-supply/return
rails in the SGW-CMOS, which is often used in high- SF+LC
performance mixed-signal design. On the other hand, the (a)
variation of power-supply current is suppressed by inten- SEL
tionally inserted RC-time constants between local and main INA
power-supply/return rails in the RSB-CMOS, which consid- Reg1
CLK1 [A]
erably reduces the voltage bounce. TSDPC modeling pro- INB Reg2
vides reliable estimates of noise amplitude for these circuit CLK2
topologies and helps to choose and/or optimize the reduced
0 0 0 0 0 0 0 0
SET
noise designs.
Full Adder [B]
3. Design of substrate noise test chip CLK3 Reg3 OUT
(b)
A test chip shown in Fig. 5(a) was fabricated in a 0.6-
Figure 5. (a) 0.6-µm CMOS test chip. (b) Noise
µm CMOS DPTM technology with a P-type bulk substrate.
source circuit.
It includes arrays of a noise source circuit comprising two
8-bit CMOS input registers and an 8-bit CMOS full adder
followed by an output register as described in Fig. 5(b), and
a highly linear substrate noise detector (SF+LC). The arrays
each includes 10 pieces of the identical CMOS circuit while clock edges while have negligibly small dependence of the
uses conventional, SGW, and RSB topologies at physical noise intensity on the input bit patterns. This reasonably in-
level design. Power-supply wirings are separated among the dicates that the most of logic activity comes from gating in
arrays. The number of the circuits to activate is controllable. flip-flops and internal clock drivers. Therefore, one of the
The power-supply voltage of 3.3 V was used. TSDPC models represents the noise source circuit in fol-
The chip has the area of 4.5 mm × 4.5 mm mostly occu- lowing full-chip substrate noise analysis.
pied by the arrays and the detector senses the substrate noise The mesh size of 151 × 151 × 6 was chosen and F-
locally at its position. Therefore, it is necessary to apply the matrices of Fh and Fv with 151 × 151 nodes were defined
chip-level substrate modeling technique for analyzing sub- for all layers identically inside the bulk substrate. Figure 6
strate noises with the effect of propagation decay. shows a simplified ground wiring system of the chip used
for defining the surface F-matrices of Fh,wire and Fv,con ,
where parts of the wirings and substrate contacts within ev-
4. Simulation and measurements ery mesh region are used for determining the resistance of
mesh elements. We designated 54 explicit analysis nodes
We generated a set of TSDPC models of the noise source all on the surface, including 1 node per 5 noise source cir-
circuit with various input binary data to the registers from cuits for every array, 1 node for the noise detector, and the
transistor-level circuit simulation results. Simulated sub- others for ties to the system ground. The chip backside was
strate noise waveforms at the source, thus without a sub- floated in assembly.
strate model, show obvious peaks strongly correlating with A system-level substrate noise simulation model shown

Proceedings of the 15th International Conference on VLSI Design (VLSID’02)

0-7695-1441-3/02 $17.00 © 2002 IEEE
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:35 from IEEE Xplore. Restrictions apply.
 Simulated
40
CMOS 30 CMOS

Vsub (mV)
20 RSB2,3
RSB1
SGW 10
0
-10

20 Measured
RSB1

Vsensor (mV)
CMOS

RSB2 0
RSB(1)-(3)
RSB3 -20
CLK
0 10 20 30 40
time (ns)
Figure 6. Simplified ground wiring system.
Figure 8. Substrate noise waveforms of con-
ventional and reduced-substrate noise CMOS
circuits.
V DDA z z V DD

Detector TSDPC
TSDPC
TSDPC
VGNDA
z z V GND Simulated Measured
60
Substrate Voltage p-p [mV]

50
CMOS
Figure 7. System-level substrate noise simu- 40
CMOS
lation model.
30
RSB(1)
20 RSB(2)
RSB(3)
10 RSB1
in Fig. 7 is described in a SPICE compatible netlist, which RSB2,3
includes the chip-level substrate model, noise source cir- 0
2 4 6 8 10 2 4 6 8 10
cuits (TSDPC models), a noise detector, and external power N Blk
sources. We inserted an inductor of 1 nH and a resistor of
1 Ω in series to every connections between ports and power Figure 9. Peak-to-peak noise amplitudes ver-
sources as well as the system ground, in order to involve sus number of active noise source circuits.
parasitic impedance networks resulting from the chip as-
sembly.
Figure 8 shows substrate noise waveforms simulated
with the model by a SPICE simulator and those actually
measured in a 100-ps 100-µV resolution by the measure- ing from the conventional CMOS noise sources, which lo-
ment system that we have established on a mixed-signal cate most distant from the detector as shown in Fig. 5(a).
IC tester [8]. The noises from the reduced noise design These analyses costed only 7-MByte memory and 80-sec
using the RSB-CMOS are also shown. Simulated and CPU time per a waveform with a PA8500-440MHz micro-
measured waveshapes are well consistent especially in pri- processor.
mal frequency components correlating with the clock edges Figure 9 compares simulated and measured peak-to-
and peak-to-peak noise amplitudes. Differences in detailed peak noise amplitudes for different numbers of active noise
structure arise dominantly from the simplified models of source circuits, which match roughly with the error of 10%.
parasitic impedance networks. We found the attenuation Note that the noise amplitude in the RSB-CMOS seems to
ratio of roughly 9.5 dB for the substrate noise propagat- be smaller than the lower limit of the measurements due to

Proceedings of the 15th International Conference on VLSI Design (VLSID’02)

0-7695-1441-3/02 $17.00 © 2002 IEEE
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:35 from IEEE Xplore. Restrictions apply.
 background noises mainly from I/O circuits. environment,” IEEE Trans. Computer-Aided Design of Inte-
grated Circuits and Systems, 19(6):671–678, June 2000.
[8] M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata,
5. Conclusions “Physical design guides for substrate noise reduction in
CMOS digital circuits,” IEEE J. Solid-State Circuits,
A substrate noise analysis methodology employing chip- 36(3):539–549, Mar. 2001.
level substrate modeling based on F-matrix computation
and digital substrate-noise injection modeling with the
time-series divided parasitic capacitance model for time-
domain power-supply current estimation has been demon-
strated. System-level simulation models generated accord-
ingly to the methodology provide rapid yet reliable esti-
mates of substrate noise waveforms. In addition, the mod-
els can be re-used among the designs with various power-
supply network topologies, which is very helpful to the
physical-level design optimization of mixed-signal chips for
achieving substrate noise reduction and/or tolerance.

Acknowledgments

This work is supported in part by Industrial Technol-

ogy Research Grant Program from NEDO and by Semicon-
ductor Technology Academic Research Center (STARC).
Chips are fabricated by Rohm Corp. and Toppan Printing
Corp. through VLSI Design and Education Center (VDEC),
the Univ. of Tokyo.

References

[1] D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Exper-

imental results and modeling techniques for substrate noise
in mixed-signal integrated circuits,” IEEE J. Solid-State Cir-
cuits, 28(4):420–430, Apr. 1993.
[2] N. K. Verghese, T. J. Schmerbeck, and D. J. Allstot, Simula-
tion Techniques and Solutions for Mixed-Signal Coupling in
Integrated Circuits, Boston, MA: Kluwer Academic Publish-
ers, 1995.
[3] I. L. Wemple and A. T. Yang, “Integrated circuit substrate
coupling models based on Voronoi tessellation,” IEEE Trans.
Computer-Aided Design of Integrated Circuits and Systems,
14(12):1459–1469, Dec. 1995.
[4] E. Charbon, R. Gharpurey, R. G. Meyer, and A. Sangiovanni-
Vincentelli, “Substrate optimization based on semi-analytical
techniques,” IEEE Trans. Computer-Aided Design of Inte-
grated Circuits and Systems, 18(2):172–190, Feb. 1999.
[5] T. A. Johnson, R. W. Knepper, V. Marcello, and W. Wang,
“Chip substrate resistance modeling technique for integrated
circuit design,” IEEE Trans. Computer-Aided Design of Inte-
grated Circuits and Systems, CAD-3(2):126–134, Apr. 1984.
[6] Y. Murasaka, M. Nagata, T. Ohmoto, T. Morie, and A. Iwata,
“Substrate noise analysis using fundamental matrix computa-
tion,” In Proc. IEEE Int. Symp. Quality Electronic Design,
pages 482–487, Mar. 2001.
[7] M. Nagata, J. Nagai, T. Morie, and A. Iwata, “Measurements
and analyses of substrate noise waveform in mixed signal IC

Proceedings of the 15th International Conference on VLSI Design (VLSID’02)

0-7695-1441-3/02 $17.00 © 2002 IEEE
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:35 from IEEE Xplore. Restrictions apply.