IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41. NO. 9.
SEPTEMBER 1994
The Effects of Impact Ionization on the
Operation of Neighboring Devices and Circuits
Koji Sakui, Member, IEEE, S. Simon Wong, Senior Member, IEEE, and Bruce A. Wooley, Fellow, IEEE
Abstract-This paper examines the detrimental effects of excess
majority carriers and photons induced by impact ionization on
the operation of neighboring pn junctions, bipolar transistors,
MOS transistors, and circuits. The experimental results show that
in addition to an increase in the substrate surface potential due to
the excess majority carriers, photons can lower the barrier of a pn
junction and, as a consequence, shift the Gummel plot of an npn
bipolar transistor. As for the neighboring circuits, an example in
which the speed of an NMOS ring oscillator is retarded by impact
ionization in a neighboring NMOS transistor is presented.
I. INTRODUCTION
I T is well known that electron-hole pairs can be generated
by impact ionization when an MOS transistor is operated
in the saturation region. The influence of such hot carriers on
the reliability of MOS transistors has been studied extensively.
Earlier work has examined both secondary impact ionization
[l], [2] and the injection of minority carriers at a source
junction due to the flow of the substrate current [3]. The
generation of photons under a high drain field condition has
also been reported [4]-[ 1 I]. Recent studies in this area have
focused on light emission from scaled MOSFET’s [ 121, [ 131.
However, the influence of excess majority carriers and photons
on nearby devices and circuits has not been investigated in
detail. This paper is devoted to examining the detrimental
effects of hot carrier induced excess majority carriers and
photons on the operation of neighboring pn junctions, bipolar
transistors, MOS transistors, and circuits. The experimental
results indicate that these effects can extend to devices located
hundreds of microns away from the point at which impact
ionization occurs.
11. EXPERIMENTAL
SETUP
Several CMOS test chips have been realized in a 2-pm
n-well process [ 141. Two 161-stage, 2-input NAND gate ring
oscillators with output buffers are located in the center of each
test chip, and a variety of bipolar and MOS transistors are
placed on the periphery of the chip at a distance of 200 to
300 pm from the ring oscillators. The test chips also contain
2 1-stage NMOS enhancement-load ring oscillators surrounded
by a number of monitor transistors. This arrangement allows us
to evaluate the behavior of individual neighboring devices as
a circuit is operated in a fashion that causes impact ionization,
Manuscript received March 12, 1993; revised April 17, 1994. The review
of this paper was arranged by Associate Editor Y. Nishi.
The authors are with Stanford University. Stanford, CA 94305 USA.
IEEE Log Number 9403540.
0018-9383/94$04.00 0 1994 IEEE
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1603
and vice versa. Fig. 1 shows a micro-photograph of one of
the test chips.
111. EXPERIMENTAL
OBSERVATIONS
A . Neighboring PN-Junction Characteristics
When electron-hole pairs are generated by impact ioniza-
tion in an NMOS transistor, excess majority carriers (holes)
increase the surface potential of the p-substrate when they
flow to the backside contact as a substrate current. As a result,
a nearby n+/p-substrate junction can become forward biased
and inject a large number of electrons into the substrate. This
phenomenon is well known and can be simulated with a 2-D
device simulator such as PISCES. Fig. 2 illustrates a structure
that has been employed for such a simulation. Fig. 3 shows the
simulated behavior of an n+p-substrate junction at a distance
of 1O-p11ifrom an NMOS transistor that is biased in the impact
ionization region with a drain-source voltage, V d , , of 6.6 V
and a gate-source voltage, of 3 V. The positive shift of the
diode current-voltage characteristic as the neighboring NMOS
is turned on confirms that the potential at the substrate surface
has been increased.
Experimental results for a CMOS ring oscillator and an
n/p-substrate junction spaced 200-p1n apart are presented
in Fig. 4. Similar characteristics are measured on the n/p-
substrate junction if a neighboring NMOS transistor, instead
of the ring oscillator, is biased in the impact ionization
region. However, the ring oscillator is more representative
of the switching occurring in a typical integrated circuit.
The experimental behavior is different from the simulation
results of Fig. 3. When impact ionization occurs in the ring
oscillator, a positive shift of the diode current-voltage charac-
teristic, as predicted by simulation, is observed experimentally.
Moreover, the reduction in the slope of the log(1) versus
V characteristic indicates that the built-in potential of the
n/p-substrate junction is lowered. This barrier lowering was
not predicted by simulation. It is believed that photons are
also generated by impact ionization in the NMOS transistors.
As these photons reach the depletion region of a nearby pn
junction, carriers are generated. When the junction is forward
biased, the photon-induced carriers lower the built-in potential
as illustrated in Fig. 5(a). Consequently, the current-voltage
characteristic exhibits a lower slope, as well as the positive
shift due to the increase in substrate surface potential. When
the diode is reversed biased, the photon-induced carriers are
swept into the neutral region, resulting in a positive current
flow as illustrated in Fig. 5(b). This current is in a direction
1604 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41. NO. 9, SEPTEMBER 1994

PISCES Simulation Configuration

vgs = 3v

Fig. 2. Structure simulated by PISCES.

-10.2

;q.\
.i............!.
1q;
.
.
.
:
-104

: : ........I.i I .......!..i -10.6

2-lnpul: NAND Gate
Output Buifer
-s -10-8

............:
g -10.10
:
(,i. I. -10-12

............
i !rD.D. D.Ds-D.D.D-. .
..........

............
-10-16

.. ..
............
Chip Size: 2.035 X 2.035mm2
(b)
Fig. 1. (a) Micro-photograph and (b) schematic of one of test chips. A
variety of bipolar and MOS transistors are placed on the periphery of the
chip at a distance of 200-300 Irm from the ring oscillators in the center.
opposite that due to the increased substrate surface potential.
When the ring oscillator supply voltage, ITee,is increased to 6
V, the number of photons generated can be large enough for
the photon-induced current in the depletion region to exceed
the current due to the increased substrate surface potential; as
a result, a net positive current is observed under a sufficiently
high reverse bias, as shown in Fig. 4. This sign change in the
current was not predicted by simulation because the effect of
the photons was not accounted for. Thus, the current observed
at a neighboring reverse-biased pn junction can be negative or
positive depending on whether the current due to the increased
substrate potential or the photon-induced current is dominant.
As illustrated in Fig. 6, the current of a pn junction with a
constant reverse bias of 1.5 V changes sign several times as the
supply voltage of the ring oscillator is increased. This confirms
that the amount of carriers and photons generated by impact
ionization in a switching circuit is not a monotonic function of
the supply voltage, but is dependent on the extent and duration
-10-18
1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5
N-Psub Voltage (V)
Fig. 3. The simulated behavior of an n+/p-substrate junction at a distance of
10 Itm from an NMOS transistor that operates in the impact ionization region
with = 6.6 V and = 3 V.
that the NMOS transistors are biased in the high field region
and hence could be quite complex. A similar variation in the
difference of two opposing currents, the reverse base current
(RBC) effect, has been observed in a bipolar transistor when
the collector-base electric field is high [ 151-[20].
B. Neighboring Bipolar Transistor Characteristics
Fig. 7 shows the changes in the Gummel plot for an npn
bipolar transistor located a distance of 200 purn from the CMOS
ring oscillator when the oscillator is turned on with I&= 4 V.
Since the n-collector/p-substrate junction of the transistor is
reverse biased at 2 V. holes generated by impact ionization
in the ring oscillator cannot affect the emitter-base junction.
However, photons generated by impact ionization can reach
the emitter-base junction and lower its barrier, as evidenced by
the reduced slope of emitter and base currents. Consequently,
electrons are injected from the emitter into the base, and
holes from the base into the emitter, even when the emitter-
base junction is zero or reverse biased. The dependence of
the emitter current-voltage behavior on the ring oscillator
supply voltage I:.,, illustrated in Fig. 8, is very similar to
 SAKUI et al.: THE EFFECTS OF IMPACT IONIZATION ON NEIGHBORING DEVICES 160.5

106 I I 1
-10-2

-104

4 -106
L

0
-10-8

1 Positive Current / ,/ f

1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5

N-Psub Voltage (V)

Fig. 4. Measured characteristics of a pn-junction which is spaced 200 p m I I

from a CMOS ring oscillator. When the ring oscillator is operated at high
bias ( I :., = 6 V), the number of photons generated is sufficiently large that 0.0 1.0 2.0 3.0 4.0 5.0 6.0
the photon-induced current in the depletion region exceeds the current due to Ring OscillatorOperational Voltage (V)
the increased substrate surface potential.
Fig. 6 . Two opposing current racing in a reverse biased pn junction.

Base Grounded 10-2

Collector. Psub = 2V
I0-4

------
-10-10 10-10
carriers cause a

I ~ I depletion region
and banierheight I -10.12
0.6 0.2 -0.2 -0.6
Emitter Voltage (V)
-1.0 -1.4
10-12

Fig. 7. Gummel plot of npn bipolar transistor. Since the photon-induced

current lowers the barrier of the emitter-base junction, electrons are injected
from the emitter into the base. even when the emitter-base junction is zero
or reverse biased.

Base Grounded
Colledor. Psub = 2V

Ring on:

+# positive photon-
induced current
(b)
-10'0

-10-12
- 2.0 1.5
l
Padtlve
Current

1.0 0.5
O 0.0
Ring oR

-0.5
" -1.0 -1.5
W

Fig. 5. Band diagram illustrating (a) the lowering of the built-in potential of Eminer Voltage (V)
a forward biased junction by photon-induced carriers, and (b) the increase of
positive current due to photon-induced carriers. Fig. 8. Emitter current characteristics as a function of the supply voltage of
a nearby ring oscillator.

that for the pn junction shown in Fig. 4. Namely, as V,,
is increased more photons are generated and the barrier is
further reduced. In addition, the emitter current changes sign
when V,, is sufficiently high. These results further confirm that
photons are responsible for the phenomenon because excess
holes generated in the substrate cannot reach the base-emitter
junction.
C. Neighboring MOS Transistor Charucteristics
It is expected that the threshold voltage of an NMOS tran-
sistor will decrease and the subthreshold current will increase
when excess holes induced by impact ionization raise the
substrate potential under the transistor's gate. Fig. 9(a) shows
the measured subthreshold current of an NMOS transistor
located 200prn from the CMOS ring oscillator. The change

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 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 41, NO. 9, SEPTEMBER 1994

- 225
a
9
1 220
0
0)

E 215
E
$ 210

’
0
P
205
Ring on:

Ring off
200
II Vds 01 nearby NMOS = 5V

0.0 1.0 2.0 3.0 4.0 5.0 6.0

Vgs 01 Nearby NMOS (V)
-10-12
0.0 0.5 1.o 1.5 2.0 Fig. 10. Gate delay time of an NMOS ring oscillator is retarded by impact
Gate Voltage (V) ionization in a neighboring NMOS transistor which is biased with I;!, = .j1.
and r,, = 2.5 \’.
(a)
0.020 10’8 I I
Vds=SV

0.6 0.8 1.0

Depth (micron)

Fig. 11. Simulated hole concentration in a zero biased junction.

Gate Voltage (V)
(b)
Fig. 9. Measured (a) subthreshold behavior and (b) threshold voltage of an
NMOS transistor which is located at a distance of 200 p m from the ring
oscillator.
in the behavior is quite different from that obtained with
simply applying a positive substrate voltage. The excess holes
accumulated under the gate effectively increase the channel
doping level. This results in a reduction of the depletion layer
under the gate, an increase in the depletion layer capacitance
and hence a higher subthreshold slope [21]. An additional
gate voltage will be needed to expel these holes from under
the gate before a channel can form. Fig. 9(b) confirms that
the extrapolated threshold voltage is slightly higher and, as a
result, the current driving capability is slightly reduced. If a
large number of photons reach the MOS transistor, the leakage
currents of the source and drain junctions will increase.
S, = 0 . 3 2 p m . The excess holes generated in the substrate by a
nearby NMOS device reduce the depletion regions and cause an increase
in the capacitance.
increase in the threshold voltage reduces the current output of
the MOS transistors. In addition, the excess holes generated in
the substrate by impact ionization reduce the depletion regions
of nearby junctions, thereby causing an increase in the junction
capacitance, as indicated by the simulation results of Fig. 11.
Thus the switching speed of a nearby circuit is reduced.
It is expected that circuits composed of bipolar transistors,
especially analog circuits and sense amplifiers, may be seri-
ously degraded by impact ionization induced photons because
of the significant change in the device current-voltage charac-
teristics. It is well known that an increase in MOS subthreshold
current or the source/drain junction leakage current will signif-
icantly influence the operation of DRAM and dynamic logic
circuits, and further studies in these areas are needed.

D. Neighhorirzg Circuit Performance IV. CONCLUSION

Impact ionization induced majority carriers and photons are
expected to seriously degrade the operation of neighboring
circuits. Fig. 10 shows an example in which the speed of
an NMOS ring oscillator is retarded by impact ionization
in a neighboring NMOS transistor operated with a drain-
source voltage of V d , = 5 V and a gate-source voltage of
Vqs= 2 . 5 V . As discussed in the previous section, the slight
The detrimental effects of excess majority carriers and
photons induced by impact ionization on neighboring de-
vices and circuits have been measured, and compared with
simulations where appropriate. The excess majority carriers
increase the surface potential of the substrate, which can
forward bias nearby pn junctions, increase junction depletion
capacitances, and increase the subthreshold leakage of nearby

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 SAKUI er al.: THE EFFECTS OF IMPACT IONIZATION ON NEIGHBORING DEVICES
MOS transistors. The photons not only increase the reverse
leakage current of a nearby pn junction, but also lower
its barrier height. These effects can significantly alter the
current-voltage characteristics of a nearby bipolar transistor.
Moreover, it is important to note that these effects can extend
to devices that are several hundred microns away from the
source of impact ionization. A complex device structure with
nested wells might be used to suppress the majority carrier
effects. However, such an approach will not be effective
against the photons. It is therefore essential that future scaled
devices be designed to minimize impact ionization.
ACKNOWLEDGMENT
The authors wish to thank Dr. John Shott and the staff of the
Integrated Circuits Laboratory at Stanford University for the
fabrication of the test circuits. Thanks are also due to Kazuhisa
Miyamoto, Lydia So, Chin-Chieh Chao, David Su, and Marc
Loinaz for technical assistance and numerous discussions.
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Koji Sakui (M‘92) was born in Tokyo, Japan, on
April 29, 1956. He received the B.E. and M.E. de-
grees, both in instrumental engineering, from Keio
University, Tokyo, Japan, in 1979 and 1981, respec-
tively.
In 1981 he joined the Toshiba Research and De-
velopment Center, Toshiba Corporation, Kawasaki,
Japan. Since then he has been engaged in the devel-
opment of high-density DRAM‘s and EEPROM’s.
From 1991 through 1993, he was a Visiting Scholar
at Stanford University. doing research in the field
of Multi-Chip Module and BiCMOS technologies.
S. Simon Wong (S‘77-M‘83-SM‘91) received the
B.E.E. and B.M.E. degrees from the University
of Minnesota at Minneapolis in 1975 and 1976,
respectively, and the M.S. and Ph.D. degrees from
the University of Califomia at Berkeley in 1978
and 1983, respectively.
From 1978 to 1980, he was with National
Semiconductor Corporation designing MOS dy-
namic memories. From 1980 to 1985, he was
e 8,’ with Hewlett Packard Laboratories working on
advanced MOS technologies. From 1985 to 1988,
he was an Assistant Professor in the School of Electrical Engineering at
Cornell University. In 1988, he joined Stanford University where he is
now an Associate Professor of Electrical Engineering. His present research
interests include high performance device structures, advanced interconnection
technology, multi-chip modules. and optical interconnections.
Bruce A. Wooleg (S‘64-MS70-SM‘76F‘82) was
born in Milwaukee, WI. on October 14, 1943. He
received the B.S., M.S., and Ph.D. degrees in elec-
trical engineering from the University of California,
Berkeley in 1966, 1968, and 1970, respectively.
From 1970 to 1984 Dr. Wooley was a member of
the research staff at Bell Laboratories in Holmdel,
NJ. In 1984 he became Professor of Electrical
Engineering at Stanford University. His research is
in the field of integrated circuit design and technol-
ogy where his interests have included monolithic
broadband amplifier design,. circuit architectures for high-speed arithmetic,
analog-to-digital conversion, digital filtering, high-speed memory design,
high-performance packaging and test systems, and high-speed instrumentation
interfaces. Prof. Wooley was the Editor of the IEEE Journal of Solid-State
Circuits from 1986 to 1989.
Dr. Wooley was the Program Chairman of the 1990 Symposium on VLSI
Circuits and the CO-Chairman of the 1991 Symposium on VLSI Circuits. He
was the Chairman of the 198 1 International Solid-State Circuits Conference,
and he is a former Chairman of the IEEE Solid-state Circuits and Technology
Committee. He has also served on the IEEE Solid-state Circuits Council and
the IEEE Circuits and Systems Society Ad Cam. In 1986, he was a member
of the NSF-sponsored JTECH Panel on Telecommunications Technology in
Japan. He is a member of Sigma Xi, Tau Beta Pi, and Eta Kappa Nu. In
1966 he was awarded the University Medal by the University of California.
Berkeley. and he was the IEEE Fortescue Fellow for 1966-1967.