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were obtained using AIM SPICE simulator and BPTM
model files released on 30/9/2005.
9.0n
Total Subthreshold Leakage Current
8.0n Total Gate Leakage Current
1.0
7.0n
0.6 5.0n
SNM(V)
4.0n
0.4
3.0n
0.2 2.0n
3.0n M5
trend.
Assuming that zero is stored in the cell as shown in
2.0n
Fig. 1, it can be readily seen that subthreshold
current arises primarily from transistors M2, M3 and
M5. Variation of subthreshold current through these 1.0n
unchanged, the subthreshold current still changes due 0.0 0.1 0.2 0.3 0.4 0.5
to change in body bias of transistors in the SRAM Vss (V)
cell. For NMOS transistors M2 and M5, the body is
connected to ground so that increase in Vss causes
Fig. 4: Variation of subthreshold leakage currents
source-body junction to become increasingly reverse
through individual transistors in the conventional
biased thereby resulting in rise in threshold voltage
SRAM cell in 65nm technology at 27°C
of these transistors. This causes a decrease in
Gate leakage is pre-dominantly due to NMOS
subthreshold current in these two transistors. The
transistors M1, M2, M5 and M6. Variation of gate
subthreshold current in M5 falls because gate-source
leakage current through each of these transistors with
voltage becomes negative as Vss rises.
Vss is shown in Fig.5. The gate to source and gate
to drain voltages of M1 and M2 transistors remains
unchanged as Vss is increased so there is little
change in their gate leakage.
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6.0n
5.0n M1
M2
5.0n
M3
3.0n 3.0n
2.0n 2.0n
1.0n
1.0n
0.0
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6.0n
8.5n
5.0n 8.0n
4.0n 7.5n
7.0n
3.0n
6.5n
2.0n
6.0n
1.0n
5.5n
0.0 0.1 0.2 0.3 0.4 0.5
0.0 Vss(V)
0.0 0.1 0.2 0.3 0.4 0.5
9.0n 12.0n
8.0n 11.0n
Total Sub Threshold Current(A)
7.0n
10.0n
6.0n
9.0n
5.0n
0.0 0.1 0.2 0.3 0.4 0.5
4.0n Vss(V)
3.0n
Fig 11 Variation of total leakage current through
2.0n SRAM cell for 65nm technology at 27°C
0.0 0.1 0.2 0.3 0.4 0.5 Since subthreshold and gate leakage currents in
Vss(V) 65nm technology are comparable and contribute
equally to total leakage current, the positive and
negative supply rails have to be altered by about the
Fig. 9: Variation of total sub threshold current same amount and minimum leakage occurs at Vss =
through conventional SRAM cell in 65nm 0.25V; Vdd = 0.75V. The leakage current is 16.35%
technology at 27°C lower compared to the case where only negative
supply rail is increased to 0.5V and Vdd = 1V and
In this case the total subthreshold current continues to 36.5% lower compared to the case where only
fall until Vss rises to 0.4V. Fig.10 shows the variation positive supply rail is reduced to 0.5V and Vss = 0V.
of total gate leakage current with increasing Vss. The
total gate leakage current is relatively larger due to 3.3 45nm Technology node
thinner gate dielectric and increases rapidly with
increasing Vss. Fig. 12 shows the variation of total subthreshold
leakage current with increasing Vss. The subthreshold
current falls until Vss rises to 0.15V.
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60.0n
58.0n
16.0n
Total Subthreshold Leakage(A)
54.0n
14.0n 52.0n
50.0n
48.0n
12.0n
46.0n
44.0n
10.0n 0.0 0.1 0.2 0.3 0.4 0.5
Vss(V)
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