Protocol Verification using

SystemVerilog Assertions
December is usually the time of holidays, relatively work load etc. Given the challenging job
scenario this is also the best time to hone your skills and face the New Year with new skills,
explore new job avenues, segments etc.
CVC is announcing a week long certificate course on standard protocol verification. At the end
of this course you would have finished developing a MIP (Monitor IP) for a standard protocol
based on SVA. Assertions are very powerful to capture temporal behavior. Broadly it covers the
following topics:
• ABV Introduction
• SystemVerilog Assertions (SVA)
• Project – develop a real life Protocol Monitor IP (MIP) with SVA
Course contents: http://www.cvcblr.com/trng_profiles/CVC_LG_SVA_profile.pdf
Topic Duration
SystemVerilog Assertions 2.0 days
Project 3.0 days

Schedule
Tentative: 2nd week of December, 2009
For exact schedule visit http://www.cvcblr.com/blog/ or contact us.
Contact

Send an email to: training@cvcblr.com and/or cvc.training@gmail.com for more details, cost
etc. Or call us at: +91-9620209226/+91-80-42134156

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