Note: Within nine months of the publication of the mention of the grant of the European patent in the European

Patent
Bulletin, any person may give notice to the European Patent Office of opposition to that patent, in accordance with the
Implementing Regulations. Notice of opposition shall not be deemed to have been filed until the opposition fee has been
paid. (Art. 99(1) European Patent Convention).
Printed by Jouve, 75001 PARIS (FR)
(19)
E
P
1

0
5
4

4
5
1
B
1
*EP001054451B1*
(11) EP 1 054 451 B1
(12) EUROPEAN PATENT SPECIFICATION
(45) Date of publication and mention
of the grant of the patent:
02.07.2014 Bulletin 2014/27
(21) Application number: 00401276.1
(22) Date of filing: 10.05.2000
(51) Int Cl.:
H01L 29/78
(2006.01)
H01L 29/423
(2006.01)
H01L 29/10
(2006.01)
H01L 29/08
(2006.01)
H01L 29/06
(2006.01)
H01L 21/336
(2006.01)
(54) MOS-gated power device and process for forming the same
MOS-gesteuerte Leistungsanordnung und Verfahren zu deren Herstellung
Dispositif de puissance commande de type MOS et sa mthode de fabrication
(84) Designated Contracting States:
DE FR GB IT SE
(30) Priority: 19.05.1999 US 314323
(43) Date of publication of application:
22.11.2000 Bulletin 2000/47
(73) Proprietor: Fairchild Semiconductor Corporation
South Portland, ME 04106 (US)
(72) Inventor: Kocon, Christopher
Plains, PA 18705 (US)
(74) Representative: Schmidt, Steffen J.
Wuesthoff & Wuesthoff
Patent- und Rechtsanwlte
Schweigerstrasse 2
81541 Mnchen (DE)
(56) References cited:
WO-A-00/05767 WO-A-02/37569
DE-A- 19 736 981
BULUCEA C ET AL: "TRENCH DMOS
TRANSISTOR TECHNOLOGY FOR HIGH-
CURRENT (100 A RANGE) SWITCHING" SOLID
STATE ELECTRONICS, vol. 34, no. 5, May 1991
(1991-05), pages 493-507, XP000201893
ELSEVIER SCIENCE PUBLISHERS, BARKING,
GB ISSN: 0038-1101
EP 1 054 451 B1
2
5
10
15
20
25
30
35
40
45
50
55
Description
[0001] The present invention relates to semiconductor
devices and, in particular, to a trench MOS-gated power
device having a doped zone separated laterally from a
drain zone by a trench.
[0002] A MOS transistor having a trench gate structure
offers important advantages over a planar transistor for
high current, low voltage switching applications. The
DMOS trench gate includes a trench extending from the
source to the drain and having sidewalls and a floor that
are each lined with a layer of thermally grown silicon di-
oxide. The lined trench is filled with doped polysilicon.
The structure of the trench gate allows less constricted
current flow and, consequently, provides lower values of
specific on-resistance. Furthermore, the trench gate
makes possible a decreased cell pitch in an MOS channel
extending along the vertical sidewalls of the trench from
the bottom of the source across the body of the transistor
to the drain below. Channel density is increased, which
reduces the contribution of the channel to on-resistance.
The structure and performance of trench DMOS transis-
tors are discussed in Bulucea and Rossen, "Trench
DMOS Transistor Technology for High-Current (100 A
Range) Switching," in Solid-State Electronics, 1991, Vol.
34, No. 5, pp 493-507. In addition to their utility in DMOS
devices, trench gates are also advantageously employed
in insulated gate bipolar transistors (IGBTs), MOS-con-
trolled thyristors (MCTs), and other MOS-gated devices.
[0003] FIG. 1 schematically depicts the cross-section
of a trench-gated N-type MOSFET device 100 of the prior
art formed on an upper layer 101a of an N+ substrate
101. Device 100 includes a trench 102 whose sidewalls
104 and floor 103 are lined with a gate dielectric such as
silicon dioxide. Trench 102 is filled with a conductive ma-
terial 105 such as doped polysilicon, which serves as an
electrode for gate region 106.
[0004] Upper layer 101a of substrate 101 further in-
cludes P-well regions 107 overlying an N-drain zone 108.
Disposed within P-well regions 107 at an upper surface
109 of upper layer 101a are heavily doped P+body re-
gions 110 and heavily doped N+ source regions 111. Am
interlevel dielectric layer 112 is formed over gate region
106 and source regions 111. Contact openings 113 en-
able metal layer 114 to contact body regions 110 and
source regions 111. The rear side 115 of N+ substrate
101 serves as a drain.
[0005] Although FIG.1 shows only one MOSFET, a de-
vice currently employed in the industry consists of an
array of them arranged in various cellular or stripe lay-
outs.
[0006] German patent application DE 197 36 981 A1
describes a vertical transistor made up of multiple cells
in which an insulator under the gate extends to the sub-
strate with opposite conductivity type drift regions on ei-
ther side of the insulator.
[0007] As a result of recent semiconductor manufac-
turing improvements enabling increased densities of
trench gated devices, the major loss in a device when in
a conduction mode occurs in its lower zone, i.e., in-
creased drain resistivity. Because the level of drain dop-
ing is typically determined by the required voltage block-
ing capability, increased drain doping for reducing resis-
tivity is not an option. Thus, there is a need for reducing
the resistivity of the drain region in a semiconductor de-
vice without also reducing its blocking capability. The
present invention meets this need. A trench MOS-gated
device in accordance with the present invention is set
out in claim 1.
[0008] A process for forming a trench MOS-gated de-
vice in accordance with the present invention is moreover
defined in independent claim 6.
[0009] Specific embodiments are disclosed in the de-
pendent claims.
[0010] The invention will also be discussed, by way of
example, with reference to the accompanying drawings
in which:
FIG. 1 schematically depicts a cross-section of a
trenchMOS-gated device 100 of the prior art.
FIG. 2 is a schematic cross-sectional representation
of a trench MOS-gated device 200 of the present
invention,
FIGS. 2A-D schematically depict a process for form-
ing device 200 of the present invention.
[0011] In FIG. 2 is schematically depicted the cross-
section of an MOS-gated power device 200 of the present
invention. In an upper layer 201a of a substrate 201 is
constructed a trench 202 that is partially filled with die-
lectric material 203. The upper portion 202a of trench
202 is lined with dielectric sidewalls 204 and filled with
conductive material 205. Dielectric material 203 and side-
walls 204 can consist of silicon dioxide, and conductive
material 205 can be doped polysilicon. Conductive ma-
terial 205 insulated by dielectric material 203 and side-
walls 204 serves as an electrode for a gate region 206
in the upper portion of trench 202.
[0012] On one side of trench 202 is a P-well region 207
overlying an N-drain zone 208. Disposed within P-well
region 207 at upper surface 209 is a heavily doped P+
body region 210 and a heavily doped N+ source region
211. On the other side of trench 202 is a doped P-zone
212. Trench 202 laterally separates doped P-zone 212
from drain zone 208, which are of opposite conduction
types. Drain zone 208 extends beneath trench 202 and
doped P-zone 212. An interlevel dielectric layer 213 is
formed over gate region 206, source region 211, and
doped P-zone 212. Contact openings 214 enable metal
layer 215 to contact body and source regions 210 and
211, respectively. A heavily doped N+ drain region is dis-
posed at the rear side 216 of substrate 201.
[0013] Doped P-zone 212 serves to deplete charge
when blocking voltage is applied, allowing a much higher
conductivity material to be used for drain construction
and thereby reducing the on-resistance of the device and
1 2
EP 1 054 451 B1
3
5
10
15
20
25
30
35
40
45
50
55
improving its efficiency. Dielectric material 203 in lower
trench portion 202b, which can beneficially be narrower
than upper trench portion 202a, prevents lateral diffusion
of dopants from doped P-zone 212 into N-drain zone 208.
Doped P-zone 212, which is thus self-aligned with gate
region 206, is shorted to source region 211 by metal layer
215. Self-alignment allows the use of structure 200 for
making high density devices with blocking voltage capa-
bilities well below 100 V. Since dielectric material 203
serves only as a barrier to dopant diffusion, its quality is
not important to the performance of device 200, which
would still function even if zones 208 and 212 were elec-
trically shorted through dielectric material 203. However,
drain zone 208 is substantially insulated laterally from
doped P-zone 212 by the thick dielectric layer formed in
the bottom of trench 202 by dielectric material 203. When
device 200 is in the blocking state, zones 208 and 212
will contribute charges with opposite signs, but the in-
duced fields in both zones will cancel out. This allows the
use of much higher doping for doped P-zone 212 and
particularly for N-drain zone 208. Current flowing through
drain zone 208 thereby undergoes a much lower resist-
ance drop, which in turn reduces the device overall on-
resistance and improves its efficiency.
[0014] The described conduction types can be re-
versed, N for P and P for N. The described device is a
power MOSFET.
[0015] A process for making MOS-gated device 200 is
schematically depicted in FIGS. 2A-D. As shown in FIG.
2A, trench 202 is etched into upper layer 201a of sub-
strate 201 and filled with dielectric material 203a, prefer-
ably oxide. A planarization etch step can be used to
planarize dielectric material 203a with upper surface 209
of upper layer 201a. A P-dopant is selectively implanted,
using standard photolithography techniques, on one side
of trench 202. High temperature diffusion drives the do-
pant deep into layer 201a, thereby forming doped P-zone
212, as depicted in FIG. 2B.
[0016] Dielectric layer 203a is recessed below upper
surface 209 to a selected depth using dry etching tech-
niques, leaving thick oxide layer 203 in the bottom portion
of trench 202. Oxide dielectric sidewalls 204 are formed
in the upper portion of trench 202, which is then filled with
conductive polysilicon 205, as shown in FIG. 2C. P-well
region 207 is implanted into upper layer 201a on the side
of trench 202 opposite that of doped P-zone 212, and P+
body region 210 and N+ source region 211 are implanted
into well region 207. Deposition of interlevel dielectric
layer 213 and metal layer 215 and formation of contact
openings 214 completes the fabrication of device 200,
as depicted in FIG. 2D.
Claims
1. A trench MOS-gated device (200) comprising a sub-
strate (201) including an upper layer (201a), said
substrate comprising doped monocrystalline semi-
conductor material of a first conduction type, a trench
(202) in said upper layer, said trench having a bottom
portion (202b) filled with a dielectric material (203),
said material forming a thick dielectric layer in said
bottom of said trench, said trench further having an
upper portion (202a) lined with sidewalls (204) con-
sisting of a dielectric material and filled with a con-
ductive material (205), said filled upper portion of
said trench forming a gate region (206), wherein a
doped zone (212) of a second conduction type op-
posite said first conduction type extends from an up-
per surface (209) into said upper layer on one side
of said trench, a drain zone (208) of said first con-
duction type in said upper layer on a further side of
said trench opposite said doped zone extends be-
neath said trench and said doped zone, said drain
zone being substantially insulated laterally from said
doped zone by said thick dielectric layer in said bot-
tom portion of said trench, a doped well region (207)
of said second conduction type overlies said drain
zone in said upper layer on said further side of said
trench, a heavily doped source region (211) of said
first conduction type and a heavily doped body region
(210) of said second conduction type are disposed
in said well region at said upper surface, an interlevel
dielectric layer (213) on said upper surface overlies
said gate and source regions, a metal layer (215)
overlies said upper surface and said interlevel die-
lectric layer, said metal layer being in electrical con-
tact with said source and body regions and said
doped zone, and a heavily doped drain region (216)
of said first conduction type is disposed at a lower
surface of said substrate and extends beneath said
drain zone.
2. A device as claimed in claim 1, wherein said doped
zone extends downwardly in said upper layer to a
depth substantially equal to the depth of the bottom
of said trench, and said lower portion of said trench
is narrower than said upper portion.
3. A device as claimed in claim 2, wherein said upper
layer is an epitaxial layer, said substrate comprises
monocrystalline silicon, said dielectric material com-
prises silicon dioxide, and said conductive material
in said trench comprises doped polysilicon.
4. A device as claimed in claim 1, wherein said first
conduction type is N and said second conduction
type is P.
5. A device as claimed in claim 1, wherein said device
comprises a plurality of trenches, said plurality of
trenches have an open-cell stripe topology, or said
plurality of trenches have a closed-cell cellular topol-
ogy.
6. A process for forming a trench MOS-gated device
3 4
EP 1 054 451 B1
4
5
10
15
20
25
30
35
40
45
50
55
(200), said process comprising forming a trench
(202) in an upper layer (201a) of a substrate (201),
said substrate comprising doped monocrystalline
semiconductor material of a first conduction type,
filling said trench with a dielectric material (203), se-
lectively implanting and diffusing a dopant of a sec-
ond conduction type opposite said first conduction
type into said upper layer on one side of said trench,
thereby forming a doped zone (212) of said second
conduction type extending from an upper surface
(209) into said upper layer, removing a selected por-
tion of said dielectric material from an upper portion
(202a) of said trench, leaving a thick dielectric layer
in a bottom portion (202b) of said trench, forming
sidewalls (204) consisting of a dielectric material on
the upper portion of said trench and filling said upper
portion with a conductive material (205), thereby
forming a gate region (206) in said upper portion of
said trench, forming a doped well region (207) of said
second conduction type in said upper layer on a fur-
ther side of said trench opposite said doped zone,
forming a heavily doped source region (211) of said
first conduction type and a heavily doped body region
(210) of said second conduction type in said well
region at said upper surface, forming an interlevel
dielectric layer (213) on said upper surface overlying
said gate and source regions, forming a metal layer
(215) overlying said upper surface and said interlevel
dielectric layer, said metal layer being in electrical
contact with said source and body regions and said
doped zone, forming a drain zone (208) of said first
conduction type in said upper layer on said further
side of said trench, said drain zone extending be-
neath said well region, said trench and said doped
zone and being substantially insulated laterally from
said doped zone by said thick dielectric layer in said
bottom portion of said trench, and forming a heavily
doped drain region (216) of said first conduction type
at a lower surface of said substrate, said heavily
doped drain region extending beneath said drain
zone.
7. A process as claimed in claim 6, wherein said upper
layer is an epitaxial layer, said substrate comprises
monocrystalline silicon, said dielectric material com-
prises silicon dioxide, and said conductive material
in said trench comprises doped polysilicon.
8. A process as claimed in any one of claims 6 and 7,
wherein said first conduction type is N and said sec-
ond conduction type is P, and the process comprises
forming a plurality of extended trenches in said sub-
strate.
9. A process as claimed in claim 8, wherein said plu-
rality of trenches have an open-cell stripe technolo-
gy, or said plurality of trenches have a closed-cell
cellular topology.
Patentansprche
1. Graben-MOS-Gate-Vorrichtung (200), umfassend:
ein Substrat (201), das eine obere Schicht (201a)
aufweist, wobei das Substrat ein dotiertes monokris-
tallines Halbleitermaterial eines ersten Leitungstyps
umfasst, einen Graben (202) in der oberen Schicht,
wobei der Graben einen mit einem dielektrischen
Material (203) gefllten Bodenbereich (202b) be-
sitzt, wobei das Material eine dicke dielektrische
Schicht im Boden des Grabens ausbildet, wobei der
Graben weiterhin einen oberen Bereich (202a) be-
sitzt, der mit Seitenwnden (204) ausgekleidet ist,
die aus einem dielektrischen Material bestehen, und
mit einem leitfhigen Material (205) gefllt ist, wobei
der gefllte obere Bereich des Grabens eine Gate-
Region (206) bildet, wobei sich eine dotierte Zone
(212) eines zum ersten Leitungstyp gegenstzlichen
zweiten Leitungstyps auf einer Seite des Grabens
von einer oberen Oberflche (209) in die obere
Schicht erstreckt, sich eine Drain-Zone (208) des
ersten Leitungstyps in der oberen Schicht auf einer
weiteren Seite des Grabens gegenber der dotierten
Zone unter den Graben und die dotierte Zone er-
streckt, wobei die Drain-Zone seitlich durch die dicke
dielektrische Schicht im Bodenbereich des Grabens
von der dotierten Zone im Wesentlichen isoliert ist,
eine dotierte Wannenregion (207) des zweiten Lei-
tungstyps die Drain-Zone in der oberen Schicht auf
der weiteren Seite des Grabens berlagert, eine
stark dotierte Source-Region (211) des ersten Lei-
tungstyps und eine stark dotierte Body-Region (210)
des zweiten Leitungstyps in der Wannenregion an
der oberen Oberflche angeordnet sind, eine dielek-
trische Zwischenebenenschicht (213) an der oberen
Oberflche die Gate- und die Source-Region ber-
lagert, eine metallische Schicht (215) die obere
Oberflche und die dielektrische Zwischenebenen-
schicht berlagert, wobei die metallische Schicht in
elektrischem Kontakt mit der Source- und der Body-
Region und der dotierten Zone steht, und eine stark
dotierte Drain-Region (216) des ersten Leitungstyps
an einer unteren Oberflche des Substrats angeord-
net ist und sich unterhalb der Drain-Zone erstreckt.
2. Vorrichtung nach Anspruch 1,
wobei sich die dotierte Zone in der oberen Schicht
nach unten bis zu einer Tiefe erstreckt, die im We-
sentlichen der Tiefe des Bodens des Grabens gleich
ist, und der untere Bereich des Grabens schmler
ist als der obere Bereich.
3. Vorrichtung nach Anspruch 2,
wobei es sich bei der oberen Schicht um eine Epi-
taxieschicht handelt, das Substrat monokristallines
Silicium umfasst, das nichtleitende Material Silicium-
dioxid umfasst und das leitfhige Material im Graben
dotiertes Polysilicium umfasst.
5 6
EP 1 054 451 B1
5
5
10
15
20
25
30
35
40
45
50
55
4. Vorrichtung nach Anspruch 1,
wobei es sich bei dem ersten Leitungstyp um N und
bei dem zweiten Leitungstyp um P handelt.
5. Vorrichtung nach Anspruch 1,
wobei die Vorrichtung eine Vielzahl von Grben um-
fasst, die Vielzahl von Grben eine offenzellige Strei-
fentopologie besitzt oder die Vielzahl von Grben
eine geschlossenzellige Zellentopologie besitzt.
6. Verfahren zum Ausbilden einer Graben-MOS-Gate-
Vorrichtung (200), wobei das Verfahren umfasst:
Ausbilden eines Grabens (202) in einer oberen
Schicht (201a) eines Substrates (201), wobei das
Substrat ein dotiertes monokristallines Halbleiter-
material eines ersten Leitungstyps umfasst, Fllen
des Grabens mit einem dielektrischen Material
(203), selektives Implantieren und Diffundieren las-
sen eines Dotiermittels eines zum ersten Lei-
tungstyp gegenstzlichen zweiten Leitungstyps in
die obere Schicht auf einer Seite des Grabens, wo-
durch eine dotierte Zone (212) des zweiten Lei-
tungstyps ausgebildet wird, die sich von einer oberen
Oberflche (209) in die obere Schicht erstreckt, Ent-
fernen eines ausgewhlten Bereichs des dielektri-
schen Materials von einem oberen Bereich (202a)
des Grabens, Belassen einer dicken dielektrischen
Schicht in einem Bodenbereich (202b) des Grabens,
Ausbilden von aus einem dielektrischen Material be-
stehenden Seitenwnden (204) am oberen Bereich
des Grabens und Fllen des oberen Bereichs mit
einem leitfhigen Material (205), wodurch eine Gate-
Region (206) im oberen Bereich des Grabens aus-
gebildet wird, Ausbilden einer dotierten Wannenre-
gion (207) des zweiten Leitungstyps in der oberen
Schicht auf einer weiteren Seite des Grabens ge-
genber der dotierten Zone, Ausbilden einer stark
dotierten Source-Region (211) des ersten Lei-
tungstyps und einer stark dotierten Body-Region
(210) des zweiten Leitungstyps in der Wannenregion
an der oberen Oberflche, Ausbilden einer dielekt-
rischen Zwischenebenenschicht (213) an der obe-
ren Oberflche, welche die Gate- und die Source-
Region berlagert, Ausbilden einer metallischen
Schicht (215), welche die obere Oberflche und die
dielektrische Zwischenebenenschicht berlagert,
wobei die metallische Schicht in elektrischem Kon-
takt mit der Source- und der Body-Region und der
dotierten Zone steht, Ausbilden einer Drain-Zone
(208) des ersten Leitungstyps in der oberen Schicht
auf der weiteren Seite des Grabens, wobei sich die
Drain-Zone unter die Wannenregion, den Graben
und die dotierte Zone erstreckt und seitlich durch die
dicke dielektrische Schicht im Bodenbereich des
Grabens von der dotierten Zone im Wesentlichen
isoliert ist, und Ausbilden einer stark dotierten Drain-
Region (216) des ersten Leitungstyps an einer un-
teren Oberflche des Substrats, wobei sich die stark
dotierte Drain-Region unter die Drain-Zone er-
streckt.
7. Verfahren nach Anspruch 6,
wobei es sich bei der oberen Schicht um eine Epi-
taxieschicht handelt, das Substrat monokristallines
Silicium umfasst, das nichtleitende Material Silicium-
dioxid umfasst, und das leitfhige Material im Gra-
ben dotiertes Polysilicium umfasst.
8. Verfahren nach einem der Ansprche 6 und 7,
wobei es sich bei dem ersten Leitungstyp um N und
dem zweiten Leitungstyp um P handelt, und das Ver-
fahren das Ausbilden einer Vielzahl ausgedehnter
Grben im Substrat umfasst.
9. Verfahren nach Anspruch 8,
wobei die Vielzahl von Grben eine offenzellige
Streifentechnologie besitzt oder die Vielzahl von
Grben eine geschlossenzellige Zellentopologie be-
sitzt.
Revendications
1. Dispositif tranche et grille MOS (200) comprenant
un substrat (201) contenant une couche suprieure
(201a), ledit substrat comprenant un matriau
semi-conducteurs monocristallin dop dun premier
type de conduction, une tranche (202) dans ladite
couche suprieure, ladite tranche ayant une partie
de fond (202b) remplie de matriau dilectrique
(203), ledit matriau formant une couche dilectri-
que paisse dans ledit fond de ladite tranche, ladite
tranche ayant en outre une partie suprieure (202a)
double de parois latrales (204) compose dun
matriau dilectrique et remplie dun matriau con-
ducteur (205), ladite partie suprieure remplie de la-
dite tranche formant une rgion de grille (206), dans
lequel une zone dope (212) dun second type de
conduction, oppos audit premier type de conduc-
tion, stend depuis une surface suprieure (209)
dans ladite couche suprieure sur un ct de ladite
tranche, une zone de drain (208) dudit premier type
de conduction dans ladite couche suprieure sur un
autre ct de ladite tranche, oppos ladite zone
dope stend en-dessous de ladite tranche et la-
dite zone dope, ladite zone de drain tant sensible-
ment isole au plan latral de ladite zone dope par
ladite couche dilectrique paisse dans ladite partie
de fond de ladite tranche, une rgion de puits dope
(207) dudit second type de conduction chevauchant
ladite zone de drain dans ladite couche suprieure
sur ledit autre ct de ladite tranche, une rgion de
source fortement dope (211) dudit premier type de
conduction et une rgion de corps fortement dope
(210) dudit second type de conduction sont dispo-
ses dans ladite rgion de puits au niveau de ladite
7 8
EP 1 054 451 B1
6
5
10
15
20
25
30
35
40
45
50
55
surface suprieure, une couche dilectrique interpo-
se (213) sur ladite surface suprieure chevauche
lesdites rgions de source et de grille, une couche
mtallique (215) chevauche ladite surface suprieu-
re et ladite couche dilectrique interpose, ladite
couche mtallique tant en contact lectrique avec
lesdites rgions de corps et de source et ladite zone
dope et une rgion de drain fortement dope (216)
dudit premier type de conduction est dispose au
niveau dune surface infrieure dudit substrat et
stend en-dessous de ladite zone de drain.
2. Dispositif tel que revendiqu dans la revendication 1,
dans lequel ladite zone dope stend vers le bas
dans ladite couche suprieure, jusqu une profon-
deur sensiblement gale la profondeur du fond de
ladite tranche et ladite partie infrieure de ladite
tranche est plus troite que ladite partie suprieure.
3. Dispositif tel que revendiqu dans la revendication 2,
dans lequel ladite couche suprieure est une couche
pitaxiale, ledit substrat comprend du silicium mo-
nocristallin, ledit matriau dilectrique comprend du
dioxyde de silicium et ledit matriau conducteur dans
ladite tranche comprend du polysilicium dop.
4. Dispositif tel que revendiqu dans la revendication 1,
dans lequel ledit premier type de conduction est N
et ledit second type de conduction est P.
5. Dispositif tel que revendiqu dans la revendication 1,
dans lequel ledit dispositif comprend une pluralit de
tranches, ladite pluralit de tranches prsentent
une topologie de ruban cellule ouverte ou ladite
pluralit de tranches prsentent une topologie cel-
lulaire cellule ferme.
6. Procd de formation dun dispositif tranche et
grille MOS (200), ledit procd comprenant la for-
mation dune tranche (202) dans une couche su-
prieure (201a) dun substrat (201), ledit substrat
comprenant un matriau semi-conducteurs mono-
cristallin dop dun premier type de conduction, le
remplissage de ladite tranche avec un matriau di-
lectrique (203), limplantation slective et la diffusion
dun dopant dun second type de conduction, oppos
audit premier type de conduction, dans ladite couche
suprieure sur un ct de ladite tranche, formant
ainsi une zone dope (212) dudit second type de
conduction stendant depuis une surface suprieu-
re (209) dans ladite couche suprieure, le retrait
dune partie slectionne dudit matriau dilectrique
dune partie suprieure (202a) de ladite tranche,
laissant une couche dilectrique paisse dans une
partie de fond (202b) de ladite tranche, la formation
de parois latrales (204) composes dun matriau
dilectrique sur la partie suprieure de ladite tran-
che et le remplissage de ladite partie suprieure
avec un matriau conducteur (205), formant ainsi
une rgion de grille (206) dans ladite partie sup-
rieure de ladite tranche, la formation dune partie
de puits dope (207) dudit second type de conduc-
tion dans ladite couche suprieure sur un autre ct
de ladite tranche, oppos ladite zone dope, la
formation dune rgion de source fortement dope
(211) dudit premier type de conduction et dune r-
gion de corps fortement dope (210) dudit second
type de conduction dans ladite rgion de puits au
niveau de ladite surface suprieure, la formation
dune couche dilectrique interpose (213) sur ladite
surface suprieure, chevauchant lesdites rgions de
source et de grille, la formation dune couche mtal-
lique (215) chevauchant ladite surface suprieure et
ladite couche dilectrique interpose, ladite couche
mtallique tant en contact lectrique avec lesdites
rgions de corps et de source et ladite zone dope,
la formation dune zone de drain (208) dudit premier
type de conduction dans ladite couche suprieure
sur ledit autre ct de ladite tranche, ladite zone de
drain stendant en-dessous de ladite rgion de
puits, ladite tranche et ladite zone dope et tant
sensiblement isole au plan latral de ladite zone
dope par ladite couche dilectrique paisse dans
ladite partie de fond de ladite tranche et la formation
dune rgion de drain fortement dope (216) dudit
premier type de conduction au niveau dune surface
infrieure dudit substrat, ladite rgion de drain forte-
ment dope stendant en-dessous de ladite zone
de drain.
7. Procd tel que revendiqu dans la revendication 6,
dans lequel ladite couche suprieure est une couche
pitaxiale, ledit substrat comprend du silicium mo-
nocristallin, ledit matriau dilectrique comprend du
dioxyde de silicium et ledit matriau conducteur dans
ladite tranche comprend du polysilicium dop.
8. Procd tel que revendiqu dans lune quelconque
des revendications 6 et 7,
dans lequel ledit premier type de conduction est N
et ledit second type de conduction est P et le procd
comprend la formation dune pluralit de tranches
tendues dans ledit substrat.
9. Procd tel que revendiqu dans la revendication 8,
dans lequel ladite pluralit de tranches prsentent
une technologie de ruban cellule ouverte ou ladite
pluralit de tranches prsentent une topologie cel-
lulaire cellule ferme.
9 10
EP 1 054 451 B1
7
EP 1 054 451 B1
8
EP 1 054 451 B1
9
EP 1 054 451 B1
10
REFERENCES CITED IN THE DESCRIPTION
This list of references cited by the applicant is for the readers convenience only. It does not form part of the European
patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be
excluded and the EPO disclaims all liability in this regard.
Patent documents cited in the description
DE 19736981 A1 [0006]
Non-patent literature cited in the description
BULUCEA ; ROSSEN. Trench DMOS Transistor
Technology for High-Current (100 A Range) Switch-
ing. Solid-State Electronics, 1991, vol. 34 (5),
493-507 [0002]