CMOS Inverter Manual

Developed By
University Program Team
CoreEL Technologies (I) Pvt. Ltd.

Introduction
This manual introduces you to the Schematic Driven Layout (SDL) IC design flow. You will learn
the design flow from the Schematic to GDSII with the help of Pyxis Schematic, Pyxis Layout
(ICGraph), Calibre and ELDO.
In this manual introduces you to the design of a basic gate, A CMOS Inverter. You will learn to
build an Inverter schematic, generate a symbol with Pyxis Schematic. The schematic design is
followed by the simulation and circuit verification (Transient Analysis and DC Analysis) with the
help of the simulation tool ELDO. The simulated results are viewed with the help of EZviewer
and the results a documented.
After the schematic entry and design verification, we proceed with the layout for the inverter.
Pyxis Layout Editor (ICgraph) is used for Schematic Driven Layout (SDL), as the name
suggests the layout is drawn with the help of Schematic, where in the devices and ports are
instantiated from the schematic. After laying out the layout in the Layout Editor you will perform
physical verification which includes DRC, LVS using Calibre. Finally, you will extract the
parasitic for the inverter and back annotate the design.
















Open the Mentor Server.
1. Xmanager is used to access the remote Linux server from the windows client. Open the folder
Xmanager Enterprise 3 to view the various options as in the figure 1 below.

Figure 1. Xmanager Enterprise 3 folder.
2. Click on Xstart to start the remote access server. Ensure that the fields highlighted in the figure 2
are filled accordingly.

Figure 2. Xstart Remote access server.
Open Server
Server IP Address

Figure 3. Xstart Remote access server.
3. The IP address of the linux server has to be filled in the HOST tab.
4. The protocol to be used to access the server is SSH.
5. Appropriate username and password are entered, check the save option.
6. Click on the dropdown for execution command and select the option 3 xterm (Linux: Type 2).
7. Click on save to save the settings for the session as in figure 3.
8. Click run (see figure 3).This will open a terminal as in figure 4 below.

Figure 4. Linux Terminal

9. Always create a new folder for a new project and then proceed, this is the good design process.
10. Create a new folder for the project using the command mkdir in the user directory. Navigate to
the new folder using cd command.
11. Source the *.cshrc file present at /home/software/cshrc to set the environment variables, use
the command source /home/software/cshrc/file_name.cshrc.
12. Invoke Pyxis Schematic with the command da_ic & , similarly for Pyxis Layout Editor run the
command ic &.
Creating a New Schematic
1. Invoke Pyxis Schematic using the command da_ic &. The Pyxis interface appears on the screen
as shown in the figure 4.


Figure 5. Pyxis Schematic Window

2. To create a new schematic click on New > Schematic, the new schematic wizard opens to
create a schematic.



Figure 6. New Schematic Wizard in Pyxis
3. Enter the design name in the file name tab and click on ok as shown in the figure 6.
4. The schematic window opens as shown below in the figure 7.

Figure 7. Pyxis window with Library on the right palate window.

5. It is in the schematic window we draw a schematic for any design.
6. .bIn the right palate window we can see Library (Figure 7) which opens a new palate with Device
Lib, Sources Lib, Generic Lib, Macro Lib and Verilog Primitive Lib.
a. Device Lib has all the devices I need for drawing my schematic (PMOS, NMOS,
Resistors, Capacitance).
b. Generic Lib has all the Ports and Global Variables I need for my schematic (input,
output, VDD, GND, etc).
c. Sources Lib has the various sources I require for my device to operate (Voltage and
current source).
Note: The model files provided by Mentor Graphics will support PMOS 4-pin, NMOS 4-pin, Resistance
and Capacitance.
7. To place the device in the schematic window click on Library > Device Lib in the IC Library
palate window and choose PMOS Transistor (4-pin) and place it on the schematic window,
similarly place the NMOS Transistor (4-pin).
8. Change the Transistor properties by selecting the transistor symbol (PMOS or NMOS) , press
Q or right click the selected device choose edit properties and change the ASIM_Model
name, Length (L) and Width (W)
PCH to P | L = 2u | W = 13u
NCH to N | L = 2u | W = 5u
9. The transistor placement is followed by the port (input and output) placement, In the IC Library
palate window click Library > Generic Lib > Port in under Ports for input ports and Library >
Generic Lib > Port out under Ports for output port and place it in the schematic window or you
can add ports with the shortcut on the left palate window as shown in figure 8.
10. To add VDD click on Library > Generic Lib > VDD under Globals and to add ground click on
Library > Generic Lib > ground under Globals in the IC Library palate window.

Figure 8. Schematic of Inverter
11. To change the net names, right click on the port select edit properties from the options change
the net name.
12. The connections are made using add wire from the palate window on the right side as shown in
the figure 8.
13. One click to start the wire, another click to turn and double click to end the wire.
14. After the complete wiring you will check and save the schematic as show in figure 8.








Creating a Symbol
1. Now we proceed to create a symbol which will help me instantiate the symbol multiple times in
any schematic.
2. To create a symbol, from the menu bar at the top click Add > Generate Symbol.
3. Check Replace Existing and Activate Symbol option as shown in figure 9.a.
4. Choose a shape for symbol (Buffer in this case which is similar to an inverter, just that a
bubble needs to be inserted)
5. Click ok to generate a symbol.

Figure 9.a. Add symbol for inverter.


Figure 9.b. Symbol for inverter before and after editing.

6. A Symbol Sheet open with buffer as shown in figure 9 A.
7. Edit the buffer to make it resemble an inverter symbol as shown in figure 9 B. Check and Save
the symbol.
Note: We can only make or edit a symbol in the symbol page.
It must also be noted the shape of the symbol doesnt matter it is the schematic within it that
defines the symbol.

A B
Test bench Creation
1. Close all the windows inside Pyxis (schematic and symbol).
2. Create another new Schematic.
3. We will instantiate the inverter symbol here to create a test bench for simulations.
4. To add the symbol on to the schematic, go to Add > Instance > Choose symbol.
5. Add input and output ports from Library > Generic Lib > Portin and Library > Generic Lib >
Portout in the IC Library palate window as shown in figure 10.
6. Add the sources to the schematic, Global DC and Pulse wave, from Library > Sources Lib >
PULSE (V) and Library > Sources Lib > DC (V) in the IC Library palate window as shown in
figure 10 and change the net names.
7. Click back in the Sources Lib window and come back to IC Library palate.
8. To edit the properties of Pulse source, right click on Pulse (V) and select edit properties.
9. Edit the Properties as below
Initial = 0V | Pulse = 5V | Delay = 10nS | Rise = 1nS
Fall = 1nS | Width = 25nS | Period = 50ns.

10. To edit the properties of DC source, right click on DC (V) and select edit properties.
DC = 5V
11. Complete the connections using wire as shown in figure 10.

Figure 10: Test Bench for Inverter simulation.
12. Check & save the test bench to report any errors.



Simulation
1. In the IC Library palate window click on Simulation.
2. The Entering Simulation mode window will pop up as shown in figure 11 (A).
3. To create a new configuration click on New Design Configuration as seen in figure 11 (B).
4. The New Design Configuration window will pop up as seen in figure 11 (D)
Enter a name and select the simulation type Eldo | ADMS | ADiT. Default simulation type is Eldo
and click ok as in figure 11 (C, E& F).
5. The new configuration is now displayed in the Design Configuration list.
6. Click ok and At this point, Pyxis Schematic is in Simulation Mode; and the Design
Configuration has been initialized.
7. Eldo simulator work in command prompt. Here with the help of pyxis schematic we are
creating the setup file for eldo simulation, a *.cir file is created at the end of this setup.

Figure 11: Simulation mode in Pyxis.
8. For Eldo simulator to run a simulation 4 basic setups are required-
a. A spice netlist of the schematic.
b. A model file targeting a technology node must be selected.
c. The Analysis type (DC, Transient, AC etc..).
d. The appropriate nets where the simulation results are to be plotted as a waveform.

Figure 12. Schematic Simulation setup
9. As discussed in step 8; b, c and d setups are shown in figure 12 under schematic sim.
10. To include the model files (b), click on Lib/Temp/Inc in the schematic sim palate window this
opens a drop down. Click on Include file in the dropdown.
11. The Setup Simulation window pops up as shown in figure 13.

Figure 13. File browser to include model file.
Browse Location Map
Browse
b and c
d
12. Click on the browse ( ) which opens the file browser as shown in figure 13.
13. In the file browser click on browse location map ( ) as shown in figure 13.
14. To select the model file double click on $MODELS which open the model folder as shown in
figure 13, select the appropriate model file and click ok.
15. Scroll down the Setup Simulation window and click apply. This adds the model file for
simulation.

Figure 14. Analysis setup for DC.
16. After the model files are added we need to configure the Analysis.
17. Click on Analysis (c) as shown in figure 12.
18. Below Analysis Selector box, various analyses are defined which are configured accordingly.
19. Select DC in Analysis Selector, and set as below, refer figure 14 for details
Sweep Type Source | click and select the Pulse source
Start 0 | Stop 5V | Step 10m
20. Scroll down and apply the DC settings.
21. Select TRAN in Analysis Selector, and set as below, refer figure 15 below for details
Start time 0 | Stop time 300ns
Note: Set the stop time for TRANSIENT Simulation based on the delay parameter for Pulse wave we
set during the test bench creation.
22. Scroll down and apply the TRAN settings.






Figure 15. Analysis setup for Transient.
23. With the analyses set. We select the appropriate nets where the results are to be plotted on a
waveform.
24. To select the nets (d), click on Outputs in the schematic sim palate which opens the Setup
Simulation window as below in figure 16.
25. Click on the schematic window, we need the results to be plotted for input net and output net.
26. Click on the input port, press control (to select multiple nets) and select the output port. Once
selected the nets are highlighted red.
27. Come back to the Setup simulation window. The selected nets will be listed under Specified
Outputs.
28. To view the currents in the nets, check Currents under Global Outputs as seen in figure 16
below.
29. To add the analyses to plot, in the same window select from the drop down next to Analysis
(Refer figure 16), select the Task as PLOT and click on Add.
Analysis DC | Analysis TRAN
Task PLOT | Task PLOT
30. Scroll down and click on apply.



Figure 16. Output setup.
31. This creates the configuration file for eldo simulation.
32. To start simulation click on Run ELDO.
33. In the Message Area if it reads simulation completed successfully, we can go ahead and see
the result. If it says simulation failed, read the error in log window and rectify it run the
simulation.
34. To view the waveform click on View Waves, this pops up the EZWave tool window with the
configured analyses as shown in figure 17.

Figure 17. Waveform for inverter simulation.
35. The DC analysis result waveform is a shown below in the figure 18.

Figure 18. DC Analysis Result for Inverter.
36. The waveform shows the DC response for inverter with the input voltage varying from 0V to 5V,
along with the current at the drain of NMOS as shown in figure 18.

Figure 19. TRANSIENT Analysis Result for Inverter.
37. Figure 19 shows the waveform for TRANSIENT Response for Inverter along with the current at
the drain of NMOS.
38. Select the output waveform and click on which open the measurement tool. In the
dropdown of measurement tool select Risetime / Falltime and click apply. The risetime and
falltime for the inverter are calculated as shown in figure 19.
39. This completes the procedure to draw a schematic and simulate the same and we can proceed to
draw the Layout.
40. Before we close the pyxis window, it necessary to change the ASIM_MODEL name of the
devices.
For PMOS, change from P to PMOS.
For NMOS, change from N to NMOS.