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Schematics tutorial

Spring 2004
Creating Schematic
(1) By this point you are in Cadence and have created a library Inverter and a layout
cellview Inv1.
(2) ow create a sche!atic cell view using" #ile$ew$Cell %iew. &his will open up a
new window. Choose the Inverter library and 'ill in the cell na!e with Inv1"
&hen( clic) o). &his will open up a blan) sche!atic window.
(*) Instantiate the transistor !odels 'ro! the library
(a) +ress ,i- while the sche!atic window is active. (.ou can also use the pull
down !enu 'ro! the sche!atic window). &his will bring up 2 windows as
shown below
(b) Choose the correct transistor !odel and 'ill the desired si/e. &hen clic) 0ide
and place the transistor in the sche!atic window.
(c) 1'ter you have placed all device sy!bols down. .ou can use wires (hot)ey w)
to connect all the devices together to create an inverter as shown below. 2se
1dd+in to put down input( output and supply pins that !atch the pins you
created in the layout view.
Cross Probing with Virtuoso Layout Editor and Schematic
Composer
3nce you have drawn both the layout and sche!atics( you can use the cross4
probing 'unction. &his allows you to select a piece o' layout and highlight the
corresponding ob5ect in the sche!atic( or vice versa. .ou can initiate cross probing 'ro!
either the 6ayout 7ditor or Sche!atic Co!poser.
Tools Setup
(1) Setup 6ayout 86. &his is a power'ul tool that allows you to 9uic)ly chec)
correspondence between sche!atic and layout views. In larger designs( 6ayout 86 can
be very use'ul in guiding you through layout based on an e:isting sche!atic.
3pen the sche!atic in Co!poser and choose &ools ;esign Synthesis 6ayout 86
'ro! the !enu.
Clic) 3< and the ne:t window will as) you to choose the layout view
&his will bring up side4by4side copies o' your sche!atic and layout views. &he layout
window is so!eti!es called the ,6ayout 86- window( as this is where editing is
!ost o'ten done with this tool( but it is basically 5ust the %irtuoso 6ayout 7ditor
with so!e new options.
Cross-Probing
.ou can probe (highlight) ob5ects while wor)ing in the sche!atic or layout editors.
ote that probing an ob5ect re!oves the e:isting highlights. =hen you probe a pin or net
in one view( it will be highlighted in the other view as well.
Cross-Probing from Virtuoso XL
=ith the Connectivity 4 +robe co!!and( you can probe an ob5ect in the %irtuoso 86
or %irtuoso sche!atic co!poser windows and highlight the ob5ect in the %irtuoso 86(
%irtuoso sche!atic co!poser.
1.Choose Connectivity >86 +robe in the %irtuoso 86 window.
ote" I' you do not see this co!!and in the !enu( choose &ools 4 %irtuoso 86.
3ptionally( press #* to display the %irtuoso 86 +robe 3ptions 'or!.
2.Clic) on a pin( net( or device in the %irtuoso 86 or sche!atic co!poser window.
Cross-Probing from the Composer
.ou can use the co!poser ;esign 4 +robe 4 1dd sub!enu co!!ands to initiate cross4
probing. #ollow these steps"
1. In the Co!poser window( choose 1dd et( 1dd +in( or 1dd Instance 'ro! the
;esign 4 +robe !enu.
2.+ress #*( i' necessary( to display the 1pplications to Cross +robe 'or!.
*.Select the !as)6ayout view type.
4.Clic) in the sche!atic to place the probe. .ou will see both the sche!atic and
corresponding layout highlighted.
Layout vs Schematic !LVS" chec#ing !$ptional"
&he ;?C layout chec) that you are 'a!iliar with only chec)s to !a)e sure that the
shapes you drew are physically possible to !anu'acture. &here is no guarantee that what
you drew is actually the sa!e circuit as what you have in your sche!atic. &he 6%S
chec) is a tool that can analy/e your layout and 'ind all o' the devices and connections
between the!( and then co!pare this to your sche!atic view. 7ven 'or s!all cells li)e
an inverter it is necessary to run this chec)( because i' there is a s!all error here it will
turn into a lot o' errors when you use the inverter cell in a larger design. &his is one o'
the ways that hierarchical design can be used to help you by veri'ying your design in
s!all( !anageable sections. #or larger cells( it is usually di''icult to pass 6%S the 'irst
ti!e( which !a)es you reali/e how i!portant a tool it is@ =ithout 6%S( you have al!ost
no chance o' ever getting a chip that wor)s.
%unning LVS
&he 6%S chec) is split into two parts (it see!s silly( but there is a reason)s"
1) ,7:tracting- the layout. &his is where the devices and connectivity are
deter!ined 'ro! your layout view.
2) ,6%S- chec)( which actually co!pares the ,e:tracted- view (not the layout view)
against the sche!atic.
E&tracing your layout
#ro! the layout editor( choose %eri'y7:tractA and 'ill in the 'or! as shown below.
=hen e:traction is co!plete it will print a !essage in the ic'b window telling you how
!any devices it 'ound (o'ten a use'ul 'irst chec)) and i' there were any errors during the
e:traction process itsel'.
&here will also be a new view in your cell called ,e:tracted-. .ou donBt need to do
anything with this view 'or now( but i' you loo) at it you will notice that it loo)s a lot li)e
your layout( but has transistor sy!bols on it indicating devices that the e:tractor 'ound.
.ou can /oo! in on these devices and see what net na!es they are connected to and
co!pare this to your sche!atic i' there are any proble!s.
Starting LVS
I' there are no errors during e:traction( choose %eri'y6%SA 'ro! the layout editor and
!a)e sure all o' the 'ields !atch those shown below.
Clic) ,?un- to start the chec). It will e:ecute in the bac)ground and noti'y you a 'ew
seconds later when the chec) is co!plete. It will say that the 6%S 5ob 'ailed or
succeeded. &his doesnBt re'er to the veri'ication result( but only whether it was able to
even start the chec). I' it 'ailed( ,Chec) and Save- the sche!atic and try running 6%S
again. I' that doesnBt wor)( !a)e sure you entered the library and cell na!es correctly.
3nce 6%S succeeds( clic) the ,3utput- button to view a te:t 'ile listing the results. It
will have so!e su!!ary in'or!ation( such as a list o' the nu!ber o' devices and nets in
each cell view. =hat you are loo)ing 'or is a line that says ,&he net4lists !atch-.
I' instead you get ,&he net4lists !atch logically( but have !is!atched para!eters-( that
!eans that both the sche!atic and layout have the sa!e type o' transistors hoo)ed up the
sa!e way( but the device si/es donBt !atch. In this case( it would !ean that the layout is
still a standard inverter( but it wonBt per'or! the sa!e as the one in your sche!atic.
I' the 6%S chec) turns up errors( they will generally be listed twice. #irst it lists things in
the sche!atic that it couldnBt 'ind a !atch 'or in the layout( and then it lists things in the
layout it couldnBt 'ind a !atch 'or in the sche!atic. &hese errors will help you 'ind the
proble!( but they can be very cryptic di''icult to 'ollow. 1s you beco!e e:perienced
with 6%S chec)ing( you will get so!e intuition about how to 'ollow these errors( and
learn so!e techni9ues to trac) the! down so!ewhat syste!atically.
1t so!e point you will 'ind yoursel' with a layout that you thin) is ,clean- but 6%S
reports errors. .ou will insist until you are blue in the 'ace that the co!puter is wrong.
Be assured that this is not the case. So!eti!es the error is subtle or di''erent 'ro! what
is listed in the error report( but 6%S doesnBt report errors i' your cell is truly clean. .ou
will be very !ad at 6%S until you 'ind the proble!( at which point you will be very
happy that 6%S was there 'or you.