Low IQ LDOs Valapala 2011

LOW QUIESCENT CURRENT LOW-DROPOUT VOLTAGE REGULATORS
WITH IMPROVED TRANSIENT-RESPONSE

BY
HARISH VALAPALA, B.Tech
A thesis submitted to the Graduate School
in partial fulllment of the requirements
for the degree
Master of Sciences, Engineering
Specialization in: Electrical Engineering
New Mexico State University
Las Cruces, New Mexico
March 2011
Low Quiescent Current Low-Dropout Voltage Regulators With Improved Transient-
Response, a thesis prepared by Harish Valapala in partial fulllment of the re-
quirements for the degree, Master of Sciences has been approved and accepted by
the following:
Linda Lacey
Dean of the Graduate School
Paul M. Furth
Chair of the Examining Committee
Date
Committee in charge:
Dr. Paul M. Furth, Associate Professor, Chair.
Dr. Jaime Ramirez-Angulo, Klipsch Distinguished Professor, IEEE fellow.
Thomas W. Jenkins, Professor.
ii
DEDICATION
Dedicated to my mother Raghumala Valapala, father Damodara Naidu
Valapala, brother Sandeep Kumar Valapala, my friend Swetha Peri, my advisor
Dr. Paul M. Furth and to all my friends.
iii
ACKNOWLEDGMENTS
I came to NMSU with a goal of pursuing my higher education with an
emphasis on VLSI Design. I have been fortunate to have Dr. Paul M. Furth
as my advisor over this period. I would like to thank him for encouraging me
throughout my Master
s Program. His teaching skills pushed me to give my best

toward everything.
I would also like to thank Dr. Jaime Ramirez-Angulo and Thomas W.
Jenkins for being part of my committee on such short notice.
Thank you to my Mother, Raghumala Valapala, my Father, Damodara
Naidu Valapala and my Brother, Sandeep Kumar Valapala for their love and for
always supporting me and encouraging me throughout my journey.
I extend my gratitude to Annajirao Rao Garimella for his input during
the beginning of my thesis work. He gave me much advice while I was pursuing
my MS.
I would also take this opportunity to thank my team V 6.0 (VLSI Ver-
sion 6.0) : Ramesh Korupolu, Chaitanya Mohan, Venkat Rajannagari, Rajesh
Satyavada and Punith Surkanti. I would also like to thank Pulla Ailuri, Kaushik
Chavali, Wasequr Rashid, Javier Hernandez, Sailaja Kasaraneni, Shanta Thoutam,
Swetha Peri, Kalyan Bonam, Likith Lanka, Avinash Vandhanapu, Raghunath
Kandlakunta, Santosh Gunna, Rakesh Govind, Raghavender Guggila, Vamsi Kr-
ishna Oliveti, Vijay Kiran, Sreenath Bellary, Sainath Kilaru, Chaitanya Tanikella,
iv
Raghavendra Prasad Punukollu, Venugopal Tondupally, Varun Kommineni, Lalith
Damaraju, Sravan Buggaveeti, Madhusudhan Nagireddy, Suresh Jetty, Nikhlesh
Ravi, Karan Gampa, Santosh Sikha, Sandeep Yemewar, Arun Showry Bellamkonda,
Pudi Srinivasu, Sri Harsh Pakala, Harish Nammi, Thilak Raju, Nitya Thota,
Rashmi Subramanyam and the whole ISA and VLSI student community for pro-
viding a congenial and fun environment to work and study in. Through the past
two years we shared many memorable moments which made my student life fun
here.
Last, but not least, I am deeply indebted to The Almighty.
v
VITA
February 28, 1987 Born in Hyderabad, India.
Education
2004 - 2008 B.Tech. Electronics and Communication Engineering,
Jawaharlal Nehru Technological University, India
2009 - 2010 Teaching Assistant,
New Mexico State University,USA
Since 2008 M.S in Electrical Engineering,
New Mexico State University, USA
Awards and Achievments
2008 - 2011 In-State Tuition, NMSU,USA.
2010 - 2011 Outstanding Teaching Assistant Award, NMSU, USA.
Field of Study
Major Field: Electrical Engineering (Analog or Digital IC Design)
vi
ABSTRACT
LOW QUIESCENT CURRENT LOW-DROPOUT VOLTAGE REGULATORS
WITH IMPROVED TRANSIENT-RESPONSE
BY
HARISH VALAPALA, B.Tech
Master of Sciences, Engineering
Specialization in Electrical Engineering
New Mexico State University
Las Cruces, New Mexico, 2011
Dr. Paul M. Furth, Chair
We introduce two extremely low quiescent current (I
Q
) low-dropout (LDO)
voltage regulators. The Low I
Q
-LDO (LI
Q
-LDO) uses 13 A of quiescent current
and is designed for maximum load current of 50 mA. The second design, Micro I
Q
-
LDO (MI
Q
-LDO) uses 1.2 A of quiescent current and is designed for maximum
load current of 5 mA. Multiple compensation techniques are adopted that improve
line and load transient response. AC analysis is performed to ensure the stability
of the circuit. Both designs are fully integrated to drive on-chip capacitive load of
100 pF. The line and load transients are measured with rise and fall times of 100
ns. In load transient, the total variation in output voltage for LI
Q
-LDO and MI
Q
-
LDO is 1 V and 950 mV, respectively and the load regulation is 0.1 mV/mA and
vii
0.8 mV/mA, respectively. A gure of merit (FOM), that can be used to compare
design across dierent technologies, for LI
Q
-LDO is 0.52 ps and for MI
Q
-LDO is
4.52 ps. The total area occupied by both the designs is 0.691 mm
2
in a 0.5-m
CMOS process.
viii
TABLE OF CONTENTS
LIST OF TABLES xii
LIST OF FIGURES xiv
1 INTRODUCTION 1
2 BACKGROUND 4
2.1 Basics of LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Source Cross-Coupled Pairs . . . . . . . . . . . . . . . . . . . . . 8
2.3 Work done in [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Figure of Merit (FOM) from [1] . . . . . . . . . . . . . . . . . . . 10
3 DESIGN AND SIMULATION 13
3.1 Scaling Design From 0.18-m to 0.5-m . . . . . . . . . . . . . . . 13
3.2 LDO from [1] in 0.5-m process . . . . . . . . . . . . . . . . . . . 14
3.2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.2 Small-Signal Model . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Compensated form of LDO in [1] . . . . . . . . . . . . . . . . . . 16
3.3.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Low-Power I
Q
LDO (LI
Q
-LDO) . . . . . . . . . . . . . . . . . . . 20
ix
3.4.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Micro-Power I
Q
LDO (MI
Q
-LDO) . . . . . . . . . . . . . . . . . . 24
3.5.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6.1 AC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6.2 Dropout Voltage . . . . . . . . . . . . . . . . . . . . . . . 27
3.6.3 Line Transient . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.6.4 Load Transient . . . . . . . . . . . . . . . . . . . . . . . . 33
4 EXPERIMENTAL RESULTS 36
4.1 Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.2 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.3 Dropout Voltage Measurements . . . . . . . . . . . . . . . . . . . 39
4.4 Line Transient Measurements . . . . . . . . . . . . . . . . . . . . 41
4.5 Load Transient Measurements . . . . . . . . . . . . . . . . . . . . 42
5 DISCUSSION AND CONCLUSION 47
APPENDICES 50
A. Test Document 51
A.1 Circuit 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
A.1.1 Procedure for Measuring Dropout Voltage: . . . . . . . . . 52
A.1.2 Procedure for Measuring Ground Current: . . . . . . . . . 55
A.1.3 Line Transient Test Procedure: . . . . . . . . . . . . . . . 56
x
A.1.4 Load Transient Test Procedure: . . . . . . . . . . . . . . . 59
A.2 Circuit 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
A.3 Circuit 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
A.4 Circuit 4: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
B. PCB Design 66
C. Maple Work for Small-Signal Analysis 70
D. Matlab Code for Plotting Simulated and Measured Results 73
REFERENCES 84
xi
LIST OF TABLES
2.1 Ratio of sizes of transistors from [1] . . . . . . . . . . . . . . . . . 10
2.2 Performance Comparision from [1] . . . . . . . . . . . . . . . . . . 12
3.1 Scaled values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Sizes of Transistors in both the process . . . . . . . . . . . . . . . 14
3.3 Poles and Zeros of LDO in 0.5-m process . . . . . . . . . . . . . 18
3.4 Compensated form of LDO from [1] . . . . . . . . . . . . . . . . . 20
3.5 Poles and Zeros of LI
Q
-LDO . . . . . . . . . . . . . . . . . . . . . 24
3.6 Poles and Zeros of MI
Q
-LDO . . . . . . . . . . . . . . . . . . . . 26
3.7 Gain Equations of all designs . . . . . . . . . . . . . . . . . . . . 29
3.8 Compensation Capacitors and Resistors . . . . . . . . . . . . . . . 30
3.9 AC Response at I
L
= I
L,max
. . . . . . . . . . . . . . . . . . . . . 31
4.1 Measured Dropout Voltage . . . . . . . . . . . . . . . . . . . . . . 40
4.2 Line Transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.3 Load Transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.4 Measured Quiescent Current . . . . . . . . . . . . . . . . . . . . . 45
5.1 FOM Comparision Table . . . . . . . . . . . . . . . . . . . . . . . 48
1 Current Flowing through each resistor . . . . . . . . . . . . . . . 53
xii
3 Dropout Voltage Table . . . . . . . . . . . . . . . . . . . . . . . . 64
4 Current Flowing through Vs . . . . . . . . . . . . . . . . . . . . . 65
5 Current Flowing through ground . . . . . . . . . . . . . . . . . . 65
xiii
LIST OF FIGURES
2.1 Basic architecture of an LDO [2] . . . . . . . . . . . . . . . . . . . 5
2.2 Sample dropout voltage waveforms . . . . . . . . . . . . . . . . . 6
2.3 Sample line transient waveforms . . . . . . . . . . . . . . . . . . . 7
2.4 Sample load transient waveforms . . . . . . . . . . . . . . . . . . 7
2.5 Source cross-coupled pair from [3] . . . . . . . . . . . . . . . . . 9
2.6 Push-pull high slew-rate LDO from [1] . . . . . . . . . . . . . . . 11
3.1 LDO from [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Small signal model. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3 Compensated form of previous LDO . . . . . . . . . . . . . . . . . 19
3.5 Schematic of Low-Power I
Q
LDO (LI
Q
-LDO) . . . . . . . . . . . 22
3.7 Loop breaking in AC analysis . . . . . . . . . . . . . . . . . . . . 28
3.8 Gain plot of all designs at maximum load current. An oset of
20dB was intentionally added for visibility. . . . . . . . . . . . . . 31
3.9 Phase plot of all designs at maximum load current. An oset of
20
was intentionally added for visibility. . . . . . . . . . . . . . . 32

3.10 Dropout voltage testbench . . . . . . . . . . . . . . . . . . . . . . 32
3.11 Dropout voltage measurement from simulation . . . . . . . . . . . 33
3.12 Line transient testbench . . . . . . . . . . . . . . . . . . . . . . . 33
xiv
3.13 Line transient. (a) Output voltage with 100 pF load capacitance,
(b) output voltage without 100 pF load capacitance, (c) Input Volt-
age. An oset of 1 V was intentionally added for visibility. . . . . 34
3.14 Load transient test bench . . . . . . . . . . . . . . . . . . . . . . 34
3.15 Load transient. (a) Output voltage with 100 pF load capacitance,
(b) output voltage without 100 pF load capacitance, (c) Load Cur-
rent. An oset of 2 V was intentionally added for visibility. . . . . 35
4.1 Layout of LDO from [1] in 0.5-m process . . . . . . . . . . . . . 37
4.2 Layout of compensated form of LDO from [1] . . . . . . . . . . . 38
4.3 Layout of LI
Q
-LDO . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.4 Layout of MI
Q
-LDO . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.5 Layout all LDO designs . . . . . . . . . . . . . . . . . . . . . . . . 41
4.6 Micrograph view of all LDO designs . . . . . . . . . . . . . . . . . 42
4.7 Dropout voltage measurement at maximum load current . . . . . 43
4.8 Line Transient Response. (a) Input Waveform, (b) output voltage
with 100 pF load capacitance and (c) output voltage without 100
pF load capacitance at load current of 1 mA. An oset of 1 V was
intentionally added for visibility. . . . . . . . . . . . . . . . . . . . 44
4.9 Load transient response. (a) Load current (b) output voltage with
100 pF load capacitance (c) output voltage without load capaci-
tance. An oset of 2 V was intentionally added for visibility. . . . 46
A.1 Jumper Conguration for Dropout Voltage on Circuit 1 . . . . . . 52
A.2 Setup for Measuring 100 nA . . . . . . . . . . . . . . . . . . . . . 54
A.3 Jumper Conguration for Measuring Ground Current on Circuit 1 55
A.4 Jumper Conguration for Line Transient on Circuit 1 . . . . . . . 56
A.5 Jumper Conguration for Load Transient on Circuit 5 . . . . . . . 60
A.6 Schematic of PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
A.7 Layout of PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
xv
A.8 Final PCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
xvi
Chapter 1
INTRODUCTION
LDOs have become an essential part of many battery powered systems. Their
applications range from a simple portable music player to a complex micropro-
cessing unit. The main features of an LDO are well-regulated output voltage, low
power consumption and area. An LDO simultaneously drives many circuits of a
complex power-management system. If one circuit in these systems goes to sleep,
the output of the LDO should remain constant so that the other circuits are not
eected. Hence, an LDO should have minimum variation in the output voltage
when the load changes [4],[5]. Area is one of the biggest issues in portable devices,
such as music players. Hence an LDO, which is fully-integrated with no external
capacitors, is in a great demand [6],[7] and [8].
The important issue with any battery powered system is the power con-
sumption. A real-time clock, which is an important part of mobile phones, requires
an extremely long battery life [9], which implies an LDO in the mobile phone
should use extremely low battery power. This is only possible when the LDO uses
extremely low quiescent current [10],[11]. Long battery life is also important in
many implantable electronic devices, such as pacemakers. Once implanted in a
body, it has battery power as its only source, which can last a long time only if
the LDO dissipates extremely low power.
We began our work by replicating in simulation the work done in [1] in a
0.18-m process. After that, we scaled the design to a 0.5-m process by scaling
1
few parameters. In this work, we have implemented four LDOs. The rst LDO
is intended to be a replication of their work, but in a 0.5-m process. The next
LDO is an improved version using compensation networks. The next two LDOs
are extremely enhanced versions of the LDO presented in [1]. The third LDO,
which is called the low-quiescent current-LDO (LI
Q
-LDO), uses 13 A of quiescent
current with 50 mA as its maximum load current, while the fourth LDO, called
the micro-quiescent current (MI
Q
-LDO), uses 1.2 A of quiescent current with
5 mA as its maximum load current. The fourth design has its main application
in implantable devices which do not draw large load currents.
The circuit proposed in [1] uses 1.2 A of quiescent current driving a load
of 50 mA with a load capacitance of 100 pF in a 0.18-m process. There are three
major drawbacks associated with their design. Firstly, the minimum load current
is 50 A. In a practical implementation of this 50 A minimum load, the designer
would add an external resistance to ground, essentially wasting 50 A current.
Secondly, the design proposed in [1] has no provision for scaling V
OUT
, that is,
there is no resistive feedback network. In a complex power management system
dynamic voltage scaling (DVS), that is, adjusting an LDOs output voltage is
considered an important approach for reducing power dissipation [12]. Thirdly,
AC modeling was not performed, so that design in terms of pole-zero placement
was not studied.
The report is organized in the following way. Chapter 2 deals with basics
of LDO and operation of source cross-coupled pairs, followed by analysis and
discussion of work done in [1]. In Chapter 3, we discuss scaling the work in [1]
to a 0.5-m process followed by our four proposed LDO designs along with their
AC models and simulation results. The experimental measurements and plots are
discussed in Chapter 4. Chapter 5 compares our work with work done by others.
2
In the appendix, we give a detailed description of test procedure and also show
the layout of our PCB. The latter part of the appendix shows Maple work which
is used to estimate the poles and zeros of all the small-signal models and Matlab
codes to plot simulation and experimental results.
3
Chapter 2
BACKGROUND
This chapter gives an overview of Low Dropout Voltage Regulator (LDO) and a
few denitions associated with it. The latter part deals with source cross-coupled
pairs which is a major element in the LDO described in this work. Finally, we
discuss the work done in [1], along with their Figure of Merit (FOM), which is the
basis for this work.
2.1 Basics of LDO
The basic architecture of low-dropout voltage regulator (LDO) is shown in
Fig. 2.1. The error amplier, feedback resistors and pass element are the main
parts of an LDO. The pass element is usually a PMOS transistor that is in a
common-source conguration. This transistor is very large in size in order to
accomodate huge load currents. The feedback resistors scale the output voltage
to a value comparable to the reference voltage. This scaled voltage is fed to the
negative terminal of the error amplier. The feedback resistors are chosen in such
a way that they bleed a current of I
B
.
The reference voltage, which is typically a band-gap reference voltage, is
applied to the positive terminal of the error amplier. Any changes in the output
voltage are scaled through the feedback network and compared to the reference
voltage. The error amplier generates a signal based on the dierence between
these two voltages. This voltage is multiplied by the gain of the error amplier to
4
Error
Amplifier
Pass
Element
Reference
V
IN
V
OUT
V
fb
V
ref
V
SS
+
-
Feedback
Resistors
R
1
R
2
Figure 2.1: Basic architecture of an LDO [2]
control the gate of the pass element. By controlling the current through the pass
element, the output voltage is stabilized.
The dropout voltage, overshoot, undershoot and regulation are the im-
portant characteristics of an LDO. Dropout voltage is dened as the dierence
between the regulated output voltage and unregulated input voltage (at which
the output voltage starts regulating). Fig. 2.2 shows the dropout voltage mea-
surement. The above denition is one of the simplest ways of dening dropout
voltage. The dropout voltage can also be dened by [13]
V
DO
(V
s
V
out
)|
V
out
=V
out,max
100mV
(2.1)
Dropout voltage is always measured at maximum load current.
5
Figure 2.2: Sample dropout voltage waveforms
Fig. 2.3 shows sample line transient measurements. While performing a
line transient test, the input voltage is varied with a rise and fall times of 100 ns.
As the input increases from a nominal value, the output tends to increase as well.
This increase in output voltage can be attributed to the capacitance associated
with the input and output nodes. Similarly, when the input voltage decreases
from a value to the nominal value, the output voltage also decreases. The amount
of increase and decrease in the output voltage is called overshoot and undershoot,
respectively. The line regulation is dened as the ratio of change in output voltage
to the change in input voltage and is generally expressed in mV/V.
Fig. 2.4 shows sample load transient measurements. When load transient is
performed, the load current is varied from 0 mA to maximum load current that an
LDO is designed for, with rise and fall times of 100 ns. The output voltage tends
to decrease when the load current increases and increases when the load current
decreases. When load current increases, the output voltage decreases because, the
current discharges the capacitor at the output node. Similarly, when the current
6
Figure 2.3: Sample line transient waveforms
drops, the current from the pass transistor charges the capacitor at the output
node [14]. The overshoot and undershoot are dened in the same way as in line
transient. The load regulation is dened as the ratio of change in output voltage
to change in load current and is generally expressed in mV/mA.
Figure 2.4: Sample load transient waveforms
7
The next section explains the operation of source cross-coupled pairs, which
is a major block of LDOs in this work
2.2 Source Cross-Coupled Pairs
The LDO in this work employs a source cross-coupled pair. This section
gives the operation of a source-cross coupled pair. Fig. 2.5 shows the source
cross-coupled pair from [3]. Large changes in the dierential input voltage V
I1
V
I2
result in huge amount of current in transistors M
1
and M
3
, or M
2
and M
4
.
This current is mirrored to the output branch and hence class-AB operation is
obtained [3].
When the voltage V
I1
is increased, the source voltage of M
11
is also in-
creased, since the current owing through it is constant. This increase in source
voltage decreases the V
SG
of M
4
and V
GS
of M
2
, thereby decreasing the current
I
D1
in transistors M
4
and M
2
. On the other hand, the increase in voltage V
I1
increases the V
GS
of M
1
and V
SG
of M
3
, increasing the current I
D2
.
The current I
D2
is mirrored to the output stage and the node V
OUT
is
pulled to V
SS
. Similarly, when the input voltage V
I2
is increased, the current I
D1
is increased and mirrored to the output stage. This current sources current to the
node V
OUT
. Hence, depending upon the voltages V
I1
and V
I2
, the output node is
pulled to V
SS
or V
DD
. Hence, a true class-AB operation is achieved. This type of
operation is highly desirable in an LDO.
In an LDO, the stage driving the huge pass transistor benets from being
driven by a class-AB dierential amplier, because it needs to sink or source a
large amount of current to quickly drive the gate voltage of the pass transistor
either high or low.
The next part of this chapter describes the work done in [1] and exposes
the drawbacks with their design.
8
V
DD
V
DD
V
DD V
DD
I
D1 I
D2
I
SS I
SS
I
D2
I
D1
M
11
M
21
M
31
M
41
M
1
M
2
M
4
M
3
V
I1
V
I2
+
-
+
-
V
DD
V
OUT
I
D1
I
D2
I
OUT
M
5
M
6
M
8
M
7
Figure 2.5: Source cross-coupled pair from [3]
2.3 Work done in [1]
In [1], they introduce an LDO and state that it uses only 1.2A of quiescent
current. The LDO is shown in Fig. 2.6. The ratio of transistors is given in
Table 2.1. In [1], the LDO is comprised of two parts, a reference buer and
an error amplier. The main purpose of the reference buer is to transfer the
reference voltage in order to drive the low input impedance of the error amplier.
The reference buer is a two stage CMOS op-amp with a feed-forward path that
increases the slew-rate. It has no slew-rate limitation when sourcing current onto
node V
A
. It is slew-rate limited while sinking current o from node V
A
because
the current in M
a8
is limited to 2I
B
.
The error amplier has two-stages. The rst stage is source cross-coupled
pairs with wide-swing output mirrors. When there is a voltage dierence between
nodes V
A
and V
OUT
, huge current is generated which is transferred to the second
stage with the help of wide swing current mirrors. The current generated by this
9
Table 2.1: Ratio of sizes of transistors from [1]
Transistors Ratio
M
Ha
: M
Hb
, M
La
: M
Lb
, M
21
: M
22
& M
a1
: M
a2
1 : 1
M
11
: M
12
& M
31
: M
32
1 : 3
M
Ba
: M
BH
: M
BL
: M
BIAS
1 : 1 : 1 : 1
M
a3
: M
a4
: M
a5
: M
a6
1 : 1 : 6 : 2
rst stage in independent of the bias current which implies that this stage is not
slew-rate limited and hence it is a class AB stage. The second stage is a common-
source amplier with a huge pass transistor. Node V
B
swings rail-to-rail to control
the output current of the LDO.
The stage before the pass transistor needs to have high current, because
this current is used to charge or discharge the gate capacitance of the huge pass
transistor. This gate capacitance controls the output voltage. Hence the transis-
tors M
12
and M
32
are sized three times greater than other transistors.
Next section shows, how the work done in [1] was compared with other
LDO designs.
2.4 Figure of Merit (FOM) from [1]
In [1], they use an FOM to compare their work with previous work. The
FOM is given by [15]
FOM =
T
R
I
Q
I
LOADMAX
(2.2)
The lower the FOM, the better the design. Table 2.2 shows the performance
comparision of work done by [1] from others. T
R
is the time taken by their LDO
10
V
R
E
F
V
O
U
T
V
S
V
B
V
B
V
B
V
S
S
M
a
5
M
a
3
M
a
4
M
a
1
M
a
2
M
B
a
M
B
I
A
S
M
a
8
M
1
1
M
1
2
M
2
1
M
2
2
M
3
1
M
3
2
M
P
A
S
S
M
H
b
M
H
a
M
L
a
M
L
b
M
B
L
M
B
H
M
a
6
M
a
7
R
e
f
e
r
e
n
c
e
B
u
f
f
e
r
E
r
r
o
r
A
m
p
l
i
f
i
e
r
V
A
V
B
I
B
3
I
B
I
B
I
B
I
B
I
B
I
B
I
B
I
B
I
B
F
i
g
u
r
e
2
.
6
:
P
u
s
h
-
p
u
l
l
h
i
g
h
s
l
e
w
-
r
a
t
e
L
D
O
f
r
o
m
[
1
]
11
Table 2.2: Performance Comparision from [1]
[16] [15] [7] [1]
Year 2003 2004 2007 2007
Tech. ([m]) 0.6 0.09 0.35 0.35
V
IN
[V] 1.5 1.2 1.2 1.0
V
DO
[V] 0.2 0.3 0.2 0.1
I
LOAD,MAX
[mA] 100 100 100 50
I
Q
[mA] 0.038 6 0.1 0.0012
T
R
(s) 2 0.00054 50 2.8
FOM (ns) 0.76 0.032 50 0.067
to recover and I
Q
is the total quiescent current. In their FOM, they do not include
the minimum load current even though it constitutes for the power consumption.
This is the reason they have a pretty good FOM when compared to others.
In section 1, we have exposed the three major drawbacks associated with
their LDO design. In the next chapter we address all the above issues and over-
come them, and present you a true micro-power LDO design which uses only 1.2
A of quiescent current.
12
Chapter 3
DESIGN AND SIMULATION
This section explains all four LDO designs which are based on the LDO design
from [1]. This section starts with scaling of voltages from a 0.18-m process to
a 0.5-m process. The latter part of the chapter deals with operation and small-
signal modeling of four LDO designs. The nal part of the chapter shows the
AC response, dropout voltage measurement, line and load transient simulation
responses of all four LDO designs. Appendix C shows the required Maple work
to estimate the gain, poles and zeros of all the proposed designs.
3.1 Scaling Design From 0.18-m to 0.5-m
The LDO in [1] was implemented in a 0.18-m CMOS process. This is
shown in Fig. 2.6. The ratio of sizes of transistors is given in Table 2.1. Scaling
is done for the purpose of comparing the design in [1] with the two designs we
introduce. The values are scaled based on threshold voltages of transistors in both
the processes. Assumed threshold voltage in 0.18-m is 0.5 V and in 0.5-m is
0.8 V. Table 3.1 shows all the scaled values. This circuit was scaled to a 0.5-m
process in such way that both the circuits yield comparable results. For example,
the size of pass transistor in 0.18-m process is 5.94 mm/0.18 m [1] and that of
0.5-m process is 12 mm/0.5 m.
Using the above scaled values, we have designed our LDO in 0.5-m pro-
cess, which is described next.
13
Table 3.1: Scaled values
0.18-m process 0.5-m process
V
TH
0.5 V 0.8 V
V
IN
1.2 V 2V
V
DO
100 mV 167 mV
V
OUT
0.9 V 1.5 V
V
IN
0.5 V 0.8 V
W
L
PASS
5.94 mm
0.18m
12 mm
0.5m
variation of input voltage in line transient.

Table 3.2: Sizes of Transistors in both the process
0.18-m process
Width (W) Length (L)
PMOS 3.6 m 0.5 m
NMOS 1.8 m 0.5 m
Pass Transistor 5.94 mm 0.2 m
0.5-m process
PMOS 9.6 m 1.05 m
NMOS 4.8 m 1.05 m
Pass Transistor 12 mm 0.5 m
3.2 LDO from [1] in 0.5-m process
This section gives the operation and small signal modeling. The LDO from
Fig. 2.6 was rst implemented in 0.18-m process. After yielding comparable
results, the design was scaled to 0.5-m process. Table 3.2 gives the sizes of
transistors in both of the processes.
14
V
R
E
F
V
O
U
T
V
S
V
B
V
B
V
B
V
S
S
M
a
5
M
a
3
M
a
4
M
a
1
M
a
2
M
B
a
M
B
I
A
S
M
a
8
M
1
1
M
1
2
M
2
1
M
2
2
M
3
1
M
3
2
M
P
A
S
S
M
H
b
M
H
a
M
L
a
M
L
b
M
B
L
M
B
H
M
a
6
M
a
7
R
e
f
e
r
e
n
c
e
B
u
f
f
e
r
E
r
r
o
r
A
m
p
l
i
f
i
e
r
V
A
V
B
I
B
3
I
B
I
B
I
B
I
B
I
B
I
B
I
B
I
B
I
B
F
i
g
u
r
e
3
.
1
:
L
D
O
f
r
o
m
[
1
]
15
3.2.1 Operation
The operation of this design is similar to the one explained in Section 2.3.
The high slew-rate push-pull amplier is treated as error amplier. Loop is broken
in the error amplier for AC modeling.
3.2.2 Small-Signal Model
The small signal model is shown in Fig. 3.2. The small signal model has two
parts - closed-loop reference buer and open-loop error amplier. The capacitors
shown in the Fig. 3.2 are the parasitic capacitances of transistors M
a5
and M
PASS
,
respectively. The reference buer has a feed-forward path, hence there are two
current branches to the node V
4
in Fig. 3.2. The parasitic capacitance of M
a5
forms a right-half plane zero.
The open-loop error amplier can be realized by treating the nodes V
4
and V
i
as separate nodes with an impedance Z
i
between them, where Z
i
is the
resistance seen into a source of a transistor. The parasitic capacitance of M
PASS
splits the two dominant poles and also creates a right-half plane zero. The poles
and zeros of this design are given in Table. 3.3.
The above design exhibited instability when tested with rise and fall times
of 100 ns in transient tests. Hence, we have used multiple compensation networks
to stabilize this LDO design. The compensated LDO design is described in the
next section.
3.3 Compensated form of LDO in [1]
This section deals with the compensated form of LDO from [1], but imple-
mented in 0.5-m process.
3.3.1 Operation
This LDO similar to the LDO described in [1], but there are few major
changes. The topology of this circuit is shown in Fig. 3.3. Firstly, the feed-
16
(a) Closed-loop reference buer
(b) Open-loop error amplier
Figure 3.2: Small signal model.
forward path is removed from the reference buer. This path has no eect on
the line and the load transients and thus wasting 100 nA of current. Secondly,
this circuit topology has a resistor divider. By adding the resistor divider there
is an added exibility of scaling the reference voltage as desired. These resistors
have compensation capacitors in parallel. This resistor divider branch draws the
same current as the feed-forward path, hence we have maintained the same ground
current. This circuit uses minimum load current of 50 A, hence the total ground
17
Table 3.3: Poles and Zeros of LDO in 0.5-m process
[1] in 0.5-m process
p1
1
r
1
c
gdp
g
mp
r
2
p2
g
mp
C
L
z1
g
mp
c
gdp
current is 51.2 A Apart from these, few compensation capacitors and resistors
were used to improve the line and load transient response.
The small signal model is shown in Fig. 3.4. It is similar to the one shown
in Fig. 3.2. However, the compensation networks are included in the model. As
there is no feed forward path in this design, we have removed a current branch at
the node V
4
in Fig. 3.2 and added the resistive feedback impedances as shown in
Fig. 3.4.
In the open-loop error amplier we have a compensation capacitance to a
internal node called V
y
. Hence, we have exposed this internal node in the Fig. 3.4.
This node is not shown in Fig. 3.2, because there is no compensation at this node.
The rst compensation capacitor not only splits the two dominant poles,
but also creates a right half-plane zero. The second compensation capacitor creates
a left half-plane zero, which can be moved to cancel a pole. The poles and zeros
are given in Table. 3.4.
18
V
R
E
F
V
O
U
T
V
S
V
B
I
A
S
V
B
I
A
S
V
B
I
A
S
V
S
S
M
a
5
M
a
3
M
a
4
M
a
1
M
a
2
M
B
a
M
B
I
A
S
M
a
8
M
1
1
M
1
2
M
2
1
M
2
2
M
3
1
M
3
2
M
P
A
S
S
M
H
b
M
H
a
M
L
a
M
L
b
M
B
L
M
B
H
R
e
f
e
r
e
n
c
e
B
u
f
f
e
r
E
r
r
o
r
A
m
p
l
i
f
i
e
r
V
B
I
A
S
Z
c
1
C
F
2
C
F
1
R
F
1
R
F
2
V
A
V
B
I
B
3
I
B
I
B
I
B
I
B
I
B
I
B
I
B
I
B
I
B
Z
c
y
F
i
g
u
r
e
3
.
3
:
C
o
m
p
e
n
s
a
t
e
d
f
o
r
m
o
f
p
r
e
v
i
o
u
s
L
D
O
19
Table 3.4: Compensated form of LDO from [1]
Compensated form of LDO in [1] in 0.5-m process
p1
1
r
1
C
C1
g
mp
r
2
p2
g
mp
C
L
z1
g
mp
c
gdp
z2
g
xy
C
C2
After employing multiple compensation techniques, this LDO was stable,
however it was using quiescent current of 51.2A. In order to reduce the quiescent
current, we have introduced an LDO which is described in the next section.
3.4 Low-Power I
Q
LDO (LI
Q
-LDO)
This LDO eectively reduces the total quiescent current. This section
starts with the operation followed by its small signal model.
3.4.1 Operation
The topology of the design LI
Q
-LDO is shown in Fig. 3.5. The main pur-
pose of this design is to decrease the total ground current. The bias current used
is 1 A and the minimum load current is 1 A. The total quiescent current includ-
ing the minimum load current is 13 A, which is approximately 4 times smaller
than total quiescent current used by the LDO in [1]. The maximum load current
that it can handle is 50 mA.This design is similar to the design described in [1],
20
but there are three major changes. Firstly, the feed-forward path is removed from
the reference buer. This path has no eect on the line and the load transients
and thus is wasting a current of I
B
. Secondly, this design topology has a resis-
tor divider. By adding the resistor divider there is an added exibility of scaling
the reference voltage as desired. These resistors have compensation capacitors in
parallel. This resistor divider branch draws the same current as the feed-forward
path, hence we have maintained the same ground current. The reference voltage
applied is 1.2 V and is scaled to 1.5 V with the help of resistor divider. The third
major change is the addition of multiple compensation capacitors and resistors
which improved the line and load transient response.
21
V
R
E
F
V
O
U
T
V
S
V
B
I
A
S
V
B
I
A
S
V
B
I
A
S
V
S
S
M
a
5
M
a
3
M
a
4
M
a
1
M
a
2
M
B
a
M
B
I
A
S
M
a
8
M
1
1
M
1
2
M
2
1
M
2
2
M
3
1
M
3
2
M
P
A
S
S
M
H
b
M
H
a
M
L
a
M
L
b
M
B
L
M
B
H
R
e
f
e
r
e
n
c
e
B
u
f
f
e
r
E
r
r
o
r
A
m
p
l
i
f
i
e
r
V
B
I
A
S
Z
c
1
V
S
S
Z
c
2
V
S
S Z
c
3
C
F
2
C
F
1
R
F
1
R
F
2
V
A
V
B
I
B
3
I
B
I
B
I
B
I
B
I
B
I
B
I
B
I
B
I
B
F
i
g
u
r
e
3
.
5
:
S
c
h
e
m
a
t
i
c
o
f
L
o
w
-
P
o
w
e
r
I
Q
L
D
O
(
L
I
Q
-
L
D
O
)
22
The small signal model is shown in Fig. 3.6. It is similar to the one shown in
Fig. 3.4. The only change in the model is that the internal node V
y
is not shown
in this model, because there is no compensation capacitor at this node. Also,
the dierent compensation networks are also introduced. The rst compensation
capacitor splits the two dominant poles and also creates a right half-plane zero.
The second and third compensation networks are connected to the low impedance
nodes. These compensation networks create zeros which exactly cancels the poles
at nodes V
OUT
and V
A
. The poles and zeros are given in Table. 3.5.
23
Table 3.5: Poles and Zeros of LI
Q
-LDO
LI
Q
-LDO
p1
1
r
1
C
c1
g
mp
r
2
p2
1
R
c2
C
c2
+R
c3
C
c3
p3
1
R
c2
C
c2
+
1
R
c3
C
c3
p4
g
mp
C
L
z1
1
R
c2
C
c2
+R
c3
C
c3
z2
1
R
c2
C
c2
+
1
R
c3
C
c3
z3
g
mp
C
c1
The LDO described in this section uses 13A of quiescent current. In order
to design a true micro-power LDO, we have proposed a new LDO, described in
the next section.
3.5 Micro-Power I
Q
LDO (MI
Q
-LDO)
This section gives the true micro-power design which uses only 1.2 A of
quiescent current. The design is similar to the LI
Q
-LDO.
24
3.5.1 Operation
The topology of this circuit is identical to the LI
Q
-LDO. This topology is
a true micro power LDO which uses only 1.2 A quiescent current including the
minimum load current of 0 A. All parameters, such as the size of pass transistor,
bias current and maximum load current are decreased by a factor of 10. Hence,
compared to LI
Q
-LDO, the MI
Q
-LDO has bias current of 100 nA and the max-
imum load current is reduced to 5 mA. This circuit has no load resistor to Vss
at the output which implies that the minimum load current is 0 A. Hence, the
quiescent current is 1.2 A.
The small signal model is similar to the previous design and is shown in
Fig. 3.6. The compensation networks are the same, however the rst compensation
capacitor has a resistor in series with the compensation capacitor. This adds the
exibility of moving the zero from left-half plane to right-half plane. The poles
and zeros are given in Table. 3.6.
In the next section, the simulation results of all the above LDO designs are
provided.
3.6 Simulation Results
This section provides the simulation results of all the designs. It starts
with the AC analysis of all the four designs, followed by the dropout voltage and
then the line and load transient measurements.
3.6.1 AC Analysis
The loop was broken in the error amplier with the help of a large inductor
and a capacitor [17]. Fig. 3.7 shows the breaking of loop in the error amplier for
AC analysis. The inductor used is 100 MH along with a capacitor of 1 F. The
inductor blocks the AC signals and allows the DC signals. From the DC signals
25
Table 3.6: Poles and Zeros of MI
Q
-LDO
LI
Q
-LDO
p1
1
r
1
C
c1
g
mp
r
2
p2
1
R
c2
C
c2
+R
c3
C
c3
p3
1
R
c2
C
c2
+
1
R
c3
C
c3
p4
g
mp
C
L
z1
1
R
c2
C
c2
+R
c3
C
c3
z2
1
R
c2
C
c2
+
1
R
c3
C
c3
z3
1
C
c1
R
c1
1
g
mp
point of view there is no open loop and hence the circuit is in a balanced state
with all the expected bias currents. From the AC analysis point of view it is an
open circuit.
AC modeling of the design in Fig. 2.6 is not discussed in [1]. This design
is uncompensated. The small-signal model has been divided into two parts - the
closed-loop reference buer and the open-loop error amplier. The gain of the
26
open-loop error amplier is given by
Gain
EA
= 2g
m1
r
1
g
mp
r
2
(3.1)
where, EA refers to open-loop error amplier. The pair of source cross-coupled
transistors act as a double dierential pair, accounting for the factor of 2 in (3.1).
For the LDO implemented in 0.5-m process, which does not have the resistor
feedback network, the reference buer reduces the overall gain, and is given by
Gain =
Gain
(EA)
R
(in, EA)
R
(in, EA)
+R
(out, RB)
(3.2)
where, RB refers to reference buer.
For the next three designs the gain of the open-loop error amplier is the
same, however, the reference buer modies the gain due to its feedback network.
The gain equations of all the designs is given in the Table. 3.7.
The placement of all the compensation capacitors, with optional series
resistors, are identical and the equations for Z
c1
, Z
c2
and Z
c3
are given by
Z
C
1,2,3
=
1
S C
1,2,3
+R
1,2,3
(3.3)
The values of compensation capacitors and resistors are given in Table. 3.8.
AC analysis is performed for all designs at their maximum load current. The
simulation plots for all the designs is given in Fig. 3.8 and Fig. 3.9. The AC
analysis of all designs is summarized in Table. 3.9.
3.6.2 Dropout Voltage
The testbench for dropout voltage measurement is shown in Fig. 3.10. The
testbench has a current mirror which mirrors the current to the output of the LDO.
27
V
R
E
F
V
O
U
T
V
S
V
B
I
A
S
V
B
I
A
S
V
B
I
A
S
V
S
S
M
a
5
M
a
3
M
a
4
M
a
1
M
a
2
M
B
a
M
B
I
A
S
M
a
8
M
1
1
M
1
2
M
2
1
M
2
2
M
3
1
M
3
2
M
P
A
S
S
M
H
b
M
H
a
M
L
a
M
L
b
M
B
L
M
B
H
R
e
f
e
r
e
n
c
e
B
u
f
f
e
r
E
r
r
o
r
A
m
p
l
i
f
i
e
r
V
B
I
A
S
Z
c
1
V
S
S
Z
c
2
V
S
S Z
c
3
C
F
2
C
F
1
R
F
1
R
F
2
V
A
V
B
I
B
3
I
B
I
B
I
B
I
B
I
B
I
B
I
B
I
B
I
B
+
V
S
S
V
I
N
L
C
1

F
1
0
0

M
H
F
i
g
u
r
e
3
.
7
:
L
o
o
p
b
r
e
a
k
i
n
g
i
n
A
C
a
n
a
l
y
s
i
s
28
Table 3.7: Gain Equations of all designs
Gain
[1] in 0.5-
m
process
2g
m1
r
1
g
mp
r
2
1
g
mi
1
g
mi
r
4
g
m3
r
3
g
m4
r
4
Compensated
form of LDO
in [1]
2g
m1
r
1
g
mp
r
2
1
g
mi
1
g
mi
r
4
(R
f1
+R
f2
)
r
4
+g
m3
r
3
g
m4
r
4
R
f2
+(R
f1
+R
f2
)
LI
Q
-LDO
MI
Q
-LDO
The ratios of transistor sizes are given in Fig. 3.10. This current mirror handles
maximum load current. A bleeding resistor is attached to the output node, which
always bleeds the minimum load current. An external capacitor is attached to
this node.
The impedance of bonding wire is modeled in the Fig. 3.10. Each bonding
wire has an impedance of 10 nH and 200 m. In order to decrease the overall
eective impedance of the bonding wire, the output node is attached to four
bonding wires. The maximum load current is seen by these four branches. A
fth branch is used to measure the output voltage. The pad in the frame and the
substrate form a capacitor. This capacitor is also modeled in the Fig. 3.10. The
parasitic capacitance from a pad to substrate is 120 fF. Since there are ve such
29
Table 3.8: Compensation Capacitors and Resistors
Compensated
form of LDO
from [1]
LI
Q
-LDO MI
Q
-LDO
C
C1
1 pF 3 pF 300 fF
C
C2
20 pF 20 pF 20 pF
C
C3
10 pF 30 pF
R
C1
100 k
R
C2
30 k 50 k
R
C3
10 k 100 k
C
F1
4 pF
C
F2
1 pF
R
F1
3 M 300 k 3 M
R
F2
12 M 1.2 M 12 M
branches, which can be treated as ve bonding wires, the total capacitance from
all the pads to substrate is 600 fF. The 50 resistance at the reference voltage is
the source resistance of the power supply.
The resistors R
1
and R
b
are used to generate load and bias currents, re-
spectively. A slow triangular wave of rise and fall times of 25 ms is fed to V
S
.
Fig. 3.11 shows the dropout voltage measurement at maximum load current. The
dropout voltage that the LDO is designed for is 100 mV.
3.6.3 Line Transient
Fig. 3.12 shows the line transient testbench. The load current used in this
testbench is 1 mA. The input voltage V
S
is varied with rise and fall times of 100 ns.
30
10
1
10
2
10
3
10
4
10
5
10
6
10
7
!50
0
50
100
Frequency
G
a
i
n
(
d
B
)
Compensated form of LDO from [1]
LI
Q
!LDO
Design from [1]
implemented in 0.5!m
process
MI
Q
!LDO
Figure 3.8: Gain plot of all designs at maximum load current. An oset of 20dB
was intentionally added for visibility.
Table 3.9: AC Response at I
L
= I
L,max
[1] in 0.5-
m pro-
cess
Compensated
form of LDO
from [1]
LI
Q
-LDO MI
Q
-LDO
I
L,max
50 mA 50 mA 50 mA 5 mA
Gain 55.7 dB 55.7 dB 55.7 dB 59.4 dB
f
t
360 kHz 392 kHz 1.7 MHz 1.9 MHz
Phase Margin 72.9
74
76.5
45
Since, the load current is 1 mA, not 50 mA, the sizes of load transistors is made
small when compared to the transistor sizes in the dropout voltage measurement
31
10
1
10
2
10
3
10
4
10
5
10
6
10
7
!200
!150
!100
!50
0
50
100
Frequency
P
h
a
s
e
LI
Q
!LDO
MI
Q
!LDO
Design from [1]
implemented in 0.5!m
process
Compensated form of
LDO from [1]
Figure 3.9: Phase plot of all designs at maximum load current. An oset of 20
was intentionally added for visibility.

Vs VL Vb
Vref
Vs Vb
Vref
VL
Vout1
RL CL
Rb
R1
200 m
200 m
200 m
200 m
10 nH
10 nH
10 nH
10 nH
200 m
10 nH
10 pF
50
LDO
IL,MIN
IL,MAX
Vout
X 1 X 4
600 fF
Triangular pulse with rise
and fall times of 25 ms
Figure 3.10: Dropout voltage testbench
testbench. Fig. 3.13 shows the line transient response of all the four designs. The
waveforms are plotted using Matlab. (See appendix D for code).
32
Figure 3.11: Dropout voltage measurement from simulation
VS VL Vb
Vref
Pulse with rise and fall
times of 100 ns
Vs Vb
Vref
VL
Vout1
RL CL
Rb
R1
200 m
200 m
200 m
200 m
10 nH
10 nH
10 nH
10 nH
200 m
10 nH
10 pF
50
LDO
IL,MIN
IL,MAX
Vout
X 1 X 4
600 fF
Figure 3.12: Line transient testbench
3.6.4 Load Transient
Fig. 3.14 shows the testbench for the load transient test. Here the load
current is varied with a rise and fall times of 100 ns. This is achieved by varying
the voltage V
L
with rise and fall times of approximately 100 ns. Fig. 3.15 shows
the load transient response of all the four designs. The waveforms are plotted
using Matlab. (See appendix D for code).
33
0 2 4 6 8 10 12
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
O
u
t
p
u
t

(
V
)
0 2 4 6 8 10 12
2
2.2
2.4
2.6
2.8
I
n
p
u
t

(
V
)
Time (s)
0 2 4 6 8 10 12
0
1
2
3
4
5
O
u
t
p
u
t

(
V
)
100 ns
MI
Q
!LDO
LDO from [1] in 0.5!m process
LI
Q
!LDO
MI
Q
!LDO
100 ns
(b)
(a)
(c)
Compensated form of LDO in [1]
LI
Q
!LDO
Figure 3.13: Line transient. (a) Output voltage with 100 pF load capacitance, (b)
output voltage without 100 pF load capacitance, (c) Input Voltage. An oset of
1 V was intentionally added for visibility.
VL VS Vb
Vref
Pulse with rise and fall
times of 100 ns
Vs Vb
Vref
VL
Vout1
RL CL
Rb
R1
200 m
200 m
200 m
200 m
10 nH
10 nH
10 nH
10 nH
200 m
10 nH
10 pF
50
LDO
IL,MIN
IL,MAX
Vout
X 1 X 4
600 fF
Figure 3.14: Load transient test bench
34
0 5 10 15 20 25
0
1
2
3
4
5
6
7
8
O
u
t
p
u
t

(
V
)
0 5 10 15 20 25
0
20
40
L
o
a
d

C
u
r
r
e
n
t

(
m
A
)
Time (s)
0 2 4 6 8 10 12
0
1
2
3
4
5
6
7
8
O
u
t
p
u
t

(
V
)
LI
Q
!LDO
MI
Q
!LDO
MI
Q
!LDO
LI
Q
!LDO
50 mA
5 mA
100 ns 100 ns
(c)
(b)
(a)
Figure 3.15: Load transient. (a) Output voltage with 100 pF load capacitance,
(b) output voltage without 100 pF load capacitance, (c) Load Current. An oset
of 2 V was intentionally added for visibility.
The next chapter begins with the layout and the latter part shows experi-
mental results of the above four LDO designs.
35
Chapter 4
EXPERIMENTAL RESULTS
This section shows the layout and micrograph of all the LDOs. It is then followed
by experimental setup and nally the dropout, line and load hardware measure-
ments.
4.1 Layout
The LDOs proposed in Chapter 3 were designed and simulated in the Ca-
dence design environment and fabricated in the ON-Semi 0.5-m CMOS process.
Fig. 4.5 shows the layout of all designs. Fig. 4.6 shows the micrograph of all de-
signs. A technique called strapping was used to layout the huge pass transistor.
With the help of this technique, the maximum load current can be suciently
accommodated in the huge pass transistor. Common-centroid technique is used
to match the transistors in the dierential pairs and also in the current mirrors
to exactly mirror the current. Layout of all the individual LDOs is shown in
Fig. 4.1, Fig. 4.2, Fig. 4.3 and Fig. 4.4.
4.2 Experimental Setup
All the LDO designs should be tested with and without an external capac-
itor of 100 pF. If the chip is placed on a bread board, it automatically gets loaded
with the huge parasitic capacitance of the bread board. Hence, testing with no
external capacitance is not possible on a bread board. Hence the chip was tested
on a PCB which has less parasitic capacitance when compared to the bread board.
36
Figure 4.1: Layout of LDO from [1] in 0.5-m process
Appendix A describes the procedure for testing all LDO designs. The
designs were tested on a PCB. Used Express SCH and Express PCB to draw
schematic and layout of the PCB. Appendix B gives the layout of the PCB.
37
Figure 4.2: Layout of compensated form of LDO from [1]
The equipment used for testing all the above designs is given below.
1. Oscilloscope: Hewlett Packard: 54600B: 100 MHz, Digital Storage Oscil-
loscope.
2. Function Generator: Agilent : 33120A: 15 MHz Function/Arbitary Wave-
form Generator.
3. Digital Multimeter: Agilent : 34401A : 6
1
2
Digit Multimeter.
4. DC Power Supply: Agilent : E3631A : 0-6 V,5A/,0-25V, 1A Triple
Output DC Power Supply.
38
Figure 4.3: Layout of LI
Q
-LDO
4.3 Dropout Voltage Measurements
The dropout voltage for all designs were calculated using the denition [13]
V
DO
(V
s
V
out
)|
V
out
=V
out,max
100mV
(4.1)
39
Figure 4.4: Layout of MI
Q
-LDO
Table 4.1: Measured Dropout Voltage
Design Dropout Voltage
LDO from [1] in 0.5-m process 164 mV
Compensated form of LDO in [1] 164 mV
LI
Q
-LDO 164 mV
MI
Q
-LDO 129 mV
A measured plot for V
in
and V
out
for a slowly rising V
in
is shown in Fig. 4.7.
Matlab was used for plotting waveforms (See Appendix D for code). The measured
dropout voltage at the maximum load current for all designs is given in Table 4.1.
40
Figure 4.5: Layout all LDO designs
4.4 Line Transient Measurements
In [1], while performing the transient test, their input voltage was varied
from 1.2 V to 1.7 V, hence using the scaling factor we have varied the input voltage
from 2 V to 2.8 V. From the plots provided in [1], the rise and fall times are 350
ns and 750 ns, respectively, which tend to decrease measured values of overshoot
and undershoot. Unlike [1], we have tested our circuits with rise and fall times of
100 ns. The load current for this test is 1 mA. Fig. 4.8 shows the performance
41
LDO 1 LDO 2
LDO 3 LDO 4
Figure 4.6: Micrograph view of all LDO designs
of all designs, with and without a capacitive load of 100 pF. Matlab was used for
plotting waveforms (See Appendix D for code). The undershoot, overshoot and
the regulation of all designs are given in Table 4.2.
4.5 Load Transient Measurements
While performing the load transient test in [1], the rise and fall times are
500 ns and 200 ns respectively. But, in our load transient test, the load current
was varied with rise and fall times of 100 ns. The load current for the LDO in [1]
and its compensated form is varied from 50 A to 50 mA. The load current for
42
0 1 2
0
1
2
V
i
n

a
n
d

V
o
u
t
0 1 2
0
1
2
V
i
n

a
n
d

V
o
u
t
Vin
Dropout Voltage
= 129 mV
Dropout Voltage
= 164 mV
100 mV
100 mV
Vout
Peak
Vout
Peak
Figure 4.7: Dropout voltage measurement at maximum load current
Table 4.2: Line Transient
With Load Capacitance of 100 pF
Design 1
Design 2
LI
Q
-LDO MI
Q
-LDO
Overshoot 567 mV 331 mV 309 mV 265 mV
Undershoot 788 mV 551 mV 359 mV 334 mV
Regulation 0.9 mV/V 0.8 mV/V 0.8 mV/V 0.8 mV/V
Total Variation 1.36 V 882 mV 668 mV 599 mV
Without Load Capacitance of 100 pF
Undershoot 787 mV 567 mV 315 mV 321 mV
Regulation 0.6 mV/V 0.8 mV/V 1 mV/V 0.3 mV/V
Total Variation 1.34 V 898 mV 586 mV 561 mV
Design 1 refers to LDO from [1] in 0.5-m process and design 2 refers to
compensated form of design 1
43
0 2 4 6 8 10 12 14 16 18 20
1.5
2
2.5
3
I
n
p
u
t
0 2 4 6 8 10 12 14 16 18 20
0
1
2
3
4
5
O
u
t
p
u
t
0 2 4 6 8 10 12 14 16 18 20
0
1
2
3
4
5
O
u
t
p
u
t
Time (s)
(a)
(b)
(c)
100 ns 100 ns
MI
Q
!LDO
LI
Q
!LDO
MI
Q
!LDO
LI
Q
!LDO
Figure 4.8: Line Transient Response. (a) Input Waveform, (b) output voltage with
100 pF load capacitance and (c) output voltage without 100 pF load capacitance
at load current of 1 mA. An oset of 1 V was intentionally added for visibility.
the design LI
Q
-LDO is varied from 1 A to 50 mA and for the design MI
Q
-LDO,
it is varied from 0 to 5 mA. Fig. 4.9 shows the performance of all designs, with
and without a capacitive load of 100 pF. Matlab was used for plotting waveforms
(See Appendix D for code). The undershoot, overshoot and the regulation of all
designs are given in Table 4.3.
The measured value of quiescent current for all designs with no load current
is given in Table 4.4.
The next chapter compares our LDO designs with the other LDO designs
using a FOM.
44
Table 4.3: Load Transient
With Load Capacitance of 100 pF
Design 1
Design 2
LI
Q
-LDO MI
Q
-LDO
Undershoot 1.3 V 885 mV 622 mV 776 mV
Regulation 0.07 mV/mA 0.1 mV/mA 0.1 mV/mA 0.8 mV/mA
Total Variation 1.83 V 1.3 V 1 V 0.95
Without Load Capacitance of 100 pF
Undershoot 1.2 V 978 mV 747 mV 1 V
Regulation 0.07 mV/mA 0.1 mV/mA 0.1 mV/mA 0.75 mV/mA
Total Variation 1.73 V 1.48 V 1.2 V 1.2 V
Design 1 refers to LDO from [1] in 0.5-m process and design 2 refers to
compensated form of design 1
Table 4.4: Measured Quiescent Current
Design Quiescent Current
LDO from [1] in 0.5-m process 2 A
Compensated form of LDO in [1] 1.4 A
LI
Q
-LDO 12 A
MI
Q
-LDO 1.1 A
45
0 2 4 6 8 10 12 14 16 18 20
0
1
2
3
4
5
6
7
8
Time (s)
O
u
t
p
u
t
0 5 10 15 20 25 30 35 40
0
20
40
L
o
a
d

C
u
r
r
e
n
t
0 5 10 15 20 25 30 35 40
0
1
2
3
4
5
6
7
8
O
u
t
p
u
t
100 ns
50 mA
5 mA
100 ns
MI
Q
!LDO
LI
Q
!LDO
LI
Q
!LDO
MI
Q
!LDO
Figure 4.9: Load transient response. (a) Load current (b) output voltage with
100 pF load capacitance (c) output voltage without load capacitance. An oset
of 2 V was intentionally added for visibility.
46
Chapter 5
DISCUSSION AND CONCLUSION
We propose a Figure of Merit (FOM), which is based on the FOM proposed in
[18]. The FOM is given by
FOM =
C
OUT
V
OUT
(I
Q@I
L,MAX
+I
L,MIN
)
I
2
L,MAX
(5.1)
In the above equation, we have included the minimum load current, be-
cause it also constitutes for the power consumption. An LDO should have less
variation in output voltage, low quiescent current, low output capacitance and
should withstand a large amount of variation in load current. Hence, the lower
the FOM, the better the design. Table 5.1 compares our LDO designs with oth-
ers. From the table it is evident that the design LI
Q
-LDO has the lowest FOM
compared to the other designs. Designs C-LDO (compensated form of LDO from
[1]) and MI
Q
-LDO has higher FOM compared to [1], but the design in [1] was not
tested with rise and fall times of 100 ns. The rise and fall times are 500 ns and
200 ns, which tend to decrease the total variation in output. When the design
in [1] was tested with rise and fall times of 100 ns, their design exhibited insta-
bility which is evident from Fig. 4.9. Hence, our designs perform better with rise
and fall times of 100 ns.
The circuit topology in [1] is unstable when tested with rise and fall times of
100 ns. Hence, the topology is helpful only if it is compensated. From the above
47
Table 5.1: FOM Comparision Table
Previous Work This Work
[4] [1] [18] C-LDO
LI
Q
MI
Q
Year 2007 2007 2010 2011 2011 2011
Process (m) 0.35 0.18 0.5 0.5 0.5 0.5
V
LINE
(V) 2.0- 5.5 1.0-1.7 1.4-4.2 1.66-2.8 1.66-2.8 1.63-2.8
V
OUT
(V) 1.8 0.9 1.21 1.5 1.5 1.5
V
DO
(V) 0.2 0.1 0.2 0.16 0.16 0.13
V
OUT
(V) 54m 700m
120m 1.3 1 950m

I
L,MAX
(mA) 200 50 100 50 50 5
I
L,MIN
(A) 0 50 1 50 1 0
I
Q@I
L
=0
(A) 340 1.2 45 1.2 12 1.2
C
OUT
1 F 100 pF 100 nF 100 pF 100 pF 100 pF
FOM (ps) 459 1.436 55.2 2.65 0.52 4.56
C-LDO refers to compensated form of LDO in [1] in 0.5-m process.
T
rise
and T
fall
are 500 ns and 200 ns, respectively. Estimated from the plots
provided in [1].
results we can conclude that our design LI
Q
-LDO is suitable for low powered
applications as it uses 13 A of quiescent current and its output voltage can be
scaled accordingly with the help of feedback resistors. The design MI
Q
-LDO is a
true micro-power LDO design which uses only 1.2 A of quiescent current, making
it suitable for implantable electronic devices.
In this work, the total variation in output voltage cannot be handled by
micro-processors. Hence, this work can be extended by reducing the total variation
of output voltage of all the designs. AC analysis was not performed at dierent
48
load currents. All designs should be veried for stability at dierent load currents.
The MI
Q
-LDO design can be further improved by reducing the total quiescent
current to 120 nA or 1.2 nA.
One of the issues with the MI
Q
-LDO design is the settling time. It takes
a longer time to settle when compared to the simulation results. The dropout
voltage for all the designs in simulation was 100 mV, but our hardware measure-
ments gave a dropout voltage of 160 mV for the rst three LDO designs and for
the fourth design it was 130 mV.
49
APPENDICES
APPENDIX A
Test Document
A.1 Circuit 1:
A.1.1 Procedure for Measuring Dropout Voltage:
1. Place the chip on a PCB (Printed Circuit Board). (Note: Placing and testing
the chip on breadboard loads the output pin with a capacitance of up to
60 pF. Hence, testing the chip with no external capacitor is not possible on
a breadboard).
2. The setup for measuring dropout voltage is shown in Fig. A.1.
3. Ground pin 12 (Vss 1).
4. Close the jumpers J11 and J12 to attach the BJT current mirror to pins
16, 17, 18 and 19 as shown in Fig. A.1. Close the jumper J4 to connect
the resistor R1a. The other end of the resistor R1a is connected to the DC
power supply 4 which supplies a voltage of 2 V. The value of R
1a
is chosen
Figure A.1: Jumper Conguration for Dropout Voltage on Circuit 1
52
Table 1: Current Flowing through each resistor
Measured R Expected I Measured Voltage Drop Computed I
R1a 12.5 mA
R4c 50 mA
R5c 12.5 mA
in such way that the current owing through it is 12.5 mA. The value of
resistor R
1a
can be estimated from the equation below.
R
1a
=
2 0.7
12.5 10
3
= 104 (1)
Close the jumpers J9a and J9b. The main purpose of the resistors R
4c
and
R
5c
is to ensure that the right amount of current is owing through the
BJTs. The BJT current mirror can be built with an IC whose part number
is CA 3046. The value of resistors R
4c
and R
5c
is given in Fig. A.1. Measure
the voltage drops across R
1a
, R
4c
and R
5c
and complete the below table 1.
5. Apply Vref 1 = 1.5 V from the DC power supply 1 to pin 22.
6. Close the jumper J2 to connect the resistor R
2a
to the pins 16, 17, 18 and
19. Connect the other end of the resistor to Vss 1 (pin 12). The value of
R
2a
is chosen in such a way that the current owing through it is 50 A.
The resistor R
2a
can be estimated from the equation below
R
2a
=
1.5
50 10
6
= 30k (2)
7. Close the jumper J13 to connect the the resistor R
3a
to pin 21. Connect the
other end of the resistor to the DC power supply 2 which supplies a voltage
of 2 V. The value of R
3a
is chosen in such a way that the current owing
53
Figure A.2: Setup for Measuring 100 nA
through it is 100 nA. The value of R
3a
can be estimated from the equation
below
R
3a
=
2 0.635
100 10
9
= 13.65M (3)
Note: As the value of R3 (R
3a
, R
3b
, R
3c
, R
3d
) is higher, it may be built with
two resistors in series.
To measure the current owing through R
3a
, add a wire connection from V
b
to CMOS op-amp follower as shown in Fig. A.2. Measure the voltage drop
from the DC power supply 2 to output of follower. Measure the voltage
drops across R
2a
and R
3a
R2a 50 uA
R3a 100 nA
8. Connect 10 F tantalum capacitors to pins 13, 14, 15, 21 and 22 to reduce
noise.
54
Figure A.3: Jumper Conguration for Measuring Ground Current on Circuit 1
9. Attach a DMM to pin 20. The value of Vout 1 can be measured using DMM.
10. Attach the DC power supply 3 to pins 13, 14 and 15. By hand slowly vary
the voltage from 0 V to 2 V. item Complete the below table 3. Measure the
dropout voltage using the equation
V
DO
(V
s
V
out
)|
V
out
=V
out,max
100mV
(4)
Verify that I
L
= 50 mA at dropout voltage measurement.
A.1.2 Procedure for Measuring Ground Current:
1. The setup for measuring ground current is shown in Fig. A.3.
2. Open the jumper J4 to disconnect the resistor R
1a
. Connect a DMM in
between DC power supply 3 and pins 13, 14 and 15 to measure the current
i2 owing through Vs at 0 A load current. Complete the table 4.
55
3. The current i
1
owing through resistor R
3a
is known and current i
3
owing
through R
2a
is also known.
4. The ground current is calculated using the following equation
i
Ground
= i
1
+i
2
i
3
(5)
Complete the table 5.
A.1.3 Line Transient Test Procedure:
1. The setup for line transient is shown in Fig. A.4.
2. Open the jumper J10 to disconnect the capacitor from pins 13, 14 and 15.
(Note: The main purpose of detaching the capacitor from Vs is that, the
Figure A.4: Jumper Conguration for Line Transient on Circuit 1
56
capacitor doesnot allow Vs to vary 0.8 V within 100 ns i.e. with the capacitor
attached to Vs it is not possible to vary Vs with rise and fall times of 100 ns).
3. Open the jumper J4 and close the jumper J5 to connect the resistor R
1b
.
The value of resistor R
1b
is chosen in such a way that the current owing
through it 250 A. The value of resistor R
1b
can be estimated from the
equation below. Complete the table table 6.
R
1b
=
2 0.7
250 10
6
= 5.2k (6)
4. Open the jumpers J9a and J9b and connect the jumpers J7a and J7b to
ensure that the current owing through the BJT current mirror is 1 mA.
The values of resistors R
4a
and R
5a
are given in g. 3. Measure the voltage
drops across R
4a
and R
5a
5. Now input a wave varying from 2.05 V to 2.85 V with rise and fall time
of 100 ns to pins 13, 14 and 15. (Note: As the function generator has an
internal resistance of 50 and the current owing through it is 1 mA, the
voltage drop across it is 50 mV. Hence, varying the input wave from 2.05 V
to 2.85 V at the function generator ensures the input varies from 2 V to 2.8
V at the pins 13, 14 and 15). The frequency of the waveform is 50 kHz.
Procedure for Generating a 100 ns Rise and Fall Times Waveform:
(a) Connect the CPU (Central Processing Unit) of the system to func-
tion generator with the help of GPIB (General Purpose Interface Bus).
GPIB which was developed by HP (Hewlett Packard), is a common
protocol used by dierent testing equipments for their communication.
57
With help of probes connect the function generator and the oscillo-
scope.
(b) On the desktop, launch the waveform editor.
(c) From the communications menu, select connection, when the connec-
tion dialog window appears double click on GPIB::10::INSTR, then
select the Internal Type Arb and then click connect.
(d) From the menu select Line Draw Mode, then draw the desired waveform
with help of mouse.
(e) After drawing the waveform, click on Send Waveform to Arb on the
menu. When the window appears, set the desired frequency and am-
plitude and then click send.
(f) Observe the waveform on the scope.
(g) With the help of function generator, parameters like frequency, ampli-
tude of the waveform on the scope can be changed.
6. After generating the waveform, the function generator is connected to a DC
power supply 3 which is connected to the pins 13, 14 and 15 (shown in gure
3). The voltage from DC power supply 3 is 2.05 V. The function generator
pulses from 0 V to 0.8 V. (Note: An oset of 2 V is not possible for the
function generator. The maximum low-level voltage is 0 V for the function
generator). Complete the table 8
7. The BJT current mirror setup remains the same and the load current is
1 mA.
8. With the help of 10x probes observe both Vs 1 and Vout 1 (pin 20) wave-
forms on oscilloscope (on DC coupling, with 0.5V/div on vertical scale)
58
and measure the undershoot, overshoot, line regulation, trise and tfall using
cursors. Plot the observed waveforms below.
9. Store the waveforms on Digital Scope and save to oppy in x,y data format.
10. Now close the jumper J1 to attach an external capacitor of 100 pF to pins
16, 17, 18 and 19 and measure the undershoot, overshoot, line regulation,
trise and tfall. Plot the observed waveforms below.
A.1.4 Load Transient Test Procedure:
1. The setup for load transient is shown in Fig. A.5.
2. Open the jumper J1 to disconnect 100 pF external capacitor from pins 16,
17, 18 and 19.
3. Connect the jumper J10 to attach the capacitor to pins 13, 14 and 15.
4. Disconnect the function generator from pins 13, 14 and 15 and apply Vs 1
= 2 V from DC power supply 3.
1b
and close the jumper J4
to attach the resistor R
1a
to the setup. Similarly, open the jumpers J7a and
J7b to disconnect the resistors R
4a
and R
5a
and close the jumpers J9a and
J9b to reconnect the resistors R
4c
and R
5c
to the setup.
6. Disconnect the other end of R
1a
from DC power supply 4 and connect to the
function generator. Input a wave varying from voltages 0 V to 2 V with rise
and fall times of 133 ns. The value of V1 is chosen in such a way that the
current owing through it should vary from 0 to 50 mA. Follow the above
59
Figure A.5: Jumper Conguration for Load Transient on Circuit 5
procedure for generating a 133 ns rise and fall times waveform. Initially set
the frequency to 1 Hz and measure the voltage drops across the resistors
R
1a
, R
4c
and R
5c
and complete the table below. Set the frequency to 50 kHz
once the measurements are done. (Note: The rise and fall times should be
set to 133 ns because after 33 ns the emitter voltage reaches 0.5 V which
turns ON the BJT and hence the current starts owing through the BJT
after 33 ns. So, the load current has rise and fall times of 100 ns).
7. Detach the scope probe from pins 13, 14 and 15 and connect it across resis-
tors R4c.
8. With the help of 10x probes observe the waveforms of voltage drop across
R
4c
on oscilloscope and measure the undershoot, overshoot, load regulation,
trise and tfall using cursors. Plot the observed waveforms below.
60
10. Now close the jumper J1 to attach an external capacitor of 100 pF to pins
16, 17, 18 and 19 and measure the undershoot, overshoot,load regulation,
trise and tfall. Plot the observed waveforms below.
A.2 Circuit 2:
1. Repeat all the steps above, except for step 5. Instead apply Vref 2 = 1.2 V
from DC power supply 1 to pin 11.
2. Open the jumpers J11 and J12 to disconnect the BJT current mirror setup
from circuit 1 and close the jumpers J16 and J17 to connect the BJT current
mirror to circuit 2.
3b
to the setup. The value of R
3b
is same as R
3a
.
4. Open the jumper J15 while performing line transient test procedure.
A.3 Circuit 3:
from circuit 2 and close the jumpers J20 and J21 to connect the BJT current
mirror to circuit 3.
3c
3c
can be estimated from the below equation
R
3c
=
2 0.754
1 10
6
= 1.2453M (7)
61
2a
and close the jumper J3
to connect the resistor R
2b
to the setup. The value of resistor R
2b
is chosen
in such a way that the current owing through it is 1 A. The value of
resistor R
2b
can be estimated from the equation below. Complete the table
below.
R
2b
=
1.5
1 10
6
= 1.5M (8)
A.4 Circuit 4:
from circuit 3 and close the jumper J24 to connect the BJT current mirror
to circuit 4.
3. Open the jumper J18 and close the jumper J22 to connect the resistor R3d
3d
is same as R
3a
.
2b
from the setup.
5. While performing dropout and load transient tests, open jumpers J7a, J7b,
J9a, J9b, J4 and J5 and close the jumpers J8a, J8b and J6 to connect the
resistors R
4b
, R
5b
and R
1c
to the setup. The value of resistors R
4b
and R
5b
is given the gures. The value of resistor R
1c
is chosen in such a way that
the current owing through it 1.25 mA. The value of resistor R
1c
can be
estimated from the equation below. Measure the voltage drops across the
62
resistors and complete the table below.
R
1c
=
2 0.7
1.25 10
3
= 1040 (9)
Note: In the testing setup, there are four dierent R
3
resistors (R
3a
, R
3b
, R
3c
and R
3d
) for four dierent circuits. All these have same value and current ow-
ing through them is 100 nA. Dierent jumpers should be used to connect and
disconnect these resistors from the setup. There is only one BJT current mirror
circuit in the testing setup. Dierent set of jumpers should be used to connect
and disconnect this BJT current mirror setup to dierent circuits.
63
Table 3: Dropout Voltage Table
Vs Vout IL
0
0.2
0.4
0.6
0.8
1
1.2
1.25
1.3
1.35
1.4
1.45
1.5
1.55
1.6
1.65
1.7
1.8
1.9
2.0
64
Table 4: Current Flowing through Vs
Expected I Measured I
i
2
51.2 A
Table 5: Current Flowing through ground
Expected I Measured I
Ground Current 1.2 A
R1b 250 muA
R4a 1 mA
R5a 250 A
R1a 12.5 mA
R4c 50 mA
R5c 12.5 mA
65
APPENDIX B
PCB Design
F
i
g
u
r
e
A
.
6
:
S
c
h
e
m
a
t
i
c
o
f
P
C
B
67
F
i
g
u
r
e
A
.
7
:
L
a
y
o
u
t
o
f
P
C
B
68
F
i
g
u
r
e
A
.
8
:
F
i
n
a
l
P
C
B
69
APPENDIX C
Maple Work for Small-Signal Analysis
(3) (3)
(2) (2)
(1) (1)
(4) (4)
collect solve Vs = V4 KVi, 2 gm1$Vs C
V1
z1
Ci1 = 0, gmp$V1 C
Vo
z2
Ci2 Ki1 = 0, i1
=
V1 KVo
zc1
, i2 =
Vo
zc2
, z1 = r1, z2 =
r2
1 Cs$r2$CL
, zc1 =
1
s$cc1
, zc2 =
1 Cs$rc2$cc2
s$cc2
,
V4 KVi = i5$Zi, Vref KVf = Vd, gm3$Vd C
V3
z3
Ci3 = 0, V3 KV4 = i3$zc3, gm4$V3 C
V4
z4
C
V4
zc4
Ci5 Ci4 Ki3 = 0, V4 KVf = i4$zf1, Vf = i4$zf2, z3 = r3, z4 = r4, zc3 =
1
s$cgd1
, zc4
=
1 Cs$rc4$cc4
s$cc4
, zf1 = Rf1, zf2 = Rf2, Zi =
1
gmi
, i1, i2, V1, Vo, zc1, zc2, z1, z2, i3, i4, i5,
V3, V4, Vf, Vd, z3, z4, zc3, zc4, zf1, zf2, Zi, Vs , s
After solving the above set of equations for Vo and setting 's' = 0 and 'Vref' = 0, the obtained Vo is:
Vo = K
2 r2 gm1 r1 gmp Vi gm4 r4 gm3 r3 Rf2 Cr4 CRf1 CRf2
r4 CRf1 CRf2 Cgm4 r4 gm3 r3 Rf2 Cgmi r4 Rf2 Cgmi r4 Rf1
, Vref = 0, s = 0
Considering the denominator in Vo equation:
By taking the co-efficient of 's' from the Vo equation and neglecting terms (small in value), the first pole
can be approximated as:
wp1 =
1
r2 cc1 gmp r1
From the below equation, second pole can be approximated as
solve wp1 =
1
r2 cc1 gmp r1
, wp1$wp2 =
1
co Kefficients of 'S
2
'
, wp1, wp2
wp2 =
1
rc4 cc4 Crc2 cc2
From the below equation, third pole can be approximated as
solve wp1 =
1
r2 cc1 gmp r1
, wp2 =
1
rc4 cc4 Crc2 cc2
, wp1$wp2$wp3
=
1
3
'
, wp1, wp2, wp3
wp3 =
1
rc2 cc2
C
1
rc4 cc4
From the below equation, fourth pole can be approximated as
solve wp1 =
1
r2 cc1 gmp r1
, wp2 =
1
rc4 cc4 Crc2 cc2
, wp3 =
1
rc2 cc2
C
1
rc4 cc4
, wp1$wp2$wp3
71
(5) (5)
(8) (8)
(6) (6)
(7) (7)
$wp4 =
1
4
'
, wp1, wp2, wp3, wp4
wp4 =
gmp
CL
Considering Denominator in Vo equation:
Taking co-efficients of 's', and neglecting terms, the first zero can be approximated as:
wz1 =
1
rc4 cc4 Crc2 cc2
solve wz1 =
1
rc4 cc4 Crc2 cc2
, wz1$wz2 =
1
co Kefficients of S
2
, wz1, wz2
wz2 =
1
rc2 cc2
C
1
rc4 cc4
solve wz1 =
1
rc4 cc4 Crc2 cc2
, wz2 =
1
rc2 cc2
C
1
rc4 cc4
, wz1$wz2$wz3
=
1
co Kefficients of s
3
, wz1, wz2, wz3
wz3 = K
gmp
cc1
72
APPENDIX D
Matlab Codes for Plotting Simulated and Measured Results
Code to plot dropout voltage measurement for all designs from
simulation
1 clc;
2 close all;
3 clear all;
4 a=csvread(vdo.csv);
5 a(:,1) = a(:,1)*10^3;
6 plot (a(:,1),a(:,2:1:3),k);
7 ylabel(Voltage);
8 xlabel(Time (ms));
9 axis([0 50 0 2]);
10 grid on;
Code to plot Gain for all designs from simulation
1 clc;
2 clear all;
3 close all;
4 a=csvread(Gain.csv);
5 a(:,3) = a(:,3)+10;
6 a(:,4) = a(:,4)+20;
7 a(:,5) = a(:,5)+30;
8 plot(a(:,1),a(:,2:1:5),k);
9 grid on;
Code to plot Phase for all designs from simulation
1 clc;
2 clear all;
3 close all;
4 a=csvread(Phase.csv);
5 a(:,3) = a(:,3)+20;
6 a(:,4) = a(:,4)+40;
7 a(:,5) = a(:,5)+60;
8 plot(a(:,1),a(:,2:1:5),k);
9 grid on;
Code to plot line transient for all designs from simulation
74
1 clc;
2 close all;
3 clear all;
4 a=csvread(Line_With.csv);
5 a(:,1) = a(:,1)*10^6;
6 a(:,4) = a(:,4)+1;
7 a(:,5) = a(:,5)+2;
8 a(:,6) = a(:,6)+3;
9 subplot(3,1,1);
10 plot (a(:,1),a(:,3:1:6),k);
11 ylabel(Output (V));
12 axis([0 12 0 5]);
13 grid on;
14 subplot(3,1,3);
15 plot (a(:,1),a(:,2),k);
16 ylabel(Input (V));
17 xlabel(Time (us));
18 axis([0 12 2 2.9]);
19 grid on;
20
21 b=csvread(Line_Without.csv);
22 b(:,1) = b(:,1)*10^6;
23 b(:,4) = b(:,4)+1;
24 b(:,5) = b(:,5)+2;
25 b(:,6) = b(:,6)+3;
26 subplot(3,1,2);
27 plot (b(:,1),b(:,3:1:6),k);
29 axis([0 12 0 5]);
30 grid on;
Code to plot load transient for all designs from simulation
1 clc;
2 close all;
3 clear all;
4 a=csvread(Load_With.csv);
5 a(:,1) = a(:,1)*10^6;
6 a(:,3) = a(:,3)+2;
7 a(:,4) = a(:,4)+4;
8 a(:,5) = a(:,5)+6;
9 a(:,6) = a(:,6)*10^3;
10 a(:,7) = a(:,7)*10^3;
11 a(:,8) = a(:,8)*10^3;
12 a(:,9) = a(:,9)*10^3;
13 subplot(3,1,1);
14 plot (a(:,1),a(:,2:1:5),k);
16 axis([0 25 0 8]);
75
17 grid on;
18 subplot(3,1,3);
19 plot (a(:,1),a(:,6:1:9),k);
20 ylabel(Load Current (mA));
21 xlabel(TIme (us));
22 axis([0 25 0 55]);
23 grid on;
24
25 b=csvread(Load_Without.csv);
26 b(:,1) = b(:,1)*10^6;
27 b(:,8) = b(:,8)+2;
28 b(:,7) = b(:,7)+4;
29 b(:,6) = b(:,6)+6;
30 subplot(3,1,2);
31 plot (b(:,1),b(:,6:1:9),k);
33 axis([0 12 0 8]);
34 grid on;
Code to plot dropout voltage measurement for all designs from
hardware measurements
1 clc;
2 clear all;
3 close all;
4 a=csvread(VDO2.csv);
5 % subplot(2,2,1);
6 % plot (a(:,5),a(:,1:4:5),k);
7 % title(Circuit 1);
8 % ylabel(Vin and Vout);
9 % xlabel(Vin);
10 % grid on;
11 %
12 % subplot(2,2,2);
13 % plot (a(:,5),a(:,2:3:5),k);
14 % title(Circuit 2a);
15 % ylabel(Vin and Vout);
16 % xlabel(Vin);
17 % grid on;
18
19 subplot(2,1,1);
20 plot (a(:,5),a(:,3:2:5),k);
21 % title(Circuit 2b);
22 ylabel(Vin and Vout);
23 xlabel(Vin);
24 grid on;
25
26 subplot(2,1,2);
76
27 plot (a(:,5),a(:,4:1:5),k);
28 % title(Circuit 3);
29 ylabel(Vin and Vout);
30 xlabel(Vin);
31 grid on;
Code to plot line transient results for all designs from hardware
measurements
1 clc;
2 clear all;
3 close all;
4 q = 20;
5 H = 0:q/1999:q;
6 H1 = transpose(H);
7 a1=csvread(1Output_With.csv);
8 a2=csvread(1Input_With.csv);
9 a1(:,1)=(a1(:,1)*2)+1.5;
10 a2(:,1)=a2(:,1)*2;
11 a2(:,1) = a2(:,1)+2;
12 b1=csvread(2Output_With.csv);
13 b2=csvread(2Input_With.csv);
14 b1(:,1)=(b1(:,1)*2)+2.5;
15 b2(:,1)=b2(:,1)*2;
16 b2(:,1) = b2(:,1)+2;
17
18 c1=csvread(3Output_With.csv);
19 c2=csvread(3Input_With.csv);
20 c1(:,1)=(c1(:,1)*0.8)+3.5;
21 c2(:,1)=c2(:,1)*2;
22 c2(:,1) =c2(:,1)+2;
23
24 %d1=csvread(4Output_With.csv);
25 %d1=csvread(4Output_With_50pF.csv);
26 d1=csvread(4Output_With_78pF.csv);
27 d2=csvread(4Input_With.csv);
28 d1(:,1)=(d1(:,1)*0.8)+4.5;
29 d2(:,1)=d2(:,1)*2;
30 d2(:,1) = d2(:,1)+2;
31 aq1=csvread(1Output_Without.csv);
32 aq2=csvread(1Input_Without.csv);
33 aq1(:,1)=(aq1(:,1)*2)+1.5;
34 aq2(:,1)=aq2(:,1)*2;
35 aq2(:,1) = aq2(:,1)+2;
36
37
38 bq1=csvread(2Output_Without.csv);
39 bq2=csvread(2Input_Without.csv);
77
40 bq1(:,1)=(bq1(:,1)*2)+2.5;
41 bq2(:,1)=bq2(:,1)*2;
42 bq2(:,1) = bq2(:,1)+2;
43
44 cq1=csvread(3Output_Without.csv);
45 cq2=csvread(3Input_Without.csv);
46 cq1(:,1)=(cq1(:,1)*0.8)+3.5;
47 cq2(:,1)=cq2(:,1)*2;
48 cq2(:,1) =cq2(:,1)+2;
49
50
51 dq1=csvread(4Output_Without.csv);
52 dq2=csvread(4Input_Without.csv);
53 dq1(:,1)=(dq1(:,1)*0.8)+4.5;
54 dq2(:,1)=dq2(:,1)*2;
55 dq2(:,1) = dq2(:,1)+2;
56
57 subplot(3,1,1);
58 % plot(H1(:,1),a2(:,1),k,H1(:,1),b2(:,1),k,
59 %H1(:,1),c2(:,1),k,H1(:,1),d2(:,1),k);
60 plot(H1(:,1),b2(:,1),k);
61 ylabel(Input);
62 grid on;
63 subplot(3,1,2);
64 plot(H1(:,1),a1(:,1),k,H1(:,1),b1(:,1),k,
65 H1(:,1),c1(:,1),k,H1(:,1),d1(:,1),k);
66 ylabel(Output);
67 grid on;
68 subplot(3,1,3);
69 plot(H1(:,1),aq1(:,1),k,H1(:,1),bq1(:,1),k,
70 H1(:,1),cq1(:,1),k,H1(:,1),dq1(:,1),k);
71 ylabel(Output);
73 grid on;
Code to plot load transient results for all designs from hardware
measurements
1 clc;
2 clear all;
3 close all;
4
5 q = 20;
6 H = 0:q/1999:q;
7 H1 = transpose(H);
8
9 a1=csvread(1Input_Without1.csv);
78
25
26 b1=csvread(1Output_Without_m.csv);
27 b1(:,1)=(b1(:,1)*2)+1.5;
28
29 a(:,1)=(a1(:,1)+a2(:,1)+a3(:,1)+a4(:,1)+a5(:,1)
30 +a6(:,1)+a7(:,1)+a8(:,1)
31 +a9(:,1)+a10(:,1)+a11(:,1)+a12(:,1)
32 +a13(:,1)+a14(:,1)+a15(:,1)+a16(:,1))/(16);
33 a(:,1)=(((a(:,1)*0.08)+0.00285)/1.098)*1000;
34
35 % subplot(4,2,1);
36 % plot(H1(:,1),a(:,1),k);
37 % subplot(4,2,3);
38 % plot(H1(:,1),b1(:,1),k);
39
40 c1=csvread(2Input_Without1.csv);
56
57 d1=csvread(2Output_Without_m.csv);
58 d1(:,1)=(d1(:,1)*2)+2+1.5;
59
60 c(:,1)=(c1(:,1)+c2(:,1)+c3(:,1)+c4(:,1)+c5(:,1)
61 +c6(:,1)+c7(:,1)+c8(:,1)+c9(:,1)+c10(:,1)+c11(:,1)
79
62 +c12(:,1)+c13(:,1)+c14(:,1)+c15(:,1)+c16(:,1))/(16);
63 c(:,1)=((((c(:,1)*0.08))+0.00285)/1.098)*1000;
64
65 % subplot(4,2,2);
66 % plot(H1(:,1),c(:,1),k);
67 % subplot(4,2,4);
68 % plot(H1(:,1),d1(:,1),k);
69
70 e1=csvread(3Input_Without1.csv);
86
87 f1=csvread(3Output_Without_m.csv);
88 f1(:,1)=(f1(:,1)*2)+4+1.5;
89
90 e(:,1)=(e1(:,1)+e2(:,1)+e3(:,1)+e4(:,1)+e5(:,1)
91 +e6(:,1)+e7(:,1)+e8(:,1)+e9(:,1)+e10(:,1)+e11(:,1)
92 +e12(:,1)+e13(:,1)+e14(:,1)+e15(:,1)+e16(:,1))/(16);
93 e(:,1)=(((e(:,1)*0.08)+0.00285)/1.098)*1000;
94
95 % subplot(4,2,5);
96 % plot(H1(:,1),e(:,1),k);
97 % subplot(4,2,7);
98 % plot(H1(:,1),f1(:,1),k);
99
100 g1=csvread(4Input_Without1.csv);
80
116
117 h1=csvread(4Output_Without_m.csv);
118 h1(:,1)=(h1(:,1)*2)+6+1.5;
119
120 g(:,1)=(g1(:,1)+g2(:,1)+g3(:,1)+g4(:,1)+g5(:,1)
121 +g6(:,1)+g7(:,1)+g8(:,1)+g9(:,1)+g10(:,1)+g11(:,1)
122 +g12(:,1)+g13(:,1)+g14(:,1)+g15(:,1)+g16(:,1))/(16);
123 g(:,1)=(((g(:,1)*0.08))/9.956)*1000;
124
125 % subplot(4,1,1);
126 % plot(H1(:,1),a(:,1),k,H1(:,1),c(:,1),k,
127 %H1(:,1),e(:,1),k,H1(:,1),g(:,1),k);
128 subplot(3,1,3);
129 plot(H1(:,1),b1(:,1),k,H1(:,1),d1(:,1),k,
130 H1(:,1),f1(:,1),k,H1(:,1),h1(:,1),k);
132 ylabel(Output);
133 axis([0 20 0 8.5]);
134
135 % % % % % % % % % % % % % % % % % % % % %
136
137 qq = 40;
138 Hq = 0:qq/1999:qq;
139 Hq1 = transpose(Hq);
140
141 aq1=csvread(1Input_With1.csv);
157
158 bq1=csvread(1Output_With.csv);
159 bq1(:,1)=(bq1(:,1)*2)+1.5;
160
161 aq(:,1)=(aq1(:,1)+aq2(:,1)+aq3(:,1)+aq4(:,1)+
162 aq5(:,1)+aq6(:,1)+aq7(:,1)+aq8(:,1)+aq9(:,1)+
163 aq10(:,1)+aq11(:,1)+aq12(:,1)+aq13(:,1)+aq14(:,1)+
81
164 aq15(:,1)+aq16(:,1))/(16);
165 aq(:,1)=(((aq(:,1)*0.08))/1.098)*1000;
166
167
168 cq1=csvread(2Input_With1.csv);
184
185 dq1=csvread(2Output_With.csv);
186 dq1(:,1)=(dq1(:,1)*2)+2+1.5;
187
188 cq(:,1)=(cq1(:,1)+cq2(:,1)+cq3(:,1)+cq4(:,1)+cq5(:,1)
189 +cq6(:,1)+cq7(:,1)+cq8(:,1)+cq9(:,1)+cq10(:,1)+
190 cq11(:,1)+cq12(:,1)+cq13(:,1)+cq14(:,1)+
191 cq15(:,1)+cq16(:,1))/(16);
192 cq(:,1)=((((cq(:,1)*0.08))+0.0003)/1.098)*1000;
193
194
195 eq1=csvread(3Input_With1.csv);
211
212 fq1=csvread(3Output_With.csv);
213 fq1(:,1)=(fq1(:,1)*2)+4+1.5;
214
82
215 eq(:,1)=(eq1(:,1)+eq2(:,1)+eq3(:,1)+eq4(:,1)+
216 eq5(:,1)+eq6(:,1)+eq7(:,1)+eq8(:,1)+eq9(:,1)+
217 eq10(:,1)+eq11(:,1)+eq12(:,1)+eq13(:,1)+eq14(:,1)
218 +eq15(:,1)+eq16(:,1))/(16);
219 eq(:,1)=(((eq(:,1)*0.08))/1.098)*1000;
220
221
222 gq1=csvread(4Input_With1.csv);
238
239 hq1=csvread(4Output_With.csv);
240 hq1(:,1)=(hq1(:,1)*2)+6+1.5;
241
242 gq(:,1)=(gq1(:,1)+gq2(:,1)+gq3(:,1)+gq4(:,1)
243 +gq5(:,1)+gq6(:,1)+gq7(:,1)+gq8(:,1)+gq9(:,1)
244 +gq10(:,1)+gq11(:,1)+gq12(:,1)+gq13(:,1)
245 +gq14(:,1)+gq15(:,1)+gq16(:,1))/(16);
246 gq(:,1)=(((gq(:,1)*0.08))/9.956)*1000;
247
248 subplot(3,1,1);
249 plot(Hq1(:,1),aq(:,1),k,Hq1(:,1),cq(:,1),
250 k,Hq1(:,1),eq(:,1),k,Hq1(:,1),gq(:,1),k);
251 ylabel(Load Current);
252 axis([0 40 0 54]);
253 % grid on;
254 subplot(3,1,2);
255 plot(Hq1(:,1),bq1(:,1),k,Hq1(:,1),dq1(:,1),
256 k,Hq1(:,1),fq1(:,1),k,Hq1(:,1),hq1(:,1),k);
257 ylabel(Output);
258 axis([0 40 0 8.5]);
259 % grid on;
83
REFERENCES
[1] T. Y. Man, P. K. T. Mok, and M. Chan, A High Slew-Rate Push-Pull
Output Amplier for Low-Quiescent Current Low-Dropout Regulators With
Transient-Response Improvement, IEEE Trans. Cir. Syst. II, vol. 54, no. 9,
pp. 755759, Sept. 2007.
[2] A. R. Garimella, On The Design of Analog, Mixed-Signal and Power Man-
agement Circuits for System-On-Chip Applications, 2010.
[3] R. J. Baker, CMOS Circuit Design, Layout and Simulation. Piscataway,
NJ, USA: A John Wiley and Sons, INC., Publication, 2005.
[4] M. Al-Shyoukh, H. Lee, and R. Perez, A Transient-Enhanced Low- Quies-
cent Current Low-Dropout Regulator With Buer Impedance Attenuation,
IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 17321742, Aug 2007.
[5] A. Asteriadis, T. Laopoulos, S. Siskosl, and M. Baeur, A Low Quiescent-
Current, Low Supply-Voltage Linear Regulator, in Proc. 21st IEEE Instrum.
Meas. Technol. Conf., May 2004, pp. 15361541.
[6] H. Lee, P. K. T. Mok, and K. N. Leung, Design of Low-Power Analog Drivers
Based on Slew-Rate Enhanced Crcuits for CMOS Low-Dropout Regulators,
IEEE Trans. Circuits Syst.II Exp. Briefs, vol. 52, no. 9, p. 563, Sep 2005.
[7] S. K. Lau, P. K. T. Mok, and K. N. Leung, A Low-Dropout Regulator for
SoC With Q-Reduction, IEEE Trans. Circuits Syst.II Exp. Briefs, vol. 42,
no. 3, p. 658, Mar 2007.
[8] W. Y. Leung, T. Y. Man, W. T. Chan, and M. Chan, A High Precision,
Output-Capacitor-Free Low Dropout Regulator for System-on-Chip Design,
in Circ. and Syst. ISCAS, IEEE Intl. Symp., May 2008, pp. 22422245.
[9] D. Grith, F. Dulger, G. Feygin, A. N. Mohieldin, and P. Vallur, A 65nm
CMOS DCXO System for Generating 38.4MHz and a Real Time Clock from
a Single Crystal in 0.09mm
2
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IEEE, May 2010, pp. 321324.
84
[10] G. A. Rincon-Mora and P. E. Allen, A Low-Voltage, Low Quiescent Current,
Low Drop-Out Regulator, IEEE J. Solid-State Circuits, vol. 33, no. 1, pp.
3644, Jan 1998.
[11] , Optimized Frequency Shaping Circuit topologies for LDOs, IEEE
Trans, Circuits Syst. II, vol. 45, no. 6, pp. 703708, June 1998.
[12] K. H. Chen, H. W. Huang, and S. Y. Kuo, Fast Transient DC-DC Converter
with On-Chip Compensated Error Amplier, IEEE Trans. Cir. Syst. II,
Exp. Briefs, vol. 54, no. 12, p. 1150, Dec 2007.
[13] M. Day. (2002, May) Understanding Low Drop Out LDO Regulators. [On-
line]. Available: http://focus.ti.com/download/trng/docs/seminar/Topic%
209%20-%20Understanding%20LDO%20dropout.pdf
[14] G. A. Rincon-Mora, Analog IC Design With Low-Dropout Regulators. New
York, USA: McGraw-Hill, 2009.
[15] P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan, and S. Borkar,
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Regulator With Damping-Factor-Control Frequency Compensation, IEEE
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85

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LOW QUIESCENT CURRENT LOW-DROPOUT VOLTAGE REGULATORS

WITH IMPROVED TRANSIENT-RESPONSE

s Program. His teaching skills pushed me to give my best

was intentionally added for visibility. . . . . . . . . . . . . . . 32

variation of input voltage in line transient.

was intentionally added for visibility.

120m 1.3 1 950m

C-LDO refers to compensated form of LDO in [1] in 0.5-m process.

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