1942
12, DECEMBER 2000
A Low-Power Low-Noise Accurate Linear-in-dB
Variable-Gain Amplifier with 500-MHz Bandwidth
Shoji Otaka, Gaku Takemura, and Hiroshi Tanimoto, Member, IEEE
Abstract—A linear-in-dB variable-gain amplifier (VGA) using
a pre-distortion circuit to generate the gain-control signal is fabri-
cated in a BiCMOS process with = 20 GHz. The VGA com-
prises two cascaded stages of signal-summing VGA and has a vari-
able-gain range of over 70 dB. It can operate at up to 500 MHz and
dissipates 36 mW from a 3-V supply. A noise figure of below 5 dB
and IIP3 of over 38 dBm at 43-dB gain were obtained. The VGA
achieved a gain error of less than 2 dB over 70-dB gain range, and
it occupies approximately 1 mm2 . The VGA is applicable to future
code division multiple access (CDMA) receivers.
Index Terms—Code division multiple access (CDMA),
gain-compensated circuit, linear-in-dB gain characteristic, tem-
perature-compensation circuit, variable-gain amplifier (VGA).
I. INTRODUCTION
C ODE division multiple access (CDMA) systems capable
of obtaining large channel capacity have been emerging.
A desired signal must be amplified linearly through downcon-
version in the analog blocks of the CDMA receiver because
many unwanted signals occupy the same frequency range as
the desired signal and the unwanted signals have almost the
same power as the desired signal. Thus, CDMA systems require
variable-gain amplifiers (VGAs) with high linearity and wide
gain range in the receiver. There are two options in realizing
the highly linear wide-gain-range VGA. One is a digitally con-
trolled VGA which comprises a series of switchable gain stages
[1], [2]. The other is an analog linear-in-dB VGA which uses a
variable transconductance or a variable resistance controlled by
an analog gain-control signal [3]–[7]. The analog linear-in-dB
VGA is preferred because it needs only one gain-control signal
line.
Future CDMA systems will require wider signal bandwidth
than that of narrow-band CDMA systems because they must
handle high-rate data transmission. A wide signal bandwidth
causes high insertion loss for an IF band-pass filter which is
equipped in front of an IF VGA. This degrades the noise per-
formance of the receiver. In order to reduce the insertion loss
of the IF band-pass filter with wide signal bandwidth, the IF
frequency is required to be higher. This is because the required
quality factor ( ) of the IF band-pass filter becomes lower when
Manuscript received April 24, 2000; revised July 10, 2000.
S. Otaka is with the Corporate Research and Development Center, Toshiba
Corporation, Kawasaki 212-8582, Japan (e-mail: otaka@csl.rdc.toshiba.co.jp).
G. Takemura is with the System LSI Group, Semiconductor Company,
Toshiba Corporation, Kawasaki 212-8582, Japan.
H. Tanimoto is with the Kitami Institute of Technology, Hokkaido 090-8507,
Japan.
Publisher Item Identifier S 0018-9200(00)09474-9.
0018–9200/00$10.00 © 2000 IEEE
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO.
the IF frequency is higher, that is, the order of the band-pass
filter can be lower.
The transmission/reception frequency of future CDMA sys-
tems is expected to be above 2 GHz, which is twice that of
narrow-band CDMA systems, i.e, 900 MHz. This requires an IF
frequency of over 150 MHz to reject image frequency compo-
nents down to the allowable level by using a low-cost small-size
image rejection filter, because the ratio of the image frequency
to the desired frequency will be almost the same as that of
the typical narrow-band CDMA case for obtaining a necessary
image signal rejection.
Considering the signal bandwidth and the transmission/re-
ception frequency in future CDMA systems, a high-frequency
VGA is desired; however, circuits dissipate higher power when
the operating frequency becomes higher. Therefore, power re-
duction techniques are required for high-frequency IF VGA.
This paper describes low-power high-frequency VGA circuit
techniques for future CDMA receivers with high reception fre-
quency and wide signal bandwidth. In Section II, our design
objectives are described. We discuss VGA implementations re-
specting high-frequency operation, low-power operation, and
obtainable gain range, and, for that purpose, compare the four
reported types of VGAs in Section III. A circuit design of the
VGA for the receiver is illustrated in Section IV, where a pre-dis-
tortion circuit to generate the gain-control signal and tempera-
ture-compensation circuits are proposed. Section V shows mea-
sured results when the VGA chip is mounted on a circuit board.
Section VI summarizes the techniques employed for the VGA.
II. DESIGN OBJECTIVES
We aim to design a low-power high-frequency VGA for
future CDMA systems. For a low-insertion-loss IF band-pass
filter, the operable frequency range for our design objective
is assigned from 150–400 MHz. An insertion loss of less
than 10 dB is expected for a signal bandwidth of 4 MHz in
that IF frequency range. This insertion-loss value of the IF
band-pass filter is acceptable for realizing low-noise receivers.
A sufficient image rejection can also be achieved for an RF
signal of over 2 GHz when the IF frequency is over 150 MHz.
CDMA systems require a gain range exceeding 80 dB in total.
A gain range of less than 70 dB is preferable for the IF VGA
from the viewpoint of the realization of a low-noise and low-
distortion receiver. The variable-gain range of 70 dB includes a
10-dB margin, assuming that a 20-dB gain range is assigned to
the RF stage.
A noise figure (NF) of 7 dB and an input-referred intercept
point (IIP3) of 50 dBm are required at maximum gain to
achieve a wide dynamic range receiver. The intercept point at a
 OTAKA et al.: LOW-POWER LOW-NOISE ACCURATE LINEAR-IN-dB VARIABLE-GAIN AMPLIFIER
Fig. 1. Comparison of the VGAs. (a) Signal-summing VGA. (b) A VGA using differential pairs with MOS emitter-degeneration variable resistors. (c) “Triplus”
variable-g m cell VGA. (d) A variable current amplifier in which a gain is controlled in linear-in-dB fashion for current ratio, I =I .
minimum gain is determined to be 8 dBm with the help of a
VGA or a variable attenuator at the RF stage.
The power dissipation target is 36 mW, which is almost the
same power dissipation as that of the VGA for narrow-band
CDMA system [5]. The gain-control signal range is from
0.3–2 V, where the maximum gain is set at 2 V.
III. COMPARISON OF VGA CIRCUITS
VGAs with a wide gain range have been studied for many
years [1], [4]–[7]. Fig. 1(a) shows a signal-summing VGA
which is advantageous in terms of low-noise and low-distortion
characteristics [3], [4]. The signal-summing VGA can also
operate at high frequency, because the gain-control stages
operate as common-base transistors. However, there remains
an unusable gain-control range of about 20 dB around the
maximum gain in linear-in-dB VGAs of this type. This is
because the current gain ( ) dependence on the gain-control
signal is given by the following expression [8]:
(1)
where and are the transconductances of and
, respectively, and is the thermal voltage. The current
gain is an approximately exponential function of only for
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1943
. This condition requires the VGA to operate
with a 20-dB headroom from the maximum gain. This damages
the noise performance and reduces the operable gain range.
A VGA using a differential pair with an MOS emitter-degen-
eration variable resistor [Fig. 1(b)] has high-frequency opera-
tion capability, low noise, and low distortion [5]. The resistance
of the MOS resistor must be set to about a few hundred ohms at
high gain setting in order to reduce the error in the linear-in-dB
gain characteristic. This is because the resistance of the MOS
resistor must be set much larger than , where
is the equivalent resistance in series with the MOS resistor and
is set to a few tens of ohms for low-power operation. In this case,
the resistance of the MOS resistor becomes a few ten-thousands
of ohms at low gain setting. Considering that the cut-off fre-
quency due to the MOS resistor and MOS parasitic capacitances
which exist between the source and/or drain electrode and sub-
strate electrode is decreased at low gain setting, the linear-in-dB
gain range is reduced at high-frequency operation.
Fig. 1(c) shows a “triplus” variable-gm cell which has an
excellent linear-in-dB variable-gain characteristic [6]. Since its
gain is controlled by changing the bias current of transistors, this
type of VGA degrades frequency response at low gain settings
in the case that a multiplication factor of transistors must be
large, for example , to obtain low-noise performance.
Therefore, this VGA is not suitable for high-frequency opera-
tion up to 400 MHz.
Fig. 1(d) shows a variable current amplifier in which the gain
is controlled in a linear-in-dB fashion through the current ratio
 1944 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 12, DECEMBER 2000

Fig. 2. Signal-summing VGA circuit with CSC.

[5]. This configuration can operate at high frequency be- of the VGA stages must be increased so as to obtain the desired
cause the gain is determined by the current ratio, , and the gain range.
range over which tail currents and change can be reduced By subtracting one from the denominator in (1), the signal-
compared to that for the VGA shown in Fig. 1(c). However, this summing VGA can have a complete linear-in-dB characteristic
configuration dissipates a large amount of power because two and 20-dB wider gain range. This realizes a gain range of 40 dB
stages of the amplifier are required in the signal path. using one gain stage. Thus, only two cascaded stages of the
The signal-summing VGA [Fig. 1(a)] and the differential signal-summing VGA are needed to obtain an 80-dB gain range,
pair VGA with an MOS resistor [Fig. 1(b)] are superior among which reduces the power dissipation of the VGA by approxi-
the four types of VGAs from the viewpoint of high-frequency mately one-half.
and low-power operation. We adopted the signal-summing
VGA because, as outlined below, a linear-in-dB function can B. VGA with Accurate Linear-in-dB Gain Control
be achieved over the complete gain-range by modifying the
The biggest issue in using the signal-summing VGA is the
gain-control signal, which does not affect signal path. Hence,
large gain deviation from the linear-in-dB gain-control charac-
there is no need to consider the frequency response of the gain
teristic at high gain. We propose a gain compensation scheme
compensation circuit. On the other hand, the differential pair
in which the gain-control signal is applied to a pre-distortion
VGA with an MOS resistor deviates from the linear-in-dB gain
circuit. Fig. 2 shows the signal-summing VGA with the pro-
characteristic at high frequency even if the gain-control signal
posed pre-distortion circuit, which is referred to as a control
is modified for linear-in-dB characteristic at some frequency.
signal converter (CSC). Signal currents ( ) are input
to the VGA (emitters of , , and , ) and attenuated
IV. CIRCUIT DESIGN according to the gain-control signal . The CSC converts the
gain-control signal into to obtain a linear-in-dB vari-
A design consideration for low-power operation and the
able-gain characteristic up to the maximum gain of the VGA.
VGA circuit implementation are described in this section.
To realize a linear-in-dB characteristic based on (1), the transfer
In particular, we focus on a proposed gain-compensation
function of the CSC must satisfy
scheme and temperature-compensation techniques for realizing
an accurate linear-in-dB function up to the maximum gain.
These techniques enable a low-power operation of the VGA. (2)
Two temperature-compensation techniques are applied to the
gain-compensation scheme and a differential amplifier of the
where is a constant. The gain-control signal
first stage of the VGA, which are explained in Sections IV-C
generates a voltage drop of between the
and IV-D, respectively.
bases of and . Due to the exponential nature
of bipolar transistors and , the collector cur-
A. Design Consideration for Lower-Power Operation rents of and are and
The signal-summing VGA has an unusable gain-control , respectively. The resulting
range of about 20 dB below its maximum gain. Supposing that base voltage difference satisfies (2) for
the minimum current gain is limited to 40 dB due to signal . Thus, the current gain is expressed as follows:
feedthrough, the VGA will have a usable gain range of only
20 dB. This reduced gain range due to incomplete linear-in-dB
(3)
function causes high power consumption because the number

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 OTAKA et al.: LOW-POWER LOW-NOISE ACCURATE LINEAR-IN-dB VARIABLE-GAIN AMPLIFIER 1945

Fig. 3. Block diagram of the temperature compensation.

Therefore, the CSC can steer the signal-summing VGA to op-

erate in a linear-in-dB fashion up to its maximum gain.
A common base transistor and a current mirror com-
prising transistor and compensate for the base cur-
rents of transistor , , and . Fig. 4. Temperature-dependent current source.

C. Temperature Compensation Techniques for the

Signal-Summing VGA
The signal-summing VGA with the proposed CSC requires
temperature compensation (TC), as in the case of conventional
VGAs, because linearly depends on temperature
. Let ( being nominal temperature,
being temperature deviation from ), then is expressed as
follows:

(4)

where is at . This equation indicates that

the temperature dependence of the current gain Fig. 5. Multiplier.
can be canceled by using the sum of a temperature-indepen-
dent current and a temperature-dependent current is generated by summing an output current from the
. Fig. 3 shows a block diagram of this -reference bias circuit and an output current from the
principle to compensate for the temperature dependence of -reference bias circuit. Then, the temperature dependence
the current gain . The temperature compensation is of is canceled because the temperature coefficient of
achieved by using a temperature-dependent current source and the -reference bias circuit is the inverse of that of the
a multiplier. To obtain a highly accurate temperature compen- -reference bias circuit.
sation, two temperature-compensation circuits are used: one An output current of
for temperatures higher than and the other for temperatures is generated by subtracting from the of the
lower than . In the following, a temperature-compensation Widlar current source and multiplying by using an -ratioed
circuit for is explained, because a temperature-com- current mirror.
pensation circuit for is almost the same as that for A linear multiplier is realized using a current divider con-
, except for polarity changes. sisting of a differential pair, as shown in Fig. 5. The base-to-base
A Widlar current source is used for the implementation of the voltage of the differential pair , is copied from that
temperature-dependent current source [8] for , as shown of the differential pair , . Thus, the current dividing
in Fig. 4. The current can be approximated by: ratio for tracks , where the cur-
rent ( being constant conductance) is a control
(5) signal of the multiplier and . The output
current, , is fed to CSC, where
must be set to in order to compensate for
where temperature dependence of the variable-gain characteristic.
temperature-independent current; In this circuit, the output current is zero when be-
temperature coefficient of , approximately cause is zero. Therefore, another temperature-com-
equal to ; pensation circuit is used to compensate for gain variations below
emitter-area ratio of transistor to transistor . .

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 1946
Fig. 6. Input stage of first signal-summing VGA.
Fig. 7. Block diagram of VGA.
D. Input Stage of the VGA
In a receiver, a low-noise performance is required around the
maximum gain of the VGA. A differential amplifier without
emitter-degeneration resistor is used to obtain a low NF, as
shown in Fig. 6. The VGA satisfies our distortion specification
with help from adjustment of a gain of the RF VGA, although
IIP3 becomes small as a result of using the differential amplifier
without emitter degeneration.
The differential amplifier needs only 50- resistor for
impedance matching without bulky off-chip components such
as LC matching circuit.
Temperature compensation for the gain is required because
the transconductance of the differential pair depends on tem-
perature. The temperature dependence of the gain is compen-
sated by using a tail current proportional to temperature. A
Widlar current source is used for temperature compensation as
in the case of the current gain .
E. Input Buffer of CSC
The input buffer of the CSC comprises a control signal
inversion circuit and a voltage-to-current converter (VIC). A
gain-control signal is inverted to obtain the maximum
gain at V. This is because (4) indicates that a
maximum current gain of unity is obtained at of 0 V.
The VIC converts the inverted from voltage to current in
order to feed the desired current signal to resistor in Fig. 2.
F. Block Diagram of the VGA
Fig. 7 shows a block diagram of the VGA with two cascaded
stages of signal-summing VGA. Simulation results indicate that
two cascaded stages of the signal-summing VGA with CSC are
sufficient for obtaining a gain range of over 70 dB. Hence, the
signal-summing VGA with CSC is effective for low-power op-
eration. Temperature compensation is achieved in the first stage
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 12, DECEMBER 2000
Fig. 8. Micrograph of the VGA.
Fig. 9. Frequency response of the VGA.
of the differential amplifier and in the two stages of the VGA
through the CSC. To avoid saturation of the second stage of the
VGA due to dc offset generated by the first stage, dc blocking
capacitors are placed between the first and second stage of the
VGA.
V. MEASUREMENT RESULTS
A micrograph of the VGA is shown in Fig. 8. The VGA was
fabricated in BiCMOS process with GHz, and the die
area is approximately 1 mm . The circuit is laid out carefully,
considering device matching. Transistor is laid out close to
in the CSC shown in Fig. 2.
The IC was mounted on a glass-epoxy circuit board for evalu-
ation. The VGA characteristics were measured through on-chip
buffer circuits.
Frequency responses of the VGA both at maximum and
minimum gain are shown in Fig. 9. The VGA operates up
to 500 MHz, which surpasses our target. The dc blocking
capacitors for connecting the two cascaded stages of the
signal-summing VGA cause gain reduction for lower IF
frequency.
Fig. 10 shows linear-in-dB gain and noise characteristics at
33 C, 85 C, and 3 C, when the signal frequency is 190 MHz.
 OTAKA et al.: LOW-POWER LOW-NOISE ACCURATE LINEAR-IN-dB VARIABLE-GAIN AMPLIFIER 1947

Fig. 10. Linear-in-dB gain and noise characteristics at 190 MHz. Fig. 12. Linear-in-dB gain and noise characteristics at 500 MHz.

Fig. 13. Gain linearity of linear-in-dB gain characteristics at 500 MHz.

Fig. 11. Gain linearity of linear-in-dB gain characteristics at 190 MHz.

Over a gain range of 70 dB, the gain deviation from the gain at
room temperature was within 3 dB throughout the temperature
range. This figure indicates that the proposed VGA is success-
fully compensated for temperature variations of the gain. An
NF of less than 5 dB was obtained at the maximum gain. The
temperature dependence of the gain characteristics is mainly
caused by inaccurate device parameters used for circuit design.
The temperature dependence can be easily corrected by using a
proper parameter set.
Fig. 11 shows the gain linearity of linear-in-dB gain charac-
teristics at 190 MHz. The gain error is only 2 dB over 70-dB
gain range for each temperature. The results confirm the validity
of our ideas for obtaining accurate linear-in-dB variable-gain
characteristics.
Figs. 12 and 13 show the temperature dependence of the gain
characteristics and the gain linearity of linear-in-dB gain char- Fig. 14. Dependence of the linear-in-dB gain characteristics on the
power-supply voltage.
acteristics at 500 MHz. The results are almost the same as those
at 190 MHz.
Fig. 14 shows the dependence of the linear-in-dB gain char- The VGA had an IIP3 dBm at the maximum gain and
acteristics on the power supply voltage. The proposed VGA can an IIP3 dBm at the minimum gain. The IIP3 at the min-
operate down at 2.5 V. This indicates that the power dissipation imum gain is lower than that of the VGA for the narrow-band
of the VGA is reduced to 30 mW. The power dissipation at 2.5 V CDMA [5]. The VGA such as that shown in Fig. 1(b) or (c) is
was less than 85% that of a VGA for narrow-band CDMA [5]. preferable when high IIP3 is required at low gain.

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 1948
TABLE I
SUMMARY OF MEASURED RESULTS
The IC consumes 12 mA from a 3-V power supply. The first
and second stage of the signal-summing VGA consume 2 mA
each. The output buffer for measurement purpose consumes
2 mA. The measured results are summarized in Table I.
VI. CONCLUSION
It is shown that a signal-summing VGA operates well
respecting low-power high-frequency operation, in comparison
with the four conventional types of VGAs. However, the
signal-summing VGA has narrower linear-in-dB gain range,
which increases power dissipation because the number of
signal-summing VGA stages must be increased. A signal-sum-
ming VGA with a CSC is proposed for obtaining wide
linear-in-dB gain range. As a result, only two cascaded stages
of the signal-summing VGA are needed to achieve a 70-dB gain
range and this leads to a low-power and low-noise operation.
Temperature compensation techniques for gain variation are
also proposed.
The measured results confirm that the VGA has a su-
perior characteristics in terms of low-power dissipation,
high-frequency operation, small error in the linear-in-dB gain
characteristic, and low-noise operation. The signal-summing
VGA with CSC is applicable to IMT-2000 terminals as well as
conventional narrow-band CDMA terminals.
ACKNOWLEDGMENT
The authors wish to thank H. Fujiki and M. Araki for tech-
nical support regarding chip layout and fabrication. They are
also grateful to Dr. H. Tsurumi for valuable discussion on the
system specifications.
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Shoji Otaka received the B.E. and M.E. degrees
in electrical engineering from Tohoku University,
Sendai, Japan, in 1985 and 1987, respectively.
In 1987 he joined the Research and Development
Center, Toshiba Corporation, Kawasaki, Japan.
Since then, he has been engaged in the research
and development of high-speed digital circuits.
His present field of interest is the development of
high-speed analog ICs for communication systems.
Mr. Otaka is a member of the Institute of Elec-
tronics, Information and Communication Engineers
of Japan.
Gaku Takemura received the B.E. degree in elec-
trical engineering and the M.E. degree in electronic
communication engineering from Kyoto University,
Kyoto, Japan, in 1995 and 1997, respectively.
In 1997 he joined the System LSI Group,
Semiconductor Company, Toshiba Corporation,
Kawasaki, Japan. Since then, he has been engaged in
the development of wireless communication circuits.
Mr. Takemura is a member of the Institute of Elec-
tronics, Information and Communication Engineers
of Japan.
Hiroshi Tanimoto (M’92) received the B.E., M.E.,
and Ph.D. degrees in electronic engineering from
Hokkaido University, Sapporo, Japan, in 1975, 1977,
and 1980, respectively.
In 1980, he joined the Research and Development
Center, Toshiba Corporation, Kawasaki, Japan,
where he was engaged in research and development
of telecommunication LSIs. Since 2000, he has
been a Professor in the Department of Electrical
and Electronics Engineering, Kitami Institute of
Technology, Kitami, Japan. His main research
interests include analog integrated circuit design, analog signal processing, and
circuit simulation algorithms.
Dr. Tanimoto is a member of the IEEJ.