By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)

1
Embedded Systems Design
(CE-14376)
Fateen Mubarak
Lecture # 17
21
st
Nov 2013
By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
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SPI
Serial Peripheral Interface (SPI) is a
hardware/firmware communications
protocol developed by Motorola and later
adopted by others in the industry.
A serial peripheral interface (SPI) has a
simple 4-wire synchronous interface
protocol that enables controllers and
peripheral devices to intercommunicate.
Its a Serial Communication Protocol.
By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
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Serial Peripheral Interface
Operates in full duplex mode
It can support 1 Mbps or 10Mbps of speed.
Both single-master and multi-master
protocols are possible in SPI.
But the multi-master bus is rarely used and
look awkward, and are usually limited to a
single slave
The SPI Bus is usually used only on the
PCB.
By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
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Serial Peripheral Interface
Reason:
The SPI Bus was designed to transfer data
between various IC chips, at very high speeds.
Due to this high-speed aspect, the bus lines
cannot be too long, because their reactance
increases too much, and the Bus becomes
unusable.
However, its possible to use the SPI Bus
outside the PCB at low speeds.
By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
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Serial Peripheral Interface
An SPI Bus consists of 4 signal wires
Master Out Slave In (MOSI)
MOSI signal is generated by Master, recipient is the Slave.
Master In Slave Out (MISO)
MISO signals are generated by Slaves, recipient is the
Master.
Serial Clock (SCLK or SCK)
SCLK signal is generated by the Master to synchronize data
transfers.
Slave Select (SS#) from master to Chip Select (CS#)
of slave
SS# signal is generated by Master to select individual Slave
devices.
By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
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Serial Peripheral Interface
Data Lines:
Among these four
logic signals, MOSI &
MISO can be grouped
as data lines
Control Lines:
other two SS & SCLK
can be grouped as
control lines

By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
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Serial Peripheral Interface
Operation:
In single-master protocol, usually one SPI
device acts as the SPI Master and controls
the data flow by generating the clock signal
(SCLK) and activating the slave it wants to
communicate with slave-select signal (SS),
then receives and or transmits data via the
two data lines.
A master, usually the host micro controller,
always provides clock signal to all devices on
a bus whether it is selected or not.
By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
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Serial Peripheral Interface
The usage of these each four pins may depend
on the devices.
SDI pin may not be present if a device does not
require an input
ADC
SDO pin may not be present if a device does not
require an output
LCD controllers
If a microcontroller only needs to talk to 1 SPI
Peripheral or one slave, then the CS pin on that slave
may be grounded.
With multiple slave devices, an independent SS
signal is needed from the master for each slave
device.
By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
9
Serial Peripheral Interface
The communication is initiated by the master all the time

The master first configures the clock, using a frequency,
which is less than or equal to the maximum frequency
that the slave device supports

The master then select the desired slave for
communication by pulling the chip select (SS) line of that
particular slave-peripheral to "low" state

If a waiting period is required (such as for analog-to-
digital conversion) then the master must wait for at least
that period of time before starting to issue clock cycles
By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
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Serial Peripheral Interface
By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
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Serial Peripheral Interface
The slaves on the bus that has not been
activated by the master using its slave select
signal will disregard the input clock and MOSI
signals from the master, and must not drive
MISO. That means the master selects only one
slave at a time.
A full duplex data transmission can occur during
each clock cycle. That means the master sends
a bit on the MOSI line; the slave reads it from
that same line and the slave sends a bit on the
MISO line; the master reads it from that same
line.
By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
12
Serial Peripheral Interface
Data are usually shifted out with
the MSB first, while shifting a new
LSB into the same register.

After that register has been shifted
out, the master and slave have
exchanged their register values.

Then each device takes that value
and does the necessary operation
with it (for example, writing it to
memory).
If there are more data to be
exchanged, the shift registers are
loaded with new data and the
process is repeated.
When there are no more data to
be transmitted, the master stops
its clock.

By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
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Serial Peripheral Interface

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Serial Peripheral Interface
Data Bits on MOSI and MMISO toggle on
the SCLK falling edge and are sampled on
the SCLK rising edge.
SPI mode defines which SCLK edge is
used for toggling data and which SCLK
edge is used for sampling data
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Serial Peripheral Interface
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Clock polarity (CPOL) and clock phase (CPHA) are the main
parameters that define a clock format to be used by the SPI bus
If CPHA=0 the data are sampled on the leading (first) clock edge.
If CPHA=1 the data are sampled on the trailing (second) clock
edge,

By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
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Serial Peripheral Interface
CPOL = 0 and CPHA = 0
The data must be available before the first clock signal rising.
The data on MISO and MOSI lines must be stable while the clock is high
and can be changed when the clock is low. The data is captured on the
clock's low-to-high transition and propagated on high-to-low clock
transition.
By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
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Serial Peripheral Interface
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CPOL = 0 and CPHA = 1
The data on MISO and MOSI lines must be stable while the clock is low
and can be changed when the clock is high. The data is captured on the
clock's high-to-low transition and propagated on low-to-high clock
transition
By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
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Serial Peripheral Interface
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CPOL = 1 and CPHA = 0
The data must be available before the first clock signal falling.
The data on MISO and MOSI lines must be stable while the clock is low and
can be changed when the clock is high. The data is captured on the clock's
high-to-low transition and propagated on low-to-high clock transition
By Fateen Mubarak EMBEDDED SYSTEMS DESIGN (EE 4314)
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Serial Peripheral Interface
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CPOL = 1 and CPHA = 1
The data on MISO and MOSI lines must be stable while the clock is high and
can be changed when the clock is low.
The data is captured on the clock's low-to-high transition and propagated on
high-to-low clock transition